--- /dev/null
+/* BFD support for the Scenix IP2xxx processor.
+ Copyright (C) 2000, 2002 Free Software Foundation, Inc.
+
+ This file is part of BFD, the Binary File Descriptor library.
+
+ This program is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 2 of the License, or
+ (at your option) any later version.
+
+ This program is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program; if not, write to the Free Software
+ Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
+
+#include "bfd.h"
+#include "sysdep.h"
+#include "libbfd.h"
+
+const bfd_arch_info_type bfd_ip2k_nonext_arch =
+{
+ 32, /* Bits per word - not really true. */
+ 16, /* Bits per address. */
+ 8, /* Bits per byte. */
+ bfd_arch_ip2k, /* Architecture. */
+ bfd_mach_ip2022, /* Machine. */
+ "ip2k", /* Architecture name. */
+ "ip2022", /* Machine name. */
+ 1, /* Section align power. */
+ false, /* The default ? */
+ bfd_default_compatible, /* Architecture comparison fn. */
+ bfd_default_scan, /* String to architecture convert fn. */
+ NULL /* Next in list. */
+};
+
+const bfd_arch_info_type bfd_ip2k_arch =
+{
+ 32, /* Bits per word - not really true. */
+ 16, /* Bits per address. */
+ 8, /* Bits per byte. */
+ bfd_arch_ip2k, /* Architecture. */
+ bfd_mach_ip2022ext, /* Machine. */
+ "ip2k", /* Architecture name. */
+ "ip2022ext", /* Machine name. */
+ 1, /* Section align power. */
+ true, /* The default ? */
+ bfd_default_compatible, /* Architecture comparison fn. */
+ bfd_default_scan, /* String to architecture convert fn. */
+ & bfd_ip2k_nonext_arch /* Next in list. */
+};
--- /dev/null
+/* Scenix IP2xxx specific support for 32-bit ELF
+ Copyright 2000, 2001, 2002 Free Software Foundation, Inc.
+
+ This file is part of BFD, the Binary File Descriptor library.
+
+ This program is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 2 of the License, or
+ (at your option) any later version.
+
+ This program is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program; if not, write to the Free Software
+ Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
+
+#include "bfd.h"
+#include "sysdep.h"
+#include "libbfd.h"
+#include "elf-bfd.h"
+#include "elf/ip2k.h"
+
+/* Struct used to pass miscellaneous paramaters which
+ helps to avoid overly long parameter lists. */
+struct misc
+{
+ Elf_Internal_Shdr * symtab_hdr;
+ Elf_Internal_Rela * irelbase;
+ bfd_byte * contents;
+ bfd_byte * free_contents;
+ Elf32_External_Sym * extsyms;
+ Elf32_External_Sym * free_extsyms;
+ Elf_Internal_Rela * free_relocs;
+};
+
+/* Prototypes. */
+static reloc_howto_type * ip2k_reloc_type_lookup PARAMS ((bfd *, bfd_reloc_code_real_type));
+static void ip2k_info_to_howto_rela PARAMS ((bfd *, arelent *, Elf32_Internal_Rela *));
+static asection * ip2k_elf_gc_mark_hook PARAMS ((asection *, struct bfd_link_info *, Elf_Internal_Rela *, struct elf_link_hash_entry *, Elf_Internal_Sym *));
+static boolean ip2k_elf_gc_sweep_hook PARAMS ((bfd *, struct bfd_link_info *, asection *, const Elf_Internal_Rela *));
+static bfd_vma symbol_value PARAMS ((bfd *, Elf_Internal_Shdr *, Elf32_External_Sym *, Elf_Internal_Rela *));
+static void adjust_all_relocations PARAMS ((bfd *, asection *, bfd_vma, bfd_vma, int, int));
+static boolean ip2k_elf_relax_delete_bytes PARAMS ((bfd *, asection *, bfd_vma, int));
+static boolean ip2k_elf_relax_add_bytes PARAMS ((bfd *, asection *, bfd_vma, const bfd_byte *, int, int));
+static boolean add_page_insn PARAMS ((bfd *, asection *, Elf_Internal_Rela *, struct misc *));
+static boolean ip2k_elf_relax_section PARAMS ((bfd *, asection *, struct bfd_link_info *, boolean *));
+static boolean relax_switch_dispatch_tables_pass1 PARAMS ((bfd *, asection *, bfd_vma, struct misc *));
+static boolean unrelax_dispatch_table_entries PARAMS ((bfd *, asection *, bfd_vma, bfd_vma, boolean *, struct misc *));
+static boolean unrelax_switch_dispatch_tables_passN PARAMS ((bfd *, asection *, bfd_vma, boolean *, struct misc *));
+static boolean is_switch_128_dispatch_table_p PARAMS ((bfd *, bfd_vma, boolean, struct misc *));
+static boolean is_switch_256_dispatch_table_p PARAMS ((bfd *, bfd_vma, boolean, struct misc *));
+static void tidyup_after_error PARAMS ((struct misc *));
+static boolean ip2k_elf_relax_section_pass1 PARAMS ((bfd *, asection *, boolean *, struct misc *));
+static boolean ip2k_elf_relax_section_passN PARAMS ((bfd *, asection *, boolean *, boolean *, struct misc *));
+static bfd_reloc_status_type ip2k_final_link_relocate PARAMS ((reloc_howto_type *, bfd *, asection *, bfd_byte *, Elf_Internal_Rela *, bfd_vma));
+static boolean ip2k_elf_relocate_section PARAMS ((bfd *, struct bfd_link_info *, bfd *, asection *, bfd_byte *, Elf_Internal_Rela *, Elf_Internal_Sym *, asection **));
+
+#define IS_OPCODE(CODE0,CODE1,OPCODE) \
+ ((CODE0) == (OPCODE)[0] && (CODE1) == (OPCODE)[1])
+
+#define PAGE_INSN_0 0x00
+#define PAGE_INSN_1 0x10
+
+static const bfd_byte page_opcode[] =
+{
+ PAGE_INSN_0, PAGE_INSN_1
+};
+
+#define IS_PAGE_OPCODE(CODE0,CODE1) \
+ IS_OPCODE (CODE0, CODE1, page_opcode)
+
+#define JMP_INSN_0 0xE0
+#define JMP_INSN_1 0x00
+
+static const bfd_byte jmp_opcode[] =
+{
+ JMP_INSN_0, JMP_INSN_1
+};
+
+#define IS_JMP_OPCODE(CODE0,CODE1) \
+ IS_OPCODE (CODE0, CODE1, jmp_opcode)
+
+#define CALL_INSN_0 0xC0
+#define CALL_INSN_1 0x00
+
+static const bfd_byte call_opcode[] =
+{
+ CALL_INSN_0, CALL_INSN_1
+};
+
+#define IS_CALL_OPCODE(CODE0,CODE1) \
+ IS_OPCODE (CODE0, CODE1, call_opcode)
+
+#define ADD_PCL_W_INSN_0 0x1E
+#define ADD_PCL_W_INSN_1 0x09
+
+static const bfd_byte add_pcl_w_opcode[] =
+{
+ ADD_PCL_W_INSN_0, ADD_PCL_W_INSN_1
+};
+
+#define IS_ADD_PCL_W_OPCODE(CODE0,CODE1) \
+ IS_OPCODE (CODE0, CODE1, add_pcl_w_opcode)
+
+#define ADD_W_WREG_INSN_0 0x1C
+#define ADD_W_WREG_INSN_1 0x0A
+
+static const bfd_byte add_w_wreg_opcode[] =
+{
+ ADD_W_WREG_INSN_0, ADD_W_WREG_INSN_1
+};
+
+#define IS_ADD_W_WREG_OPCODE(CODE0,CODE1) \
+ IS_OPCODE (CODE0, CODE1, add_w_wreg_opcode)
+
+#define SNC_INSN_0 0xA0
+#define SNC_INSN_1 0x0B
+
+static const bfd_byte snc_opcode[] =
+{
+ SNC_INSN_0, SNC_INSN_1
+};
+
+#define IS_SNC_OPCODE(CODE0,CODE1) \
+ IS_OPCODE (CODE0, CODE1, snc_opcode)
+
+#define INC_1_SP_INSN_0 0x2B
+#define INC_1_SP_INSN_1 0x81
+
+static const bfd_byte inc_1_sp_opcode[] =
+{
+ INC_1_SP_INSN_0, INC_1_SP_INSN_1
+};
+
+#define IS_INC_1_SP_OPCODE(CODE0,CODE1) \
+ IS_OPCODE (CODE0, CODE1, inc_1_sp_opcode)
+
+#define ADD_2_SP_W_INSN_0 0x1F
+#define ADD_2_SP_W_INSN_1 0x82
+
+static const bfd_byte add_2_sp_w_opcode[] =
+{
+ ADD_2_SP_W_INSN_0, ADD_2_SP_W_INSN_1
+};
+
+#define IS_ADD_2_SP_W_OPCODE(CODE0,CODE1) \
+ IS_OPCODE (CODE0, CODE1, add_2_sp_w_opcode)
+
+/* Relocation tables. */
+static reloc_howto_type ip2k_elf_howto_table [] =
+{
+#define IP2K_HOWTO(t,rs,s,bs,pr,bp,name,sm,dm) \
+ HOWTO(t, /* type */ \
+ rs, /* rightshift */ \
+ s, /* size (0 = byte, 1 = short, 2 = long) */ \
+ bs, /* bitsize */ \
+ pr, /* pc_relative */ \
+ bp, /* bitpos */ \
+ complain_overflow_dont,/* complain_on_overflow */ \
+ bfd_elf_generic_reloc,/* special_function */ \
+ name, /* name */ \
+ false, /* partial_inplace */ \
+ sm, /* src_mask */ \
+ dm, /* dst_mask */ \
+ pr) /* pcrel_offset */
+
+ /* This reloc does nothing. */
+ IP2K_HOWTO (R_IP2K_NONE, 0,2,32, false, 0, "R_IP2K_NONE", 0, 0),
+ /* A 16 bit absolute relocation. */
+ IP2K_HOWTO (R_IP2K_16, 0,1,16, false, 0, "R_IP2K_16", 0, 0xffff),
+ /* A 32 bit absolute relocation. */
+ IP2K_HOWTO (R_IP2K_32, 0,2,32, false, 0, "R_IP2K_32", 0, 0xffffffff),
+ /* A 8-bit data relocation for the FR9 field. Ninth bit is computed specially. */
+ IP2K_HOWTO (R_IP2K_FR9, 0,1,9, false, 0, "R_IP2K_FR9", 0, 0x00ff),
+ /* A 4-bit data relocation. */
+ IP2K_HOWTO (R_IP2K_BANK, 8,1,4, false, 0, "R_IP2K_BANK", 0, 0x000f),
+ /* A 13-bit insn relocation - word address => right-shift 1 bit extra. */
+ IP2K_HOWTO (R_IP2K_ADDR16CJP, 1,1,13, false, 0, "R_IP2K_ADDR16CJP", 0, 0x1fff),
+ /* A 3-bit insn relocation - word address => right-shift 1 bit extra. */
+ IP2K_HOWTO (R_IP2K_PAGE3, 14,1,3, false, 0, "R_IP2K_PAGE3", 0, 0x0007),
+ /* Two 8-bit data relocations. */
+ IP2K_HOWTO (R_IP2K_LO8DATA, 0,1,8, false, 0, "R_IP2K_LO8DATA", 0, 0x00ff),
+ IP2K_HOWTO (R_IP2K_HI8DATA, 8,1,8, false, 0, "R_IP2K_HI8DATA", 0, 0x00ff),
+ /* Two 8-bit insn relocations. word address => right-shift 1 bit extra. */
+ IP2K_HOWTO (R_IP2K_LO8INSN, 1,1,8, false, 0, "R_IP2K_LO8INSN", 0, 0x00ff),
+ IP2K_HOWTO (R_IP2K_HI8INSN, 9,1,8, false, 0, "R_IP2K_HI8INSN", 0, 0x00ff),
+
+ /* Special 1 bit relocation for SKIP instructions. */
+ IP2K_HOWTO (R_IP2K_PC_SKIP, 1,1,1, false, 12, "R_IP2K_PC_SKIP", 0xfffe, 0x1000),
+ /* 16 bit word address. */
+ IP2K_HOWTO (R_IP2K_TEXT, 1,1,16, false, 0, "R_IP2K_TEXT", 0, 0xffff),
+ /* A 7-bit offset relocation for the FR9 field. Eigth and ninth bit comes from insn. */
+ IP2K_HOWTO (R_IP2K_FR_OFFSET, 0,1,9, false, 0, "R_IP2K_FR_OFFSET", 0x180, 0x007f),
+ /* Bits 23:16 of an address. */
+ IP2K_HOWTO (R_IP2K_EX8DATA, 16,1,8, false, 0, "R_IP2K_EX8DATA", 0, 0x00ff),
+};
+
+
+/* Map BFD reloc types to IP2K ELF reloc types. */
+static reloc_howto_type *
+ip2k_reloc_type_lookup (abfd, code)
+ bfd * abfd ATTRIBUTE_UNUSED;
+ bfd_reloc_code_real_type code;
+{
+ /* Note that the ip2k_elf_howto_table is indxed by the R_
+ constants. Thus, the order that the howto records appear in the
+ table *must* match the order of the relocation types defined in
+ include/elf/ip2k.h. */
+
+ switch (code)
+ {
+ case BFD_RELOC_NONE:
+ return &ip2k_elf_howto_table[ (int) R_IP2K_NONE];
+ case BFD_RELOC_16:
+ return &ip2k_elf_howto_table[ (int) R_IP2K_16];
+ case BFD_RELOC_32:
+ return &ip2k_elf_howto_table[ (int) R_IP2K_32];
+ case BFD_RELOC_IP2K_FR9:
+ return &ip2k_elf_howto_table[ (int) R_IP2K_FR9];
+ case BFD_RELOC_IP2K_BANK:
+ return &ip2k_elf_howto_table[ (int) R_IP2K_BANK];
+ case BFD_RELOC_IP2K_ADDR16CJP:
+ return &ip2k_elf_howto_table[ (int) R_IP2K_ADDR16CJP];
+ case BFD_RELOC_IP2K_PAGE3:
+ return &ip2k_elf_howto_table[ (int) R_IP2K_PAGE3];
+ case BFD_RELOC_IP2K_LO8DATA:
+ return &ip2k_elf_howto_table[ (int) R_IP2K_LO8DATA];
+ case BFD_RELOC_IP2K_HI8DATA:
+ return &ip2k_elf_howto_table[ (int) R_IP2K_HI8DATA];
+ case BFD_RELOC_IP2K_LO8INSN:
+ return &ip2k_elf_howto_table[ (int) R_IP2K_LO8INSN];
+ case BFD_RELOC_IP2K_HI8INSN:
+ return &ip2k_elf_howto_table[ (int) R_IP2K_HI8INSN];
+ case BFD_RELOC_IP2K_PC_SKIP:
+ return &ip2k_elf_howto_table[ (int) R_IP2K_PC_SKIP];
+ case BFD_RELOC_IP2K_TEXT:
+ return &ip2k_elf_howto_table[ (int) R_IP2K_TEXT];
+ case BFD_RELOC_IP2K_FR_OFFSET:
+ return &ip2k_elf_howto_table[ (int) R_IP2K_FR_OFFSET];
+ case BFD_RELOC_IP2K_EX8DATA:
+ return &ip2k_elf_howto_table[ (int) R_IP2K_EX8DATA];
+ default:
+ /* Pacify gcc -Wall. */
+ return NULL;
+ }
+ return NULL;
+}
+
+#define PAGENO(ABSADDR) ((ABSADDR) & 0x1C000)
+#define BASEADDR(SEC) ((SEC)->output_section->vma + (SEC)->output_offset)
+
+#define UNDEFINED_SYMBOL (~(bfd_vma)0)
+
+/* Return the value of the symbol associated with the relocation IREL. */
+
+static bfd_vma
+symbol_value (abfd, symtab_hdr, extsyms, irel)
+ bfd *abfd;
+ Elf_Internal_Shdr *symtab_hdr;
+ Elf32_External_Sym *extsyms;
+ Elf_Internal_Rela *irel;
+{
+ if (ELF32_R_SYM (irel->r_info) < symtab_hdr->sh_info)
+ {
+ Elf_External_Sym_Shndx *sym_shndx;
+ Elf_Internal_Shdr *shndx_hdr;
+ Elf_Internal_Sym isym;
+ asection *sym_sec;
+
+ shndx_hdr = &elf_tdata (abfd)->symtab_shndx_hdr;
+ sym_shndx = (Elf_External_Sym_Shndx *) shndx_hdr->contents;
+ sym_shndx = sym_shndx ? sym_shndx + ELF32_R_SYM (irel->r_info) : NULL;
+ bfd_elf32_swap_symbol_in (abfd, extsyms + ELF32_R_SYM (irel->r_info),
+ sym_shndx, &isym);
+ if (isym.st_shndx == SHN_UNDEF)
+ sym_sec = bfd_und_section_ptr;
+ else if (isym.st_shndx == SHN_ABS)
+ sym_sec = bfd_abs_section_ptr;
+ else if (isym.st_shndx == SHN_COMMON)
+ sym_sec = bfd_com_section_ptr;
+ else
+ sym_sec = bfd_section_from_elf_index (abfd, isym.st_shndx);
+
+ return isym.st_value + BASEADDR (sym_sec);
+ }
+ else
+ {
+ unsigned long indx;
+ struct elf_link_hash_entry *h;
+
+ indx = ELF32_R_SYM (irel->r_info) - symtab_hdr->sh_info;
+ h = elf_sym_hashes (abfd)[indx];
+ BFD_ASSERT (h != NULL);
+
+ if (h->root.type != bfd_link_hash_defined
+ && h->root.type != bfd_link_hash_defweak)
+ return UNDEFINED_SYMBOL;
+
+ return (h->root.u.def.value + BASEADDR (h->root.u.def.section));
+ }
+}
+
+/* Determine if the instruction sequence matches that for
+ the prologue of a switch dispatch table with fewer than
+ 128 entries.
+
+ sc
+ page $nnn0
+ jmp $nnn0
+ add w,wreg
+ add pcl,w
+ addr=>
+ page $nnn1
+ jmp $nnn1
+ page $nnn2
+ jmp $nnn2
+ ...
+ page $nnnN
+ jmp $nnnN
+
+ After relaxation.
+ sc
+ page $nnn0
+ jmp $nnn0
+ add pcl,w
+ addr=>
+ jmp $nnn1
+ jmp $nnn2
+ ...
+ jmp $nnnN */
+
+static boolean
+is_switch_128_dispatch_table_p (abfd, addr, relaxed, misc)
+ bfd *abfd ATTRIBUTE_UNUSED;
+ bfd_vma addr;
+ boolean relaxed;
+ struct misc *misc;
+{
+ bfd_byte code0, code1;
+
+ if (addr < (3 * 2))
+ return false;
+
+ code0 = bfd_get_8 (abfd, misc->contents + addr - 2);
+ code1 = bfd_get_8 (abfd, misc->contents + addr - 1);
+
+ /* Is it ADD PCL,W */
+ if (! IS_ADD_PCL_W_OPCODE (code0, code1))
+ return false;
+
+ code0 = bfd_get_8 (abfd, misc->contents + addr - 4);
+ code1 = bfd_get_8 (abfd, misc->contents + addr - 3);
+
+ if (relaxed)
+ /* Is it ADD W,WREG */
+ return ! IS_ADD_W_WREG_OPCODE (code0, code1);
+
+ else
+ {
+ /* Is it ADD W,WREG */
+ if (! IS_ADD_W_WREG_OPCODE (code0, code1))
+ return false;
+
+ code0 = bfd_get_8 (abfd, misc->contents + addr - 6);
+ code1 = bfd_get_8 (abfd, misc->contents + addr - 5);
+
+ /* Is it JMP $nnnn */
+ if (! IS_JMP_OPCODE (code0, code1))
+ return false;
+ }
+
+ /* It looks like we've found the prologue for
+ a 1-127 entry switch dispatch table. */
+ return true;
+}
+
+/* Determine if the instruction sequence matches that for
+ the prologue switch dispatch table with fewer than
+ 256 entries but more than 127.
+
+ Before relaxation.
+ push %lo8insn(label) ; Push address of table
+ push %hi8insn(label)
+ add w,wreg ; index*2 => offset
+ snc ; CARRY SET?
+ inc 1(sp) ; Propagate MSB into table address
+ add 2(sp),w ; Add low bits of offset to table address
+ snc ; and handle any carry-out
+ inc 1(sp)
+ addr=>
+ page __indjmp ; Do an indirect jump to that location
+ jmp __indjmp
+ label: ; case dispatch table starts here
+ page $nnn1
+ jmp $nnn1
+ page $nnn2
+ jmp $nnn2
+ ...
+ page $nnnN
+ jmp $nnnN
+
+ After relaxation.
+ push %lo8insn(label) ; Push address of table
+ push %hi8insn(label)
+ add 2(sp),w ; Add low bits of offset to table address
+ snc ; and handle any carry-out
+ inc 1(sp)
+ addr=>
+ page __indjmp ; Do an indirect jump to that location
+ jmp __indjmp
+ label: ; case dispatch table starts here
+ jmp $nnn1
+ jmp $nnn2
+ ...
+ jmp $nnnN */
+
+static boolean
+is_switch_256_dispatch_table_p (abfd, addr, relaxed, misc)
+ bfd *abfd ATTRIBUTE_UNUSED;
+ bfd_vma addr;
+ boolean relaxed;
+ struct misc *misc;
+{
+ bfd_byte code0, code1;
+
+ if (addr < (8 * 2))
+ return false;
+
+ code0 = bfd_get_8 (abfd, misc->contents + addr - 2);
+ code1 = bfd_get_8 (abfd, misc->contents + addr - 1);
+
+ /* Is it INC 1(SP). */
+ if (! IS_INC_1_SP_OPCODE (code0, code1))
+ return false;
+
+ code0 = bfd_get_8 (abfd, misc->contents + addr - 4);
+ code1 = bfd_get_8 (abfd, misc->contents + addr - 3);
+
+ /* Is it SNC. */
+ if (! IS_SNC_OPCODE (code0, code1))
+ return false;
+
+ code0 = bfd_get_8 (abfd, misc->contents + addr - 6);
+ code1 = bfd_get_8 (abfd, misc->contents + addr - 5);
+
+ /* Is it ADD 2(SP),W. */
+ if (! IS_ADD_2_SP_W_OPCODE (code0, code1))
+ return false;
+
+ code0 = bfd_get_8 (abfd, misc->contents + addr - 8);
+ code1 = bfd_get_8 (abfd, misc->contents + addr - 7);
+
+ if (relaxed)
+ /* Is it INC 1(SP). */
+ return ! IS_INC_1_SP_OPCODE (code0, code1);
+
+ else
+ {
+ /* Is it INC 1(SP). */
+ if (! IS_INC_1_SP_OPCODE (code0, code1))
+ return false;
+
+ code0 = bfd_get_8 (abfd, misc->contents + addr - 10);
+ code1 = bfd_get_8 (abfd, misc->contents + addr - 9);
+
+ /* Is it SNC. */
+ if (! IS_SNC_OPCODE (code0, code1))
+ return false;
+
+ code0 = bfd_get_8 (abfd, misc->contents + addr - 12);
+ code1 = bfd_get_8 (abfd, misc->contents + addr - 11);
+
+ /* Is it ADD W,WREG. */
+ if (! IS_ADD_W_WREG_OPCODE (code0, code1))
+ return false;
+ }
+
+ /* It looks like we've found the prologue for
+ a 128-255 entry switch dispatch table. */
+ return true;
+}
+
+static boolean
+relax_switch_dispatch_tables_pass1 (abfd, sec, addr, misc)
+ bfd *abfd;
+ asection *sec;
+ bfd_vma addr;
+ struct misc *misc;
+{
+ if (addr + 3 < sec->_cooked_size)
+ {
+ bfd_byte code0 = bfd_get_8 (abfd, misc->contents + addr + 2);
+ bfd_byte code1 = bfd_get_8 (abfd, misc->contents + addr + 3);
+
+ if (IS_JMP_OPCODE (code0, code1)
+ && is_switch_128_dispatch_table_p (abfd, addr, false, misc))
+ {
+ /* Delete ADD W,WREG from prologue. */
+ ip2k_elf_relax_delete_bytes (abfd, sec, addr - (2 * 2), (1 * 2));
+ return true;
+ }
+
+ if (IS_JMP_OPCODE (code0, code1)
+ && is_switch_256_dispatch_table_p (abfd, addr, false, misc))
+ {
+ /* Delete ADD W,WREG; SNC ; INC 1(SP) from prologue. */
+ ip2k_elf_relax_delete_bytes (abfd, sec, addr - 6 * 2, 3 * 2);
+ return true;
+ }
+ }
+
+ return true;
+}
+
+static boolean
+unrelax_dispatch_table_entries (abfd, sec, first, last, changed, misc)
+ bfd *abfd;
+ asection *sec;
+ bfd_vma first;
+ bfd_vma last;
+ boolean *changed;
+ struct misc *misc;
+{
+ bfd_vma addr = first;
+
+ while (addr < last)
+ {
+ bfd_byte code0 = bfd_get_8 (abfd, misc->contents + addr);
+ bfd_byte code1 = bfd_get_8 (abfd, misc->contents + addr + 1);
+
+ /* We are only expecting to find PAGE or JMP insns
+ in the dispatch table. If we find anything else
+ something has gone wrong failed the relaxation
+ which will cause the link to be aborted. */
+
+ if (IS_PAGE_OPCODE (code0, code1))
+ /* Skip the PAGE and JMP insns. */
+ addr += 4;
+ else if (IS_JMP_OPCODE (code0, code1))
+ {
+ Elf_Internal_Rela * irelend = misc->irelbase
+ + sec->reloc_count;
+ Elf_Internal_Rela * irel;
+
+ /* Find the relocation entry. */
+ for (irel = misc->irelbase; irel < irelend; irel++)
+ {
+ if (irel->r_offset == addr
+ && ELF32_R_TYPE (irel->r_info) == R_IP2K_ADDR16CJP)
+ {
+ if (! add_page_insn (abfd, sec, irel, misc))
+ /* Something has gone wrong. */
+ return false;
+
+ *changed = true;
+ break;
+ }
+ }
+
+ /* If we fell off the end something has gone wrong. */
+ if (irel >= irelend)
+ /* Something has gone wrong. */
+ return false;
+
+ /* Skip the PAGE and JMP isns. */
+ addr += 4;
+ /* Acount for the new PAGE insn. */
+ last += 2;
+ }
+ else
+ /* Something has gone wrong. */
+ return false;
+ }
+
+ return true;
+}
+
+static boolean
+unrelax_switch_dispatch_tables_passN (abfd, sec, addr, changed, misc)
+ bfd *abfd;
+ asection *sec;
+ bfd_vma addr;
+ boolean *changed;
+ struct misc *misc;
+{
+ if (2 <= addr && (addr + 3) < sec->_cooked_size)
+ {
+ bfd_byte code0 = bfd_get_8 (abfd, misc->contents + addr - 2);
+ bfd_byte code1 = bfd_get_8 (abfd, misc->contents + addr - 1);
+
+ if (IS_PAGE_OPCODE (code0, code1))
+ {
+ addr -= 2;
+ code0 = bfd_get_8 (abfd, misc->contents + addr + 2);
+ code1 = bfd_get_8 (abfd, misc->contents + addr + 3);
+ }
+ else
+ {
+ code0 = bfd_get_8 (abfd, misc->contents + addr);
+ code1 = bfd_get_8 (abfd, misc->contents + addr + 1);
+ }
+
+ if (IS_JMP_OPCODE (code0, code1)
+ && is_switch_128_dispatch_table_p (abfd, addr, true, misc))
+ {
+ bfd_vma first = addr;
+ bfd_vma last = first;
+ boolean relaxed = true;
+
+ /* On the final pass we must check if *all* entries in the
+ dispatch table are relaxed. If *any* are not relaxed
+ then we must unrelax *all* the entries in the dispach
+ table and also unrelax the dispatch table prologue. */
+
+ /* Find the last entry in the dispach table. */
+ while (last < sec->_cooked_size)
+ {
+ code0 = bfd_get_8 (abfd, misc->contents + last);
+ code1 = bfd_get_8 (abfd, misc->contents + last + 1);
+
+ if (IS_PAGE_OPCODE (code0, code1))
+ relaxed = false;
+ else if (! IS_JMP_OPCODE (code0, code1))
+ break;
+
+ last += 2;
+ }
+
+ /* We should have found the end of the dispatch table
+ before reaching the end of the section. If we've have
+ reached the end then fail the relaxation which will
+ cause the link to be aborted. */
+ if (last >= sec->_cooked_size)
+ /* Something has gone wrong. */
+ return false;
+
+ /* If we found an unrelaxed entry then
+ unlrelax all the switch table entries. */
+ if (! relaxed )
+ {
+ if (! unrelax_dispatch_table_entries (abfd, sec, first,
+ last, changed, misc))
+ /* Something has gone wrong. */
+ return false;
+
+ if (! is_switch_128_dispatch_table_p (abfd, addr, true, misc))
+ /* Something has gone wrong. */
+ return false;
+
+ /* Unrelax the prologue. */
+
+ /* Insert an ADD W,WREG insnstruction. */
+ if (! ip2k_elf_relax_add_bytes (abfd, sec,
+ addr - 2,
+ add_w_wreg_opcode,
+ sizeof (add_w_wreg_opcode),
+ 0))
+ /* Something has gone wrong. */
+ return false;
+ }
+
+ return true;
+ }
+
+ if (IS_JMP_OPCODE (code0, code1)
+ && is_switch_256_dispatch_table_p (abfd, addr, true, misc))
+ {
+ bfd_vma first = addr;
+ bfd_vma last;
+ boolean relaxed = true;
+
+ /* On the final pass we must check if *all* entries in the
+ dispatch table are relaxed. If *any* are not relaxed
+ then we must unrelax *all* the entries in the dispach
+ table and also unrelax the dispatch table prologue. */
+
+ /* Note the 1st PAGE/JMP instructions are part of the
+ prologue and can safely be relaxed. */
+
+ code0 = bfd_get_8 (abfd, misc->contents + first);
+ code1 = bfd_get_8 (abfd, misc->contents + first + 1);
+
+ if (IS_PAGE_OPCODE (code0, code1))
+ {
+ first += 2;
+ code0 = bfd_get_8 (abfd, misc->contents + first);
+ code1 = bfd_get_8 (abfd, misc->contents + first + 1);
+ }
+
+ if (! IS_JMP_OPCODE (code0, code1))
+ /* Something has gone wrong. */
+ return false;
+
+ first += 2;
+ last = first;
+
+ /* Find the last entry in the dispach table. */
+ while (last < sec->_cooked_size)
+ {
+ code0 = bfd_get_8 (abfd, misc->contents + last);
+ code1 = bfd_get_8 (abfd, misc->contents + last + 1);
+
+ if (IS_PAGE_OPCODE (code0, code1))
+ relaxed = false;
+ else if (! IS_JMP_OPCODE (code0, code1))
+ break;
+
+ last += 2;
+ }
+
+ /* We should have found the end of the dispatch table
+ before reaching the end of the section. If we have
+ reached the end of the section then fail the
+ relaxation. */
+ if (last >= sec->_cooked_size)
+ return false;
+
+ /* If we found an unrelaxed entry then
+ unrelax all the switch table entries. */
+ if (! relaxed)
+ {
+ if (! unrelax_dispatch_table_entries (abfd, sec, first,
+ last, changed, misc))
+ return false;
+
+ if (! is_switch_256_dispatch_table_p (abfd, addr, true, misc))
+ return false;
+
+ /* Unrelax the prologue. */
+
+ /* Insert an INC 1(SP) insnstruction. */
+ if (! ip2k_elf_relax_add_bytes (abfd, sec,
+ addr - 6,
+ inc_1_sp_opcode,
+ sizeof (inc_1_sp_opcode),
+ 0))
+ return false;
+
+ /* Insert an SNC insnstruction. */
+ if (! ip2k_elf_relax_add_bytes (abfd, sec,
+ addr - 6,
+ snc_opcode,
+ sizeof (snc_opcode),
+ 0))
+ return false;
+
+ /* Insert an ADD W,WREG insnstruction. */
+ if (! ip2k_elf_relax_add_bytes (abfd, sec,
+ addr - 6,
+ add_w_wreg_opcode,
+ sizeof (add_w_wreg_opcode),
+ 0))
+ return false;
+ }
+
+ return true;
+ }
+ }
+
+ return true;
+}
+
+/* This function handles relaxing for the ip2k. */
+
+static boolean
+ip2k_elf_relax_section (abfd, sec, link_info, again)
+ bfd *abfd;
+ asection *sec;
+ struct bfd_link_info *link_info;
+ boolean *again;
+{
+ Elf_External_Sym_Shndx *shndx_buf;
+ Elf_Internal_Shdr *shndx_hdr;
+ static asection * first_section = NULL;
+ static asection * last_section = NULL;
+ static boolean changed = false;
+ static boolean final_pass = false;
+ static unsigned int pass = 0;
+ struct misc misc;
+ asection *stab;
+
+ /* Assume nothing changes. */
+ *again = false;
+
+ if (first_section == NULL)
+ first_section = sec;
+
+ if (first_section == sec)
+ {
+ changed = false;
+ pass++;
+ }
+
+ /* If we make too many passes then it's a sign that
+ something is wrong and we fail the relaxation.
+ Note if everything is working correctly then the
+ relaxation should converge reasonably quickly. */
+ if (pass == 4096)
+ return false;
+
+ /* We don't have to do anything for a relocatable link,
+ if this section does not have relocs, or if this is
+ not a code section. */
+ if (link_info->relocateable
+ || (sec->flags & SEC_RELOC) == 0
+ || sec->reloc_count == 0
+ || (sec->flags & SEC_CODE) == 0)
+ return true;
+
+ if (pass == 1)
+ last_section = sec;
+
+ misc.symtab_hdr = NULL;
+ misc.irelbase = NULL;
+ misc.contents = NULL;
+ misc.free_contents = NULL;
+ misc.extsyms = NULL;
+ misc.free_extsyms = NULL;
+ misc.free_relocs = NULL;
+
+ /* If this is the first time we have been called
+ for this section, initialise the cooked size. */
+ if (sec->_cooked_size == 0)
+ sec->_cooked_size = sec->_raw_size;
+
+ misc.symtab_hdr = &elf_tdata (abfd)->symtab_hdr;
+ shndx_hdr = &elf_tdata (abfd)->symtab_shndx_hdr;
+
+ misc.irelbase = _bfd_elf32_link_read_relocs (abfd, sec, NULL,
+ (Elf_Internal_Rela *)NULL,
+ link_info->keep_memory);
+ if (misc.irelbase == NULL)
+ {
+ tidyup_after_error (&misc);
+ return false;
+ }
+
+ if (! link_info->keep_memory)
+ misc.free_relocs = misc.irelbase;
+
+ /* Make sure the stac.rela stuff gets read in. */
+ stab = bfd_get_section_by_name (abfd, ".stab");
+
+ if (stab)
+ {
+ /* So stab does exits. */
+ Elf_Internal_Rela * irelbase;
+
+ irelbase = _bfd_elf32_link_read_relocs (abfd, stab, NULL,
+ (Elf_Internal_Rela *)NULL,
+ link_info->keep_memory);
+ }
+
+ /* Get section contents cached copy if it exists. */
+ if (elf_section_data (sec)->this_hdr.contents != NULL)
+ misc.contents = elf_section_data (sec)->this_hdr.contents;
+ else
+ {
+ /* Go get them of disk. */
+ misc.contents = (bfd_byte *) bfd_malloc (sec->_raw_size);
+ if (misc.contents == NULL)
+ {
+ tidyup_after_error (&misc);
+ return false;
+ }
+
+ misc.free_contents = misc.contents;
+ if (! bfd_get_section_contents (abfd, sec, misc.contents,
+ (file_ptr)0,
+ sec->_raw_size))
+ {
+ tidyup_after_error (&misc);
+ return false;
+ }
+ }
+
+ /* Read this BFD's symbols cached copy if it exists. */
+ if (misc.symtab_hdr->contents != NULL)
+ misc.extsyms = (Elf32_External_Sym *) misc.symtab_hdr->contents;
+ else
+ {
+ /* Go get them off disk. */
+ misc.extsyms = ((Elf32_External_Sym *)bfd_malloc (misc.symtab_hdr->sh_size));
+ if (misc.extsyms == NULL)
+ {
+ tidyup_after_error (&misc);
+ return false;
+ }
+
+ misc.free_extsyms = misc.extsyms;
+ if (bfd_seek (abfd, misc.symtab_hdr->sh_offset, SEEK_SET) != 0
+ || (bfd_read (misc.extsyms, 1, misc.symtab_hdr->sh_size, abfd)
+ != misc.symtab_hdr->sh_size))
+ {
+ tidyup_after_error (&misc);
+ return false;
+ }
+ }
+
+ if (shndx_hdr->sh_size != 0)
+ {
+ bfd_size_type amt;
+
+ amt = misc.symtab_hdr->sh_info * sizeof (Elf_External_Sym_Shndx);
+ shndx_buf = (Elf_External_Sym_Shndx *) bfd_malloc (amt);
+ if (shndx_buf == NULL)
+ {
+ tidyup_after_error (&misc);
+ return false;
+ }
+ if (bfd_seek (abfd, shndx_hdr->sh_offset, SEEK_SET) != 0
+ || bfd_bread ((PTR) shndx_buf, amt, abfd) != amt)
+ {
+ tidyup_after_error (&misc);
+ return false;
+ }
+ shndx_hdr->contents = (PTR) shndx_buf;
+ }
+
+ /* This is where all the relaxation actually get done. */
+
+ if (pass == 1)
+ {
+ /* On the first pass we remove *all* page instructions and
+ relax the prolog for switch dispatch tables. This gets
+ us to the starting point for subsequent passes where
+ we add page instructions back in as needed. */
+
+ if (! ip2k_elf_relax_section_pass1 (abfd, sec, again, &misc))
+ {
+ tidyup_after_error (&misc);
+ return false;
+ }
+
+ changed |= *again;
+ }
+ else
+ {
+ /* Add page instructions back in as needed but we ignore
+ the issue with sections (functions) crossing a page
+ boundary until we have converged to an approximate
+ solution (i.e. nothing has changed on this relaxation
+ pass) and we then know roughly where the page boundaries
+ will end up.
+
+ After we have have converged to an approximate solution
+ we set the final pass flag and continue relaxing. On these
+ final passes if a section (function) cross page boundary
+ we will add *all* the page instructions back into such
+ sections.
+
+ After adding *all* page instructions back into a section
+ which crosses a page bounbdary we reset the final pass flag
+ so the we will again interate until we find a new approximate
+ solution which is closer to the final solution. */
+
+ if (! ip2k_elf_relax_section_passN (abfd, sec, again,
+ &final_pass, &misc))
+ {
+ tidyup_after_error (&misc);
+ return false;
+ }
+
+ changed |= *again;
+
+ /* If nothing has changed on this relaxation
+ pass restart the final relaxaton pass. */
+ if (! changed && last_section == sec)
+ {
+ /* If this was the final pass and we didn't reset
+ the final pass flag then we are done, otherwise
+ do another final pass. */
+ if (! final_pass)
+ {
+ final_pass = true;
+ *again = true;
+ }
+ }
+ }
+
+ /* Perform some house keeping after relaxing the section. */
+
+ if (misc.free_relocs != NULL)
+ {
+ free (misc.free_relocs);
+ misc.free_relocs = NULL;
+ }
+
+ if (misc.free_contents != NULL)
+ {
+ if (! link_info->keep_memory)
+ free (misc.free_contents);
+ else
+ {
+ /* Cache the section contents for elf_link_input_bfd. */
+ elf_section_data (sec)->this_hdr.contents = misc.contents;
+ }
+
+ misc.free_contents = NULL;
+ }
+
+ if (misc.free_extsyms != NULL)
+ {
+ if (! link_info->keep_memory)
+ free (misc.free_extsyms);
+ else
+ {
+ /* Cache the symbols for elf_link_input_bfd. */
+ misc.symtab_hdr->contents = misc.extsyms;
+ }
+
+ misc.free_extsyms = NULL;
+ }
+
+ return true;
+}
+
+static void
+tidyup_after_error (misc)
+ struct misc *misc;
+{
+ if (misc->free_relocs != NULL)
+ {
+ free (misc->free_relocs);
+ misc->free_relocs = NULL;
+ }
+
+ if (misc->free_contents != NULL)
+ {
+ free (misc->free_contents);
+ misc->free_contents = NULL;
+ }
+
+ if (misc->free_extsyms != NULL)
+ {
+ free (misc->free_extsyms);
+ misc->free_extsyms = NULL;
+ }
+
+ return;
+}
+
+/* This function handles relaxation during the first pass. */
+
+static boolean
+ip2k_elf_relax_section_pass1 (abfd, sec, again, misc)
+ bfd *abfd;
+ asection *sec;
+ boolean *again;
+ struct misc * misc;
+{
+ Elf_Internal_Rela *irelend = misc->irelbase + sec->reloc_count;
+ Elf_Internal_Rela *irel;
+
+ /* Walk thru the section looking for relaxation opertunities. */
+ for (irel = misc->irelbase; irel < irelend; irel++)
+ {
+ if (ELF32_R_TYPE (irel->r_info) == (int) R_IP2K_PAGE3)
+ {
+ bfd_byte code0 = bfd_get_8 (abfd,
+ misc->contents + irel->r_offset);
+ bfd_byte code1 = bfd_get_8 (abfd,
+ misc->contents + irel->r_offset + 1);
+
+ /* Verify that this is the PAGE opcode. */
+ if (IS_PAGE_OPCODE (code0, code1))
+ {
+ /* Note that we've changed the relocs, section contents, etc. */
+ elf_section_data (sec)->relocs = misc->irelbase;
+ misc->free_relocs = NULL;
+
+ elf_section_data (sec)->this_hdr.contents = misc->contents;
+ misc->free_contents = NULL;
+
+ misc->symtab_hdr->contents = (bfd_byte *) misc->extsyms;
+ misc->free_extsyms = NULL;
+
+ /* Handle switch dispatch tables/prologues. */
+ if (! relax_switch_dispatch_tables_pass1 (abfd, sec,
+ irel->r_offset, misc))
+ return false;
+
+ /* Fix the relocation's type. */
+ irel->r_info = ELF32_R_INFO (ELF32_R_SYM (irel->r_info),
+ R_IP2K_NONE);
+
+ /* Delete the PAGE insn. */
+ if (! ip2k_elf_relax_delete_bytes (abfd, sec,
+ irel->r_offset,
+ sizeof (page_opcode)))
+ return false;
+
+ /* That will change things, so, we should relax again.
+ Note that this is not required, and it may be slow. */
+ *again = true;
+ }
+ }
+ }
+
+ return true;
+}
+
+/* This function handles relaxation for 2nd and subsequent passes. */
+
+static boolean
+ip2k_elf_relax_section_passN (abfd, sec, again, final_pass, misc)
+ bfd *abfd;
+ asection *sec;
+ boolean *again;
+ boolean *final_pass;
+ struct misc * misc;
+{
+ Elf_Internal_Rela *irelend = misc->irelbase + sec->reloc_count;
+ Elf_Internal_Rela *irel;
+ boolean add_all;
+
+ /* If we are on the final relaxation pass and the section crosses
+ then set a flag to indicate that *all* page instructions need
+ to be added back into this section. */
+ if (*final_pass)
+ {
+ add_all = (PAGENO (BASEADDR (sec))
+ != PAGENO (BASEADDR (sec) + sec->_cooked_size));
+
+ /* If this section crosses a page boundary set the crossed
+ page boundary flag. */
+ if (add_all)
+ sec->userdata = sec;
+ else
+ {
+ /* If the section had previously crossed a page boundary
+ but on this pass does not then reset crossed page
+ boundary flag and rerun the 1st relaxation pass on
+ this section. */
+ if (sec->userdata)
+ {
+ sec->userdata = NULL;
+ if (! ip2k_elf_relax_section_pass1 (abfd, sec, again, misc))
+ return false;
+ }
+ }
+ }
+ else
+ add_all = false;
+
+ /* Walk thru the section looking for call/jmp
+ instructions which need a page instruction. */
+ for (irel = misc->irelbase; irel < irelend; irel++)
+ {
+ if (ELF32_R_TYPE (irel->r_info) == (int) R_IP2K_ADDR16CJP)
+ {
+ /* Get the value of the symbol referred to by the reloc. */
+ bfd_vma symval = symbol_value (abfd, misc->symtab_hdr, misc->extsyms,
+ irel);
+ bfd_byte code0, code1;
+
+ if (symval == UNDEFINED_SYMBOL)
+ {
+ /* This appears to be a reference to an undefined
+ symbol. Just ignore it--it will be caught by the
+ regular reloc processing. */
+ continue;
+ }
+
+ /* For simplicity of coding, we are going to modify the section
+ contents, the section relocs, and the BFD symbol table. We
+ must tell the rest of the code not to free up this
+ information. It would be possible to instead create a table
+ of changes which have to be made, as is done in coff-mips.c;
+ that would be more work, but would require less memory when
+ the linker is run. */
+
+ /* Get the opcode. */
+ code0 = bfd_get_8 (abfd, misc->contents + irel->r_offset);
+ code1 = bfd_get_8 (abfd, misc->contents + irel->r_offset + 1);
+
+ if (IS_JMP_OPCODE (code0, code1) || IS_CALL_OPCODE (code0, code1))
+ {
+ if (*final_pass)
+ {
+ if (! unrelax_switch_dispatch_tables_passN (abfd, sec,
+ irel->r_offset,
+ again, misc))
+ return false;
+
+ if (*again)
+ add_all = false;
+ }
+
+ code0 = bfd_get_8 (abfd, misc->contents + irel->r_offset - 2);
+ code1 = bfd_get_8 (abfd, misc->contents + irel->r_offset - 1);
+
+ if (! IS_PAGE_OPCODE (code0, code1))
+ {
+ bfd_vma value = symval + irel->r_addend;
+ bfd_vma addr = BASEADDR (sec) + irel->r_offset;
+
+ if (add_all || PAGENO (addr) != PAGENO (value))
+ {
+ if (! add_page_insn (abfd, sec, irel, misc))
+ return false;
+
+ /* That will have changed things, so, we must relax again. */
+ *again = true;
+ }
+ }
+ }
+ }
+ }
+
+ /* If anything changed reset the final pass flag. */
+ if (*again)
+ *final_pass = false;
+
+ return true;
+}
+
+/* Parts of a Stabs entry. */
+
+#define STRDXOFF (0)
+#define TYPEOFF (4)
+#define OTHEROFF (5)
+#define DESCOFF (6)
+#define VALOFF (8)
+#define STABSIZE (12)
+
+/* Adjust all the relocations entries after adding or inserting instructions. */
+
+static void
+adjust_all_relocations (abfd, sec, addr, endaddr, count, noadj)
+ bfd *abfd;
+ asection *sec;
+ bfd_vma addr;
+ bfd_vma endaddr;
+ int count;
+ int noadj;
+{
+ Elf_Internal_Shdr *symtab_hdr;
+ Elf32_External_Sym *extsyms;
+ int shndx, index;
+ bfd_byte *contents;
+ Elf_Internal_Rela *irel, *irelend, *irelbase;
+ Elf32_External_Sym *esym, *esymend;
+ asection *stab;
+ bfd_byte *stabp, *stabend, *stabcontents;
+ Elf_Internal_Shdr *shndx_hdr;
+ Elf_External_Sym_Shndx *sym_shndx;
+
+ symtab_hdr = &elf_tdata (abfd)->symtab_hdr;
+ extsyms = (Elf32_External_Sym *) symtab_hdr->contents;
+
+ shndx = _bfd_elf_section_from_bfd_section (abfd, sec);
+
+ contents = elf_section_data (sec)->this_hdr.contents;
+
+ irelbase = elf_section_data (sec)->relocs;
+ irelend = irelbase + sec->reloc_count;
+
+ for (irel = irelbase; irel < irelend; irel++)
+ {
+ if (ELF32_R_TYPE (irel->r_info) != R_IP2K_NONE)
+ {
+ /* Get the value of the symbol referred to by the reloc. */
+ if (ELF32_R_SYM (irel->r_info) < symtab_hdr->sh_info)
+ {
+ Elf_Internal_Sym isym;
+ asection *sym_sec;
+ Elf_External_Sym_Shndx *sym_shndx;
+ Elf_Internal_Shdr *shndx_hdr;
+
+ /* A local symbol. */
+
+ shndx_hdr = &elf_tdata (abfd)->symtab_shndx_hdr;
+ sym_shndx = (Elf_External_Sym_Shndx *) shndx_hdr->contents;
+ sym_shndx = (sym_shndx
+ ? sym_shndx + ELF32_R_SYM (irel->r_info) : NULL);
+ bfd_elf32_swap_symbol_in (abfd,
+ extsyms + ELF32_R_SYM (irel->r_info),
+ sym_shndx, &isym);
+
+ if (isym.st_shndx == SHN_UNDEF)
+ sym_sec = bfd_und_section_ptr;
+ else if (isym.st_shndx == SHN_ABS)
+ sym_sec = bfd_abs_section_ptr;
+ else if (isym.st_shndx == SHN_COMMON)
+ sym_sec = bfd_com_section_ptr;
+ else
+ sym_sec = bfd_section_from_elf_index (abfd, isym.st_shndx);
+
+ if (sym_sec == sec)
+ {
+ bfd_vma baseaddr = BASEADDR (sec);
+ bfd_vma symval = BASEADDR (sym_sec) + isym.st_value
+ + irel->r_addend;
+
+ if ((baseaddr + addr + noadj) <= symval
+ && symval < (baseaddr + endaddr))
+ irel->r_addend += count;
+ }
+ }
+ }
+
+ /* Do this only for PC space relocations. */
+ if (addr <= irel->r_offset && irel->r_offset < endaddr)
+ irel->r_offset += count;
+ }
+
+ /* Now fix the stab relocations. */
+ stab = bfd_get_section_by_name (abfd, ".stab");
+ if (stab)
+ {
+ irelbase = elf_section_data (stab)->relocs;
+ irelend = irelbase + stab->reloc_count;
+
+ /* Pull out the contents of the stab section. */
+ if (elf_section_data (stab)->this_hdr.contents != NULL)
+ stabcontents = elf_section_data (stab)->this_hdr.contents;
+ else
+ {
+ stabcontents = (bfd_byte *) bfd_alloc (abfd, stab->_raw_size);
+ if (stabcontents == NULL)
+ return;
+ if (! bfd_get_section_contents (abfd, stab, stabcontents,
+ (file_ptr) 0, stab->_raw_size))
+ return;
+
+ /* We need to remember this. */
+ elf_section_data (stab)->this_hdr.contents = stabcontents;
+ }
+
+ stabend = stabcontents + stab->_raw_size;
+
+ for (irel = irelbase; irel < irelend; irel++)
+ {
+ if (ELF32_R_TYPE (irel->r_info) != R_IP2K_NONE)
+ {
+ /* Get the value of the symbol referred to by the reloc. */
+ if (ELF32_R_SYM (irel->r_info) < symtab_hdr->sh_info)
+ {
+ Elf_Internal_Sym isym;
+ asection *sym_sec;
+ Elf_External_Sym_Shndx *sym_shndx;
+ Elf_Internal_Shdr *shndx_hdr;
+
+ /* A local symbol. */
+ shndx_hdr = &elf_tdata (abfd)->symtab_shndx_hdr;
+ sym_shndx = (Elf_External_Sym_Shndx *) shndx_hdr->contents;
+ sym_shndx = (sym_shndx
+ ? sym_shndx + ELF32_R_SYM (irel->r_info)
+ : NULL);
+
+ bfd_elf32_swap_symbol_in (abfd,
+ (extsyms
+ + ELF32_R_SYM (irel->r_info)),
+ sym_shndx, &isym);
+
+ if (isym.st_shndx == SHN_UNDEF)
+ sym_sec = bfd_und_section_ptr;
+ else if (isym.st_shndx == SHN_ABS)
+ sym_sec = bfd_abs_section_ptr;
+ else if (isym.st_shndx == SHN_COMMON)
+ sym_sec = bfd_com_section_ptr;
+ else
+ sym_sec = bfd_section_from_elf_index (abfd, isym.st_shndx);
+
+ if (sym_sec == sec)
+ {
+ const char *name;
+ unsigned long strx;
+ unsigned char type, other;
+ unsigned short desc;
+ bfd_vma value;
+ bfd_vma baseaddr = BASEADDR (sec);
+ bfd_vma symval = BASEADDR (sym_sec) + isym.st_value
+ + irel->r_addend;
+
+ if ((baseaddr + addr) <= symval
+ && symval <= (baseaddr + endaddr))
+ irel->r_addend += count;
+
+ /* Go hunt up a function and fix its line info if needed. */
+ stabp = stabcontents + irel->r_offset - 8;
+
+ /* Go pullout the stab entry. */
+ strx = bfd_h_get_32 (abfd, stabp + STRDXOFF);
+ type = bfd_h_get_8 (abfd, stabp + TYPEOFF);
+ other = bfd_h_get_8 (abfd, stabp + OTHEROFF);
+ desc = bfd_h_get_16 (abfd, stabp + DESCOFF);
+ value = bfd_h_get_32 (abfd, stabp + VALOFF);
+
+ name = bfd_get_stab_name (type);
+
+ if (strcmp (name, "FUN") == 0)
+ {
+ int function_adjusted = 0;
+
+ if (symval > (baseaddr + addr))
+ /* Not in this function. */
+ continue;
+
+ /* Hey we got a function hit. */
+ stabp += STABSIZE;
+ for (;stabp < stabend; stabp += STABSIZE)
+ {
+ /* Go pullout the stab entry. */
+ strx = bfd_h_get_32 (abfd, stabp + STRDXOFF);
+ type = bfd_h_get_8 (abfd, stabp + TYPEOFF);
+ other = bfd_h_get_8 (abfd, stabp + OTHEROFF);
+ desc = bfd_h_get_16 (abfd, stabp + DESCOFF);
+ value = bfd_h_get_32 (abfd, stabp + VALOFF);
+ name = bfd_get_stab_name (type);
+
+ if (strcmp (name, "FUN") == 0)
+ {
+ /* Hit another function entry. */
+ if (function_adjusted)
+ {
+ /* Adjust the value. */
+ value += count;
+
+ /* We need to put it back. */
+ bfd_h_put_32 (abfd, value,stabp + VALOFF);
+ }
+
+ /* And then bale out. */
+ break;
+ }
+
+ if (strcmp (name, "SLINE") == 0)
+ {
+ /* Got a line entry. */
+ if ((baseaddr + addr) <= (symval + value))
+ {
+ /* Adjust the line entry. */
+ value += count;
+
+ /* We need to put it back. */
+ bfd_h_put_32 (abfd, value,stabp + VALOFF);
+ function_adjusted = 1;
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+
+ /* When adding an instruction back it is sometimes necessary to move any
+ global or local symbol that was referencing the first instruction of
+ the moved block to refer to the first instruction of the inserted block.
+
+ For example adding a PAGE instruction before a CALL or JMP requires
+ that any label on the CALL or JMP is moved to the PAGE insn. */
+ addr += noadj;
+
+ /* Adjust the local symbols defined in this section. */
+ shndx_hdr = &elf_tdata (abfd)->symtab_shndx_hdr;
+ sym_shndx = (Elf_External_Sym_Shndx *) shndx_hdr->contents;
+ esym = extsyms;
+ esymend = esym + symtab_hdr->sh_info;
+ for (; esym < esymend; esym++, sym_shndx = (sym_shndx ? sym_shndx + 1: NULL))
+ {
+ Elf_Internal_Sym isym;
+ Elf_External_Sym_Shndx dummy;
+
+ bfd_elf32_swap_symbol_in (abfd, esym, sym_shndx, &isym);
+
+ if (isym.st_shndx == shndx)
+ {
+ if (addr <= isym.st_value && isym.st_value < endaddr)
+ {
+ isym.st_value += count;
+ bfd_elf32_swap_symbol_out (abfd, &isym, esym, &dummy);
+ }
+ }
+ }
+
+ /* Now adjust the global symbols defined in this section. */
+ shndx_hdr = &elf_tdata (abfd)->symtab_shndx_hdr;
+ sym_shndx = (Elf_External_Sym_Shndx *) shndx_hdr->contents;
+ esym = extsyms + symtab_hdr->sh_info;
+ esymend = extsyms + (symtab_hdr->sh_size / sizeof (Elf32_External_Sym));
+ for (index = 0; esym < esymend;
+ esym++, index++, sym_shndx = (sym_shndx ? sym_shndx + 1: NULL))
+ {
+ Elf_Internal_Sym isym;
+ struct elf_link_hash_entry *sym_hash;
+
+ bfd_elf32_swap_symbol_in (abfd, esym, sym_shndx, &isym);
+ sym_hash = elf_sym_hashes (abfd)[index];
+
+ if (isym.st_shndx == shndx
+ && (sym_hash->root.type == bfd_link_hash_defined
+ || sym_hash->root.type == bfd_link_hash_defweak)
+ && sym_hash->root.u.def.section == sec)
+ {
+ if (addr <= sym_hash->root.u.def.value
+ && sym_hash->root.u.def.value < endaddr)
+ {
+ Elf_External_Sym_Shndx dummy;
+
+ sym_hash->root.u.def.value += count;
+ bfd_elf32_swap_symbol_out (abfd, &isym, esym, &dummy);
+ }
+ }
+ }
+
+ return;
+}
+
+static boolean
+add_page_insn (abfd, sec, irel, misc)
+ bfd *abfd;
+ asection *sec;
+ Elf_Internal_Rela *irel;
+ struct misc *misc;
+{
+ /* Note that we've changed the relocs, section contents, etc. */
+ elf_section_data (sec)->relocs = misc->irelbase;
+ misc->free_relocs = NULL;
+
+ elf_section_data (sec)->this_hdr.contents = misc->contents;
+ misc->free_contents = NULL;
+
+ misc->symtab_hdr->contents = (bfd_byte *) misc->extsyms;
+ misc->free_extsyms = NULL;
+
+ /* Add the PAGE insn. */
+ if (! ip2k_elf_relax_add_bytes (abfd, sec, irel->r_offset,
+ page_opcode,
+ sizeof (page_opcode),
+ sizeof (page_opcode)))
+ return false;
+ else
+ {
+ Elf32_Internal_Rela * jrel = irel - 1;
+
+ /* Add relocation for PAGE insn added. */
+ if (ELF32_R_TYPE (jrel->r_info) != R_IP2K_NONE)
+ {
+ bfd_byte code0, code1;
+ char *msg = NULL;
+
+ /* Get the opcode. */
+ code0 = bfd_get_8 (abfd, misc->contents + irel->r_offset);
+ code1 = bfd_get_8 (abfd, misc->contents + irel->r_offset + 1);
+
+ if (IS_JMP_OPCODE (code0, code1))
+ msg = "\tJMP instruction missing a preceeding PAGE instruction in %s\n\n";
+
+ else if (IS_CALL_OPCODE (code0, code1))
+ msg = "\tCALL instruction missing a preceeding PAGE instruction in %s\n\n";
+
+ if (msg)
+ {
+ fprintf (stderr, "\n\t *** LINKER RELAXATION failure ***\n");
+ fprintf (stderr, msg, sec->owner->filename);
+ }
+
+ return false;
+ }
+
+ jrel->r_addend = irel->r_addend;
+ jrel->r_offset = irel->r_offset - sizeof (page_opcode);
+ jrel->r_info = ELF32_R_INFO (ELF32_R_SYM (irel->r_info),
+ R_IP2K_PAGE3);
+ }
+
+ return true;
+}
+
+/* Insert bytes into a section while relaxing. */
+
+static boolean
+ip2k_elf_relax_add_bytes (abfd, sec, addr, bytes, count, noadj)
+ bfd *abfd;
+ asection *sec;
+ bfd_vma addr;
+ const bfd_byte *bytes;
+ int count;
+ int noadj;
+{
+ bfd_byte *contents = elf_section_data (sec)->this_hdr.contents;
+ bfd_vma endaddr = sec->_cooked_size;
+
+ /* Make room to insert the bytes. */
+ memmove (contents + addr + count, contents + addr, endaddr - addr);
+
+ /* Insert the bytes into the section. */
+ memcpy (contents + addr, bytes, count);
+
+ sec->_cooked_size += count;
+
+ adjust_all_relocations (abfd, sec, addr, endaddr, count, noadj);
+ return true;
+}
+
+/* Delete some bytes from a section while relaxing. */
+
+static boolean
+ip2k_elf_relax_delete_bytes (abfd, sec, addr, count)
+ bfd *abfd;
+ asection *sec;
+ bfd_vma addr;
+ int count;
+{
+ bfd_byte *contents = elf_section_data (sec)->this_hdr.contents;
+ bfd_vma endaddr = sec->_cooked_size;
+
+ /* Actually delete the bytes. */
+ memmove (contents + addr, contents + addr + count,
+ endaddr - addr - count);
+
+ sec->_cooked_size -= count;
+
+ adjust_all_relocations (abfd, sec, addr + count, endaddr, -count, 0);
+ return true;
+}
+
+/* -------------------------------------------------------------------- */
+
+/* XXX: The following code is the result of a cut&paste. This unfortunate
+ practice is very widespread in the various target back-end files. */
+
+/* Set the howto pointer for a IP2K ELF reloc. */
+
+static void
+ip2k_info_to_howto_rela (abfd, cache_ptr, dst)
+ bfd * abfd ATTRIBUTE_UNUSED;
+ arelent * cache_ptr;
+ Elf32_Internal_Rela * dst;
+{
+ unsigned int r_type;
+
+ r_type = ELF32_R_TYPE (dst->r_info);
+ switch (r_type)
+ {
+ default:
+ cache_ptr->howto = & ip2k_elf_howto_table [r_type];
+ break;
+ }
+}
+
+/* Perform a single relocation.
+ By default we use the standard BFD routines. */
+
+static bfd_reloc_status_type
+ip2k_final_link_relocate (howto, input_bfd, input_section, contents, rel,
+ relocation)
+ reloc_howto_type * howto;
+ bfd * input_bfd;
+ asection * input_section;
+ bfd_byte * contents;
+ Elf_Internal_Rela * rel;
+ bfd_vma relocation;
+{
+ bfd_reloc_status_type r = bfd_reloc_ok;
+
+ switch (howto->type)
+ {
+ /* Handle data space relocations. */
+ case R_IP2K_FR9:
+ case R_IP2K_BANK:
+ if ((relocation & IP2K_DATA_MASK) == IP2K_DATA_VALUE)
+ relocation &= ~IP2K_DATA_MASK;
+ else
+ r = bfd_reloc_notsupported;
+ break;
+
+ case R_IP2K_LO8DATA:
+ case R_IP2K_HI8DATA:
+ case R_IP2K_EX8DATA:
+ break;
+
+ /* Handle insn space relocations. */
+ case R_IP2K_ADDR16CJP:
+ case R_IP2K_PAGE3:
+ case R_IP2K_LO8INSN:
+ case R_IP2K_HI8INSN:
+ case R_IP2K_PC_SKIP:
+ if ((relocation & IP2K_INSN_MASK) == IP2K_INSN_VALUE)
+ relocation &= ~IP2K_INSN_MASK;
+ else
+ r = bfd_reloc_notsupported;
+ break;
+
+ case R_IP2K_16:
+ /* If this is a relocation involving a TEXT
+ symbol, reduce it to a word address. */
+ if ((relocation & IP2K_INSN_MASK) == IP2K_INSN_VALUE)
+ howto = &ip2k_elf_howto_table[ (int) R_IP2K_TEXT];
+ break;
+
+ /* Pass others through. */
+ default:
+ break;
+ }
+
+ /* Only install relocation if above tests did not disqualify it. */
+ if (r == bfd_reloc_ok)
+ r = _bfd_final_link_relocate (howto, input_bfd, input_section,
+ contents, rel->r_offset,
+ relocation, rel->r_addend);
+
+ return r;
+}
+
+/* Relocate a IP2K ELF section.
+ There is some attempt to make this function usable for many architectures,
+ both USE_REL and USE_RELA ['twould be nice if such a critter existed],
+ if only to serve as a learning tool.
+
+ The RELOCATE_SECTION function is called by the new ELF backend linker
+ to handle the relocations for a section.
+
+ The relocs are always passed as Rela structures; if the section
+ actually uses Rel structures, the r_addend field will always be
+ zero.
+
+ This function is responsible for adjusting the section contents as
+ necessary, and (if using Rela relocs and generating a relocateable
+ output file) adjusting the reloc addend as necessary.
+
+ This function does not have to worry about setting the reloc
+ address or the reloc symbol index.
+
+ LOCAL_SYMS is a pointer to the swapped in local symbols.
+
+ LOCAL_SECTIONS is an array giving the section in the input file
+ corresponding to the st_shndx field of each local symbol.
+
+ The global hash table entry for the global symbols can be found
+ via elf_sym_hashes (input_bfd).
+
+ When generating relocateable output, this function must handle
+ STB_LOCAL/STT_SECTION symbols specially. The output symbol is
+ going to be the section symbol corresponding to the output
+ section, which means that the addend must be adjusted
+ accordingly. */
+
+static boolean
+ip2k_elf_relocate_section (output_bfd, info, input_bfd, input_section,
+ contents, relocs, local_syms, local_sections)
+ bfd * output_bfd ATTRIBUTE_UNUSED;
+ struct bfd_link_info * info;
+ bfd * input_bfd;
+ asection * input_section;
+ bfd_byte * contents;
+ Elf_Internal_Rela * relocs;
+ Elf_Internal_Sym * local_syms;
+ asection ** local_sections;
+{
+ Elf_Internal_Shdr * symtab_hdr;
+ struct elf_link_hash_entry ** sym_hashes;
+ Elf_Internal_Rela * rel;
+ Elf_Internal_Rela * relend;
+
+ symtab_hdr = & elf_tdata (input_bfd)->symtab_hdr;
+ sym_hashes = elf_sym_hashes (input_bfd);
+ relend = relocs + input_section->reloc_count;
+
+ for (rel = relocs; rel < relend; rel ++)
+ {
+ reloc_howto_type * howto;
+ unsigned long r_symndx;
+ Elf_Internal_Sym * sym;
+ asection * sec;
+ struct elf_link_hash_entry * h;
+ bfd_vma relocation;
+ bfd_reloc_status_type r;
+ const char * name = NULL;
+ int r_type;
+
+ r_type = ELF32_R_TYPE (rel->r_info);
+
+ r_symndx = ELF32_R_SYM (rel->r_info);
+
+ if (info->relocateable)
+ {
+ /* This is a relocateable link. We don't have to change
+ anything, unless the reloc is against a section symbol,
+ in which case we have to adjust according to where the
+ section symbol winds up in the output section. */
+ if (r_symndx < symtab_hdr->sh_info)
+ {
+ sym = local_syms + r_symndx;
+
+ if (ELF_ST_TYPE (sym->st_info) == STT_SECTION)
+ {
+ sec = local_sections [r_symndx];
+ rel->r_addend += sec->output_offset + sym->st_value;
+ }
+ }
+
+ continue;
+ }
+
+ /* This is a final link. */
+ howto = ip2k_elf_howto_table + ELF32_R_TYPE (rel->r_info);
+ h = NULL;
+ sym = NULL;
+ sec = NULL;
+
+ if (r_symndx < symtab_hdr->sh_info)
+ {
+ sym = local_syms + r_symndx;
+ sec = local_sections [r_symndx];
+ relocation = BASEADDR (sec) + sym->st_value;
+
+ name = bfd_elf_string_from_elf_section
+ (input_bfd, symtab_hdr->sh_link, sym->st_name);
+ name = (name == NULL) ? bfd_section_name (input_bfd, sec) : name;
+ }
+ else
+ {
+ h = sym_hashes [r_symndx - symtab_hdr->sh_info];
+
+ while (h->root.type == bfd_link_hash_indirect
+ || h->root.type == bfd_link_hash_warning)
+ h = (struct elf_link_hash_entry *) h->root.u.i.link;
+
+ name = h->root.root.string;
+
+ if (h->root.type == bfd_link_hash_defined
+ || h->root.type == bfd_link_hash_defweak)
+ {
+ sec = h->root.u.def.section;
+ relocation = h->root.u.def.value + BASEADDR (sec);
+ }
+ else if (h->root.type == bfd_link_hash_undefweak)
+ {
+ relocation = 0;
+ }
+ else
+ {
+ if (! ((*info->callbacks->undefined_symbol)
+ (info, h->root.root.string, input_bfd,
+ input_section, rel->r_offset,
+ (! info->shared || info->no_undefined))))
+ return false;
+ relocation = 0;
+ }
+ }
+
+ /* Finally, the sole IP2K-specific part. */
+ r = ip2k_final_link_relocate (howto, input_bfd, input_section,
+ contents, rel, relocation);
+
+ if (r != bfd_reloc_ok)
+ {
+ const char * msg = (const char *) NULL;
+
+ switch (r)
+ {
+ case bfd_reloc_overflow:
+ r = info->callbacks->reloc_overflow
+ (info, name, howto->name, (bfd_vma) 0,
+ input_bfd, input_section, rel->r_offset);
+ break;
+
+ case bfd_reloc_undefined:
+ r = info->callbacks->undefined_symbol
+ (info, name, input_bfd, input_section, rel->r_offset, true);
+ break;
+
+ case bfd_reloc_outofrange:
+ msg = _("internal error: out of range error");
+ break;
+
+ /* This is how ip2k_final_link_relocate tells us of a non-kosher
+ reference between insn & data address spaces. */
+ case bfd_reloc_notsupported:
+ if (sym != NULL) /* Only if it's not an unresolved symbol. */
+ msg = _("unsupported relocation between data/insn address spaces");
+ break;
+
+ case bfd_reloc_dangerous:
+ msg = _("internal error: dangerous relocation");
+ break;
+
+ default:
+ msg = _("internal error: unknown error");
+ break;
+ }
+
+ if (msg)
+ r = info->callbacks->warning
+ (info, msg, name, input_bfd, input_section, rel->r_offset);
+
+ if (! r)
+ return false;
+ }
+ }
+
+ return true;
+}
+
+static asection *
+ip2k_elf_gc_mark_hook (sec, info, rel, h, sym)
+ asection *sec;
+ struct bfd_link_info *info ATTRIBUTE_UNUSED;
+ Elf_Internal_Rela *rel;
+ struct elf_link_hash_entry *h;
+ Elf_Internal_Sym *sym;
+{
+ if (h != NULL)
+ {
+ switch (ELF32_R_TYPE (rel->r_info))
+ {
+#if 0
+ case R_IP2K_GNU_VTINHERIT:
+ case R_IP2K_GNU_VTENTRY:
+ break;
+#endif
+
+ default:
+ switch (h->root.type)
+ {
+ case bfd_link_hash_defined:
+ case bfd_link_hash_defweak:
+ return h->root.u.def.section;
+
+ case bfd_link_hash_common:
+ return h->root.u.c.p->section;
+
+ default:
+ break;
+ }
+ }
+ }
+ else
+ {
+ if (!(elf_bad_symtab (sec->owner)
+ && ELF_ST_BIND (sym->st_info) != STB_LOCAL)
+ && ! ((sym->st_shndx <= 0 || sym->st_shndx >= SHN_LORESERVE)
+ && sym->st_shndx != SHN_COMMON))
+ {
+ return bfd_section_from_elf_index (sec->owner, sym->st_shndx);
+ }
+ }
+ return NULL;
+}
+
+static boolean
+ip2k_elf_gc_sweep_hook (abfd, info, sec, relocs)
+ bfd *abfd ATTRIBUTE_UNUSED;
+ struct bfd_link_info *info ATTRIBUTE_UNUSED;
+ asection *sec ATTRIBUTE_UNUSED;
+ const Elf_Internal_Rela *relocs ATTRIBUTE_UNUSED;
+{
+ /* we don't use got and plt entries for ip2k */
+ return true;
+}
+
+
+/* -------------------------------------------------------------------- */
+
+
+#define TARGET_BIG_SYM bfd_elf32_ip2k_vec
+#define TARGET_BIG_NAME "elf32-ip2k"
+
+#define ELF_ARCH bfd_arch_ip2k
+#define ELF_MACHINE_CODE EM_IP2K
+#define ELF_MAXPAGESIZE 1 /* No pages on the IP2K */
+
+#undef USE_REL
+#define USE_RELA
+
+#define elf_info_to_howto_rel NULL
+#define elf_info_to_howto ip2k_info_to_howto_rela
+
+#define elf_backend_can_gc_sections 1
+#define elf_backend_gc_mark_hook ip2k_elf_gc_mark_hook
+#define elf_backend_gc_sweep_hook ip2k_elf_gc_sweep_hook
+
+#define elf_backend_relocate_section ip2k_elf_relocate_section
+
+#define elf_symbol_leading_char '_'
+#define bfd_elf32_bfd_reloc_type_lookup ip2k_reloc_type_lookup
+#define bfd_elf32_bfd_relax_section ip2k_elf_relax_section
+
+
+#include "elf32-target.h"
+
--- /dev/null
+/* BFD back-end for BSD and Ultrix/VAX (1K page size) a.out-ish binaries.
+ Copyright 2002 Free Software Foundation, Inc.
+
+This file is part of BFD, the Binary File Descriptor library.
+
+This program is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2 of the License, or
+(at your option) any later version.
+
+This program is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with this program; if not, write to the Free Software
+Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
+
+#define N_HEADER_IN_TEXT(x) 0
+#define BYTES_IN_WORD 4
+#define ENTRY_CAN_BE_ZERO
+#define N_SHARED_LIB(x) 0 /* Avoids warning */
+#define TEXT_START_ADDR 0
+#define TARGET_PAGE_SIZE 1024
+#define SEGMENT_SIZE TARGET_PAGE_SIZE
+#define DEFAULT_ARCH bfd_arch_vax
+
+/* Do not "beautify" the CONCAT* macro args. Traditional C will not remove whitespace added here, and thus will fail to concatenate the tokens. */
+#define MY(OP) CONCAT2 (vaxbsd_,OP)
+
+#define TARGETNAME "a.out-vax-bsd"
+
+#include "bfd.h"
+#include "sysdep.h"
+#include "libbfd.h"
+#include "libaout.h"
+
+#include "aout-target.h"
--- /dev/null
+/* Low level interface for debugging AIX 4.3+ pthreads.
+
+ Copyright 1999, 2000, 2002 Free Software Foundation, Inc.
+ Written by Nick Duffek <nsd@redhat.com>.
+
+ This file is part of GDB.
+
+ This program is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 2 of the License, or
+ (at your option) any later version.
+
+ This program is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program; if not, write to the Free Software
+ Foundation, Inc., 59 Temple Place - Suite 330,
+ Boston, MA 02111-1307, USA. */
+
+
+/* This module uses the libpthdebug.a library provided by AIX 4.3+ for
+ debugging pthread applications.
+
+ Some name prefix conventions:
+ pthdb_ provided by libpthdebug.a
+ pdc_ callbacks that this module provides to libpthdebug.a
+ pd_ variables or functions interfacing with libpthdebug.a
+
+ libpthdebug peculiarities:
+
+ - pthdb_ptid_pthread() is prototyped in <sys/pthdebug.h>, but
+ it's not documented, and after several calls it stops working
+ and causes other libpthdebug functions to fail.
+
+ - pthdb_tid_pthread() doesn't always work after
+ pthdb_session_update(), but it does work after cycling through
+ all threads using pthdb_pthread().
+
+ */
+
+#include "defs.h"
+#include "gdb_assert.h"
+#include "gdbthread.h"
+#include "target.h"
+#include "inferior.h"
+#include "regcache.h"
+#include "gdbcmd.h"
+
+#if 0
+#include "coff/internal.h" /* for libcoff.h */
+#include "bfd/libcoff.h" /* for xcoff_data */
+#endif
+
+#include <procinfo.h>
+#include <sys/types.h>
+#include <sys/ptrace.h>
+#include <sys/reg.h>
+#if 0
+#include <pthread.h>
+#endif
+#include <sched.h>
+#include <sys/pthdebug.h>
+
+/* Whether to emit debugging output. */
+static int debug_aix_thread;
+
+/* In AIX 5.1, functions use pthdb_tid_t instead of tid_t. */
+#ifndef PTHDB_VERSION_3
+#define pthdb_tid_t tid_t
+#endif
+
+/* Return whether to treat PID as a debuggable thread id. */
+
+#define PD_TID(ptid) (pd_active && ptid_get_tid (ptid) != 0)
+
+/* Build a thread ptid. */
+#define BUILD_THREAD(TID, PID) ptid_build (PID, 0, TID)
+
+/* Build and lwp ptid. */
+#define BUILD_LWP(LWP, PID) MERGEPID (PID, LWP)
+
+/* pthdb_user_t value that we pass to pthdb functions. 0 causes
+ PTHDB_BAD_USER errors, so use 1. */
+
+#define PD_USER 1
+
+/* Success and failure values returned by pthdb callbacks. */
+
+#define PDC_SUCCESS PTHDB_SUCCESS
+#define PDC_FAILURE PTHDB_CALLBACK
+
+/* Private data attached to each element in GDB's thread list. */
+
+struct private_thread_info {
+ pthdb_pthread_t pdtid; /* thread's libpthdebug id */
+ pthdb_tid_t tid; /* kernel thread id */
+};
+
+/* Information about a thread of which libpthdebug is aware. */
+
+struct pd_thread {
+ pthdb_pthread_t pdtid;
+ pthread_t pthid;
+ pthdb_tid_t tid;
+};
+
+/* This module's target-specific operations, active while pd_able is true. */
+
+static struct target_ops ops;
+
+/* Copy of the target over which ops is pushed.
+ This is more convenient than a pointer to child_ops or core_ops,
+ because they lack current_target's default callbacks. */
+
+static struct target_ops base_ops;
+
+/* Address of the function that libpthread will call when libpthdebug
+ is ready to be initialized. */
+
+static CORE_ADDR pd_brk_addr;
+
+/* Whether the current application is debuggable by pthdb. */
+
+static int pd_able = 0;
+
+/* Whether a threaded application is being debugged. */
+
+static int pd_active = 0;
+
+/* Whether the current architecture is 64-bit.
+ Only valid when pd_able is true. */
+
+static int arch64;
+
+/* Saved pointer to previous owner of target_new_objfile_hook. */
+
+static void (*target_new_objfile_chain)(struct objfile *);
+
+/* Forward declarations for pthdb callbacks. */
+
+static int pdc_symbol_addrs (pthdb_user_t, pthdb_symbol_t *, int);
+static int pdc_read_data (pthdb_user_t, void *, pthdb_addr_t, size_t);
+static int pdc_write_data (pthdb_user_t, void *, pthdb_addr_t, size_t);
+static int pdc_read_regs (pthdb_user_t user, pthdb_tid_t tid,
+ unsigned long long flags,
+ pthdb_context_t *context);
+static int pdc_write_regs (pthdb_user_t user, pthdb_tid_t tid,
+ unsigned long long flags,
+ pthdb_context_t *context);
+static int pdc_alloc (pthdb_user_t, size_t, void **);
+static int pdc_realloc (pthdb_user_t, void *, size_t, void **);
+static int pdc_dealloc (pthdb_user_t, void *);
+
+/* pthdb callbacks. */
+
+static pthdb_callbacks_t pd_callbacks = {
+ pdc_symbol_addrs,
+ pdc_read_data,
+ pdc_write_data,
+ pdc_read_regs,
+ pdc_write_regs,
+ pdc_alloc,
+ pdc_realloc,
+ pdc_dealloc,
+ NULL
+};
+
+/* Current pthdb session. */
+
+static pthdb_session_t pd_session;
+
+/* Return a printable representation of pthdebug function return
+ STATUS. */
+
+static char *
+pd_status2str (int status)
+{
+ switch (status)
+ {
+ case PTHDB_SUCCESS: return "SUCCESS";
+ case PTHDB_NOSYS: return "NOSYS";
+ case PTHDB_NOTSUP: return "NOTSUP";
+ case PTHDB_BAD_VERSION: return "BAD_VERSION";
+ case PTHDB_BAD_USER: return "BAD_USER";
+ case PTHDB_BAD_SESSION: return "BAD_SESSION";
+ case PTHDB_BAD_MODE: return "BAD_MODE";
+ case PTHDB_BAD_FLAGS: return "BAD_FLAGS";
+ case PTHDB_BAD_CALLBACK: return "BAD_CALLBACK";
+ case PTHDB_BAD_POINTER: return "BAD_POINTER";
+ case PTHDB_BAD_CMD: return "BAD_CMD";
+ case PTHDB_BAD_PTHREAD: return "BAD_PTHREAD";
+ case PTHDB_BAD_ATTR: return "BAD_ATTR";
+ case PTHDB_BAD_MUTEX: return "BAD_MUTEX";
+ case PTHDB_BAD_MUTEXATTR: return "BAD_MUTEXATTR";
+ case PTHDB_BAD_COND: return "BAD_COND";
+ case PTHDB_BAD_CONDATTR: return "BAD_CONDATTR";
+ case PTHDB_BAD_RWLOCK: return "BAD_RWLOCK";
+ case PTHDB_BAD_RWLOCKATTR: return "BAD_RWLOCKATTR";
+ case PTHDB_BAD_KEY: return "BAD_KEY";
+ case PTHDB_BAD_PTID: return "BAD_PTID";
+ case PTHDB_BAD_TID: return "BAD_TID";
+ case PTHDB_CALLBACK: return "CALLBACK";
+ case PTHDB_CONTEXT: return "CONTEXT";
+ case PTHDB_HELD: return "HELD";
+ case PTHDB_NOT_HELD: return "NOT_HELD";
+ case PTHDB_MEMORY: return "MEMORY";
+ case PTHDB_NOT_PTHREADED: return "NOT_PTHREADED";
+ case PTHDB_SYMBOL: return "SYMBOL";
+ case PTHDB_NOT_AVAIL: return "NOT_AVAIL";
+ case PTHDB_INTERNAL: return "INTERNAL";
+ default: return "UNKNOWN";
+ }
+}
+
+/* A call to ptrace(REQ, ID, ...) just returned RET. Check for
+ exceptional conditions and either return nonlocally or else return
+ 1 for success and 0 for failure. */
+
+static int
+ptrace_check (int req, int id, int ret)
+{
+ if (ret == 0 && !errno)
+ return 1;
+
+ /* According to ptrace(2), ptrace may fail with EPERM if "the
+ Identifier parameter corresponds to a kernel thread which is
+ stopped in kernel mode and whose computational state cannot be
+ read or written." This happens quite often with register reads. */
+
+ switch (req)
+ {
+ case PTT_READ_GPRS:
+ case PTT_READ_FPRS:
+ case PTT_READ_SPRS:
+ if (ret == -1 && errno == EPERM)
+ {
+ if (debug_aix_thread)
+ fprintf_unfiltered (gdb_stdlog,
+ "ptrace (%d, %d) = %d (errno = %d)",
+ req, id, ret, errno);
+ return ret == -1 ? 0 : 1;
+ }
+ break;
+ }
+ error ("aix-thread: ptrace (%d, %d) returned %d (errno = %d %s)",
+ req, id, ret, errno, safe_strerror (errno));
+ return 0; /* Not reached. */
+}
+
+/* Call ptracex (REQ, ID, ADDR, DATA, BUF). Return success. */
+
+static int
+ptrace64aix (int req, int id, long long addr, int data, int *buf)
+{
+ errno = 0;
+ return ptrace_check (req, id, ptracex (req, id, addr, data, buf));
+}
+
+/* Call ptrace (REQ, ID, ADDR, DATA, BUF). Return success. */
+
+static int
+ptrace32 (int req, int id, int *addr, int data, int *buf)
+{
+ errno = 0;
+ return ptrace_check (req, id,
+ ptrace (req, id, (int *)addr, data, buf));
+}
+
+/* If *PIDP is a composite process/thread id, convert it to a
+ process id. */
+
+static void
+pid_to_prc (ptid_t *ptidp)
+{
+ ptid_t ptid;
+
+ ptid = *ptidp;
+ if (PD_TID (ptid))
+ *ptidp = pid_to_ptid (PIDGET (ptid));
+}
+
+/* pthdb callback: for <i> from 0 to COUNT, set SYMBOLS[<i>].addr to
+ the address of SYMBOLS[<i>].name. */
+
+static int
+pdc_symbol_addrs (pthdb_user_t user, pthdb_symbol_t *symbols, int count)
+{
+ struct minimal_symbol *ms;
+ int i;
+ char *name;
+
+ if (debug_aix_thread)
+ fprintf_unfiltered (gdb_stdlog,
+ "pdc_symbol_addrs (user = %ld, symbols = 0x%lx, count = %d)",
+ user, (long) symbols, count);
+
+ for (i = 0; i < count; i++)
+ {
+ name = symbols[i].name;
+ if (debug_aix_thread)
+ fprintf_unfiltered (gdb_stdlog,
+ " symbols[%d].name = \"%s\"", i, name);
+
+ if (!*name)
+ symbols[i].addr = 0;
+ else
+ {
+ if (!(ms = lookup_minimal_symbol (name, NULL, NULL)))
+ {
+ if (debug_aix_thread)
+ fprintf_unfiltered (gdb_stdlog, " returning PDC_FAILURE");
+ return PDC_FAILURE;
+ }
+ symbols[i].addr = SYMBOL_VALUE_ADDRESS (ms);
+ }
+ if (debug_aix_thread)
+ fprintf_unfiltered (gdb_stdlog, " symbols[%d].addr = 0x%llx",
+ i, symbols[i].addr);
+ }
+ if (debug_aix_thread)
+ fprintf_unfiltered (gdb_stdlog, " returning PDC_SUCCESS");
+ return PDC_SUCCESS;
+}
+
+/* Read registers call back function should be able to read the
+ context information of a debuggee kernel thread from an active
+ process or from a core file. The information should be formatted
+ in context64 form for both 32-bit and 64-bit process.
+ If successful return 0, else non-zero is returned. */
+
+static int
+pdc_read_regs (pthdb_user_t user,
+ pthdb_tid_t tid,
+ unsigned long long flags,
+ pthdb_context_t *context)
+{
+ /* This function doesn't appear to be used, so we could probably
+ just return 0 here. HOWEVER, if it is not defined, the OS will
+ complain and several thread debug functions will fail. In case
+ this is needed, I have implemented what I think it should do,
+ however this code is untested. */
+
+ uint64_t gprs64[32];
+ uint32_t gprs32[32];
+ double fprs[32];
+ struct ptxsprs sprs64;
+ struct ptsprs sprs32;
+
+ if (debug_aix_thread)
+ fprintf_unfiltered (gdb_stdlog, "pdc_read_regs tid=%d flags=%llx\n",
+ (int)tid, flags);
+
+ /* General-purpose registers. */
+ if (flags & PTHDB_FLAG_GPRS)
+ {
+ if (arch64)
+ {
+ if (!ptrace64aix (PTT_READ_GPRS, tid,
+ (unsigned long) gprs64, 0, NULL))
+ memset (gprs64, 0, sizeof (gprs64));
+ memcpy (context->gpr, gprs64, sizeof(gprs64));
+ }
+ else
+ {
+ if (!ptrace32 (PTT_READ_GPRS, tid, gprs32, 0, NULL))
+ memset (gprs32, 0, sizeof (gprs32));
+ memcpy (context->gpr, gprs32, sizeof(gprs32));
+ }
+ }
+
+ /* Floating-point registers. */
+ if (flags & PTHDB_FLAG_FPRS)
+ {
+ if (!ptrace32 (PTT_READ_FPRS, tid, (int *) fprs, 0, NULL))
+ memset (fprs, 0, sizeof (fprs));
+ memcpy (context->fpr, fprs, sizeof(fprs));
+ }
+
+ /* Special-purpose registers. */
+ if (flags & PTHDB_FLAG_SPRS)
+ {
+ if (arch64)
+ {
+ if (!ptrace64aix (PTT_READ_SPRS, tid,
+ (unsigned long) &sprs64, 0, NULL))
+ memset (&sprs64, 0, sizeof (sprs64));
+ memcpy (&context->msr, &sprs64, sizeof(sprs64));
+ }
+ else
+ {
+ if (!ptrace32 (PTT_READ_SPRS, tid, (int *) &sprs32, 0, NULL))
+ memset (&sprs32, 0, sizeof (sprs32));
+ memcpy (&context->msr, &sprs32, sizeof(sprs32));
+ }
+ }
+ return 0;
+}
+
+/* Write register function should be able to write requested context
+ information to specified debuggee's kernel thread id.
+ If successful return 0, else non-zero is returned. */
+
+static int
+pdc_write_regs (pthdb_user_t user,
+ pthdb_tid_t tid,
+ unsigned long long flags,
+ pthdb_context_t *context)
+{
+ /* This function doesn't appear to be used, so we could probably
+ just return 0 here. HOWEVER, if it is not defined, the OS will
+ complain and several thread debug functions will fail. In case
+ this is needed, I have implemented what I think it should do,
+ however this code is untested. */
+
+ if (debug_aix_thread)
+ fprintf_unfiltered (gdb_stdlog, "pdc_write_regs tid=%d flags=%llx\n",
+ (int)tid, flags);
+
+ /* General-purpose registers. */
+ if (flags & PTHDB_FLAG_GPRS)
+ {
+ if (arch64)
+ ptrace64aix (PTT_WRITE_GPRS, tid,
+ (unsigned long)context->gpr, 0, NULL);
+ else
+ ptrace32 (PTT_WRITE_GPRS, tid, (int *)context->gpr, 0, NULL);
+ }
+
+ /* Floating-point registers. */
+ if (flags & PTHDB_FLAG_FPRS)
+ {
+ ptrace32 (PTT_WRITE_FPRS, tid, (int *)context->fpr, 0, NULL);
+ }
+
+ /* Special-purpose registers. */
+ if (flags & PTHDB_FLAG_SPRS)
+ {
+ if (arch64)
+ {
+ ptrace64aix (PTT_WRITE_SPRS, tid,
+ (unsigned long) &context->msr, 0, NULL);
+ }
+ else
+ {
+ ptrace32 (PTT_WRITE_SPRS, tid, (int *)&context->msr, 0, NULL);
+ }
+ }
+ return 0;
+}
+
+/* pthdb callback: read LEN bytes from process ADDR into BUF. */
+
+static int
+pdc_read_data (pthdb_user_t user, void *buf,
+ pthdb_addr_t addr, size_t len)
+{
+ int status, ret;
+
+ if (debug_aix_thread)
+ fprintf_unfiltered (gdb_stdlog,
+ "pdc_read_data (user = %ld, buf = 0x%lx, addr = 0x%llx, len = %ld)",
+ user, (long) buf, addr, len);
+
+ status = target_read_memory (addr, buf, len);
+ ret = status == 0 ? PDC_SUCCESS : PDC_FAILURE;
+
+ if (debug_aix_thread)
+ fprintf_unfiltered (gdb_stdlog, " status=%d, returning %s",
+ status, pd_status2str (ret));
+ return ret;
+}
+
+/* pthdb callback: write LEN bytes from BUF to process ADDR. */
+
+static int
+pdc_write_data (pthdb_user_t user, void *buf,
+ pthdb_addr_t addr, size_t len)
+{
+ int status, ret;
+
+ if (debug_aix_thread)
+ fprintf_unfiltered (gdb_stdlog,
+ "pdc_write_data (user = %ld, buf = 0x%lx, addr = 0x%llx, len = %ld)",
+ user, (long) buf, addr, len);
+
+ status = target_write_memory (addr, buf, len);
+ ret = status == 0 ? PDC_SUCCESS : PDC_FAILURE;
+
+ if (debug_aix_thread)
+ fprintf_unfiltered (gdb_stdlog, " status=%d, returning %s", status,
+ pd_status2str (ret));
+ return ret;
+}
+
+/* pthdb callback: allocate a LEN-byte buffer and store a pointer to it
+ in BUFP. */
+
+static int
+pdc_alloc (pthdb_user_t user, size_t len, void **bufp)
+{
+ if (debug_aix_thread)
+ fprintf_unfiltered (gdb_stdlog,
+ "pdc_alloc (user = %ld, len = %ld, bufp = 0x%lx)",
+ user, len, (long) bufp);
+ *bufp = xmalloc (len);
+ if (debug_aix_thread)
+ fprintf_unfiltered (gdb_stdlog,
+ " malloc returned 0x%lx", (long) *bufp);
+
+ /* Note: xmalloc() can't return 0; therefore PDC_FAILURE will never
+ be returned. */
+
+ return *bufp ? PDC_SUCCESS : PDC_FAILURE;
+}
+
+/* pthdb callback: reallocate BUF, which was allocated by the alloc or
+ realloc callback, so that it contains LEN bytes, and store a
+ pointer to the result in BUFP. */
+
+static int
+pdc_realloc (pthdb_user_t user, void *buf, size_t len, void **bufp)
+{
+ if (debug_aix_thread)
+ fprintf_unfiltered (gdb_stdlog,
+ "pdc_realloc (user = %ld, buf = 0x%lx, len = %ld, bufp = 0x%lx)",
+ user, (long) buf, len, (long) bufp);
+ *bufp = xrealloc (buf, len);
+ if (debug_aix_thread)
+ fprintf_unfiltered (gdb_stdlog,
+ " realloc returned 0x%lx", (long) *bufp);
+ return *bufp ? PDC_SUCCESS : PDC_FAILURE;
+}
+
+/* pthdb callback: free BUF, which was allocated by the alloc or
+ realloc callback. */
+
+static int
+pdc_dealloc (pthdb_user_t user, void *buf)
+{
+ if (debug_aix_thread)
+ fprintf_unfiltered (gdb_stdlog,
+ "pdc_free (user = %ld, buf = 0x%lx)", user,
+ (long) buf);
+ xfree (buf);
+ return PDC_SUCCESS;
+}
+
+/* Return a printable representation of pthread STATE. */
+
+static char *
+state2str (pthdb_state_t state)
+{
+ switch (state)
+ {
+ case PST_IDLE: return "idle"; /* being created */
+ case PST_RUN: return "running"; /* running */
+ case PST_SLEEP: return "sleeping"; /* awaiting an event */
+ case PST_READY: return "ready"; /* runnable */
+ case PST_TERM: return "finished"; /* awaiting a join/detach */
+ default: return "unknown";
+ }
+}
+
+/* qsort() comparison function for sorting pd_thread structs by pthid. */
+
+static int
+pcmp (const void *p1v, const void *p2v)
+{
+ struct pd_thread *p1 = (struct pd_thread *) p1v;
+ struct pd_thread *p2 = (struct pd_thread *) p2v;
+ return p1->pthid < p2->pthid ? -1 : p1->pthid > p2->pthid;
+}
+
+/* iterate_over_threads() callback for counting GDB threads. */
+
+static int
+giter_count (struct thread_info *thread, void *countp)
+{
+ (*(int *) countp)++;
+ return 0;
+}
+
+/* iterate_over_threads() callback for accumulating GDB thread pids. */
+
+static int
+giter_accum (struct thread_info *thread, void *bufp)
+{
+ **(struct thread_info ***) bufp = thread;
+ (*(struct thread_info ***) bufp)++;
+ return 0;
+}
+
+/* ptid comparison function */
+
+static int
+ptid_cmp (ptid_t ptid1, ptid_t ptid2)
+{
+ int pid1, pid2;
+
+ if (ptid_get_pid (ptid1) < ptid_get_pid (ptid2))
+ return -1;
+ else if (ptid_get_pid (ptid1) > ptid_get_pid (ptid2))
+ return 1;
+ else if (ptid_get_tid (ptid1) < ptid_get_tid (ptid2))
+ return -1;
+ else if (ptid_get_tid (ptid1) > ptid_get_tid (ptid2))
+ return 1;
+ else if (ptid_get_lwp (ptid1) < ptid_get_lwp (ptid2))
+ return -1;
+ else if (ptid_get_lwp (ptid1) > ptid_get_lwp (ptid2))
+ return 1;
+ else
+ return 0;
+}
+
+/* qsort() comparison function for sorting thread_info structs by pid. */
+
+static int
+gcmp (const void *t1v, const void *t2v)
+{
+ struct thread_info *t1 = *(struct thread_info **) t1v;
+ struct thread_info *t2 = *(struct thread_info **) t2v;
+ return ptid_cmp (t1->ptid, t2->ptid);
+}
+
+/* Synchronize GDB's thread list with libpthdebug's.
+
+ There are some benefits of doing this every time the inferior stops:
+
+ - allows users to run thread-specific commands without needing to
+ run "info threads" first
+
+ - helps pthdb_tid_pthread() work properly (see "libpthdebug
+ peculiarities" at the top of this module)
+
+ - simplifies the demands placed on libpthdebug, which seems to
+ have difficulty with certain call patterns */
+
+static void
+sync_threadlists (void)
+{
+ int cmd, status, infpid;
+ int pcount, psize, pi, gcount, gi;
+ struct pd_thread *pbuf;
+ struct thread_info **gbuf, **g, *thread;
+ pthdb_pthread_t pdtid;
+ pthread_t pthid;
+ pthdb_tid_t tid;
+
+ /* Accumulate an array of libpthdebug threads sorted by pthread id. */
+
+ pcount = 0;
+ psize = 1;
+ pbuf = (struct pd_thread *) xmalloc (psize * sizeof *pbuf);
+
+ for (cmd = PTHDB_LIST_FIRST;; cmd = PTHDB_LIST_NEXT)
+ {
+ status = pthdb_pthread (pd_session, &pdtid, cmd);
+ if (status != PTHDB_SUCCESS || pdtid == PTHDB_INVALID_PTHREAD)
+ break;
+
+ status = pthdb_pthread_ptid (pd_session, pdtid, &pthid);
+ if (status != PTHDB_SUCCESS || pthid == PTHDB_INVALID_PTID)
+ continue;
+
+ if (pcount == psize)
+ {
+ psize *= 2;
+ pbuf = (struct pd_thread *) xrealloc (pbuf,
+ psize * sizeof *pbuf);
+ }
+ pbuf[pcount].pdtid = pdtid;
+ pbuf[pcount].pthid = pthid;
+ pcount++;
+ }
+
+ for (pi = 0; pi < pcount; pi++)
+ {
+ status = pthdb_pthread_tid (pd_session, pbuf[pi].pdtid, &tid);
+ if (status != PTHDB_SUCCESS)
+ tid = PTHDB_INVALID_TID;
+ pbuf[pi].tid = tid;
+ }
+
+ qsort (pbuf, pcount, sizeof *pbuf, pcmp);
+
+ /* Accumulate an array of GDB threads sorted by pid. */
+
+ gcount = 0;
+ iterate_over_threads (giter_count, &gcount);
+ g = gbuf = (struct thread_info **) xmalloc (gcount * sizeof *gbuf);
+ iterate_over_threads (giter_accum, &g);
+ qsort (gbuf, gcount, sizeof *gbuf, gcmp);
+
+ /* Apply differences between the two arrays to GDB's thread list. */
+
+ infpid = PIDGET (inferior_ptid);
+ for (pi = gi = 0; pi < pcount || gi < gcount;)
+ {
+ if (pi == pcount)
+ {
+ delete_thread (gbuf[gi]->ptid);
+ gi++;
+ }
+ else if (gi == gcount)
+ {
+ thread = add_thread (BUILD_THREAD (pbuf[pi].pthid, infpid));
+ thread->private = xmalloc (sizeof (struct private_thread_info));
+ thread->private->pdtid = pbuf[pi].pdtid;
+ thread->private->tid = pbuf[pi].tid;
+ pi++;
+ }
+ else
+ {
+ ptid_t pptid, gptid;
+ int cmp_result;
+
+ pptid = BUILD_THREAD (pbuf[pi].pthid, infpid);
+ gptid = gbuf[gi]->ptid;
+ pdtid = pbuf[pi].pdtid;
+ tid = pbuf[pi].tid;
+
+ cmp_result = ptid_cmp (pptid, gptid);
+
+ if (cmp_result == 0)
+ {
+ gbuf[gi]->private->pdtid = pdtid;
+ gbuf[gi]->private->tid = tid;
+ pi++;
+ gi++;
+ }
+ else if (cmp_result > 0)
+ {
+ delete_thread (gptid);
+ gi++;
+ }
+ else
+ {
+ thread = add_thread (pptid);
+ thread->private = xmalloc (sizeof (struct private_thread_info));
+ thread->private->pdtid = pdtid;
+ thread->private->tid = tid;
+ pi++;
+ }
+ }
+ }
+
+ xfree (pbuf);
+ xfree (gbuf);
+}
+
+/* Iterate_over_threads() callback for locating a thread whose kernel
+ thread just received a trap signal. */
+
+static int
+iter_trap (struct thread_info *thread, void *unused)
+{
+ struct thrdsinfo64 thrinf;
+ pthdb_tid_t tid;
+
+ /* getthrds(3) isn't prototyped in any AIX 4.3.3 #include file. */
+ extern int getthrds (pid_t, struct thrdsinfo64 *,
+ int, pthdb_tid_t *, int);
+
+ tid = thread->private->tid;
+ if (tid == PTHDB_INVALID_TID)
+ return 0;
+
+ if (getthrds (PIDGET (inferior_ptid), &thrinf,
+ sizeof (thrinf), &tid, 1) != 1)
+ return 0;
+
+ return thrinf.ti_cursig == SIGTRAP;
+}
+
+/* Synchronize libpthdebug's state with the inferior and with GDB,
+ generate a composite process/thread <pid> for the current thread,
+ set inferior_ptid to <pid> if SET_INFPID, and return <pid>. */
+
+static ptid_t
+pd_update (int set_infpid)
+{
+ int status;
+ ptid_t ptid;
+ struct thread_info *thread;
+
+ if (!pd_active)
+ return inferior_ptid;
+
+ status = pthdb_session_update (pd_session);
+ if (status != PTHDB_SUCCESS)
+ return inferior_ptid;
+
+ sync_threadlists ();
+
+ /* Define "current thread" as one that just received a trap signal. */
+
+ thread = iterate_over_threads (iter_trap, NULL);
+ if (!thread)
+ ptid = inferior_ptid;
+ else
+ {
+ ptid = thread->ptid;
+ if (set_infpid)
+ inferior_ptid = ptid;
+ }
+ return ptid;
+}
+
+/* Try to start debugging threads in the current process.
+ If successful and SET_INFPID, set inferior_ptid to reflect the
+ current thread. */
+
+static ptid_t
+pd_activate (int set_infpid)
+{
+ int status;
+
+ status = pthdb_session_init (PD_USER, arch64 ? PEM_64BIT : PEM_32BIT,
+ PTHDB_FLAG_REGS, &pd_callbacks,
+ &pd_session);
+ if (status != PTHDB_SUCCESS)
+ {
+ return inferior_ptid;
+ }
+ pd_active = 1;
+ return pd_update (set_infpid);
+}
+
+/* Undo the effects of pd_activate(). */
+
+static void
+pd_deactivate (void)
+{
+ if (!pd_active)
+ return;
+ pthdb_session_destroy (pd_session);
+
+ pid_to_prc (&inferior_ptid);
+ pd_active = 0;
+}
+
+/* An object file has just been loaded. Check whether the current
+ application is pthreaded, and if so, prepare for thread debugging. */
+
+static void
+pd_enable (void)
+{
+ int status;
+ char *stub_name;
+ struct minimal_symbol *ms;
+
+ /* Don't initialize twice. */
+ if (pd_able)
+ return;
+
+ /* Check application word size. */
+ arch64 = REGISTER_RAW_SIZE (0) == 8;
+
+ /* Check whether the application is pthreaded. */
+ stub_name = NULL;
+ status = pthdb_session_pthreaded (PD_USER, PTHDB_FLAG_REGS,
+ &pd_callbacks, &stub_name);
+ if ((status != PTHDB_SUCCESS &&
+ status != PTHDB_NOT_PTHREADED) || !stub_name)
+ return;
+
+ /* Set a breakpoint on the returned stub function. */
+ if (!(ms = lookup_minimal_symbol (stub_name, NULL, NULL)))
+ return;
+ pd_brk_addr = SYMBOL_VALUE_ADDRESS (ms);
+ if (!create_thread_event_breakpoint (pd_brk_addr))
+ return;
+
+ /* Prepare for thread debugging. */
+ base_ops = current_target;
+ push_target (&ops);
+ pd_able = 1;
+
+ /* If we're debugging a core file or an attached inferior, the
+ pthread library may already have been initialized, so try to
+ activate thread debugging. */
+ pd_activate (1);
+}
+
+/* Undo the effects of pd_enable(). */
+
+static void
+pd_disable (void)
+{
+ if (!pd_able)
+ return;
+ if (pd_active)
+ pd_deactivate ();
+ pd_able = 0;
+ unpush_target (&ops);
+}
+
+/* target_new_objfile_hook callback.
+
+ If OBJFILE is non-null, check whether a threaded application is
+ being debugged, and if so, prepare for thread debugging.
+
+ If OBJFILE is null, stop debugging threads. */
+
+static void
+new_objfile (struct objfile *objfile)
+{
+ if (objfile)
+ pd_enable ();
+ else
+ pd_disable ();
+
+ if (target_new_objfile_chain)
+ target_new_objfile_chain (objfile);
+}
+
+/* Attach to process specified by ARGS. */
+
+static void
+ops_attach (char *args, int from_tty)
+{
+ base_ops.to_attach (args, from_tty);
+ pd_activate (1);
+}
+
+/* Detach from the process attached to by ops_attach(). */
+
+static void
+ops_detach (char *args, int from_tty)
+{
+ pd_deactivate ();
+ base_ops.to_detach (args, from_tty);
+}
+
+/* Tell the inferior process to continue running thread PID if != -1
+ and all threads otherwise. */
+
+static void
+ops_resume (ptid_t ptid, int step, enum target_signal sig)
+{
+ struct thread_info *thread;
+ pthdb_tid_t tid[2];
+
+ if (!PD_TID (ptid))
+ {
+ struct cleanup *cleanup = save_inferior_ptid ();
+ inferior_ptid = pid_to_ptid (PIDGET (inferior_ptid));
+ base_ops.to_resume (ptid, step, sig);
+ do_cleanups (cleanup);
+ }
+ else
+ {
+ thread = find_thread_pid (ptid);
+ if (!thread)
+ error ("aix-thread resume: unknown pthread %ld",
+ TIDGET (ptid));
+
+ tid[0] = thread->private->tid;
+ if (tid[0] == PTHDB_INVALID_TID)
+ error ("aix-thread resume: no tid for pthread %ld",
+ TIDGET (ptid));
+ tid[1] = 0;
+
+ if (arch64)
+ ptrace64aix (PTT_CONTINUE, tid[0], 1,
+ target_signal_to_host (sig), (int *)tid);
+ else
+ ptrace32 (PTT_CONTINUE, tid[0], (int *) 1,
+ target_signal_to_host (sig), (int *)tid);
+ }
+}
+
+/* Wait for thread/process ID if != -1 or for any thread otherwise.
+ If an error occurs, return -1, else return the pid of the stopped
+ thread. */
+
+static ptid_t
+ops_wait (ptid_t ptid, struct target_waitstatus *status)
+{
+ struct cleanup *cleanup = save_inferior_ptid ();
+
+ pid_to_prc (&ptid);
+
+ inferior_ptid = pid_to_ptid (PIDGET (inferior_ptid));
+ ptid = base_ops.to_wait (ptid, status);
+ do_cleanups (cleanup);
+
+ if (PIDGET (ptid) == -1)
+ return pid_to_ptid (-1);
+
+ /* Check whether libpthdebug might be ready to be initialized. */
+ if (!pd_active && status->kind == TARGET_WAITKIND_STOPPED &&
+ status->value.sig == TARGET_SIGNAL_TRAP &&
+ read_pc_pid (ptid) - DECR_PC_AFTER_BREAK == pd_brk_addr)
+ return pd_activate (0);
+
+ return pd_update (0);
+}
+
+/* Record that the 64-bit general-purpose registers contain VALS. */
+
+static void
+supply_gprs64 (uint64_t *vals)
+{
+ int regno;
+
+ for (regno = 0; regno < 32; regno++)
+ supply_register (regno, (char *) (vals + regno));
+}
+
+/* Record that 32-bit register REGNO contains VAL. */
+
+static void
+supply_reg32 (int regno, uint32_t val)
+{
+ supply_register (regno, (char *) &val);
+}
+
+/* Record that the floating-point registers contain VALS. */
+
+static void
+supply_fprs (double *vals)
+{
+ int regno;
+
+ for (regno = 0; regno < 32; regno++)
+ supply_register (regno + FP0_REGNUM, (char *) (vals + regno));
+}
+
+/* Record that the special registers contain the specified 64-bit and
+ 32-bit values. */
+
+static void
+supply_sprs64 (uint64_t iar, uint64_t msr, uint32_t cr,
+ uint64_t lr, uint64_t ctr, uint32_t xer)
+{
+ int regno = FIRST_UISA_SP_REGNUM;
+
+ supply_register (regno, (char *) &iar);
+ supply_register (regno + 1, (char *) &msr);
+ supply_register (regno + 2, (char *) &cr);
+ supply_register (regno + 3, (char *) &lr);
+ supply_register (regno + 4, (char *) &ctr);
+ supply_register (regno + 5, (char *) &xer);
+}
+
+/* Record that the special registers contain the specified 32-bit
+ values. */
+
+static void
+supply_sprs32 (uint32_t iar, uint32_t msr, uint32_t cr,
+ uint32_t lr, uint32_t ctr, uint32_t xer)
+{
+ int regno = FIRST_UISA_SP_REGNUM;
+
+ supply_register (regno, (char *) &iar);
+ supply_register (regno + 1, (char *) &msr);
+ supply_register (regno + 2, (char *) &cr);
+ supply_register (regno + 3, (char *) &lr);
+ supply_register (regno + 4, (char *) &ctr);
+ supply_register (regno + 5, (char *) &xer);
+}
+
+/* Fetch all registers from pthread PDTID, which doesn't have a kernel
+ thread.
+
+ There's no way to query a single register from a non-kernel
+ pthread, so there's no need for a single-register version of this
+ function. */
+
+static void
+fetch_regs_lib (pthdb_pthread_t pdtid)
+{
+ int status, i;
+ pthdb_context_t ctx;
+
+ if (debug_aix_thread)
+ fprintf_unfiltered (gdb_stdlog, "fetch_regs_lib %lx\n", (long)pdtid);
+ status = pthdb_pthread_context (pd_session, pdtid, &ctx);
+ if (status != PTHDB_SUCCESS)
+ error ("aix-thread: fetch_registers: pthdb_pthread_context returned %s",
+ pd_status2str (status));
+
+ /* General-purpose registers. */
+
+ if (arch64)
+ supply_gprs64 (ctx.gpr);
+ else
+ for (i = 0; i < 32; i++)
+ supply_reg32 (i, ctx.gpr[i]);
+
+ /* Floating-point registers. */
+
+ supply_fprs (ctx.fpr);
+
+ /* Special registers. */
+
+ if (arch64)
+ supply_sprs64 (ctx.iar, ctx.msr, ctx.cr, ctx.lr, ctx.ctr, ctx.xer);
+ else
+ supply_sprs32 (ctx.iar, ctx.msr, ctx.cr, ctx.lr, ctx.ctr, ctx.xer);
+}
+
+/* Fetch register REGNO if != -1 or all registers otherwise from
+ kernel thread TID.
+
+ AIX provides a way to query all of a kernel thread's GPRs, FPRs, or
+ SPRs, but there's no way to query individual registers within those
+ groups. Therefore, if REGNO != -1, this function fetches an entire
+ group.
+
+ Unfortunately, kernel thread register queries often fail with
+ EPERM, indicating that the thread is in kernel space. This breaks
+ backtraces of threads other than the current one. To make that
+ breakage obvious without throwing an error to top level (which is
+ bad e.g. during "info threads" output), zero registers that can't
+ be retrieved. */
+
+static void
+fetch_regs_kern (int regno, pthdb_tid_t tid)
+{
+ uint64_t gprs64[32];
+ uint32_t gprs32[32];
+ double fprs[32];
+ struct ptxsprs sprs64;
+ struct ptsprs sprs32;
+ int i;
+
+ if (debug_aix_thread)
+ fprintf_unfiltered (gdb_stdlog,
+ "fetch_regs_kern tid=%lx regno=%d arch64=%d\n",
+ (long)tid, regno, arch64);
+
+ /* General-purpose registers. */
+ if (regno == -1 || regno < FP0_REGNUM)
+ {
+ if (arch64)
+ {
+ if (!ptrace64aix (PTT_READ_GPRS, tid,
+ (unsigned long) gprs64, 0, NULL))
+ memset (gprs64, 0, sizeof (gprs64));
+ supply_gprs64 (gprs64);
+ }
+ else
+ {
+ if (!ptrace32 (PTT_READ_GPRS, tid, gprs32, 0, NULL))
+ memset (gprs32, 0, sizeof (gprs32));
+ for (i = 0; i < 32; i++)
+ supply_reg32 (i, gprs32[i]);
+ }
+ }
+
+ /* Floating-point registers. */
+
+ if (regno == -1 || (regno >= FP0_REGNUM && regno <= FPLAST_REGNUM))
+ {
+ if (!ptrace32 (PTT_READ_FPRS, tid, (int *) fprs, 0, NULL))
+ memset (fprs, 0, sizeof (fprs));
+ supply_fprs (fprs);
+ }
+
+ /* Special-purpose registers. */
+
+ if (regno == -1 ||
+ (regno > FPLAST_REGNUM && regno <= LAST_UISA_SP_REGNUM))
+ {
+ if (arch64)
+ {
+ if (!ptrace64aix (PTT_READ_SPRS, tid,
+ (unsigned long) &sprs64, 0, NULL))
+ memset (&sprs64, 0, sizeof (sprs64));
+ supply_sprs64 (sprs64.pt_iar, sprs64.pt_msr, sprs64.pt_cr,
+ sprs64.pt_lr, sprs64.pt_ctr, sprs64.pt_xer);
+ }
+ else
+ {
+ if (!ptrace32 (PTT_READ_SPRS, tid, (int *) &sprs32, 0, NULL))
+ memset (&sprs32, 0, sizeof (sprs32));
+ supply_sprs32 (sprs32.pt_iar, sprs32.pt_msr, sprs32.pt_cr,
+ sprs32.pt_lr, sprs32.pt_ctr, sprs32.pt_xer);
+
+ if (REGISTER_RAW_SIZE (LAST_UISA_SP_REGNUM))
+ supply_register (LAST_UISA_SP_REGNUM, (char *) &sprs32.pt_mq);
+ }
+ }
+}
+
+/* Fetch register REGNO if != -1 or all registers otherwise in the
+ thread/process specified by inferior_ptid. */
+
+static void
+ops_fetch_registers (int regno)
+{
+ struct thread_info *thread;
+ pthdb_tid_t tid;
+
+ if (!PD_TID (inferior_ptid))
+ base_ops.to_fetch_registers (regno);
+ else
+ {
+ thread = find_thread_pid (inferior_ptid);
+ tid = thread->private->tid;
+
+ if (tid == PTHDB_INVALID_TID)
+ fetch_regs_lib (thread->private->pdtid);
+ else
+ fetch_regs_kern (regno, tid);
+ }
+}
+
+/* Store the gp registers into an array of uint32_t or uint64_t. */
+
+static void
+fill_gprs64 (uint64_t *vals)
+{
+ int regno;
+
+ for (regno = 0; regno < FP0_REGNUM; regno++)
+ if (register_cached (regno))
+ regcache_collect (regno, vals + regno);
+}
+
+static void
+fill_gprs32 (uint32_t *vals)
+{
+ int regno;
+
+ for (regno = 0; regno < FP0_REGNUM; regno++)
+ if (register_cached (regno))
+ regcache_collect (regno, vals + regno);
+}
+
+/* Store the floating point registers into a double array. */
+static void
+fill_fprs (double *vals)
+{
+ int regno;
+
+ for (regno = FP0_REGNUM; regno < FPLAST_REGNUM; regno++)
+ if (register_cached (regno))
+ regcache_collect (regno, vals + regno);
+}
+
+/* Store the special registers into the specified 64-bit and 32-bit
+ locations. */
+
+static void
+fill_sprs64 (uint64_t *iar, uint64_t *msr, uint32_t *cr,
+ uint64_t *lr, uint64_t *ctr, uint32_t *xer)
+{
+ int regno = FIRST_UISA_SP_REGNUM;
+
+ gdb_assert (sizeof (*iar) == REGISTER_RAW_SIZE (regno));
+
+ if (register_cached (regno))
+ regcache_collect (regno, iar);
+ if (register_cached (regno + 1))
+ regcache_collect (regno + 1, msr);
+ if (register_cached (regno + 2))
+ regcache_collect (regno + 2, cr);
+ if (register_cached (regno + 3))
+ regcache_collect (regno + 3, lr);
+ if (register_cached (regno + 4))
+ regcache_collect (regno + 4, ctr);
+ if (register_cached (regno + 5))
+ regcache_collect (regno + 5, xer);
+}
+
+static void
+fill_sprs32 (unsigned long *iar, unsigned long *msr, unsigned long *cr,
+ unsigned long *lr, unsigned long *ctr, unsigned long *xer)
+{
+ int regno = FIRST_UISA_SP_REGNUM;
+
+ /* If this assert() fails, the most likely reason is that GDB was
+ built incorrectly. In order to make use of many of the header
+ files in /usr/include/sys, GDB needs to be configured so that
+ sizeof (long) == 4). */
+ gdb_assert (sizeof (*iar) == REGISTER_RAW_SIZE (regno));
+
+ if (register_cached (regno))
+ regcache_collect (regno, iar);
+ if (register_cached (regno + 1))
+ regcache_collect (regno + 1, msr);
+ if (register_cached (regno + 2))
+ regcache_collect (regno + 2, cr);
+ if (register_cached (regno + 3))
+ regcache_collect (regno + 3, lr);
+ if (register_cached (regno + 4))
+ regcache_collect (regno + 4, ctr);
+ if (register_cached (regno + 5))
+ regcache_collect (regno + 5, xer);
+}
+
+/* Store all registers into pthread PDTID, which doesn't have a kernel
+ thread.
+
+ It's possible to store a single register into a non-kernel pthread,
+ but I doubt it's worth the effort. */
+
+static void
+store_regs_lib (pthdb_pthread_t pdtid)
+{
+ int status, i;
+ pthdb_context_t ctx;
+ uint32_t int32;
+ uint64_t int64;
+ double dbl;
+
+ if (debug_aix_thread)
+ fprintf_unfiltered (gdb_stdlog,
+ "store_regs_lib %lx\n", (long)pdtid);
+
+ /* Retrieve the thread's current context for its non-register
+ values. */
+ status = pthdb_pthread_context (pd_session, pdtid, &ctx);
+ if (status != PTHDB_SUCCESS)
+ error ("aix-thread: store_registers: pthdb_pthread_context returned %s",
+ pd_status2str (status));
+
+ /* Collect general-purpose register values from the regcache. */
+
+ for (i = 0; i < 32; i++)
+ if (register_cached (i))
+ {
+ if (arch64)
+ {
+ regcache_collect (i, (void *) &int64);
+ ctx.gpr[i] = int64;
+ }
+ else
+ {
+ regcache_collect (i, (void *) &int32);
+ ctx.gpr[i] = int32;
+ }
+ }
+
+ /* Collect floating-point register values from the regcache. */
+ fill_fprs (ctx.fpr);
+
+ /* Special registers (always kept in ctx as 64 bits). */
+ if (arch64)
+ {
+ fill_sprs64 (&ctx.iar, &ctx.msr, &ctx.cr, &ctx.lr, &ctx.ctr, &ctx.xer);
+ }
+ else
+ {
+ /* Problem: ctx.iar etc. are 64 bits, but raw_registers are 32.
+ Solution: use 32-bit temp variables. (The assert() in fill_sprs32()
+ will fail if the size of an unsigned long is incorrect. If this
+ happens, GDB needs to be reconfigured so that longs are 32-bits.) */
+ unsigned long tmp_iar, tmp_msr, tmp_cr, tmp_lr, tmp_ctr, tmp_xer;
+
+ fill_sprs32 (&tmp_iar, &tmp_msr, &tmp_cr, &tmp_lr, &tmp_ctr, &tmp_xer);
+ if (register_cached (FIRST_UISA_SP_REGNUM))
+ ctx.iar = tmp_iar;
+ if (register_cached (FIRST_UISA_SP_REGNUM + 1))
+ ctx.msr = tmp_msr;
+ if (register_cached (FIRST_UISA_SP_REGNUM + 2))
+ ctx.cr = tmp_cr;
+ if (register_cached (FIRST_UISA_SP_REGNUM + 3))
+ ctx.lr = tmp_lr;
+ if (register_cached (FIRST_UISA_SP_REGNUM + 4))
+ ctx.ctr = tmp_ctr;
+ if (register_cached (FIRST_UISA_SP_REGNUM + 5))
+ ctx.xer = tmp_xer;
+ }
+
+ status = pthdb_pthread_setcontext (pd_session, pdtid, &ctx);
+ if (status != PTHDB_SUCCESS)
+ error ("aix-thread: store_registers: pthdb_pthread_setcontext returned %s",
+ pd_status2str (status));
+}
+
+/* Store register REGNO if != -1 or all registers otherwise into
+ kernel thread TID.
+
+ AIX provides a way to set all of a kernel thread's GPRs, FPRs, or
+ SPRs, but there's no way to set individual registers within those
+ groups. Therefore, if REGNO != -1, this function stores an entire
+ group. */
+
+static void
+store_regs_kern (int regno, pthdb_tid_t tid)
+{
+ uint64_t gprs64[32];
+ uint32_t gprs32[32];
+ double fprs[32];
+ struct ptxsprs sprs64;
+ struct ptsprs sprs32;
+ int i;
+
+ if (debug_aix_thread)
+ fprintf_unfiltered (gdb_stdlog, "store_regs_kern tid=%lx regno=%d\n",
+ (long)tid, regno);
+
+ /* General-purpose registers. */
+ if (regno == -1 || regno < FP0_REGNUM)
+ {
+ if (arch64)
+ {
+ /* Pre-fetch: some regs may not be in the cache. */
+ ptrace64aix (PTT_READ_GPRS, tid, (unsigned long) gprs64, 0, NULL);
+ fill_gprs64 (gprs64);
+ ptrace64aix (PTT_WRITE_GPRS, tid, (unsigned long) gprs64, 0, NULL);
+ }
+ else
+ {
+ /* Pre-fetch: some regs may not be in the cache. */
+ ptrace32 (PTT_READ_GPRS, tid, gprs32, 0, NULL);
+ fill_gprs32 (gprs32);
+ ptrace32 (PTT_WRITE_GPRS, tid, gprs32, 0, NULL);
+ }
+ }
+
+ /* Floating-point registers. */
+
+ if (regno == -1 || (regno >= FP0_REGNUM && regno <= FPLAST_REGNUM))
+ {
+ /* Pre-fetch: some regs may not be in the cache. */
+ ptrace32 (PTT_READ_FPRS, tid, (int *) fprs, 0, NULL);
+ fill_fprs (fprs);
+ ptrace32 (PTT_WRITE_FPRS, tid, (int *) fprs, 0, NULL);
+ }
+
+ /* Special-purpose registers. */
+
+ if (regno == -1 ||
+ (regno > FPLAST_REGNUM && regno <= LAST_UISA_SP_REGNUM))
+ {
+ if (arch64)
+ {
+ /* Pre-fetch: some registers won't be in the cache. */
+ ptrace64aix (PTT_READ_SPRS, tid,
+ (unsigned long) &sprs64, 0, NULL);
+ fill_sprs64 (&sprs64.pt_iar, &sprs64.pt_msr, &sprs64.pt_cr,
+ &sprs64.pt_lr, &sprs64.pt_ctr, &sprs64.pt_xer);
+ ptrace64aix (PTT_WRITE_SPRS, tid,
+ (unsigned long) &sprs64, 0, NULL);
+ }
+ else
+ {
+ /* Pre-fetch: some registers won't be in the cache. */
+ ptrace32 (PTT_READ_SPRS, tid, (int *) &sprs32, 0, NULL);
+
+ fill_sprs32 (&sprs32.pt_iar, &sprs32.pt_msr, &sprs32.pt_cr,
+ &sprs32.pt_lr, &sprs32.pt_ctr, &sprs32.pt_xer);
+
+ if (REGISTER_RAW_SIZE (LAST_UISA_SP_REGNUM))
+ if (register_cached (LAST_UISA_SP_REGNUM))
+ regcache_collect (LAST_UISA_SP_REGNUM, &sprs32.pt_mq);
+
+ ptrace32 (PTT_WRITE_SPRS, tid, (int *) &sprs32, 0, NULL);
+ }
+ }
+}
+
+/* Store gdb's current view of the register set into the
+ thread/process specified by inferior_ptid. */
+
+static void
+ops_store_registers (int regno)
+{
+ struct thread_info *thread;
+ pthdb_tid_t tid;
+
+ if (!PD_TID (inferior_ptid))
+ base_ops.to_store_registers (regno);
+ else
+ {
+ thread = find_thread_pid (inferior_ptid);
+ tid = thread->private->tid;
+
+ if (tid == PTHDB_INVALID_TID)
+ store_regs_lib (thread->private->pdtid);
+ else
+ store_regs_kern (regno, tid);
+ }
+}
+
+/* Transfer LEN bytes of memory from GDB address MYADDR to target
+ address MEMADDR if WRITE and vice versa otherwise. */
+
+static int
+ops_xfer_memory (CORE_ADDR memaddr, char *myaddr, int len, int write,
+ struct mem_attrib *attrib,
+ struct target_ops *target)
+{
+ int n;
+ struct cleanup *cleanup = save_inferior_ptid ();
+
+ inferior_ptid = pid_to_ptid (PIDGET (inferior_ptid));
+ n = base_ops.to_xfer_memory (memaddr, myaddr, len,
+ write, attrib, &base_ops);
+ do_cleanups (cleanup);
+
+ return n;
+}
+
+/* Kill and forget about the inferior process. */
+
+static void
+ops_kill (void)
+{
+ struct cleanup *cleanup = save_inferior_ptid ();
+
+ inferior_ptid = pid_to_ptid (PIDGET (inferior_ptid));
+ base_ops.to_kill ();
+ do_cleanups (cleanup);
+}
+
+/* Clean up after the inferior exits. */
+
+static void
+ops_mourn_inferior (void)
+{
+ pd_deactivate ();
+ base_ops.to_mourn_inferior ();
+}
+
+/* Return whether thread PID is still valid. */
+
+static int
+ops_thread_alive (ptid_t ptid)
+{
+ if (!PD_TID (ptid))
+ return base_ops.to_thread_alive (ptid);
+
+ /* We update the thread list every time the child stops, so all
+ valid threads should be in the thread list. */
+ return in_thread_list (ptid);
+}
+
+/* Return a printable representation of composite PID for use in
+ "info threads" output. */
+
+static char *
+ops_pid_to_str (ptid_t ptid)
+{
+ static char *ret = NULL;
+
+ if (!PD_TID (ptid))
+ return base_ops.to_pid_to_str (ptid);
+
+ /* Free previous return value; a new one will be allocated by
+ xasprintf(). */
+ xfree (ret);
+
+ xasprintf (&ret, "Thread %ld", ptid_get_tid (ptid));
+ return ret;
+}
+
+/* Return a printable representation of extra information about
+ THREAD, for use in "info threads" output. */
+
+static char *
+ops_extra_thread_info (struct thread_info *thread)
+{
+ struct ui_file *buf;
+ int status;
+ pthdb_pthread_t pdtid;
+ pthdb_tid_t tid;
+ pthdb_state_t state;
+ pthdb_suspendstate_t suspendstate;
+ pthdb_detachstate_t detachstate;
+ int cancelpend;
+ long length;
+ static char *ret = NULL;
+
+ if (!PD_TID (thread->ptid))
+ return NULL;
+
+ buf = mem_fileopen ();
+
+ pdtid = thread->private->pdtid;
+ tid = thread->private->tid;
+
+ if (tid != PTHDB_INVALID_TID)
+ fprintf_unfiltered (buf, "tid %d", tid);
+
+ status = pthdb_pthread_state (pd_session, pdtid, &state);
+ if (status != PTHDB_SUCCESS)
+ state = PST_NOTSUP;
+ fprintf_unfiltered (buf, ", %s", state2str (state));
+
+ status = pthdb_pthread_suspendstate (pd_session, pdtid,
+ &suspendstate);
+ if (status == PTHDB_SUCCESS && suspendstate == PSS_SUSPENDED)
+ fprintf_unfiltered (buf, ", suspended");
+
+ status = pthdb_pthread_detachstate (pd_session, pdtid,
+ &detachstate);
+ if (status == PTHDB_SUCCESS && detachstate == PDS_DETACHED)
+ fprintf_unfiltered (buf, ", detached");
+
+ pthdb_pthread_cancelpend (pd_session, pdtid, &cancelpend);
+ if (status == PTHDB_SUCCESS && cancelpend)
+ fprintf_unfiltered (buf, ", cancel pending");
+
+ ui_file_write (buf, "", 1);
+
+ xfree (ret); /* Free old buffer. */
+
+ ret = ui_file_xstrdup (buf, &length);
+ ui_file_delete (buf);
+
+ return ret;
+}
+
+/* Initialize target ops. */
+
+static void
+init_ops (void)
+{
+ ops.to_shortname = "aix-threads";
+ ops.to_longname = "AIX pthread support";
+ ops.to_doc = "AIX pthread support";
+
+ ops.to_attach = ops_attach;
+ ops.to_detach = ops_detach;
+ ops.to_resume = ops_resume;
+ ops.to_wait = ops_wait;
+ ops.to_fetch_registers = ops_fetch_registers;
+ ops.to_store_registers = ops_store_registers;
+ ops.to_xfer_memory = ops_xfer_memory;
+ /* No need for ops.to_create_inferior, because we activate thread
+ debugging when the inferior reaches pd_brk_addr. */
+ ops.to_kill = ops_kill;
+ ops.to_mourn_inferior = ops_mourn_inferior;
+ ops.to_thread_alive = ops_thread_alive;
+ ops.to_pid_to_str = ops_pid_to_str;
+ ops.to_extra_thread_info = ops_extra_thread_info;
+ ops.to_stratum = thread_stratum;
+ ops.to_magic = OPS_MAGIC;
+}
+
+/* Module startup initialization function, automagically called by
+ init.c. */
+
+void
+_initialize_aix_thread (void)
+{
+ init_ops ();
+ add_target (&ops);
+
+ /* Notice when object files get loaded and unloaded. */
+ target_new_objfile_chain = target_new_objfile_hook;
+ target_new_objfile_hook = new_objfile;
+
+ add_show_from_set (add_set_cmd ("aix-thread", no_class, var_zinteger,
+ (char *) &debug_aix_thread,
+ "Set debugging of AIX thread module.\n"
+ "Enables printf debugging output.\n",
+ &setdebuglist),
+ &showdebuglist);
+}
--- /dev/null
+/* Native support for GNU/Linux x86-64.
+
+ Copyright 2001, 2002 Free Software Foundation, Inc. Contributed by
+ Jiri Smid, SuSE Labs.
+
+ This file is part of GDB.
+
+ This program is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 2 of the License, or
+ (at your option) any later version.
+
+ This program is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program; if not, write to the Free Software
+ Foundation, Inc., 59 Temple Place - Suite 330,
+ Boston, MA 02111-1307, USA. */
+
+#ifndef NM_X86_64_H
+#define NM_X86_64_H
+
+#include "config/nm-linux.h"
+
+#define I386_USE_GENERIC_WATCHPOINTS
+#include "i386/nm-i386.h"
+
+/* Support for 8-byte wide hw watchpoints. */
+#define TARGET_HAS_DR_LEN_8 1
+
+/* Provide access to the i386 hardware debugging registers. */
+
+extern void x86_64_linux_dr_set_control (unsigned long control);
+#define I386_DR_LOW_SET_CONTROL(control) \
+ x86_64_linux_dr_set_control (control)
+
+extern void x86_64_linux_dr_set_addr (int regnum, CORE_ADDR addr);
+#define I386_DR_LOW_SET_ADDR(regnum, addr) \
+ x86_64_linux_dr_set_addr (regnum, addr)
+
+extern void x86_64_linux_dr_reset_addr (int regnum);
+#define I386_DR_LOW_RESET_ADDR(regnum) \
+ x86_64_linux_dr_reset_addr (regnum)
+
+extern unsigned long x86_64_linux_dr_get_status (void);
+#define I386_DR_LOW_GET_STATUS() \
+ x86_64_linux_dr_get_status ()
+\f
+
+#define REGISTER_U_ADDR(addr, blockend, regno) \
+ (addr) = x86_64_register_u_addr ((blockend),(regno));
+CORE_ADDR x86_64_register_u_addr (CORE_ADDR, int);
+
+/* Return the size of the user struct. */
+#define KERNEL_U_SIZE kernel_u_size()
+extern int kernel_u_size (void);
+
+/* Offset of the registers within the user area. */
+#define U_REGS_OFFSET 0
+
+/* This is the amount to subtract from u.u_ar0
+ to get the offset in the core file of the register values. */
+#define KERNEL_U_ADDR 0x0
+
+#define PTRACE_ARG3_TYPE void*
+#define PTRACE_XFER_TYPE unsigned long
+\f
+
+/* We define this if link.h is available, because with ELF we use SVR4 style
+ shared libraries. */
+
+#ifdef HAVE_LINK_H
+#define SVR4_SHARED_LIBS
+#include "solib.h" /* Support for shared libraries. */
+#endif
+
+/* Override copies of {fetch,store}_inferior_registers in `infptrace.c'. */
+#define FETCH_INFERIOR_REGISTERS
+
+#undef PREPARE_TO_PROCEED
+
+#include <signal.h>
+
+extern void lin_thread_get_thread_signals (sigset_t * mask);
+#define GET_THREAD_SIGNALS(mask) lin_thread_get_thread_signals (mask)
+
+#endif /* NM_X86_64.h */
--- /dev/null
+/* Definitions to target GDB to GNU/Linux on x86-64.
+
+ Copyright 2002 Free Software Foundation, Inc.
+
+ Contributed by Michal Ludvig, SuSE Labs.
+
+ This file is part of GDB.
+
+ This program is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 2 of the License, or
+ (at your option) any later version.
+
+ This program is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program; if not, write to the Free Software
+ Foundation, Inc., 59 Temple Place - Suite 330,
+ Boston, MA 02111-1307, USA. */
+
+#ifndef TM_X86_64LINUX_H
+#define TM_X86_64LINUX_H
+
+/* We define SVR4_SHARED_LIBS unconditionally, on the assumption that
+ * link.h is available on all linux platforms. For I386 and SH3/4,
+ * we hard-code the information rather than use link.h anyway (for
+ * the benefit of cross-debugging). We may move to doing that for
+ * other architectures as well. */
+
+#define SVR4_SHARED_LIBS
+#include "solib.h" /* Support for shared libraries. */
+
+#endif /* #ifndef TM_X86_64LINUX_H */
--- /dev/null
+/* Definitions to make GDB run on a vax under 4.2bsd.
+ Copyright 1986, 1987, 1989, 1991, 1993, 1994, 1996, 1998, 1999, 2000, 2002
+ Free Software Foundation, Inc.
+
+ This file is part of GDB.
+
+ This program is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 2 of the License, or
+ (at your option) any later version.
+
+ This program is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program; if not, write to the Free Software
+ Foundation, Inc., 59 Temple Place - Suite 330,
+ Boston, MA 02111-1307, USA. */
+
+#ifndef TM_VAXBSD_H
+#define TM_VAXBSD_H
+
+#include "vax/tm-vax.h"
+
+#define TARGET_UPAGES 14
+#define TARGET_NBPG 512
+#define STACK_END_ADDR (0x80000000 - (TARGET_UPAGES * TARGET_NBPG))
+
+/* On the VAX, sigtramp is in the u area. Can't check the exact
+ addresses because for cross-debugging we don't have VAX include
+ files around. This should be close enough. */
+#define SIGTRAMP_START(pc) STACK_END_ADDR
+#define SIGTRAMP_END(pc) 0x80000000
+
+/* Offset to saved PC in sigcontext, from <sys/signal.h>. */
+/* XXXJRT should go away */
+#define SIGCONTEXT_PC_OFFSET 12
+
+#endif /* TM_VAXBSD_H */
--- /dev/null
+/* Target-dependent code for the Fujitsu FR-V, for GDB, the GNU Debugger.
+ Copyright 2002 Free Software Foundation, Inc.
+
+ This file is part of GDB.
+
+ This program is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 2 of the License, or
+ (at your option) any later version.
+
+ This program is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program; if not, write to the Free Software
+ Foundation, Inc., 59 Temple Place - Suite 330,
+ Boston, MA 02111-1307, USA. */
+
+#include "defs.h"
+#include "inferior.h"
+#include "symfile.h" /* for entry_point_address */
+#include "gdbcore.h"
+#include "arch-utils.h"
+#include "regcache.h"
+
+extern void _initialize_frv_tdep (void);
+
+static gdbarch_init_ftype frv_gdbarch_init;
+
+static gdbarch_register_name_ftype frv_register_name;
+static gdbarch_register_raw_size_ftype frv_register_raw_size;
+static gdbarch_register_virtual_size_ftype frv_register_virtual_size;
+static gdbarch_register_virtual_type_ftype frv_register_virtual_type;
+static gdbarch_register_byte_ftype frv_register_byte;
+static gdbarch_breakpoint_from_pc_ftype frv_breakpoint_from_pc;
+static gdbarch_frame_chain_ftype frv_frame_chain;
+static gdbarch_frame_saved_pc_ftype frv_frame_saved_pc;
+static gdbarch_skip_prologue_ftype frv_skip_prologue;
+static gdbarch_frame_init_saved_regs_ftype frv_frame_init_saved_regs;
+static gdbarch_deprecated_extract_return_value_ftype frv_extract_return_value;
+static gdbarch_deprecated_extract_struct_value_address_ftype frv_extract_struct_value_address;
+static gdbarch_use_struct_convention_ftype frv_use_struct_convention;
+static gdbarch_frameless_function_invocation_ftype frv_frameless_function_invocation;
+static gdbarch_init_extra_frame_info_ftype stupid_useless_init_extra_frame_info;
+static gdbarch_store_return_value_ftype frv_store_return_value;
+static gdbarch_store_struct_return_ftype frv_store_struct_return;
+static gdbarch_push_arguments_ftype frv_push_arguments;
+static gdbarch_push_return_address_ftype frv_push_return_address;
+static gdbarch_pop_frame_ftype frv_pop_frame;
+static gdbarch_saved_pc_after_call_ftype frv_saved_pc_after_call;
+
+static void frv_pop_frame_regular (struct frame_info *frame);
+
+/* Register numbers. You can change these as needed, but don't forget
+ to update the simulator accordingly. */
+enum {
+ /* The total number of registers we know exist. */
+ frv_num_regs = 147,
+
+ /* Register numbers 0 -- 63 are always reserved for general-purpose
+ registers. The chip at hand may have less. */
+ first_gpr_regnum = 0,
+ sp_regnum = 1,
+ fp_regnum = 2,
+ struct_return_regnum = 3,
+ last_gpr_regnum = 63,
+
+ /* Register numbers 64 -- 127 are always reserved for floating-point
+ registers. The chip at hand may have less. */
+ first_fpr_regnum = 64,
+ last_fpr_regnum = 127,
+
+ /* Register numbers 128 on up are always reserved for special-purpose
+ registers. */
+ first_spr_regnum = 128,
+ pc_regnum = 128,
+ psr_regnum = 129,
+ ccr_regnum = 130,
+ cccr_regnum = 131,
+ tbr_regnum = 135,
+ brr_regnum = 136,
+ dbar0_regnum = 137,
+ dbar1_regnum = 138,
+ dbar2_regnum = 139,
+ dbar3_regnum = 140,
+ lr_regnum = 145,
+ lcr_regnum = 146,
+ last_spr_regnum = 146
+};
+
+static LONGEST frv_call_dummy_words[] =
+{0};
+
+
+/* The contents of this structure can only be trusted after we've
+ frv_frame_init_saved_regs on the frame. */
+struct frame_extra_info
+ {
+ /* The offset from our frame pointer to our caller's stack
+ pointer. */
+ int fp_to_callers_sp_offset;
+
+ /* Non-zero if we've saved our return address on the stack yet.
+ Zero if it's still sitting in the link register. */
+ int lr_saved_on_stack;
+ };
+
+
+/* A structure describing a particular variant of the FRV.
+ We allocate and initialize one of these structures when we create
+ the gdbarch object for a variant.
+
+ At the moment, all the FR variants we support differ only in which
+ registers are present; the portable code of GDB knows that
+ registers whose names are the empty string don't exist, so the
+ `register_names' array captures all the per-variant information we
+ need.
+
+ in the future, if we need to have per-variant maps for raw size,
+ virtual type, etc., we should replace register_names with an array
+ of structures, each of which gives all the necessary info for one
+ register. Don't stick parallel arrays in here --- that's so
+ Fortran. */
+struct gdbarch_tdep
+{
+ /* How many general-purpose registers does this variant have? */
+ int num_gprs;
+
+ /* How many floating-point registers does this variant have? */
+ int num_fprs;
+
+ /* How many hardware watchpoints can it support? */
+ int num_hw_watchpoints;
+
+ /* How many hardware breakpoints can it support? */
+ int num_hw_breakpoints;
+
+ /* Register names. */
+ char **register_names;
+};
+
+#define CURRENT_VARIANT (gdbarch_tdep (current_gdbarch))
+
+
+/* Allocate a new variant structure, and set up default values for all
+ the fields. */
+static struct gdbarch_tdep *
+new_variant (void)
+{
+ struct gdbarch_tdep *var;
+ int r;
+ char buf[20];
+
+ var = xmalloc (sizeof (*var));
+ memset (var, 0, sizeof (*var));
+
+ var->num_gprs = 64;
+ var->num_fprs = 64;
+ var->num_hw_watchpoints = 0;
+ var->num_hw_breakpoints = 0;
+
+ /* By default, don't supply any general-purpose or floating-point
+ register names. */
+ var->register_names = (char **) xmalloc (frv_num_regs * sizeof (char *));
+ for (r = 0; r < frv_num_regs; r++)
+ var->register_names[r] = "";
+
+ /* Do, however, supply default names for the special-purpose
+ registers. */
+ for (r = first_spr_regnum; r <= last_spr_regnum; ++r)
+ {
+ sprintf (buf, "x%d", r);
+ var->register_names[r] = xstrdup (buf);
+ }
+
+ var->register_names[pc_regnum] = "pc";
+ var->register_names[lr_regnum] = "lr";
+ var->register_names[lcr_regnum] = "lcr";
+
+ var->register_names[psr_regnum] = "psr";
+ var->register_names[ccr_regnum] = "ccr";
+ var->register_names[cccr_regnum] = "cccr";
+ var->register_names[tbr_regnum] = "tbr";
+
+ /* Debug registers. */
+ var->register_names[brr_regnum] = "brr";
+ var->register_names[dbar0_regnum] = "dbar0";
+ var->register_names[dbar1_regnum] = "dbar1";
+ var->register_names[dbar2_regnum] = "dbar2";
+ var->register_names[dbar3_regnum] = "dbar3";
+
+ return var;
+}
+
+
+/* Indicate that the variant VAR has NUM_GPRS general-purpose
+ registers, and fill in the names array appropriately. */
+static void
+set_variant_num_gprs (struct gdbarch_tdep *var, int num_gprs)
+{
+ int r;
+
+ var->num_gprs = num_gprs;
+
+ for (r = 0; r < num_gprs; ++r)
+ {
+ char buf[20];
+
+ sprintf (buf, "gr%d", r);
+ var->register_names[first_gpr_regnum + r] = xstrdup (buf);
+ }
+}
+
+
+/* Indicate that the variant VAR has NUM_FPRS floating-point
+ registers, and fill in the names array appropriately. */
+static void
+set_variant_num_fprs (struct gdbarch_tdep *var, int num_fprs)
+{
+ int r;
+
+ var->num_fprs = num_fprs;
+
+ for (r = 0; r < num_fprs; ++r)
+ {
+ char buf[20];
+
+ sprintf (buf, "fr%d", r);
+ var->register_names[first_fpr_regnum + r] = xstrdup (buf);
+ }
+}
+
+
+static const char *
+frv_register_name (int reg)
+{
+ if (reg < 0)
+ return "?toosmall?";
+ if (reg >= frv_num_regs)
+ return "?toolarge?";
+
+ return CURRENT_VARIANT->register_names[reg];
+}
+
+
+static int
+frv_register_raw_size (int reg)
+{
+ return 4;
+}
+
+static int
+frv_register_virtual_size (int reg)
+{
+ return 4;
+}
+
+static struct type *
+frv_register_virtual_type (int reg)
+{
+ if (reg >= 64 && reg <= 127)
+ return builtin_type_float;
+ else
+ return builtin_type_int;
+}
+
+static int
+frv_register_byte (int reg)
+{
+ return (reg * 4);
+}
+
+static const unsigned char *
+frv_breakpoint_from_pc (CORE_ADDR *pcptr, int *lenp)
+{
+ static unsigned char breakpoint[] = {0xc0, 0x70, 0x00, 0x01};
+ *lenp = sizeof (breakpoint);
+ return breakpoint;
+}
+
+static CORE_ADDR
+frv_frame_chain (struct frame_info *frame)
+{
+ CORE_ADDR saved_fp_addr;
+
+ if (frame->saved_regs && frame->saved_regs[fp_regnum] != 0)
+ saved_fp_addr = frame->saved_regs[fp_regnum];
+ else
+ /* Just assume it was saved in the usual place. */
+ saved_fp_addr = frame->frame;
+
+ return read_memory_integer (saved_fp_addr, 4);
+}
+
+static CORE_ADDR
+frv_frame_saved_pc (struct frame_info *frame)
+{
+ frv_frame_init_saved_regs (frame);
+
+ /* Perhaps the prologue analyzer recorded where it was stored.
+ (As of 14 Oct 2001, it never does.) */
+ if (frame->saved_regs && frame->saved_regs[pc_regnum] != 0)
+ return read_memory_integer (frame->saved_regs[pc_regnum], 4);
+
+ /* If the prologue analyzer tells us the link register was saved on
+ the stack, get it from there. */
+ if (frame->extra_info->lr_saved_on_stack)
+ return read_memory_integer (frame->frame + 8, 4);
+
+ /* Otherwise, it's still in LR.
+ However, if FRAME isn't the youngest frame, this is kind of
+ suspicious --- if this frame called somebody else, then its LR
+ has certainly been overwritten. */
+ if (! frame->next)
+ return read_register (lr_regnum);
+
+ /* By default, assume it's saved in the standard place, relative to
+ the frame pointer. */
+ return read_memory_integer (frame->frame + 8, 4);
+}
+
+
+/* Return true if REG is a caller-saves ("scratch") register,
+ false otherwise. */
+static int
+is_caller_saves_reg (int reg)
+{
+ return ((4 <= reg && reg <= 7)
+ || (14 <= reg && reg <= 15)
+ || (32 <= reg && reg <= 47));
+}
+
+
+/* Return true if REG is a callee-saves register, false otherwise. */
+static int
+is_callee_saves_reg (int reg)
+{
+ return ((16 <= reg && reg <= 31)
+ || (48 <= reg && reg <= 63));
+}
+
+
+/* Return true if REG is an argument register, false otherwise. */
+static int
+is_argument_reg (int reg)
+{
+ return (8 <= reg && reg <= 13);
+}
+
+
+/* Scan an FR-V prologue, starting at PC, until frame->PC.
+ If FRAME is non-zero, fill in its saved_regs with appropriate addresses.
+ We assume FRAME's saved_regs array has already been allocated and cleared.
+ Return the first PC value after the prologue.
+
+ Note that, for unoptimized code, we almost don't need this function
+ at all; all arguments and locals live on the stack, so we just need
+ the FP to find everything. The catch: structures passed by value
+ have their addresses living in registers; they're never spilled to
+ the stack. So if you ever want to be able to get to these
+ arguments in any frame but the top, you'll need to do this serious
+ prologue analysis. */
+static CORE_ADDR
+frv_analyze_prologue (CORE_ADDR pc, struct frame_info *frame)
+{
+ /* When writing out instruction bitpatterns, we use the following
+ letters to label instruction fields:
+ P - The parallel bit. We don't use this.
+ J - The register number of GRj in the instruction description.
+ K - The register number of GRk in the instruction description.
+ I - The register number of GRi.
+ S - a signed imediate offset.
+ U - an unsigned immediate offset.
+
+ The dots below the numbers indicate where hex digit boundaries
+ fall, to make it easier to check the numbers. */
+
+ /* Non-zero iff we've seen the instruction that initializes the
+ frame pointer for this function's frame. */
+ int fp_set = 0;
+
+ /* If fp_set is non_zero, then this is the distance from
+ the stack pointer to frame pointer: fp = sp + fp_offset. */
+ int fp_offset = 0;
+
+ /* Total size of frame prior to any alloca operations. */
+ int framesize = 0;
+
+ /* The number of the general-purpose register we saved the return
+ address ("link register") in, or -1 if we haven't moved it yet. */
+ int lr_save_reg = -1;
+
+ /* Non-zero iff we've saved the LR onto the stack. */
+ int lr_saved_on_stack = 0;
+
+ /* If gr_saved[i] is non-zero, then we've noticed that general
+ register i has been saved at gr_sp_offset[i] from the stack
+ pointer. */
+ char gr_saved[64];
+ int gr_sp_offset[64];
+
+ memset (gr_saved, 0, sizeof (gr_saved));
+
+ while (! frame || pc < frame->pc)
+ {
+ LONGEST op = read_memory_integer (pc, 4);
+
+ /* The tests in this chain of ifs should be in order of
+ decreasing selectivity, so that more particular patterns get
+ to fire before less particular patterns. */
+
+ /* Setting the FP from the SP:
+ ori sp, 0, fp
+ P 000010 0100010 000001 000000000000 = 0x04881000
+ 0 111111 1111111 111111 111111111111 = 0x7fffffff
+ . . . . . . . .
+ We treat this as part of the prologue. */
+ if ((op & 0x7fffffff) == 0x04881000)
+ {
+ fp_set = 1;
+ fp_offset = 0;
+ }
+
+ /* Move the link register to the scratch register grJ, before saving:
+ movsg lr, grJ
+ P 000100 0000011 010000 000111 JJJJJJ = 0x080d01c0
+ 0 111111 1111111 111111 111111 000000 = 0x7fffffc0
+ . . . . . . . .
+ We treat this as part of the prologue. */
+ else if ((op & 0x7fffffc0) == 0x080d01c0)
+ {
+ int gr_j = op & 0x3f;
+
+ /* If we're moving it to a scratch register, that's fine. */
+ if (is_caller_saves_reg (gr_j))
+ lr_save_reg = gr_j;
+ /* Otherwise it's not a prologue instruction that we
+ recognize. */
+ else
+ break;
+ }
+
+ /* To save multiple callee-saves registers on the stack, at
+ offset zero:
+
+ std grK,@(sp,gr0)
+ P KKKKKK 0000011 000001 000011 000000 = 0x000c10c0
+ 0 000000 1111111 111111 111111 111111 = 0x01ffffff
+
+ stq grK,@(sp,gr0)
+ P KKKKKK 0000011 000001 000100 000000 = 0x000c1100
+ 0 000000 1111111 111111 111111 111111 = 0x01ffffff
+ . . . . . . . .
+ We treat this as part of the prologue, and record the register's
+ saved address in the frame structure. */
+ else if ((op & 0x01ffffff) == 0x000c10c0
+ || (op & 0x01ffffff) == 0x000c1100)
+ {
+ int gr_k = ((op >> 25) & 0x3f);
+ int ope = ((op >> 6) & 0x3f);
+ int count;
+ int i;
+
+ /* Is it an std or an stq? */
+ if (ope == 0x03)
+ count = 2;
+ else
+ count = 4;
+
+ /* Is it really a callee-saves register? */
+ if (is_callee_saves_reg (gr_k))
+ {
+ for (i = 0; i < count; i++)
+ {
+ gr_saved[gr_k + i] = 1;
+ gr_sp_offset[gr_k + i] = 4 * i;
+ }
+ }
+ else
+ /* It's not a prologue instruction. */
+ break;
+ }
+
+ /* Adjusting the stack pointer. (The stack pointer is GR1.)
+ addi sp, S, sp
+ P 000001 0010000 000001 SSSSSSSSSSSS = 0x02401000
+ 0 111111 1111111 111111 000000000000 = 0x7ffff000
+ . . . . . . . .
+ We treat this as part of the prologue. */
+ else if ((op & 0x7ffff000) == 0x02401000)
+ {
+ /* Sign-extend the twelve-bit field.
+ (Isn't there a better way to do this?) */
+ int s = (((op & 0xfff) - 0x800) & 0xfff) - 0x800;
+
+ framesize -= s;
+ }
+
+ /* Setting the FP to a constant distance from the SP:
+ addi sp, S, fp
+ P 000010 0010000 000001 SSSSSSSSSSSS = 0x04401000
+ 0 111111 1111111 111111 000000000000 = 0x7ffff000
+ . . . . . . . .
+ We treat this as part of the prologue. */
+ else if ((op & 0x7ffff000) == 0x04401000)
+ {
+ /* Sign-extend the twelve-bit field.
+ (Isn't there a better way to do this?) */
+ int s = (((op & 0xfff) - 0x800) & 0xfff) - 0x800;
+ fp_set = 1;
+ fp_offset = s;
+ }
+
+ /* To spill an argument register to a scratch register:
+ ori GRi, 0, GRk
+ P KKKKKK 0100010 IIIIII 000000000000 = 0x00880000
+ 0 000000 1111111 000000 111111111111 = 0x01fc0fff
+ . . . . . . . .
+ For the time being, we treat this as a prologue instruction,
+ assuming that GRi is an argument register. This one's kind
+ of suspicious, because it seems like it could be part of a
+ legitimate body instruction. But we only come here when the
+ source info wasn't helpful, so we have to do the best we can.
+ Hopefully once GCC and GDB agree on how to emit line number
+ info for prologues, then this code will never come into play. */
+ else if ((op & 0x01fc0fff) == 0x00880000)
+ {
+ int gr_i = ((op >> 12) & 0x3f);
+
+ /* If the source isn't an arg register, then this isn't a
+ prologue instruction. */
+ if (! is_argument_reg (gr_i))
+ break;
+ }
+
+ /* To spill 16-bit values to the stack:
+ sthi GRk, @(fp, s)
+ P KKKKKK 1010001 000010 SSSSSSSSSSSS = 0x01442000
+ 0 000000 1111111 111111 000000000000 = 0x01fff000
+ . . . . . . . .
+ And for 8-bit values, we use STB instructions.
+ stbi GRk, @(fp, s)
+ P KKKKKK 1010000 000010 SSSSSSSSSSSS = 0x01402000
+ 0 000000 1111111 111111 000000000000 = 0x01fff000
+ . . . . . . . .
+ We check that GRk is really an argument register, and treat
+ all such as part of the prologue. */
+ else if ( (op & 0x01fff000) == 0x01442000
+ || (op & 0x01fff000) == 0x01402000)
+ {
+ int gr_k = ((op >> 25) & 0x3f);
+
+ if (! is_argument_reg (gr_k))
+ break; /* Source isn't an arg register. */
+ }
+
+ /* To save multiple callee-saves register on the stack, at a
+ non-zero offset:
+
+ stdi GRk, @(sp, s)
+ P KKKKKK 1010011 000001 SSSSSSSSSSSS = 0x014c1000
+ 0 000000 1111111 111111 000000000000 = 0x01fff000
+ . . . . . . . .
+ stqi GRk, @(sp, s)
+ P KKKKKK 1010100 000001 SSSSSSSSSSSS = 0x01501000
+ 0 000000 1111111 111111 000000000000 = 0x01fff000
+ . . . . . . . .
+ We treat this as part of the prologue, and record the register's
+ saved address in the frame structure. */
+ else if ((op & 0x01fff000) == 0x014c1000
+ || (op & 0x01fff000) == 0x01501000)
+ {
+ int gr_k = ((op >> 25) & 0x3f);
+ int count;
+ int i;
+
+ /* Is it a stdi or a stqi? */
+ if ((op & 0x01fff000) == 0x014c1000)
+ count = 2;
+ else
+ count = 4;
+
+ /* Is it really a callee-saves register? */
+ if (is_callee_saves_reg (gr_k))
+ {
+ /* Sign-extend the twelve-bit field.
+ (Isn't there a better way to do this?) */
+ int s = (((op & 0xfff) - 0x800) & 0xfff) - 0x800;
+
+ for (i = 0; i < count; i++)
+ {
+ gr_saved[gr_k + i] = 1;
+ gr_sp_offset[gr_k + i] = s + (4 * i);
+ }
+ }
+ else
+ /* It's not a prologue instruction. */
+ break;
+ }
+
+ /* Storing any kind of integer register at any constant offset
+ from any other register.
+
+ st GRk, @(GRi, gr0)
+ P KKKKKK 0000011 IIIIII 000010 000000 = 0x000c0080
+ 0 000000 1111111 000000 111111 111111 = 0x01fc0fff
+ . . . . . . . .
+ sti GRk, @(GRi, d12)
+ P KKKKKK 1010010 IIIIII SSSSSSSSSSSS = 0x01480000
+ 0 000000 1111111 000000 000000000000 = 0x01fc0000
+ . . . . . . . .
+ These could be almost anything, but a lot of prologue
+ instructions fall into this pattern, so let's decode the
+ instruction once, and then work at a higher level. */
+ else if (((op & 0x01fc0fff) == 0x000c0080)
+ || ((op & 0x01fc0000) == 0x01480000))
+ {
+ int gr_k = ((op >> 25) & 0x3f);
+ int gr_i = ((op >> 12) & 0x3f);
+ int offset;
+
+ /* Are we storing with gr0 as an offset, or using an
+ immediate value? */
+ if ((op & 0x01fc0fff) == 0x000c0080)
+ offset = 0;
+ else
+ offset = (((op & 0xfff) - 0x800) & 0xfff) - 0x800;
+
+ /* If the address isn't relative to the SP or FP, it's not a
+ prologue instruction. */
+ if (gr_i != sp_regnum && gr_i != fp_regnum)
+ break;
+
+ /* Saving the old FP in the new frame (relative to the SP). */
+ if (gr_k == fp_regnum && gr_i == sp_regnum)
+ ;
+
+ /* Saving callee-saves register(s) on the stack, relative to
+ the SP. */
+ else if (gr_i == sp_regnum
+ && is_callee_saves_reg (gr_k))
+ {
+ gr_saved[gr_k] = 1;
+ gr_sp_offset[gr_k] = offset;
+ }
+
+ /* Saving the scratch register holding the return address. */
+ else if (lr_save_reg != -1
+ && gr_k == lr_save_reg)
+ lr_saved_on_stack = 1;
+
+ /* Spilling int-sized arguments to the stack. */
+ else if (is_argument_reg (gr_k))
+ ;
+
+ /* It's not a store instruction we recognize, so this must
+ be the end of the prologue. */
+ else
+ break;
+ }
+
+ /* It's not any instruction we recognize, so this must be the end
+ of the prologue. */
+ else
+ break;
+
+ pc += 4;
+ }
+
+ if (frame)
+ {
+ frame->extra_info->lr_saved_on_stack = lr_saved_on_stack;
+
+ /* If we know the relationship between the stack and frame
+ pointers, record the addresses of the registers we noticed.
+ Note that we have to do this as a separate step at the end,
+ because instructions may save relative to the SP, but we need
+ their addresses relative to the FP. */
+ if (fp_set)
+ {
+ int i;
+
+ for (i = 0; i < 64; i++)
+ if (gr_saved[i])
+ frame->saved_regs[i] = (frame->frame
+ - fp_offset + gr_sp_offset[i]);
+
+ frame->extra_info->fp_to_callers_sp_offset = framesize - fp_offset;
+ }
+ }
+
+ return pc;
+}
+
+
+static CORE_ADDR
+frv_skip_prologue (CORE_ADDR pc)
+{
+ CORE_ADDR func_addr, func_end, new_pc;
+
+ new_pc = pc;
+
+ /* If the line table has entry for a line *within* the function
+ (i.e., not in the prologue, and not past the end), then that's
+ our location. */
+ if (find_pc_partial_function (pc, NULL, &func_addr, &func_end))
+ {
+ struct symtab_and_line sal;
+
+ sal = find_pc_line (func_addr, 0);
+
+ if (sal.line != 0 && sal.end < func_end)
+ {
+ new_pc = sal.end;
+ }
+ }
+
+ /* The FR-V prologue is at least five instructions long (twenty bytes).
+ If we didn't find a real source location past that, then
+ do a full analysis of the prologue. */
+ if (new_pc < pc + 20)
+ new_pc = frv_analyze_prologue (pc, 0);
+
+ return new_pc;
+}
+
+static void
+frv_frame_init_saved_regs (struct frame_info *frame)
+{
+ if (frame->saved_regs)
+ return;
+
+ frame_saved_regs_zalloc (frame);
+ frame->saved_regs[fp_regnum] = frame->frame;
+
+ /* Find the beginning of this function, so we can analyze its
+ prologue. */
+ {
+ CORE_ADDR func_addr, func_end;
+
+ if (find_pc_partial_function (frame->pc, NULL, &func_addr, &func_end))
+ frv_analyze_prologue (func_addr, frame);
+ }
+}
+
+/* Should we use EXTRACT_STRUCT_VALUE_ADDRESS instead of
+ EXTRACT_RETURN_VALUE? GCC_P is true if compiled with gcc
+ and TYPE is the type (which is known to be struct, union or array).
+
+ The frv returns all structs in memory. */
+
+static int
+frv_use_struct_convention (int gcc_p, struct type *type)
+{
+ return 1;
+}
+
+static void
+frv_extract_return_value (struct type *type, char *regbuf, char *valbuf)
+{
+ memcpy (valbuf, (regbuf
+ + frv_register_byte (8)
+ + (TYPE_LENGTH (type) < 4 ? 4 - TYPE_LENGTH (type) : 0)),
+ TYPE_LENGTH (type));
+}
+
+static CORE_ADDR
+frv_extract_struct_value_address (char *regbuf)
+{
+ return extract_address (regbuf + frv_register_byte (struct_return_regnum),
+ 4);
+}
+
+static void
+frv_store_struct_return (CORE_ADDR addr, CORE_ADDR sp)
+{
+ write_register (struct_return_regnum, addr);
+}
+
+static int
+frv_frameless_function_invocation (struct frame_info *frame)
+{
+ return frameless_look_for_prologue (frame);
+}
+
+static CORE_ADDR
+frv_saved_pc_after_call (struct frame_info *frame)
+{
+ return read_register (lr_regnum);
+}
+
+static void
+frv_init_extra_frame_info (int fromleaf, struct frame_info *frame)
+{
+ frame->extra_info = (struct frame_extra_info *)
+ frame_obstack_alloc (sizeof (struct frame_extra_info));
+ frame->extra_info->fp_to_callers_sp_offset = 0;
+ frame->extra_info->lr_saved_on_stack = 0;
+}
+
+#define ROUND_UP(n,a) (((n)+(a)-1) & ~((a)-1))
+#define ROUND_DOWN(n,a) ((n) & ~((a)-1))
+
+static CORE_ADDR
+frv_push_arguments (int nargs, struct value **args, CORE_ADDR sp,
+ int struct_return, CORE_ADDR struct_addr)
+{
+ int argreg;
+ int argnum;
+ char *val;
+ char valbuf[4];
+ struct value *arg;
+ struct type *arg_type;
+ int len;
+ enum type_code typecode;
+ CORE_ADDR regval;
+ int stack_space;
+ int stack_offset;
+
+#if 0
+ printf("Push %d args at sp = %x, struct_return=%d (%x)\n",
+ nargs, (int) sp, struct_return, struct_addr);
+#endif
+
+ stack_space = 0;
+ for (argnum = 0; argnum < nargs; ++argnum)
+ stack_space += ROUND_UP (TYPE_LENGTH (VALUE_TYPE (args[argnum])), 4);
+
+ stack_space -= (6 * 4);
+ if (stack_space > 0)
+ sp -= stack_space;
+
+ /* Make sure stack is dword aligned. */
+ sp = ROUND_DOWN (sp, 8);
+
+ stack_offset = 0;
+
+ argreg = 8;
+
+ if (struct_return)
+ write_register (struct_return_regnum, struct_addr);
+
+ for (argnum = 0; argnum < nargs; ++argnum)
+ {
+ arg = args[argnum];
+ arg_type = check_typedef (VALUE_TYPE (arg));
+ len = TYPE_LENGTH (arg_type);
+ typecode = TYPE_CODE (arg_type);
+
+ if (typecode == TYPE_CODE_STRUCT || typecode == TYPE_CODE_UNION)
+ {
+ store_address (valbuf, 4, VALUE_ADDRESS (arg));
+ typecode = TYPE_CODE_PTR;
+ len = 4;
+ val = valbuf;
+ }
+ else
+ {
+ val = (char *) VALUE_CONTENTS (arg);
+ }
+
+ while (len > 0)
+ {
+ int partial_len = (len < 4 ? len : 4);
+
+ if (argreg < 14)
+ {
+ regval = extract_address (val, partial_len);
+#if 0
+ printf(" Argnum %d data %x -> reg %d\n",
+ argnum, (int) regval, argreg);
+#endif
+ write_register (argreg, regval);
+ ++argreg;
+ }
+ else
+ {
+#if 0
+ printf(" Argnum %d data %x -> offset %d (%x)\n",
+ argnum, *((int *)val), stack_offset, (int) (sp + stack_offset));
+#endif
+ write_memory (sp + stack_offset, val, partial_len);
+ stack_offset += ROUND_UP(partial_len, 4);
+ }
+ len -= partial_len;
+ val += partial_len;
+ }
+ }
+ return sp;
+}
+
+static CORE_ADDR
+frv_push_return_address (CORE_ADDR pc, CORE_ADDR sp)
+{
+ write_register (lr_regnum, CALL_DUMMY_ADDRESS ());
+ return sp;
+}
+
+static void
+frv_store_return_value (struct type *type, char *valbuf)
+{
+ int length = TYPE_LENGTH (type);
+ int reg8_offset = frv_register_byte (8);
+
+ if (length <= 4)
+ write_register_bytes (reg8_offset + (4 - length), valbuf, length);
+ else if (length == 8)
+ write_register_bytes (reg8_offset, valbuf, length);
+ else
+ internal_error (__FILE__, __LINE__,
+ "Don't know how to return a %d-byte value.", length);
+}
+
+static void
+frv_pop_frame (void)
+{
+ generic_pop_current_frame (frv_pop_frame_regular);
+}
+
+static void
+frv_pop_frame_regular (struct frame_info *frame)
+{
+ CORE_ADDR fp;
+ int regno;
+
+ fp = frame->frame;
+
+ frv_frame_init_saved_regs (frame);
+
+ write_register (pc_regnum, frv_frame_saved_pc (frame));
+ for (regno = 0; regno < frv_num_regs; ++regno)
+ {
+ if (frame->saved_regs[regno]
+ && regno != pc_regnum
+ && regno != sp_regnum)
+ {
+ write_register (regno,
+ read_memory_integer (frame->saved_regs[regno], 4));
+ }
+ }
+ write_register (sp_regnum, fp + frame->extra_info->fp_to_callers_sp_offset);
+ flush_cached_frames ();
+}
+
+
+static void
+frv_remote_translate_xfer_address (CORE_ADDR memaddr, int nr_bytes,
+ CORE_ADDR *targ_addr, int *targ_len)
+{
+ *targ_addr = memaddr;
+ *targ_len = nr_bytes;
+}
+
+
+/* Hardware watchpoint / breakpoint support for the FR500
+ and FR400. */
+
+int
+frv_check_watch_resources (int type, int cnt, int ot)
+{
+ struct gdbarch_tdep *var = CURRENT_VARIANT;
+
+ /* Watchpoints not supported on simulator. */
+ if (strcmp (target_shortname, "sim") == 0)
+ return 0;
+
+ if (type == bp_hardware_breakpoint)
+ {
+ if (var->num_hw_breakpoints == 0)
+ return 0;
+ else if (cnt <= var->num_hw_breakpoints)
+ return 1;
+ }
+ else
+ {
+ if (var->num_hw_watchpoints == 0)
+ return 0;
+ else if (ot)
+ return -1;
+ else if (cnt <= var->num_hw_watchpoints)
+ return 1;
+ }
+ return -1;
+}
+
+
+CORE_ADDR
+frv_stopped_data_address (void)
+{
+ CORE_ADDR brr, dbar0, dbar1, dbar2, dbar3;
+
+ brr = read_register (brr_regnum);
+ dbar0 = read_register (dbar0_regnum);
+ dbar1 = read_register (dbar1_regnum);
+ dbar2 = read_register (dbar2_regnum);
+ dbar3 = read_register (dbar3_regnum);
+
+ if (brr & (1<<11))
+ return dbar0;
+ else if (brr & (1<<10))
+ return dbar1;
+ else if (brr & (1<<9))
+ return dbar2;
+ else if (brr & (1<<8))
+ return dbar3;
+ else
+ return 0;
+}
+
+static struct gdbarch *
+frv_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
+{
+ struct gdbarch *gdbarch;
+ struct gdbarch_tdep *var;
+
+ /* Check to see if we've already built an appropriate architecture
+ object for this executable. */
+ arches = gdbarch_list_lookup_by_info (arches, &info);
+ if (arches)
+ return arches->gdbarch;
+
+ /* Select the right tdep structure for this variant. */
+ var = new_variant ();
+ switch (info.bfd_arch_info->mach)
+ {
+ case bfd_mach_frv:
+ case bfd_mach_frvsimple:
+ case bfd_mach_fr500:
+ case bfd_mach_frvtomcat:
+ set_variant_num_gprs (var, 64);
+ set_variant_num_fprs (var, 64);
+ break;
+
+ case bfd_mach_fr400:
+ set_variant_num_gprs (var, 32);
+ set_variant_num_fprs (var, 32);
+ break;
+
+ default:
+ /* Never heard of this variant. */
+ return 0;
+ }
+
+ gdbarch = gdbarch_alloc (&info, var);
+
+ set_gdbarch_short_bit (gdbarch, 16);
+ set_gdbarch_int_bit (gdbarch, 32);
+ set_gdbarch_long_bit (gdbarch, 32);
+ set_gdbarch_long_long_bit (gdbarch, 64);
+ set_gdbarch_float_bit (gdbarch, 32);
+ set_gdbarch_double_bit (gdbarch, 64);
+ set_gdbarch_long_double_bit (gdbarch, 64);
+ set_gdbarch_ptr_bit (gdbarch, 32);
+
+ set_gdbarch_num_regs (gdbarch, frv_num_regs);
+ set_gdbarch_sp_regnum (gdbarch, sp_regnum);
+ set_gdbarch_fp_regnum (gdbarch, fp_regnum);
+ set_gdbarch_pc_regnum (gdbarch, pc_regnum);
+
+ set_gdbarch_register_name (gdbarch, frv_register_name);
+ set_gdbarch_register_size (gdbarch, 4);
+ set_gdbarch_register_bytes (gdbarch, frv_num_regs * 4);
+ set_gdbarch_register_byte (gdbarch, frv_register_byte);
+ set_gdbarch_register_raw_size (gdbarch, frv_register_raw_size);
+ set_gdbarch_max_register_raw_size (gdbarch, 4);
+ set_gdbarch_register_virtual_size (gdbarch, frv_register_virtual_size);
+ set_gdbarch_max_register_virtual_size (gdbarch, 4);
+ set_gdbarch_register_virtual_type (gdbarch, frv_register_virtual_type);
+
+ set_gdbarch_skip_prologue (gdbarch, frv_skip_prologue);
+ set_gdbarch_breakpoint_from_pc (gdbarch, frv_breakpoint_from_pc);
+
+ set_gdbarch_frame_num_args (gdbarch, frame_num_args_unknown);
+ set_gdbarch_frame_args_skip (gdbarch, 0);
+ set_gdbarch_frameless_function_invocation (gdbarch, frv_frameless_function_invocation);
+
+ set_gdbarch_saved_pc_after_call (gdbarch, frv_saved_pc_after_call);
+
+ set_gdbarch_frame_chain (gdbarch, frv_frame_chain);
+ set_gdbarch_frame_chain_valid (gdbarch, func_frame_chain_valid);
+ set_gdbarch_frame_saved_pc (gdbarch, frv_frame_saved_pc);
+ set_gdbarch_frame_args_address (gdbarch, default_frame_address);
+ set_gdbarch_frame_locals_address (gdbarch, default_frame_address);
+
+ set_gdbarch_frame_init_saved_regs (gdbarch, frv_frame_init_saved_regs);
+
+ set_gdbarch_use_struct_convention (gdbarch, frv_use_struct_convention);
+ set_gdbarch_deprecated_extract_return_value (gdbarch, frv_extract_return_value);
+
+ set_gdbarch_store_struct_return (gdbarch, frv_store_struct_return);
+ set_gdbarch_store_return_value (gdbarch, frv_store_return_value);
+ set_gdbarch_deprecated_extract_struct_value_address (gdbarch, frv_extract_struct_value_address);
+
+ /* Settings for calling functions in the inferior. */
+ set_gdbarch_use_generic_dummy_frames (gdbarch, 1);
+ set_gdbarch_call_dummy_length (gdbarch, 0);
+ set_gdbarch_coerce_float_to_double (gdbarch,
+ standard_coerce_float_to_double);
+ set_gdbarch_push_arguments (gdbarch, frv_push_arguments);
+ set_gdbarch_push_return_address (gdbarch, frv_push_return_address);
+ set_gdbarch_pop_frame (gdbarch, frv_pop_frame);
+
+ set_gdbarch_call_dummy_p (gdbarch, 1);
+ set_gdbarch_call_dummy_words (gdbarch, frv_call_dummy_words);
+ set_gdbarch_sizeof_call_dummy_words (gdbarch, sizeof (frv_call_dummy_words));
+ set_gdbarch_call_dummy_breakpoint_offset_p (gdbarch, 1);
+ set_gdbarch_init_extra_frame_info (gdbarch, frv_init_extra_frame_info);
+
+ /* Settings that should be unnecessary. */
+ set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
+
+ set_gdbarch_read_pc (gdbarch, generic_target_read_pc);
+ set_gdbarch_write_pc (gdbarch, generic_target_write_pc);
+ set_gdbarch_read_fp (gdbarch, generic_target_read_fp);
+ set_gdbarch_read_sp (gdbarch, generic_target_read_sp);
+ set_gdbarch_write_sp (gdbarch, generic_target_write_sp);
+
+ set_gdbarch_call_dummy_location (gdbarch, AT_ENTRY_POINT);
+ set_gdbarch_call_dummy_address (gdbarch, entry_point_address);
+ set_gdbarch_call_dummy_breakpoint_offset (gdbarch, 0);
+ set_gdbarch_call_dummy_start_offset (gdbarch, 0);
+ set_gdbarch_pc_in_call_dummy (gdbarch, pc_in_call_dummy_at_entry_point);
+ set_gdbarch_call_dummy_stack_adjust_p (gdbarch, 0);
+ set_gdbarch_push_dummy_frame (gdbarch, generic_push_dummy_frame);
+ set_gdbarch_fix_call_dummy (gdbarch, generic_fix_call_dummy);
+
+ set_gdbarch_get_saved_register (gdbarch, generic_get_saved_register);
+
+ set_gdbarch_decr_pc_after_break (gdbarch, 0);
+ set_gdbarch_function_start_offset (gdbarch, 0);
+ set_gdbarch_register_convertible (gdbarch, generic_register_convertible_not);
+
+ set_gdbarch_remote_translate_xfer_address
+ (gdbarch, frv_remote_translate_xfer_address);
+
+ /* Hardware watchpoint / breakpoint support. */
+ switch (info.bfd_arch_info->mach)
+ {
+ case bfd_mach_frv:
+ case bfd_mach_frvsimple:
+ case bfd_mach_fr500:
+ case bfd_mach_frvtomcat:
+ /* fr500-style hardware debugging support. */
+ var->num_hw_watchpoints = 4;
+ var->num_hw_breakpoints = 4;
+ break;
+
+ case bfd_mach_fr400:
+ /* fr400-style hardware debugging support. */
+ var->num_hw_watchpoints = 2;
+ var->num_hw_breakpoints = 4;
+ break;
+
+ default:
+ /* Otherwise, assume we don't have hardware debugging support. */
+ var->num_hw_watchpoints = 0;
+ var->num_hw_breakpoints = 0;
+ break;
+ }
+
+ return gdbarch;
+}
+
+void
+_initialize_frv_tdep (void)
+{
+ register_gdbarch_init (bfd_arch_frv, frv_gdbarch_init);
+
+ tm_print_insn = print_insn_frv;
+}
+
+\f
--- /dev/null
+/* Native-dependent code for OpenBSD/i386.
+ Copyright 2002 Free Software Foundation, Inc.
+
+ This file is part of GDB.
+
+ This program is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 2 of the License, or
+ (at your option) any later version.
+
+ This program is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program; if not, write to the Free Software
+ Foundation, Inc., 59 Temple Place - Suite 330,
+ Boston, MA 02111-1307, USA. */
+
+#include "defs.h"
+
+#include <sys/param.h>
+#include <sys/sysctl.h>
+
+/* Prevent warning from -Wmissing-prototypes. */
+void _initialize_i386obsd_nat (void);
+
+void
+_initialize_i386obsd_nat (void)
+{
+ /* OpenBSD provides a vm.psstrings sysctl that we can use to locate
+ the sigtramp. That way we can still recognize a sigtramp if its
+ location is changed in a new kernel. This is especially
+ important for OpenBSD, since it uses a different memory layout
+ than NetBSD, yet we cannot distinguish between the two.
+
+ Of course this is still based on the assumption that the sigtramp
+ is placed directly under the location where the program arguments
+ and environment can be found. */
+#ifdef VM_PSSTRINGS
+ {
+ struct _ps_strings _ps;
+ int mib[2];
+ size_t len;
+
+ extern CORE_ADDR i386nbsd_sigtramp_start;
+ extern CORE_ADDR i386nbsd_sigtramp_end;
+
+ mib[0] = CTL_VM;
+ mib[1] = VM_PSSTRINGS;
+ len = sizeof (_ps);
+ if (sysctl (mib, 2, &_ps, &len, NULL, 0) == 0)
+ {
+ i386nbsd_sigtramp_start = (CORE_ADDR)_ps.val - 128;
+ i386nbsd_sigtramp_end = (CORE_ADDR)_ps.val;
+ }
+ }
+#endif
+}
--- /dev/null
+/* IP2xxx ELF support for BFD.
+ Copyright (C) 2000, 2002 Free Software Foundation, Inc.
+
+ This file is part of BFD, the Binary File Descriptor library.
+
+ This program is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 2 of the License, or
+ (at your option) any later version.
+
+ This program is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program; if not, write to the Free Software Foundation, Inc.,
+ 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
+
+#ifndef _ELF_IP2K_H
+#define _ELF_IP2K_H
+
+#include "elf/reloc-macros.h"
+
+/* Relocations. */
+START_RELOC_NUMBERS (elf_ip2k_reloc_type)
+ RELOC_NUMBER (R_IP2K_NONE, 0)
+ RELOC_NUMBER (R_IP2K_16, 1)
+ RELOC_NUMBER (R_IP2K_32, 2)
+ RELOC_NUMBER (R_IP2K_FR9, 3)
+ RELOC_NUMBER (R_IP2K_BANK, 4)
+ RELOC_NUMBER (R_IP2K_ADDR16CJP, 5)
+ RELOC_NUMBER (R_IP2K_PAGE3, 6)
+ RELOC_NUMBER (R_IP2K_LO8DATA, 7)
+ RELOC_NUMBER (R_IP2K_HI8DATA, 8)
+ RELOC_NUMBER (R_IP2K_LO8INSN, 9)
+ RELOC_NUMBER (R_IP2K_HI8INSN, 10)
+ RELOC_NUMBER (R_IP2K_PC_SKIP, 11)
+ RELOC_NUMBER (R_IP2K_TEXT, 12)
+ RELOC_NUMBER (R_IP2K_FR_OFFSET, 13)
+ RELOC_NUMBER (R_IP2K_EX8DATA, 14)
+END_RELOC_NUMBERS(R_IP2K_max)
+
+
+/* Define the data & instruction memory discriminator. In a linked
+ executable, an symbol should be deemed to point to an instruction
+ if ((address & IP2K_INSN_MASK) == IP2K_INSN_VALUE), and similarly
+ for the data space. See also `ld/emulparams/elf32ip2k.sh'. */
+/* ??? Consider extending the _MASK values to include all the
+ intermediate bits that must be zero due to the limited physical
+ memory size on the IP2K. */
+
+#define IP2K_DATA_MASK 0xff000000
+#define IP2K_DATA_VALUE 0x01000000
+#define IP2K_INSN_MASK 0xff000000
+#define IP2K_INSN_VALUE 0x02000000
+
+/* The location of the memory mapped hardware stack. */
+#define IP2K_STACK_VALUE 0x0f000000
+#define IP2K_STACK_SIZE 0x20
+
+#endif /* _ELF_IP2K_H */
--- /dev/null
+/* Assembler interface for targets using CGEN. -*- C -*-
+ CGEN: Cpu tools GENerator
+
+THIS FILE IS MACHINE GENERATED WITH CGEN.
+- the resultant file is machine generated, cgen-asm.in isn't
+
+Copyright 1996, 1997, 1998, 1999, 2000, 2001 Free Software Foundation, Inc.
+
+This file is part of the GNU Binutils and GDB, the GNU debugger.
+
+This program is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2, or (at your option)
+any later version.
+
+This program is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with this program; if not, write to the Free Software Foundation, Inc.,
+59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
+
+/* ??? Eventually more and more of this stuff can go to cpu-independent files.
+ Keep that in mind. */
+
+#include "sysdep.h"
+#include <stdio.h>
+#include "ansidecl.h"
+#include "bfd.h"
+#include "symcat.h"
+#include "ip2k-desc.h"
+#include "ip2k-opc.h"
+#include "opintl.h"
+#include "xregex.h"
+#include "libiberty.h"
+#include "safe-ctype.h"
+
+#undef min
+#define min(a,b) ((a) < (b) ? (a) : (b))
+#undef max
+#define max(a,b) ((a) > (b) ? (a) : (b))
+
+static const char * parse_insn_normal
+ PARAMS ((CGEN_CPU_DESC, const CGEN_INSN *, const char **, CGEN_FIELDS *));
+\f
+/* -- assembler routines inserted here. */
+
+/* -- asm.c */
+
+static const char *
+parse_fr (cd, strp, opindex, valuep)
+ CGEN_CPU_DESC cd;
+ const char **strp;
+ int opindex;
+ long *valuep;
+{
+ const char *errmsg;
+ char *old_strp;
+ char *afteroffset;
+ enum cgen_parse_operand_result result_type;
+ bfd_vma value;
+ extern CGEN_KEYWORD ip2k_cgen_opval_register_names;
+ long tempvalue;
+
+ old_strp = *strp;
+ afteroffset = NULL;
+
+
+ /* Check here to see if you're about to try parsing a w as the first arg */
+ /* and return an error if you are. */
+ if ( (strncmp(*strp,"w",1)==0) || (strncmp(*strp,"W",1)==0) )
+ {
+ (*strp)++;
+
+ if ( (strncmp(*strp,",",1)==0) || isspace(**strp) )
+ {
+ /* We've been passed a w. Return with an error message so that */
+ /* cgen will try the next parsing option. */
+ errmsg = _("W keyword invalid in FR operand slot.");
+ return errmsg;
+ }
+ *strp = old_strp;
+ }
+
+
+ /* Attempt parse as register keyword. */
+ /* old_strp = *strp; */
+
+ errmsg = cgen_parse_keyword (cd, strp, & ip2k_cgen_opval_register_names, valuep);
+ if ( *strp != NULL )
+ if (errmsg == NULL)
+ return errmsg;
+
+ /* Attempt to parse for "(IP)" */
+ afteroffset = strstr(*strp,"(IP)");
+
+ if ( afteroffset == NULL)
+ {
+ /* Make sure it's not in lower case */
+ afteroffset = strstr(*strp,"(ip)");
+ }
+
+ if ( afteroffset != NULL )
+ {
+ if ( afteroffset != *strp )
+ {
+ /* Invalid offset present.*/
+ errmsg = _("offset(IP) is not a valid form");
+ return errmsg;
+ }
+ else
+ {
+ *strp += 4;
+ *valuep = 0;
+ errmsg = NULL;
+ return errmsg;
+ }
+ }
+
+ /* Attempt to parse for DP. ex: mov w, offset(DP) */
+ /* mov offset(DP),w */
+
+ /* Try parsing it as an address and see what comes back */
+
+ afteroffset = strstr(*strp,"(DP)");
+
+ if ( afteroffset == NULL)
+ {
+ /* Maybe it's in lower case */
+ afteroffset = strstr(*strp,"(dp)");
+ }
+
+ if ( afteroffset != NULL )
+ {
+ if ( afteroffset == *strp )
+ {
+ /* No offset present. Use 0 by default. */
+ tempvalue = 0;
+ errmsg = NULL;
+ }
+ else
+ {
+ errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_IP2K_FR_OFFSET,
+ & result_type, & tempvalue);
+ }
+
+ if (errmsg == NULL)
+ {
+ if ( (tempvalue >= 0) && (tempvalue <= 127) )
+ {
+ /* Value is ok. Fix up the first 2 bits and return */
+ *valuep = 0x0100 | tempvalue;
+ *strp += 4; /* skip over the (DP) in *strp */
+ return errmsg;
+ } else
+ {
+ /* Found something there in front of (DP) but it's out of range. */
+ errmsg = _("(DP) offset out of range.");
+ return errmsg;
+ }
+
+ }
+ }
+
+
+ /* Attempt to parse for SP. ex: mov w, offset(SP) */
+ /* mov offset(SP), w */
+
+
+ afteroffset = strstr(*strp,"(SP)");
+
+ if (afteroffset == NULL)
+ {
+ /* Maybe it's in lower case. */
+ afteroffset = strstr(*strp, "(sp)");
+ }
+
+ if ( afteroffset != NULL )
+ {
+ if ( afteroffset == *strp )
+ {
+ /* No offset present. Use 0 by default. */
+ tempvalue = 0;
+ errmsg = NULL;
+ }
+ else
+ {
+ errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_IP2K_FR_OFFSET,
+ & result_type, & tempvalue);
+ }
+ if (errmsg == NULL)
+ {
+ if ( (tempvalue >= 0) && (tempvalue <= 127) )
+ {
+ /* Value is ok. Fix up the first 2 bits and return */
+ *valuep = 0x0180 | tempvalue;
+ *strp += 4; /* skip over the (SP) in *strp */
+ return errmsg;
+ } else
+ {
+ /* Found something there in front of (SP) but it's out of range. */
+ errmsg = _("(SP) offset out of range.");
+ return errmsg;
+ }
+
+ }
+ }
+
+
+ /* Attempt to parse as an address. */
+ *strp = old_strp;
+ errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_IP2K_FR9,
+ & result_type, & value);
+ if (errmsg == NULL)
+ {
+ *valuep = value;
+
+ /* if a parenthesis is found, warn about invalid form */
+
+ if (**strp == '(')
+ {
+ errmsg = _("illegal use of parentheses");
+ }
+ /* if a numeric value is specified, ensure that it is between 1 and 255 */
+ else if (result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER)
+ {
+ if (value < 0x1 || value > 0xff)
+ errmsg = _("operand out of range (not between 1 and 255)");
+ }
+ }
+ return errmsg;
+}
+
+static const char *
+parse_addr16 (cd, strp, opindex, valuep)
+ CGEN_CPU_DESC cd;
+ const char **strp;
+ int opindex;
+ long *valuep;
+{
+ const char *errmsg;
+ enum cgen_parse_operand_result result_type;
+ bfd_reloc_code_real_type code = BFD_RELOC_NONE;
+ long value;
+
+ if ( opindex == (CGEN_OPERAND_TYPE)IP2K_OPERAND_ADDR16H )
+ code = BFD_RELOC_IP2K_HI8DATA;
+ else if ( opindex == (CGEN_OPERAND_TYPE)IP2K_OPERAND_ADDR16L )
+ code = BFD_RELOC_IP2K_LO8DATA;
+ else
+ {
+ /* Something is very wrong. opindex has to be one of the above. */
+ errmsg = _("parse_addr16: invalid opindex.");
+ return errmsg;
+ }
+
+ errmsg = cgen_parse_address (cd, strp, opindex, code,
+ & result_type, & value);
+ if (errmsg == NULL)
+ {
+ /* We either have a relocation or a number now. */
+ if ( result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER )
+ {
+ /* We got a number back. */
+ if ( code == BFD_RELOC_IP2K_HI8DATA )
+ value >>= 8;
+ else /* code = BFD_RELOC_IP2K_LOW8DATA */
+ value &= 0x00FF;
+ }
+ *valuep = value;
+ }
+
+ return errmsg;
+}
+
+
+ static const char *
+ parse_addr16_p (cd, strp, opindex, valuep)
+ CGEN_CPU_DESC cd;
+ const char **strp;
+ int opindex;
+ long *valuep;
+ {
+ const char *errmsg;
+ enum cgen_parse_operand_result result_type;
+ bfd_reloc_code_real_type code = BFD_RELOC_IP2K_PAGE3;
+ long value;
+
+ errmsg = cgen_parse_address (cd, strp, opindex, code,
+ & result_type, & value);
+ if (errmsg == NULL)
+ {
+ if ( result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER )
+ *valuep = (value >> 13) & 0x7;
+ else if ( result_type == CGEN_PARSE_OPERAND_RESULT_QUEUED )
+ *valuep = value;
+ }
+ return errmsg;
+ }
+
+
+ static const char *
+ parse_addr16_cjp (cd, strp, opindex, valuep)
+ CGEN_CPU_DESC cd;
+ const char **strp;
+ int opindex;
+ long *valuep;
+ {
+ const char *errmsg;
+ enum cgen_parse_operand_result result_type;
+ bfd_reloc_code_real_type code = BFD_RELOC_NONE;
+ long value;
+
+ if ( opindex == (CGEN_OPERAND_TYPE)IP2K_OPERAND_ADDR16CJP )
+ code = BFD_RELOC_IP2K_ADDR16CJP;
+ else if ( opindex == (CGEN_OPERAND_TYPE)IP2K_OPERAND_ADDR16P )
+ code = BFD_RELOC_IP2K_PAGE3;
+
+ errmsg = cgen_parse_address (cd, strp, opindex, code,
+ & result_type, & value);
+ if (errmsg == NULL)
+ {
+ if ( result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER )
+ {
+ if ( (value & 0x1) == 0) /* If the address is even .... */
+ {
+ if ( opindex == (CGEN_OPERAND_TYPE)IP2K_OPERAND_ADDR16CJP )
+ *valuep = (value >> 1) & 0x1FFF; /* Should mask be 1FFF? */
+ else if ( opindex == (CGEN_OPERAND_TYPE)IP2K_OPERAND_ADDR16P )
+ *valuep = (value >> 14) & 0x7;
+ }
+ else
+ errmsg = _("Byte address required. - must be even.");
+ }else if ( result_type == CGEN_PARSE_OPERAND_RESULT_QUEUED )
+ {
+ /* This will happen for things like (s2-s1) where s2 and s1 */
+ /* are labels. */
+ *valuep = value;
+ }
+ else
+ errmsg = _("cgen_parse_address returned a symbol. Literal required.");
+ }
+ return errmsg;
+ }
+
+
+static const char *
+parse_lit8 (cd, strp, opindex, valuep)
+ CGEN_CPU_DESC cd;
+ const char **strp;
+ int opindex;
+ long *valuep;
+{
+ const char *errmsg;
+ enum cgen_parse_operand_result result_type;
+ bfd_reloc_code_real_type code = BFD_RELOC_NONE;
+ long value;
+
+ /* Parse %OP relocating operators. */
+ if (strncmp (*strp, "%bank", 5) == 0)
+ {
+ *strp += 5;
+ code = BFD_RELOC_IP2K_BANK;
+ }
+ else if (strncmp (*strp, "%lo8data", 8) == 0)
+ {
+ *strp += 8;
+ code = BFD_RELOC_IP2K_LO8DATA;
+ }
+ else if (strncmp (*strp, "%hi8data", 8) == 0)
+ {
+ *strp += 8;
+ code = BFD_RELOC_IP2K_HI8DATA;
+ }
+ else if (strncmp (*strp, "%ex8data", 8) == 0)
+ {
+ *strp += 8;
+ code = BFD_RELOC_IP2K_EX8DATA;
+ }
+ else if (strncmp (*strp, "%lo8insn", 8) == 0)
+ {
+ *strp += 8;
+ code = BFD_RELOC_IP2K_LO8INSN;
+ }
+ else if (strncmp (*strp, "%hi8insn", 8) == 0)
+ {
+ *strp += 8;
+ code = BFD_RELOC_IP2K_HI8INSN;
+ }
+
+
+ /* Parse %op operand. */
+ if (code != BFD_RELOC_NONE)
+ {
+ errmsg = cgen_parse_address (cd, strp, opindex, code,
+ & result_type, & value);
+ if ((errmsg == NULL) &&
+ (result_type != CGEN_PARSE_OPERAND_RESULT_QUEUED))
+ errmsg = _("%operator operand is not a symbol");
+
+ *valuep = value;
+ }
+ /* Parse as a number. */
+ else
+ {
+ errmsg = cgen_parse_signed_integer (cd, strp, opindex, valuep);
+
+ /* Truncate to eight bits to accept both signed and unsigned input. */
+ if (errmsg == NULL)
+ *valuep &= 0xFF;
+ }
+
+ return errmsg;
+}
+
+static const char *
+parse_bit3 (cd, strp, opindex, valuep)
+ CGEN_CPU_DESC cd;
+ const char **strp;
+ int opindex;
+ long *valuep;
+{
+ const char *errmsg;
+ char mode = 0;
+ long count = 0;
+ unsigned long value;
+
+ if (strncmp (*strp, "%bit", 4) == 0)
+ {
+ *strp += 4;
+ mode = 1;
+ }
+ else if (strncmp (*strp, "%msbbit", 7) == 0)
+ {
+ *strp += 7;
+ mode = 1;
+ }
+ else if (strncmp (*strp, "%lsbbit", 7) == 0)
+ {
+ *strp += 7;
+ mode = 2;
+ }
+
+ errmsg = cgen_parse_signed_integer (cd, strp, opindex, valuep);
+ if (errmsg) {
+ return errmsg;
+ }
+
+ if (mode) {
+ value = (unsigned long) *valuep;
+ if (value == 0) {
+ errmsg = _("Attempt to find bit index of 0");
+ return errmsg;
+ }
+
+ if (mode == 1) {
+ count = 31;
+ while ((value & 0x80000000) == 0) {
+ count--;
+ value <<= 1;
+ }
+ } else if (mode == 2) {
+ count = 0;
+ while ((value & 0x00000001) == 0) {
+ count++;
+ value >>= 1;
+ }
+ }
+
+ *valuep = count;
+ }
+
+ return errmsg;
+}
+
+
+/* -- dis.c */
+
+const char * ip2k_cgen_parse_operand
+ PARAMS ((CGEN_CPU_DESC, int, const char **, CGEN_FIELDS *));
+
+/* Main entry point for operand parsing.
+
+ This function is basically just a big switch statement. Earlier versions
+ used tables to look up the function to use, but
+ - if the table contains both assembler and disassembler functions then
+ the disassembler contains much of the assembler and vice-versa,
+ - there's a lot of inlining possibilities as things grow,
+ - using a switch statement avoids the function call overhead.
+
+ This function could be moved into `parse_insn_normal', but keeping it
+ separate makes clear the interface between `parse_insn_normal' and each of
+ the handlers. */
+
+const char *
+ip2k_cgen_parse_operand (cd, opindex, strp, fields)
+ CGEN_CPU_DESC cd;
+ int opindex;
+ const char ** strp;
+ CGEN_FIELDS * fields;
+{
+ const char * errmsg = NULL;
+ /* Used by scalar operands that still need to be parsed. */
+ long junk ATTRIBUTE_UNUSED;
+
+ switch (opindex)
+ {
+ case IP2K_OPERAND_ADDR16CJP :
+ errmsg = parse_addr16_cjp (cd, strp, IP2K_OPERAND_ADDR16CJP, &fields->f_addr16cjp);
+ break;
+ case IP2K_OPERAND_ADDR16H :
+ errmsg = parse_addr16 (cd, strp, IP2K_OPERAND_ADDR16H, &fields->f_imm8);
+ break;
+ case IP2K_OPERAND_ADDR16L :
+ errmsg = parse_addr16 (cd, strp, IP2K_OPERAND_ADDR16L, &fields->f_imm8);
+ break;
+ case IP2K_OPERAND_ADDR16P :
+ errmsg = parse_addr16_cjp (cd, strp, IP2K_OPERAND_ADDR16P, &fields->f_page3);
+ break;
+ case IP2K_OPERAND_BITNO :
+ errmsg = parse_bit3 (cd, strp, IP2K_OPERAND_BITNO, &fields->f_bitno);
+ break;
+ case IP2K_OPERAND_CBIT :
+ errmsg = cgen_parse_unsigned_integer (cd, strp, IP2K_OPERAND_CBIT, &junk);
+ break;
+ case IP2K_OPERAND_DCBIT :
+ errmsg = cgen_parse_unsigned_integer (cd, strp, IP2K_OPERAND_DCBIT, &junk);
+ break;
+ case IP2K_OPERAND_FR :
+ errmsg = parse_fr (cd, strp, IP2K_OPERAND_FR, &fields->f_reg);
+ break;
+ case IP2K_OPERAND_LIT8 :
+ errmsg = parse_lit8 (cd, strp, IP2K_OPERAND_LIT8, &fields->f_imm8);
+ break;
+ case IP2K_OPERAND_PABITS :
+ errmsg = cgen_parse_unsigned_integer (cd, strp, IP2K_OPERAND_PABITS, &junk);
+ break;
+ case IP2K_OPERAND_RETI3 :
+ errmsg = cgen_parse_unsigned_integer (cd, strp, IP2K_OPERAND_RETI3, &fields->f_reti3);
+ break;
+ case IP2K_OPERAND_ZBIT :
+ errmsg = cgen_parse_unsigned_integer (cd, strp, IP2K_OPERAND_ZBIT, &junk);
+ break;
+
+ default :
+ /* xgettext:c-format */
+ fprintf (stderr, _("Unrecognized field %d while parsing.\n"), opindex);
+ abort ();
+ }
+
+ return errmsg;
+}
+
+cgen_parse_fn * const ip2k_cgen_parse_handlers[] =
+{
+ parse_insn_normal,
+};
+
+void
+ip2k_cgen_init_asm (cd)
+ CGEN_CPU_DESC cd;
+{
+ ip2k_cgen_init_opcode_table (cd);
+ ip2k_cgen_init_ibld_table (cd);
+ cd->parse_handlers = & ip2k_cgen_parse_handlers[0];
+ cd->parse_operand = ip2k_cgen_parse_operand;
+}
+
+\f
+
+/* Regex construction routine.
+
+ This translates an opcode syntax string into a regex string,
+ by replacing any non-character syntax element (such as an
+ opcode) with the pattern '.*'
+
+ It then compiles the regex and stores it in the opcode, for
+ later use by ip2k_cgen_assemble_insn
+
+ Returns NULL for success, an error message for failure. */
+
+char *
+ip2k_cgen_build_insn_regex (insn)
+ CGEN_INSN *insn;
+{
+ CGEN_OPCODE *opc = (CGEN_OPCODE *) CGEN_INSN_OPCODE (insn);
+ const char *mnem = CGEN_INSN_MNEMONIC (insn);
+ char rxbuf[CGEN_MAX_RX_ELEMENTS];
+ char *rx = rxbuf;
+ const CGEN_SYNTAX_CHAR_TYPE *syn;
+ int reg_err;
+
+ syn = CGEN_SYNTAX_STRING (CGEN_OPCODE_SYNTAX (opc));
+
+ /* Mnemonics come first in the syntax string. */
+ if (! CGEN_SYNTAX_MNEMONIC_P (* syn))
+ return _("missing mnemonic in syntax string");
+ ++syn;
+
+ /* Generate a case sensitive regular expression that emulates case
+ insensitive matching in the "C" locale. We cannot generate a case
+ insensitive regular expression because in Turkish locales, 'i' and 'I'
+ are not equal modulo case conversion. */
+
+ /* Copy the literal mnemonic out of the insn. */
+ for (; *mnem; mnem++)
+ {
+ char c = *mnem;
+
+ if (ISALPHA (c))
+ {
+ *rx++ = '[';
+ *rx++ = TOLOWER (c);
+ *rx++ = TOUPPER (c);
+ *rx++ = ']';
+ }
+ else
+ *rx++ = c;
+ }
+
+ /* Copy any remaining literals from the syntax string into the rx. */
+ for(; * syn != 0 && rx <= rxbuf + (CGEN_MAX_RX_ELEMENTS - 7 - 4); ++syn)
+ {
+ if (CGEN_SYNTAX_CHAR_P (* syn))
+ {
+ char c = CGEN_SYNTAX_CHAR (* syn);
+
+ switch (c)
+ {
+ /* Escape any regex metacharacters in the syntax. */
+ case '.': case '[': case '\\':
+ case '*': case '^': case '$':
+
+#ifdef CGEN_ESCAPE_EXTENDED_REGEX
+ case '?': case '{': case '}':
+ case '(': case ')': case '*':
+ case '|': case '+': case ']':
+#endif
+ *rx++ = '\\';
+ *rx++ = c;
+ break;
+
+ default:
+ if (ISALPHA (c))
+ {
+ *rx++ = '[';
+ *rx++ = TOLOWER (c);
+ *rx++ = TOUPPER (c);
+ *rx++ = ']';
+ }
+ else
+ *rx++ = c;
+ break;
+ }
+ }
+ else
+ {
+ /* Replace non-syntax fields with globs. */
+ *rx++ = '.';
+ *rx++ = '*';
+ }
+ }
+
+ /* Trailing whitespace ok. */
+ * rx++ = '[';
+ * rx++ = ' ';
+ * rx++ = '\t';
+ * rx++ = ']';
+ * rx++ = '*';
+
+ /* But anchor it after that. */
+ * rx++ = '$';
+ * rx = '\0';
+
+ CGEN_INSN_RX (insn) = xmalloc (sizeof (regex_t));
+ reg_err = regcomp ((regex_t *) CGEN_INSN_RX (insn), rxbuf, REG_NOSUB);
+
+ if (reg_err == 0)
+ return NULL;
+ else
+ {
+ static char msg[80];
+
+ regerror (reg_err, (regex_t *) CGEN_INSN_RX (insn), msg, 80);
+ regfree ((regex_t *) CGEN_INSN_RX (insn));
+ free (CGEN_INSN_RX (insn));
+ (CGEN_INSN_RX (insn)) = NULL;
+ return msg;
+ }
+}
+
+\f
+/* Default insn parser.
+
+ The syntax string is scanned and operands are parsed and stored in FIELDS.
+ Relocs are queued as we go via other callbacks.
+
+ ??? Note that this is currently an all-or-nothing parser. If we fail to
+ parse the instruction, we return 0 and the caller will start over from
+ the beginning. Backtracking will be necessary in parsing subexpressions,
+ but that can be handled there. Not handling backtracking here may get
+ expensive in the case of the m68k. Deal with later.
+
+ Returns NULL for success, an error message for failure. */
+
+static const char *
+parse_insn_normal (cd, insn, strp, fields)
+ CGEN_CPU_DESC cd;
+ const CGEN_INSN *insn;
+ const char **strp;
+ CGEN_FIELDS *fields;
+{
+ /* ??? Runtime added insns not handled yet. */
+ const CGEN_SYNTAX *syntax = CGEN_INSN_SYNTAX (insn);
+ const char *str = *strp;
+ const char *errmsg;
+ const char *p;
+ const CGEN_SYNTAX_CHAR_TYPE * syn;
+#ifdef CGEN_MNEMONIC_OPERANDS
+ /* FIXME: wip */
+ int past_opcode_p;
+#endif
+
+ /* For now we assume the mnemonic is first (there are no leading operands).
+ We can parse it without needing to set up operand parsing.
+ GAS's input scrubber will ensure mnemonics are lowercase, but we may
+ not be called from GAS. */
+ p = CGEN_INSN_MNEMONIC (insn);
+ while (*p && TOLOWER (*p) == TOLOWER (*str))
+ ++p, ++str;
+
+ if (* p)
+ return _("unrecognized instruction");
+
+#ifndef CGEN_MNEMONIC_OPERANDS
+ if (* str && ! ISSPACE (* str))
+ return _("unrecognized instruction");
+#endif
+
+ CGEN_INIT_PARSE (cd);
+ cgen_init_parse_operand (cd);
+#ifdef CGEN_MNEMONIC_OPERANDS
+ past_opcode_p = 0;
+#endif
+
+ /* We don't check for (*str != '\0') here because we want to parse
+ any trailing fake arguments in the syntax string. */
+ syn = CGEN_SYNTAX_STRING (syntax);
+
+ /* Mnemonics come first for now, ensure valid string. */
+ if (! CGEN_SYNTAX_MNEMONIC_P (* syn))
+ abort ();
+
+ ++syn;
+
+ while (* syn != 0)
+ {
+ /* Non operand chars must match exactly. */
+ if (CGEN_SYNTAX_CHAR_P (* syn))
+ {
+ /* FIXME: While we allow for non-GAS callers above, we assume the
+ first char after the mnemonic part is a space. */
+ /* FIXME: We also take inappropriate advantage of the fact that
+ GAS's input scrubber will remove extraneous blanks. */
+ if (TOLOWER (*str) == TOLOWER (CGEN_SYNTAX_CHAR (* syn)))
+ {
+#ifdef CGEN_MNEMONIC_OPERANDS
+ if (CGEN_SYNTAX_CHAR(* syn) == ' ')
+ past_opcode_p = 1;
+#endif
+ ++ syn;
+ ++ str;
+ }
+ else if (*str)
+ {
+ /* Syntax char didn't match. Can't be this insn. */
+ static char msg [80];
+
+ /* xgettext:c-format */
+ sprintf (msg, _("syntax error (expected char `%c', found `%c')"),
+ CGEN_SYNTAX_CHAR(*syn), *str);
+ return msg;
+ }
+ else
+ {
+ /* Ran out of input. */
+ static char msg [80];
+
+ /* xgettext:c-format */
+ sprintf (msg, _("syntax error (expected char `%c', found end of instruction)"),
+ CGEN_SYNTAX_CHAR(*syn));
+ return msg;
+ }
+ continue;
+ }
+
+ /* We have an operand of some sort. */
+ errmsg = cd->parse_operand (cd, CGEN_SYNTAX_FIELD (*syn),
+ &str, fields);
+ if (errmsg)
+ return errmsg;
+
+ /* Done with this operand, continue with next one. */
+ ++ syn;
+ }
+
+ /* If we're at the end of the syntax string, we're done. */
+ if (* syn == 0)
+ {
+ /* FIXME: For the moment we assume a valid `str' can only contain
+ blanks now. IE: We needn't try again with a longer version of
+ the insn and it is assumed that longer versions of insns appear
+ before shorter ones (eg: lsr r2,r3,1 vs lsr r2,r3). */
+ while (ISSPACE (* str))
+ ++ str;
+
+ if (* str != '\0')
+ return _("junk at end of line"); /* FIXME: would like to include `str' */
+
+ return NULL;
+ }
+
+ /* We couldn't parse it. */
+ return _("unrecognized instruction");
+}
+\f
+/* Main entry point.
+ This routine is called for each instruction to be assembled.
+ STR points to the insn to be assembled.
+ We assume all necessary tables have been initialized.
+ The assembled instruction, less any fixups, is stored in BUF.
+ Remember that if CGEN_INT_INSN_P then BUF is an int and thus the value
+ still needs to be converted to target byte order, otherwise BUF is an array
+ of bytes in target byte order.
+ The result is a pointer to the insn's entry in the opcode table,
+ or NULL if an error occured (an error message will have already been
+ printed).
+
+ Note that when processing (non-alias) macro-insns,
+ this function recurses.
+
+ ??? It's possible to make this cpu-independent.
+ One would have to deal with a few minor things.
+ At this point in time doing so would be more of a curiosity than useful
+ [for example this file isn't _that_ big], but keeping the possibility in
+ mind helps keep the design clean. */
+
+const CGEN_INSN *
+ip2k_cgen_assemble_insn (cd, str, fields, buf, errmsg)
+ CGEN_CPU_DESC cd;
+ const char *str;
+ CGEN_FIELDS *fields;
+ CGEN_INSN_BYTES_PTR buf;
+ char **errmsg;
+{
+ const char *start;
+ CGEN_INSN_LIST *ilist;
+ const char *parse_errmsg = NULL;
+ const char *insert_errmsg = NULL;
+ int recognized_mnemonic = 0;
+
+ /* Skip leading white space. */
+ while (ISSPACE (* str))
+ ++ str;
+
+ /* The instructions are stored in hashed lists.
+ Get the first in the list. */
+ ilist = CGEN_ASM_LOOKUP_INSN (cd, str);
+
+ /* Keep looking until we find a match. */
+ start = str;
+ for ( ; ilist != NULL ; ilist = CGEN_ASM_NEXT_INSN (ilist))
+ {
+ const CGEN_INSN *insn = ilist->insn;
+ recognized_mnemonic = 1;
+
+#ifdef CGEN_VALIDATE_INSN_SUPPORTED
+ /* Not usually needed as unsupported opcodes
+ shouldn't be in the hash lists. */
+ /* Is this insn supported by the selected cpu? */
+ if (! ip2k_cgen_insn_supported (cd, insn))
+ continue;
+#endif
+ /* If the RELAX attribute is set, this is an insn that shouldn't be
+ chosen immediately. Instead, it is used during assembler/linker
+ relaxation if possible. */
+ if (CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_RELAX) != 0)
+ continue;
+
+ str = start;
+
+ /* Skip this insn if str doesn't look right lexically. */
+ if (CGEN_INSN_RX (insn) != NULL &&
+ regexec ((regex_t *) CGEN_INSN_RX (insn), str, 0, NULL, 0) == REG_NOMATCH)
+ continue;
+
+ /* Allow parse/insert handlers to obtain length of insn. */
+ CGEN_FIELDS_BITSIZE (fields) = CGEN_INSN_BITSIZE (insn);
+
+ parse_errmsg = CGEN_PARSE_FN (cd, insn) (cd, insn, & str, fields);
+ if (parse_errmsg != NULL)
+ continue;
+
+ /* ??? 0 is passed for `pc'. */
+ insert_errmsg = CGEN_INSERT_FN (cd, insn) (cd, insn, fields, buf,
+ (bfd_vma) 0);
+ if (insert_errmsg != NULL)
+ continue;
+
+ /* It is up to the caller to actually output the insn and any
+ queued relocs. */
+ return insn;
+ }
+
+ {
+ static char errbuf[150];
+#ifdef CGEN_VERBOSE_ASSEMBLER_ERRORS
+ const char *tmp_errmsg;
+
+ /* If requesting verbose error messages, use insert_errmsg.
+ Failing that, use parse_errmsg. */
+ tmp_errmsg = (insert_errmsg ? insert_errmsg :
+ parse_errmsg ? parse_errmsg :
+ recognized_mnemonic ?
+ _("unrecognized form of instruction") :
+ _("unrecognized instruction"));
+
+ if (strlen (start) > 50)
+ /* xgettext:c-format */
+ sprintf (errbuf, "%s `%.50s...'", tmp_errmsg, start);
+ else
+ /* xgettext:c-format */
+ sprintf (errbuf, "%s `%.50s'", tmp_errmsg, start);
+#else
+ if (strlen (start) > 50)
+ /* xgettext:c-format */
+ sprintf (errbuf, _("bad instruction `%.50s...'"), start);
+ else
+ /* xgettext:c-format */
+ sprintf (errbuf, _("bad instruction `%.50s'"), start);
+#endif
+
+ *errmsg = errbuf;
+ return NULL;
+ }
+}
+\f
+#if 0 /* This calls back to GAS which we can't do without care. */
+
+/* Record each member of OPVALS in the assembler's symbol table.
+ This lets GAS parse registers for us.
+ ??? Interesting idea but not currently used. */
+
+/* Record each member of OPVALS in the assembler's symbol table.
+ FIXME: Not currently used. */
+
+void
+ip2k_cgen_asm_hash_keywords (cd, opvals)
+ CGEN_CPU_DESC cd;
+ CGEN_KEYWORD *opvals;
+{
+ CGEN_KEYWORD_SEARCH search = cgen_keyword_search_init (opvals, NULL);
+ const CGEN_KEYWORD_ENTRY * ke;
+
+ while ((ke = cgen_keyword_search_next (& search)) != NULL)
+ {
+#if 0 /* Unnecessary, should be done in the search routine. */
+ if (! ip2k_cgen_opval_supported (ke))
+ continue;
+#endif
+ cgen_asm_record_register (cd, ke->name, ke->value);
+ }
+}
+
+#endif /* 0 */
--- /dev/null
+/* CPU data for ip2k.
+
+THIS FILE IS MACHINE GENERATED WITH CGEN.
+
+Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc.
+
+This file is part of the GNU Binutils and/or GDB, the GNU debugger.
+
+This program is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2, or (at your option)
+any later version.
+
+This program is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License along
+with this program; if not, write to the Free Software Foundation, Inc.,
+59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+
+*/
+
+#include "sysdep.h"
+#include <stdio.h>
+#include <stdarg.h>
+#include "ansidecl.h"
+#include "bfd.h"
+#include "symcat.h"
+#include "ip2k-desc.h"
+#include "ip2k-opc.h"
+#include "opintl.h"
+#include "libiberty.h"
+
+/* Attributes. */
+
+static const CGEN_ATTR_ENTRY bool_attr[] =
+{
+ { "#f", 0 },
+ { "#t", 1 },
+ { 0, 0 }
+};
+
+static const CGEN_ATTR_ENTRY MACH_attr[] =
+{
+ { "base", MACH_BASE },
+ { "ip2022", MACH_IP2022 },
+ { "ip2022ext", MACH_IP2022EXT },
+ { "max", MACH_MAX },
+ { 0, 0 }
+};
+
+static const CGEN_ATTR_ENTRY ISA_attr[] =
+{
+ { "ip2k", ISA_IP2K },
+ { "max", ISA_MAX },
+ { 0, 0 }
+};
+
+const CGEN_ATTR_TABLE ip2k_cgen_ifield_attr_table[] =
+{
+ { "MACH", & MACH_attr[0], & MACH_attr[0] },
+ { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
+ { "PCREL-ADDR", &bool_attr[0], &bool_attr[0] },
+ { "ABS-ADDR", &bool_attr[0], &bool_attr[0] },
+ { "RESERVED", &bool_attr[0], &bool_attr[0] },
+ { "SIGN-OPT", &bool_attr[0], &bool_attr[0] },
+ { "SIGNED", &bool_attr[0], &bool_attr[0] },
+ { 0, 0, 0 }
+};
+
+const CGEN_ATTR_TABLE ip2k_cgen_hardware_attr_table[] =
+{
+ { "MACH", & MACH_attr[0], & MACH_attr[0] },
+ { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
+ { "CACHE-ADDR", &bool_attr[0], &bool_attr[0] },
+ { "PC", &bool_attr[0], &bool_attr[0] },
+ { "PROFILE", &bool_attr[0], &bool_attr[0] },
+ { 0, 0, 0 }
+};
+
+const CGEN_ATTR_TABLE ip2k_cgen_operand_attr_table[] =
+{
+ { "MACH", & MACH_attr[0], & MACH_attr[0] },
+ { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
+ { "PCREL-ADDR", &bool_attr[0], &bool_attr[0] },
+ { "ABS-ADDR", &bool_attr[0], &bool_attr[0] },
+ { "SIGN-OPT", &bool_attr[0], &bool_attr[0] },
+ { "SIGNED", &bool_attr[0], &bool_attr[0] },
+ { "NEGATIVE", &bool_attr[0], &bool_attr[0] },
+ { "RELAX", &bool_attr[0], &bool_attr[0] },
+ { "SEM-ONLY", &bool_attr[0], &bool_attr[0] },
+ { 0, 0, 0 }
+};
+
+const CGEN_ATTR_TABLE ip2k_cgen_insn_attr_table[] =
+{
+ { "MACH", & MACH_attr[0], & MACH_attr[0] },
+ { "ALIAS", &bool_attr[0], &bool_attr[0] },
+ { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
+ { "UNCOND-CTI", &bool_attr[0], &bool_attr[0] },
+ { "COND-CTI", &bool_attr[0], &bool_attr[0] },
+ { "SKIP-CTI", &bool_attr[0], &bool_attr[0] },
+ { "DELAY-SLOT", &bool_attr[0], &bool_attr[0] },
+ { "RELAXABLE", &bool_attr[0], &bool_attr[0] },
+ { "RELAX", &bool_attr[0], &bool_attr[0] },
+ { "NO-DIS", &bool_attr[0], &bool_attr[0] },
+ { "PBB", &bool_attr[0], &bool_attr[0] },
+ { "EXT-SKIP-INSN", &bool_attr[0], &bool_attr[0] },
+ { "SKIPA", &bool_attr[0], &bool_attr[0] },
+ { 0, 0, 0 }
+};
+
+/* Instruction set variants. */
+
+static const CGEN_ISA ip2k_cgen_isa_table[] = {
+ { "ip2k", 16, 16, 16, 16 },
+ { 0, 0, 0, 0, 0 }
+};
+
+/* Machine variants. */
+
+static const CGEN_MACH ip2k_cgen_mach_table[] = {
+ { "ip2022", "ip2022", MACH_IP2022, 0 },
+ { "ip2022ext", "ip2022ext", MACH_IP2022EXT, 0 },
+ { 0, 0, 0, 0 }
+};
+
+static CGEN_KEYWORD_ENTRY ip2k_cgen_opval_register_names_entries[] =
+{
+ { "ADDRSEL", 2, {0, {0}}, 0, 0 },
+ { "ADDRX", 3, {0, {0}}, 0, 0 },
+ { "IPH", 4, {0, {0}}, 0, 0 },
+ { "IPL", 5, {0, {0}}, 0, 0 },
+ { "SPH", 6, {0, {0}}, 0, 0 },
+ { "SPL", 7, {0, {0}}, 0, 0 },
+ { "PCH", 8, {0, {0}}, 0, 0 },
+ { "PCL", 9, {0, {0}}, 0, 0 },
+ { "WREG", 10, {0, {0}}, 0, 0 },
+ { "STATUS", 11, {0, {0}}, 0, 0 },
+ { "DPH", 12, {0, {0}}, 0, 0 },
+ { "DPL", 13, {0, {0}}, 0, 0 },
+ { "SPDREG", 14, {0, {0}}, 0, 0 },
+ { "MULH", 15, {0, {0}}, 0, 0 },
+ { "ADDRH", 16, {0, {0}}, 0, 0 },
+ { "ADDRL", 17, {0, {0}}, 0, 0 },
+ { "DATAH", 18, {0, {0}}, 0, 0 },
+ { "DATAL", 19, {0, {0}}, 0, 0 },
+ { "INTVECH", 20, {0, {0}}, 0, 0 },
+ { "INTVECL", 21, {0, {0}}, 0, 0 },
+ { "INTSPD", 22, {0, {0}}, 0, 0 },
+ { "INTF", 23, {0, {0}}, 0, 0 },
+ { "INTE", 24, {0, {0}}, 0, 0 },
+ { "INTED", 25, {0, {0}}, 0, 0 },
+ { "FCFG", 26, {0, {0}}, 0, 0 },
+ { "TCTRL", 27, {0, {0}}, 0, 0 },
+ { "XCFG", 28, {0, {0}}, 0, 0 },
+ { "EMCFG", 29, {0, {0}}, 0, 0 },
+ { "IPCH", 30, {0, {0}}, 0, 0 },
+ { "IPCL", 31, {0, {0}}, 0, 0 },
+ { "RAIN", 32, {0, {0}}, 0, 0 },
+ { "RAOUT", 33, {0, {0}}, 0, 0 },
+ { "RADIR", 34, {0, {0}}, 0, 0 },
+ { "LFSRH", 35, {0, {0}}, 0, 0 },
+ { "RBIN", 36, {0, {0}}, 0, 0 },
+ { "RBOUT", 37, {0, {0}}, 0, 0 },
+ { "RBDIR", 38, {0, {0}}, 0, 0 },
+ { "LFSRL", 39, {0, {0}}, 0, 0 },
+ { "RCIN", 40, {0, {0}}, 0, 0 },
+ { "RCOUT", 41, {0, {0}}, 0, 0 },
+ { "RCDIR", 42, {0, {0}}, 0, 0 },
+ { "LFSRA", 43, {0, {0}}, 0, 0 },
+ { "RDIN", 44, {0, {0}}, 0, 0 },
+ { "RDOUT", 45, {0, {0}}, 0, 0 },
+ { "RDDIR", 46, {0, {0}}, 0, 0 },
+ { "REIN", 48, {0, {0}}, 0, 0 },
+ { "REOUT", 49, {0, {0}}, 0, 0 },
+ { "REDIR", 50, {0, {0}}, 0, 0 },
+ { "RFIN", 52, {0, {0}}, 0, 0 },
+ { "RFOUT", 53, {0, {0}}, 0, 0 },
+ { "RFDIR", 54, {0, {0}}, 0, 0 },
+ { "RGOUT", 57, {0, {0}}, 0, 0 },
+ { "RGDIR", 58, {0, {0}}, 0, 0 },
+ { "RTTMR", 64, {0, {0}}, 0, 0 },
+ { "RTCFG", 65, {0, {0}}, 0, 0 },
+ { "T0TMR", 66, {0, {0}}, 0, 0 },
+ { "T0CFG", 67, {0, {0}}, 0, 0 },
+ { "T1CNTH", 68, {0, {0}}, 0, 0 },
+ { "T1CNTL", 69, {0, {0}}, 0, 0 },
+ { "T1CAP1H", 70, {0, {0}}, 0, 0 },
+ { "T1CAP1L", 71, {0, {0}}, 0, 0 },
+ { "T1CAP2H", 72, {0, {0}}, 0, 0 },
+ { "T1CMP2H", 72, {0, {0}}, 0, 0 },
+ { "T1CAP2L", 73, {0, {0}}, 0, 0 },
+ { "T1CMP2L", 73, {0, {0}}, 0, 0 },
+ { "T1CMP1H", 74, {0, {0}}, 0, 0 },
+ { "T1CMP1L", 75, {0, {0}}, 0, 0 },
+ { "T1CFG1H", 76, {0, {0}}, 0, 0 },
+ { "T1CFG1L", 77, {0, {0}}, 0, 0 },
+ { "T1CFG2H", 78, {0, {0}}, 0, 0 },
+ { "T1CFG2L", 79, {0, {0}}, 0, 0 },
+ { "ADCH", 80, {0, {0}}, 0, 0 },
+ { "ADCL", 81, {0, {0}}, 0, 0 },
+ { "ADCCFG", 82, {0, {0}}, 0, 0 },
+ { "ADCTMR", 83, {0, {0}}, 0, 0 },
+ { "T2CNTH", 84, {0, {0}}, 0, 0 },
+ { "T2CNTL", 85, {0, {0}}, 0, 0 },
+ { "T2CAP1H", 86, {0, {0}}, 0, 0 },
+ { "T2CAP1L", 87, {0, {0}}, 0, 0 },
+ { "T2CAP2H", 88, {0, {0}}, 0, 0 },
+ { "T2CMP2H", 88, {0, {0}}, 0, 0 },
+ { "T2CAP2L", 89, {0, {0}}, 0, 0 },
+ { "T2CMP2L", 89, {0, {0}}, 0, 0 },
+ { "T2CMP1H", 90, {0, {0}}, 0, 0 },
+ { "T2CMP1L", 91, {0, {0}}, 0, 0 },
+ { "T2CFG1H", 92, {0, {0}}, 0, 0 },
+ { "T2CFG1L", 93, {0, {0}}, 0, 0 },
+ { "T2CFG2H", 94, {0, {0}}, 0, 0 },
+ { "T2CFG2L", 95, {0, {0}}, 0, 0 },
+ { "S1TMRH", 96, {0, {0}}, 0, 0 },
+ { "S1TMRL", 97, {0, {0}}, 0, 0 },
+ { "S1TBUFH", 98, {0, {0}}, 0, 0 },
+ { "S1TBUFL", 99, {0, {0}}, 0, 0 },
+ { "S1TCFG", 100, {0, {0}}, 0, 0 },
+ { "S1RCNT", 101, {0, {0}}, 0, 0 },
+ { "S1RBUFH", 102, {0, {0}}, 0, 0 },
+ { "S1RBUFL", 103, {0, {0}}, 0, 0 },
+ { "S1RCFG", 104, {0, {0}}, 0, 0 },
+ { "S1RSYNC", 105, {0, {0}}, 0, 0 },
+ { "S1INTF", 106, {0, {0}}, 0, 0 },
+ { "S1INTE", 107, {0, {0}}, 0, 0 },
+ { "S1MODE", 108, {0, {0}}, 0, 0 },
+ { "S1SMASK", 109, {0, {0}}, 0, 0 },
+ { "PSPCFG", 110, {0, {0}}, 0, 0 },
+ { "CMPCFG", 111, {0, {0}}, 0, 0 },
+ { "S2TMRH", 112, {0, {0}}, 0, 0 },
+ { "S2TMRL", 113, {0, {0}}, 0, 0 },
+ { "S2TBUFH", 114, {0, {0}}, 0, 0 },
+ { "S2TBUFL", 115, {0, {0}}, 0, 0 },
+ { "S2TCFG", 116, {0, {0}}, 0, 0 },
+ { "S2RCNT", 117, {0, {0}}, 0, 0 },
+ { "S2RBUFH", 118, {0, {0}}, 0, 0 },
+ { "S2RBUFL", 119, {0, {0}}, 0, 0 },
+ { "S2RCFG", 120, {0, {0}}, 0, 0 },
+ { "S2RSYNC", 121, {0, {0}}, 0, 0 },
+ { "S2INTF", 122, {0, {0}}, 0, 0 },
+ { "S2INTE", 123, {0, {0}}, 0, 0 },
+ { "S2MODE", 124, {0, {0}}, 0, 0 },
+ { "S2SMASK", 125, {0, {0}}, 0, 0 },
+ { "CALLH", 126, {0, {0}}, 0, 0 },
+ { "CALLL", 127, {0, {0}}, 0, 0 }
+};
+
+CGEN_KEYWORD ip2k_cgen_opval_register_names =
+{
+ & ip2k_cgen_opval_register_names_entries[0],
+ 121,
+ 0, 0, 0, 0, ""
+};
+
+
+/* The hardware table. */
+
+#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
+#define A(a) (1 << CGEN_HW_##a)
+#else
+#define A(a) (1 << CGEN_HW_/**/a)
+#endif
+
+const CGEN_HW_ENTRY ip2k_cgen_hw_table[] =
+{
+ { "h-memory", HW_H_MEMORY, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
+ { "h-sint", HW_H_SINT, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
+ { "h-uint", HW_H_UINT, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
+ { "h-addr", HW_H_ADDR, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
+ { "h-iaddr", HW_H_IADDR, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
+ { "h-spr", HW_H_SPR, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
+ { "h-registers", HW_H_REGISTERS, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { (1<<MACH_BASE) } } },
+ { "h-stack", HW_H_STACK, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
+ { "h-pabits", HW_H_PABITS, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
+ { "h-zbit", HW_H_ZBIT, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
+ { "h-cbit", HW_H_CBIT, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
+ { "h-dcbit", HW_H_DCBIT, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
+ { "h-pc", HW_H_PC, CGEN_ASM_NONE, 0, { 0|A(PROFILE)|A(PC), { (1<<MACH_BASE) } } },
+ { 0, 0, CGEN_ASM_NONE, 0, {0, {0}} }
+};
+
+#undef A
+
+
+/* The instruction field table. */
+
+#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
+#define A(a) (1 << CGEN_IFLD_##a)
+#else
+#define A(a) (1 << CGEN_IFLD_/**/a)
+#endif
+
+const CGEN_IFLD ip2k_cgen_ifld_table[] =
+{
+ { IP2K_F_NIL, "f-nil", 0, 0, 0, 0, { 0, { (1<<MACH_BASE) } } },
+ { IP2K_F_ANYOF, "f-anyof", 0, 0, 0, 0, { 0, { (1<<MACH_BASE) } } },
+ { IP2K_F_IMM8, "f-imm8", 0, 16, 7, 8, { 0, { (1<<MACH_BASE) } } },
+ { IP2K_F_REG, "f-reg", 0, 16, 8, 9, { 0|A(ABS_ADDR), { (1<<MACH_BASE) } } },
+ { IP2K_F_ADDR16CJP, "f-addr16cjp", 0, 16, 12, 13, { 0|A(ABS_ADDR), { (1<<MACH_BASE) } } },
+ { IP2K_F_DIR, "f-dir", 0, 16, 9, 1, { 0, { (1<<MACH_BASE) } } },
+ { IP2K_F_BITNO, "f-bitno", 0, 16, 11, 3, { 0, { (1<<MACH_BASE) } } },
+ { IP2K_F_OP3, "f-op3", 0, 16, 15, 3, { 0, { (1<<MACH_BASE) } } },
+ { IP2K_F_OP4, "f-op4", 0, 16, 15, 4, { 0, { (1<<MACH_BASE) } } },
+ { IP2K_F_OP4MID, "f-op4mid", 0, 16, 11, 4, { 0, { (1<<MACH_BASE) } } },
+ { IP2K_F_OP6, "f-op6", 0, 16, 15, 6, { 0, { (1<<MACH_BASE) } } },
+ { IP2K_F_OP8, "f-op8", 0, 16, 15, 8, { 0, { (1<<MACH_BASE) } } },
+ { IP2K_F_OP6_10LOW, "f-op6-10low", 0, 16, 9, 10, { 0, { (1<<MACH_BASE) } } },
+ { IP2K_F_OP6_7LOW, "f-op6-7low", 0, 16, 9, 7, { 0, { (1<<MACH_BASE) } } },
+ { IP2K_F_RETI3, "f-reti3", 0, 16, 2, 3, { 0, { (1<<MACH_BASE) } } },
+ { IP2K_F_SKIPB, "f-skipb", 0, 16, 12, 1, { 0|A(ABS_ADDR), { (1<<MACH_BASE) } } },
+ { IP2K_F_PAGE3, "f-page3", 0, 16, 2, 3, { 0, { (1<<MACH_BASE) } } },
+ { 0, 0, 0, 0, 0, 0, {0, {0}} }
+};
+
+#undef A
+
+
+
+/* multi ifield declarations */
+
+
+
+/* multi ifield definitions */
+
+
+/* The operand table. */
+
+#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
+#define A(a) (1 << CGEN_OPERAND_##a)
+#else
+#define A(a) (1 << CGEN_OPERAND_/**/a)
+#endif
+#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
+#define OPERAND(op) IP2K_OPERAND_##op
+#else
+#define OPERAND(op) IP2K_OPERAND_/**/op
+#endif
+
+const CGEN_OPERAND ip2k_cgen_operand_table[] =
+{
+/* pc: program counter */
+ { "pc", IP2K_OPERAND_PC, HW_H_PC, 0, 0,
+ { 0, &(ip2k_cgen_ifld_table[0]) },
+ { 0|A(SEM_ONLY), { (1<<MACH_BASE) } } },
+/* addr16cjp: 13-bit address */
+ { "addr16cjp", IP2K_OPERAND_ADDR16CJP, HW_H_UINT, 12, 13,
+ { 0, &(ip2k_cgen_ifld_table[4]) },
+ { 0|A(ABS_ADDR), { (1<<MACH_BASE) } } },
+/* fr: register */
+ { "fr", IP2K_OPERAND_FR, HW_H_REGISTERS, 8, 9,
+ { 0, &(ip2k_cgen_ifld_table[3]) },
+ { 0|A(ABS_ADDR), { (1<<MACH_BASE) } } },
+/* lit8: 8-bit signed literal */
+ { "lit8", IP2K_OPERAND_LIT8, HW_H_SINT, 7, 8,
+ { 0, &(ip2k_cgen_ifld_table[2]) },
+ { 0, { (1<<MACH_BASE) } } },
+/* bitno: bit number */
+ { "bitno", IP2K_OPERAND_BITNO, HW_H_UINT, 11, 3,
+ { 0, &(ip2k_cgen_ifld_table[6]) },
+ { 0, { (1<<MACH_BASE) } } },
+/* addr16p: page number */
+ { "addr16p", IP2K_OPERAND_ADDR16P, HW_H_UINT, 2, 3,
+ { 0, &(ip2k_cgen_ifld_table[16]) },
+ { 0, { (1<<MACH_BASE) } } },
+/* addr16h: high 8 bits of address */
+ { "addr16h", IP2K_OPERAND_ADDR16H, HW_H_UINT, 7, 8,
+ { 0, &(ip2k_cgen_ifld_table[2]) },
+ { 0, { (1<<MACH_BASE) } } },
+/* addr16l: low 8 bits of address */
+ { "addr16l", IP2K_OPERAND_ADDR16L, HW_H_UINT, 7, 8,
+ { 0, &(ip2k_cgen_ifld_table[2]) },
+ { 0, { (1<<MACH_BASE) } } },
+/* reti3: reti flags */
+ { "reti3", IP2K_OPERAND_RETI3, HW_H_UINT, 2, 3,
+ { 0, &(ip2k_cgen_ifld_table[14]) },
+ { 0, { (1<<MACH_BASE) } } },
+/* pabits: page bits */
+ { "pabits", IP2K_OPERAND_PABITS, HW_H_PABITS, 0, 0,
+ { 0, 0 },
+ { 0, { (1<<MACH_BASE) } } },
+/* zbit: zero bit */
+ { "zbit", IP2K_OPERAND_ZBIT, HW_H_ZBIT, 0, 0,
+ { 0, 0 },
+ { 0, { (1<<MACH_BASE) } } },
+/* cbit: carry bit */
+ { "cbit", IP2K_OPERAND_CBIT, HW_H_CBIT, 0, 0,
+ { 0, 0 },
+ { 0, { (1<<MACH_BASE) } } },
+/* dcbit: digit carry bit */
+ { "dcbit", IP2K_OPERAND_DCBIT, HW_H_DCBIT, 0, 0,
+ { 0, 0 },
+ { 0, { (1<<MACH_BASE) } } },
+ { 0, 0, 0, 0, 0, {0, {0}} }
+};
+
+#undef A
+
+
+/* The instruction table. */
+
+#define OP(field) CGEN_SYNTAX_MAKE_FIELD (OPERAND (field))
+#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
+#define A(a) (1 << CGEN_INSN_##a)
+#else
+#define A(a) (1 << CGEN_INSN_/**/a)
+#endif
+
+static const CGEN_IBASE ip2k_cgen_insn_table[MAX_INSNS] =
+{
+ /* Special null first entry.
+ A `num' value of zero is thus invalid.
+ Also, the special `invalid' insn resides here. */
+ { 0, 0, 0, 0, {0, {0}} },
+/* jmp $addr16cjp */
+ {
+ IP2K_INSN_JMP, "jmp", "jmp", 16,
+ { 0|A(UNCOND_CTI), { (1<<MACH_BASE) } }
+ },
+/* call $addr16cjp */
+ {
+ IP2K_INSN_CALL, "call", "call", 16,
+ { 0|A(UNCOND_CTI), { (1<<MACH_BASE) } }
+ },
+/* sb $fr,$bitno */
+ {
+ IP2K_INSN_SB, "sb", "sb", 16,
+ { 0|A(SKIP_CTI), { (1<<MACH_BASE) } }
+ },
+/* snb $fr,$bitno */
+ {
+ IP2K_INSN_SNB, "snb", "snb", 16,
+ { 0|A(SKIP_CTI), { (1<<MACH_BASE) } }
+ },
+/* setb $fr,$bitno */
+ {
+ IP2K_INSN_SETB, "setb", "setb", 16,
+ { 0, { (1<<MACH_BASE) } }
+ },
+/* clrb $fr,$bitno */
+ {
+ IP2K_INSN_CLRB, "clrb", "clrb", 16,
+ { 0, { (1<<MACH_BASE) } }
+ },
+/* xor W,#$lit8 */
+ {
+ IP2K_INSN_XORW_L, "xorw_l", "xor", 16,
+ { 0, { (1<<MACH_BASE) } }
+ },
+/* and W,#$lit8 */
+ {
+ IP2K_INSN_ANDW_L, "andw_l", "and", 16,
+ { 0, { (1<<MACH_BASE) } }
+ },
+/* or W,#$lit8 */
+ {
+ IP2K_INSN_ORW_L, "orw_l", "or", 16,
+ { 0, { (1<<MACH_BASE) } }
+ },
+/* add W,#$lit8 */
+ {
+ IP2K_INSN_ADDW_L, "addw_l", "add", 16,
+ { 0, { (1<<MACH_BASE) } }
+ },
+/* sub W,#$lit8 */
+ {
+ IP2K_INSN_SUBW_L, "subw_l", "sub", 16,
+ { 0, { (1<<MACH_BASE) } }
+ },
+/* cmp W,#$lit8 */
+ {
+ IP2K_INSN_CMPW_L, "cmpw_l", "cmp", 16,
+ { 0, { (1<<MACH_BASE) } }
+ },
+/* retw #$lit8 */
+ {
+ IP2K_INSN_RETW_L, "retw_l", "retw", 16,
+ { 0|A(UNCOND_CTI), { (1<<MACH_BASE) } }
+ },
+/* cse W,#$lit8 */
+ {
+ IP2K_INSN_CSEW_L, "csew_l", "cse", 16,
+ { 0|A(SKIP_CTI), { (1<<MACH_BASE) } }
+ },
+/* csne W,#$lit8 */
+ {
+ IP2K_INSN_CSNEW_L, "csnew_l", "csne", 16,
+ { 0|A(SKIP_CTI), { (1<<MACH_BASE) } }
+ },
+/* push #$lit8 */
+ {
+ IP2K_INSN_PUSH_L, "push_l", "push", 16,
+ { 0, { (1<<MACH_BASE) } }
+ },
+/* muls W,#$lit8 */
+ {
+ IP2K_INSN_MULSW_L, "mulsw_l", "muls", 16,
+ { 0, { (1<<MACH_BASE) } }
+ },
+/* mulu W,#$lit8 */
+ {
+ IP2K_INSN_MULUW_L, "muluw_l", "mulu", 16,
+ { 0, { (1<<MACH_BASE) } }
+ },
+/* loadl #$lit8 */
+ {
+ IP2K_INSN_LOADL_L, "loadl_l", "loadl", 16,
+ { 0|A(EXT_SKIP_INSN), { (1<<MACH_BASE) } }
+ },
+/* loadh #$lit8 */
+ {
+ IP2K_INSN_LOADH_L, "loadh_l", "loadh", 16,
+ { 0|A(EXT_SKIP_INSN), { (1<<MACH_BASE) } }
+ },
+/* loadl $addr16l */
+ {
+ IP2K_INSN_LOADL_A, "loadl_a", "loadl", 16,
+ { 0|A(EXT_SKIP_INSN), { (1<<MACH_BASE) } }
+ },
+/* loadh $addr16h */
+ {
+ IP2K_INSN_LOADH_A, "loadh_a", "loadh", 16,
+ { 0|A(EXT_SKIP_INSN), { (1<<MACH_BASE) } }
+ },
+/* addc $fr,W */
+ {
+ IP2K_INSN_ADDCFR_W, "addcfr_w", "addc", 16,
+ { 0, { (1<<MACH_BASE) } }
+ },
+/* addc W,$fr */
+ {
+ IP2K_INSN_ADDCW_FR, "addcw_fr", "addc", 16,
+ { 0, { (1<<MACH_BASE) } }
+ },
+/* incsnz $fr */
+ {
+ IP2K_INSN_INCSNZ_FR, "incsnz_fr", "incsnz", 16,
+ { 0|A(SKIP_CTI), { (1<<MACH_BASE) } }
+ },
+/* incsnz W,$fr */
+ {
+ IP2K_INSN_INCSNZW_FR, "incsnzw_fr", "incsnz", 16,
+ { 0|A(SKIP_CTI), { (1<<MACH_BASE) } }
+ },
+/* muls W,$fr */
+ {
+ IP2K_INSN_MULSW_FR, "mulsw_fr", "muls", 16,
+ { 0, { (1<<MACH_BASE) } }
+ },
+/* mulu W,$fr */
+ {
+ IP2K_INSN_MULUW_FR, "muluw_fr", "mulu", 16,
+ { 0, { (1<<MACH_BASE) } }
+ },
+/* decsnz $fr */
+ {
+ IP2K_INSN_DECSNZ_FR, "decsnz_fr", "decsnz", 16,
+ { 0|A(SKIP_CTI), { (1<<MACH_BASE) } }
+ },
+/* decsnz W,$fr */
+ {
+ IP2K_INSN_DECSNZW_FR, "decsnzw_fr", "decsnz", 16,
+ { 0|A(SKIP_CTI), { (1<<MACH_BASE) } }
+ },
+/* subc W,$fr */
+ {
+ IP2K_INSN_SUBCW_FR, "subcw_fr", "subc", 16,
+ { 0, { (1<<MACH_BASE) } }
+ },
+/* subc $fr,W */
+ {
+ IP2K_INSN_SUBCFR_W, "subcfr_w", "subc", 16,
+ { 0, { (1<<MACH_BASE) } }
+ },
+/* pop $fr */
+ {
+ IP2K_INSN_POP_FR, "pop_fr", "pop", 16,
+ { 0, { (1<<MACH_BASE) } }
+ },
+/* push $fr */
+ {
+ IP2K_INSN_PUSH_FR, "push_fr", "push", 16,
+ { 0, { (1<<MACH_BASE) } }
+ },
+/* cse W,$fr */
+ {
+ IP2K_INSN_CSEW_FR, "csew_fr", "cse", 16,
+ { 0|A(SKIP_CTI), { (1<<MACH_BASE) } }
+ },
+/* csne W,$fr */
+ {
+ IP2K_INSN_CSNEW_FR, "csnew_fr", "csne", 16,
+ { 0|A(SKIP_CTI), { (1<<MACH_BASE) } }
+ },
+/* incsz $fr */
+ {
+ IP2K_INSN_INCSZ_FR, "incsz_fr", "incsz", 16,
+ { 0|A(SKIP_CTI), { (1<<MACH_BASE) } }
+ },
+/* incsz W,$fr */
+ {
+ IP2K_INSN_INCSZW_FR, "incszw_fr", "incsz", 16,
+ { 0|A(SKIP_CTI), { (1<<MACH_BASE) } }
+ },
+/* swap $fr */
+ {
+ IP2K_INSN_SWAP_FR, "swap_fr", "swap", 16,
+ { 0, { (1<<MACH_BASE) } }
+ },
+/* swap W,$fr */
+ {
+ IP2K_INSN_SWAPW_FR, "swapw_fr", "swap", 16,
+ { 0, { (1<<MACH_BASE) } }
+ },
+/* rl $fr */
+ {
+ IP2K_INSN_RL_FR, "rl_fr", "rl", 16,
+ { 0, { (1<<MACH_BASE) } }
+ },
+/* rl W,$fr */
+ {
+ IP2K_INSN_RLW_FR, "rlw_fr", "rl", 16,
+ { 0, { (1<<MACH_BASE) } }
+ },
+/* rr $fr */
+ {
+ IP2K_INSN_RR_FR, "rr_fr", "rr", 16,
+ { 0, { (1<<MACH_BASE) } }
+ },
+/* rr W,$fr */
+ {
+ IP2K_INSN_RRW_FR, "rrw_fr", "rr", 16,
+ { 0, { (1<<MACH_BASE) } }
+ },
+/* decsz $fr */
+ {
+ IP2K_INSN_DECSZ_FR, "decsz_fr", "decsz", 16,
+ { 0|A(SKIP_CTI), { (1<<MACH_BASE) } }
+ },
+/* decsz W,$fr */
+ {
+ IP2K_INSN_DECSZW_FR, "decszw_fr", "decsz", 16,
+ { 0|A(SKIP_CTI), { (1<<MACH_BASE) } }
+ },
+/* inc $fr */
+ {
+ IP2K_INSN_INC_FR, "inc_fr", "inc", 16,
+ { 0, { (1<<MACH_BASE) } }
+ },
+/* inc W,$fr */
+ {
+ IP2K_INSN_INCW_FR, "incw_fr", "inc", 16,
+ { 0, { (1<<MACH_BASE) } }
+ },
+/* not $fr */
+ {
+ IP2K_INSN_NOT_FR, "not_fr", "not", 16,
+ { 0, { (1<<MACH_BASE) } }
+ },
+/* not W,$fr */
+ {
+ IP2K_INSN_NOTW_FR, "notw_fr", "not", 16,
+ { 0, { (1<<MACH_BASE) } }
+ },
+/* test $fr */
+ {
+ IP2K_INSN_TEST_FR, "test_fr", "test", 16,
+ { 0, { (1<<MACH_BASE) } }
+ },
+/* mov W,#$lit8 */
+ {
+ IP2K_INSN_MOVW_L, "movw_l", "mov", 16,
+ { 0, { (1<<MACH_BASE) } }
+ },
+/* mov $fr,W */
+ {
+ IP2K_INSN_MOVFR_W, "movfr_w", "mov", 16,
+ { 0, { (1<<MACH_BASE) } }
+ },
+/* mov W,$fr */
+ {
+ IP2K_INSN_MOVW_FR, "movw_fr", "mov", 16,
+ { 0, { (1<<MACH_BASE) } }
+ },
+/* add $fr,W */
+ {
+ IP2K_INSN_ADDFR_W, "addfr_w", "add", 16,
+ { 0, { (1<<MACH_BASE) } }
+ },
+/* add W,$fr */
+ {
+ IP2K_INSN_ADDW_FR, "addw_fr", "add", 16,
+ { 0, { (1<<MACH_BASE) } }
+ },
+/* xor $fr,W */
+ {
+ IP2K_INSN_XORFR_W, "xorfr_w", "xor", 16,
+ { 0, { (1<<MACH_BASE) } }
+ },
+/* xor W,$fr */
+ {
+ IP2K_INSN_XORW_FR, "xorw_fr", "xor", 16,
+ { 0, { (1<<MACH_BASE) } }
+ },
+/* and $fr,W */
+ {
+ IP2K_INSN_ANDFR_W, "andfr_w", "and", 16,
+ { 0, { (1<<MACH_BASE) } }
+ },
+/* and W,$fr */
+ {
+ IP2K_INSN_ANDW_FR, "andw_fr", "and", 16,
+ { 0, { (1<<MACH_BASE) } }
+ },
+/* or $fr,W */
+ {
+ IP2K_INSN_ORFR_W, "orfr_w", "or", 16,
+ { 0, { (1<<MACH_BASE) } }
+ },
+/* or W,$fr */
+ {
+ IP2K_INSN_ORW_FR, "orw_fr", "or", 16,
+ { 0, { (1<<MACH_BASE) } }
+ },
+/* dec $fr */
+ {
+ IP2K_INSN_DEC_FR, "dec_fr", "dec", 16,
+ { 0, { (1<<MACH_BASE) } }
+ },
+/* dec W,$fr */
+ {
+ IP2K_INSN_DECW_FR, "decw_fr", "dec", 16,
+ { 0, { (1<<MACH_BASE) } }
+ },
+/* sub $fr,W */
+ {
+ IP2K_INSN_SUBFR_W, "subfr_w", "sub", 16,
+ { 0, { (1<<MACH_BASE) } }
+ },
+/* sub W,$fr */
+ {
+ IP2K_INSN_SUBW_FR, "subw_fr", "sub", 16,
+ { 0, { (1<<MACH_BASE) } }
+ },
+/* clr $fr */
+ {
+ IP2K_INSN_CLR_FR, "clr_fr", "clr", 16,
+ { 0, { (1<<MACH_BASE) } }
+ },
+/* cmp W,$fr */
+ {
+ IP2K_INSN_CMPW_FR, "cmpw_fr", "cmp", 16,
+ { 0, { (1<<MACH_BASE) } }
+ },
+/* speed #$lit8 */
+ {
+ IP2K_INSN_SPEED, "speed", "speed", 16,
+ { 0, { (1<<MACH_BASE) } }
+ },
+/* ireadi */
+ {
+ IP2K_INSN_IREADI, "ireadi", "ireadi", 16,
+ { 0, { (1<<MACH_BASE) } }
+ },
+/* iwritei */
+ {
+ IP2K_INSN_IWRITEI, "iwritei", "iwritei", 16,
+ { 0, { (1<<MACH_BASE) } }
+ },
+/* fread */
+ {
+ IP2K_INSN_FREAD, "fread", "fread", 16,
+ { 0, { (1<<MACH_BASE) } }
+ },
+/* fwrite */
+ {
+ IP2K_INSN_FWRITE, "fwrite", "fwrite", 16,
+ { 0, { (1<<MACH_BASE) } }
+ },
+/* iread */
+ {
+ IP2K_INSN_IREAD, "iread", "iread", 16,
+ { 0, { (1<<MACH_BASE) } }
+ },
+/* iwrite */
+ {
+ IP2K_INSN_IWRITE, "iwrite", "iwrite", 16,
+ { 0, { (1<<MACH_BASE) } }
+ },
+/* page $addr16p */
+ {
+ IP2K_INSN_PAGE, "page", "page", 16,
+ { 0|A(EXT_SKIP_INSN), { (1<<MACH_BASE) } }
+ },
+/* system */
+ {
+ IP2K_INSN_SYSTEM, "system", "system", 16,
+ { 0, { (1<<MACH_BASE) } }
+ },
+/* reti #$reti3 */
+ {
+ IP2K_INSN_RETI, "reti", "reti", 16,
+ { 0, { (1<<MACH_BASE) } }
+ },
+/* ret */
+ {
+ IP2K_INSN_RET, "ret", "ret", 16,
+ { 0|A(UNCOND_CTI), { (1<<MACH_BASE) } }
+ },
+/* int */
+ {
+ IP2K_INSN_INT, "int", "int", 16,
+ { 0, { (1<<MACH_BASE) } }
+ },
+/* breakx */
+ {
+ IP2K_INSN_BREAKX, "breakx", "breakx", 16,
+ { 0|A(EXT_SKIP_INSN), { (1<<MACH_BASE) } }
+ },
+/* cwdt */
+ {
+ IP2K_INSN_CWDT, "cwdt", "cwdt", 16,
+ { 0, { (1<<MACH_BASE) } }
+ },
+/* ferase */
+ {
+ IP2K_INSN_FERASE, "ferase", "ferase", 16,
+ { 0, { (1<<MACH_BASE) } }
+ },
+/* retnp */
+ {
+ IP2K_INSN_RETNP, "retnp", "retnp", 16,
+ { 0|A(UNCOND_CTI), { (1<<MACH_BASE) } }
+ },
+/* break */
+ {
+ IP2K_INSN_BREAK, "break", "break", 16,
+ { 0, { (1<<MACH_BASE) } }
+ },
+/* nop */
+ {
+ IP2K_INSN_NOP, "nop", "nop", 16,
+ { 0, { (1<<MACH_BASE) } }
+ },
+};
+
+#undef OP
+#undef A
+
+/* Initialize anything needed to be done once, before any cpu_open call. */
+static void init_tables PARAMS ((void));
+
+static void
+init_tables ()
+{
+}
+
+static const CGEN_MACH * lookup_mach_via_bfd_name
+ PARAMS ((const CGEN_MACH *, const char *));
+static void build_hw_table PARAMS ((CGEN_CPU_TABLE *));
+static void build_ifield_table PARAMS ((CGEN_CPU_TABLE *));
+static void build_operand_table PARAMS ((CGEN_CPU_TABLE *));
+static void build_insn_table PARAMS ((CGEN_CPU_TABLE *));
+static void ip2k_cgen_rebuild_tables PARAMS ((CGEN_CPU_TABLE *));
+
+/* Subroutine of ip2k_cgen_cpu_open to look up a mach via its bfd name. */
+
+static const CGEN_MACH *
+lookup_mach_via_bfd_name (table, name)
+ const CGEN_MACH *table;
+ const char *name;
+{
+ while (table->name)
+ {
+ if (strcmp (name, table->bfd_name) == 0)
+ return table;
+ ++table;
+ }
+ abort ();
+}
+
+/* Subroutine of ip2k_cgen_cpu_open to build the hardware table. */
+
+static void
+build_hw_table (cd)
+ CGEN_CPU_TABLE *cd;
+{
+ int i;
+ int machs = cd->machs;
+ const CGEN_HW_ENTRY *init = & ip2k_cgen_hw_table[0];
+ /* MAX_HW is only an upper bound on the number of selected entries.
+ However each entry is indexed by it's enum so there can be holes in
+ the table. */
+ const CGEN_HW_ENTRY **selected =
+ (const CGEN_HW_ENTRY **) xmalloc (MAX_HW * sizeof (CGEN_HW_ENTRY *));
+
+ cd->hw_table.init_entries = init;
+ cd->hw_table.entry_size = sizeof (CGEN_HW_ENTRY);
+ memset (selected, 0, MAX_HW * sizeof (CGEN_HW_ENTRY *));
+ /* ??? For now we just use machs to determine which ones we want. */
+ for (i = 0; init[i].name != NULL; ++i)
+ if (CGEN_HW_ATTR_VALUE (&init[i], CGEN_HW_MACH)
+ & machs)
+ selected[init[i].type] = &init[i];
+ cd->hw_table.entries = selected;
+ cd->hw_table.num_entries = MAX_HW;
+}
+
+/* Subroutine of ip2k_cgen_cpu_open to build the hardware table. */
+
+static void
+build_ifield_table (cd)
+ CGEN_CPU_TABLE *cd;
+{
+ cd->ifld_table = & ip2k_cgen_ifld_table[0];
+}
+
+/* Subroutine of ip2k_cgen_cpu_open to build the hardware table. */
+
+static void
+build_operand_table (cd)
+ CGEN_CPU_TABLE *cd;
+{
+ int i;
+ int machs = cd->machs;
+ const CGEN_OPERAND *init = & ip2k_cgen_operand_table[0];
+ /* MAX_OPERANDS is only an upper bound on the number of selected entries.
+ However each entry is indexed by it's enum so there can be holes in
+ the table. */
+ const CGEN_OPERAND **selected =
+ (const CGEN_OPERAND **) xmalloc (MAX_OPERANDS * sizeof (CGEN_OPERAND *));
+
+ cd->operand_table.init_entries = init;
+ cd->operand_table.entry_size = sizeof (CGEN_OPERAND);
+ memset (selected, 0, MAX_OPERANDS * sizeof (CGEN_OPERAND *));
+ /* ??? For now we just use mach to determine which ones we want. */
+ for (i = 0; init[i].name != NULL; ++i)
+ if (CGEN_OPERAND_ATTR_VALUE (&init[i], CGEN_OPERAND_MACH)
+ & machs)
+ selected[init[i].type] = &init[i];
+ cd->operand_table.entries = selected;
+ cd->operand_table.num_entries = MAX_OPERANDS;
+}
+
+/* Subroutine of ip2k_cgen_cpu_open to build the hardware table.
+ ??? This could leave out insns not supported by the specified mach/isa,
+ but that would cause errors like "foo only supported by bar" to become
+ "unknown insn", so for now we include all insns and require the app to
+ do the checking later.
+ ??? On the other hand, parsing of such insns may require their hardware or
+ operand elements to be in the table [which they mightn't be]. */
+
+static void
+build_insn_table (cd)
+ CGEN_CPU_TABLE *cd;
+{
+ int i;
+ const CGEN_IBASE *ib = & ip2k_cgen_insn_table[0];
+ CGEN_INSN *insns = (CGEN_INSN *) xmalloc (MAX_INSNS * sizeof (CGEN_INSN));
+
+ memset (insns, 0, MAX_INSNS * sizeof (CGEN_INSN));
+ for (i = 0; i < MAX_INSNS; ++i)
+ insns[i].base = &ib[i];
+ cd->insn_table.init_entries = insns;
+ cd->insn_table.entry_size = sizeof (CGEN_IBASE);
+ cd->insn_table.num_init_entries = MAX_INSNS;
+}
+
+/* Subroutine of ip2k_cgen_cpu_open to rebuild the tables. */
+
+static void
+ip2k_cgen_rebuild_tables (cd)
+ CGEN_CPU_TABLE *cd;
+{
+ int i;
+ unsigned int isas = cd->isas;
+ unsigned int machs = cd->machs;
+
+ cd->int_insn_p = CGEN_INT_INSN_P;
+
+ /* Data derived from the isa spec. */
+#define UNSET (CGEN_SIZE_UNKNOWN + 1)
+ cd->default_insn_bitsize = UNSET;
+ cd->base_insn_bitsize = UNSET;
+ cd->min_insn_bitsize = 65535; /* some ridiculously big number */
+ cd->max_insn_bitsize = 0;
+ for (i = 0; i < MAX_ISAS; ++i)
+ if (((1 << i) & isas) != 0)
+ {
+ const CGEN_ISA *isa = & ip2k_cgen_isa_table[i];
+
+ /* Default insn sizes of all selected isas must be
+ equal or we set the result to 0, meaning "unknown". */
+ if (cd->default_insn_bitsize == UNSET)
+ cd->default_insn_bitsize = isa->default_insn_bitsize;
+ else if (isa->default_insn_bitsize == cd->default_insn_bitsize)
+ ; /* this is ok */
+ else
+ cd->default_insn_bitsize = CGEN_SIZE_UNKNOWN;
+
+ /* Base insn sizes of all selected isas must be equal
+ or we set the result to 0, meaning "unknown". */
+ if (cd->base_insn_bitsize == UNSET)
+ cd->base_insn_bitsize = isa->base_insn_bitsize;
+ else if (isa->base_insn_bitsize == cd->base_insn_bitsize)
+ ; /* this is ok */
+ else
+ cd->base_insn_bitsize = CGEN_SIZE_UNKNOWN;
+
+ /* Set min,max insn sizes. */
+ if (isa->min_insn_bitsize < cd->min_insn_bitsize)
+ cd->min_insn_bitsize = isa->min_insn_bitsize;
+ if (isa->max_insn_bitsize > cd->max_insn_bitsize)
+ cd->max_insn_bitsize = isa->max_insn_bitsize;
+ }
+
+ /* Data derived from the mach spec. */
+ for (i = 0; i < MAX_MACHS; ++i)
+ if (((1 << i) & machs) != 0)
+ {
+ const CGEN_MACH *mach = & ip2k_cgen_mach_table[i];
+
+ if (mach->insn_chunk_bitsize != 0)
+ {
+ if (cd->insn_chunk_bitsize != 0 && cd->insn_chunk_bitsize != mach->insn_chunk_bitsize)
+ {
+ fprintf (stderr, "ip2k_cgen_rebuild_tables: conflicting insn-chunk-bitsize values: `%d' vs. `%d'\n",
+ cd->insn_chunk_bitsize, mach->insn_chunk_bitsize);
+ abort ();
+ }
+
+ cd->insn_chunk_bitsize = mach->insn_chunk_bitsize;
+ }
+ }
+
+ /* Determine which hw elements are used by MACH. */
+ build_hw_table (cd);
+
+ /* Build the ifield table. */
+ build_ifield_table (cd);
+
+ /* Determine which operands are used by MACH/ISA. */
+ build_operand_table (cd);
+
+ /* Build the instruction table. */
+ build_insn_table (cd);
+}
+
+/* Initialize a cpu table and return a descriptor.
+ It's much like opening a file, and must be the first function called.
+ The arguments are a set of (type/value) pairs, terminated with
+ CGEN_CPU_OPEN_END.
+
+ Currently supported values:
+ CGEN_CPU_OPEN_ISAS: bitmap of values in enum isa_attr
+ CGEN_CPU_OPEN_MACHS: bitmap of values in enum mach_attr
+ CGEN_CPU_OPEN_BFDMACH: specify 1 mach using bfd name
+ CGEN_CPU_OPEN_ENDIAN: specify endian choice
+ CGEN_CPU_OPEN_END: terminates arguments
+
+ ??? Simultaneous multiple isas might not make sense, but it's not (yet)
+ precluded.
+
+ ??? We only support ISO C stdargs here, not K&R.
+ Laziness, plus experiment to see if anything requires K&R - eventually
+ K&R will no longer be supported - e.g. GDB is currently trying this. */
+
+CGEN_CPU_DESC
+ip2k_cgen_cpu_open (enum cgen_cpu_open_arg arg_type, ...)
+{
+ CGEN_CPU_TABLE *cd = (CGEN_CPU_TABLE *) xmalloc (sizeof (CGEN_CPU_TABLE));
+ static int init_p;
+ unsigned int isas = 0; /* 0 = "unspecified" */
+ unsigned int machs = 0; /* 0 = "unspecified" */
+ enum cgen_endian endian = CGEN_ENDIAN_UNKNOWN;
+ va_list ap;
+
+ if (! init_p)
+ {
+ init_tables ();
+ init_p = 1;
+ }
+
+ memset (cd, 0, sizeof (*cd));
+
+ va_start (ap, arg_type);
+ while (arg_type != CGEN_CPU_OPEN_END)
+ {
+ switch (arg_type)
+ {
+ case CGEN_CPU_OPEN_ISAS :
+ isas = va_arg (ap, unsigned int);
+ break;
+ case CGEN_CPU_OPEN_MACHS :
+ machs = va_arg (ap, unsigned int);
+ break;
+ case CGEN_CPU_OPEN_BFDMACH :
+ {
+ const char *name = va_arg (ap, const char *);
+ const CGEN_MACH *mach =
+ lookup_mach_via_bfd_name (ip2k_cgen_mach_table, name);
+
+ machs |= 1 << mach->num;
+ break;
+ }
+ case CGEN_CPU_OPEN_ENDIAN :
+ endian = va_arg (ap, enum cgen_endian);
+ break;
+ default :
+ fprintf (stderr, "ip2k_cgen_cpu_open: unsupported argument `%d'\n",
+ arg_type);
+ abort (); /* ??? return NULL? */
+ }
+ arg_type = va_arg (ap, enum cgen_cpu_open_arg);
+ }
+ va_end (ap);
+
+ /* mach unspecified means "all" */
+ if (machs == 0)
+ machs = (1 << MAX_MACHS) - 1;
+ /* base mach is always selected */
+ machs |= 1;
+ /* isa unspecified means "all" */
+ if (isas == 0)
+ isas = (1 << MAX_ISAS) - 1;
+ if (endian == CGEN_ENDIAN_UNKNOWN)
+ {
+ /* ??? If target has only one, could have a default. */
+ fprintf (stderr, "ip2k_cgen_cpu_open: no endianness specified\n");
+ abort ();
+ }
+
+ cd->isas = isas;
+ cd->machs = machs;
+ cd->endian = endian;
+ /* FIXME: for the sparc case we can determine insn-endianness statically.
+ The worry here is where both data and insn endian can be independently
+ chosen, in which case this function will need another argument.
+ Actually, will want to allow for more arguments in the future anyway. */
+ cd->insn_endian = endian;
+
+ /* Table (re)builder. */
+ cd->rebuild_tables = ip2k_cgen_rebuild_tables;
+ ip2k_cgen_rebuild_tables (cd);
+
+ /* Default to not allowing signed overflow. */
+ cd->signed_overflow_ok_p = 0;
+
+ return (CGEN_CPU_DESC) cd;
+}
+
+/* Cover fn to ip2k_cgen_cpu_open to handle the simple case of 1 isa, 1 mach.
+ MACH_NAME is the bfd name of the mach. */
+
+CGEN_CPU_DESC
+ip2k_cgen_cpu_open_1 (mach_name, endian)
+ const char *mach_name;
+ enum cgen_endian endian;
+{
+ return ip2k_cgen_cpu_open (CGEN_CPU_OPEN_BFDMACH, mach_name,
+ CGEN_CPU_OPEN_ENDIAN, endian,
+ CGEN_CPU_OPEN_END);
+}
+
+/* Close a cpu table.
+ ??? This can live in a machine independent file, but there's currently
+ no place to put this file (there's no libcgen). libopcodes is the wrong
+ place as some simulator ports use this but they don't use libopcodes. */
+
+void
+ip2k_cgen_cpu_close (cd)
+ CGEN_CPU_DESC cd;
+{
+ unsigned int i;
+ CGEN_INSN *insns;
+
+ if (cd->macro_insn_table.init_entries)
+ {
+ insns = cd->macro_insn_table.init_entries;
+ for (i = 0; i < cd->macro_insn_table.num_init_entries; ++i, ++insns)
+ {
+ if (CGEN_INSN_RX ((insns)))
+ regfree(CGEN_INSN_RX (insns));
+ }
+ }
+
+ if (cd->insn_table.init_entries)
+ {
+ insns = cd->insn_table.init_entries;
+ for (i = 0; i < cd->insn_table.num_init_entries; ++i, ++insns)
+ {
+ if (CGEN_INSN_RX (insns))
+ regfree(CGEN_INSN_RX (insns));
+ }
+ }
+
+
+
+ if (cd->macro_insn_table.init_entries)
+ free ((CGEN_INSN *) cd->macro_insn_table.init_entries);
+
+ if (cd->insn_table.init_entries)
+ free ((CGEN_INSN *) cd->insn_table.init_entries);
+
+ if (cd->hw_table.entries)
+ free ((CGEN_HW_ENTRY *) cd->hw_table.entries);
+
+ if (cd->operand_table.entries)
+ free ((CGEN_HW_ENTRY *) cd->operand_table.entries);
+
+ free (cd);
+}
+
--- /dev/null
+/* CPU data header for ip2k.
+
+THIS FILE IS MACHINE GENERATED WITH CGEN.
+
+Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc.
+
+This file is part of the GNU Binutils and/or GDB, the GNU debugger.
+
+This program is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2, or (at your option)
+any later version.
+
+This program is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License along
+with this program; if not, write to the Free Software Foundation, Inc.,
+59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+
+*/
+
+#ifndef IP2K_CPU_H
+#define IP2K_CPU_H
+
+#define CGEN_ARCH ip2k
+
+/* Given symbol S, return ip2k_cgen_<S>. */
+#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
+#define CGEN_SYM(s) ip2k##_cgen_##s
+#else
+#define CGEN_SYM(s) ip2k/**/_cgen_/**/s
+#endif
+
+
+/* Selected cpu families. */
+#define HAVE_CPU_IP2KBF
+
+#define CGEN_INSN_LSB0_P 1
+
+/* Minimum size of any insn (in bytes). */
+#define CGEN_MIN_INSN_SIZE 2
+
+/* Maximum size of any insn (in bytes). */
+#define CGEN_MAX_INSN_SIZE 2
+
+#define CGEN_INT_INSN_P 1
+
+/* Maximum number of syntax elements in an instruction. */
+#define CGEN_ACTUAL_MAX_SYNTAX_ELEMENTS 12
+
+/* CGEN_MNEMONIC_OPERANDS is defined if mnemonics have operands.
+ e.g. In "b,a foo" the ",a" is an operand. If mnemonics have operands
+ we can't hash on everything up to the space. */
+#define CGEN_MNEMONIC_OPERANDS
+
+/* Maximum number of fields in an instruction. */
+#define CGEN_ACTUAL_MAX_IFMT_OPERANDS 3
+
+/* Enums. */
+
+/* Enum declaration for op6 enums. */
+typedef enum insn_op6 {
+ OP6_OTHER1, OP6_OTHER2, OP6_SUB, OP6_DEC
+ , OP6_OR, OP6_AND, OP6_XOR, OP6_ADD
+ , OP6_TEST, OP6_NOT, OP6_INC, OP6_DECSZ
+ , OP6_RR, OP6_RL, OP6_SWAP, OP6_INCSZ
+ , OP6_CSE, OP6_POP, OP6_SUBC, OP6_DECSNZ
+ , OP6_MULU, OP6_MULS, OP6_INCSNZ, OP6_ADDC
+} INSN_OP6;
+
+/* Enum declaration for dir enums. */
+typedef enum insn_dir {
+ DIR_TO_W, DIR_NOTTO_W
+} INSN_DIR;
+
+/* Enum declaration for op4 enums. */
+typedef enum insn_op4 {
+ OP4_LITERAL = 7, OP4_CLRB = 8, OP4_SETB = 9, OP4_SNB = 10
+ , OP4_SB = 11
+} INSN_OP4;
+
+/* Enum declaration for op4mid enums. */
+typedef enum insn_op4mid {
+ OP4MID_LOADH_L = 0, OP4MID_LOADL_L = 1, OP4MID_MULU_L = 2, OP4MID_MULS_L = 3
+ , OP4MID_PUSH_L = 4, OP4MID_CSNE_L = 6, OP4MID_CSE_L = 7, OP4MID_RETW_L = 8
+ , OP4MID_CMP_L = 9, OP4MID_SUB_L = 10, OP4MID_ADD_L = 11, OP4MID_MOV_L = 12
+ , OP4MID_OR_L = 13, OP4MID_AND_L = 14, OP4MID_XOR_L = 15
+} INSN_OP4MID;
+
+/* Enum declaration for op3 enums. */
+typedef enum insn_op3 {
+ OP3_CALL = 6, OP3_JMP = 7
+} INSN_OP3;
+
+/* Enum declaration for . */
+typedef enum register_names {
+ H_REGISTERS_ADDRSEL = 2, H_REGISTERS_ADDRX = 3, H_REGISTERS_IPH = 4, H_REGISTERS_IPL = 5
+ , H_REGISTERS_SPH = 6, H_REGISTERS_SPL = 7, H_REGISTERS_PCH = 8, H_REGISTERS_PCL = 9
+ , H_REGISTERS_WREG = 10, H_REGISTERS_STATUS = 11, H_REGISTERS_DPH = 12, H_REGISTERS_DPL = 13
+ , H_REGISTERS_SPDREG = 14, H_REGISTERS_MULH = 15, H_REGISTERS_ADDRH = 16, H_REGISTERS_ADDRL = 17
+ , H_REGISTERS_DATAH = 18, H_REGISTERS_DATAL = 19, H_REGISTERS_INTVECH = 20, H_REGISTERS_INTVECL = 21
+ , H_REGISTERS_INTSPD = 22, H_REGISTERS_INTF = 23, H_REGISTERS_INTE = 24, H_REGISTERS_INTED = 25
+ , H_REGISTERS_FCFG = 26, H_REGISTERS_TCTRL = 27, H_REGISTERS_XCFG = 28, H_REGISTERS_EMCFG = 29
+ , H_REGISTERS_IPCH = 30, H_REGISTERS_IPCL = 31, H_REGISTERS_RAIN = 32, H_REGISTERS_RAOUT = 33
+ , H_REGISTERS_RADIR = 34, H_REGISTERS_LFSRH = 35, H_REGISTERS_RBIN = 36, H_REGISTERS_RBOUT = 37
+ , H_REGISTERS_RBDIR = 38, H_REGISTERS_LFSRL = 39, H_REGISTERS_RCIN = 40, H_REGISTERS_RCOUT = 41
+ , H_REGISTERS_RCDIR = 42, H_REGISTERS_LFSRA = 43, H_REGISTERS_RDIN = 44, H_REGISTERS_RDOUT = 45
+ , H_REGISTERS_RDDIR = 46, H_REGISTERS_REIN = 48, H_REGISTERS_REOUT = 49, H_REGISTERS_REDIR = 50
+ , H_REGISTERS_RFIN = 52, H_REGISTERS_RFOUT = 53, H_REGISTERS_RFDIR = 54, H_REGISTERS_RGOUT = 57
+ , H_REGISTERS_RGDIR = 58, H_REGISTERS_RTTMR = 64, H_REGISTERS_RTCFG = 65, H_REGISTERS_T0TMR = 66
+ , H_REGISTERS_T0CFG = 67, H_REGISTERS_T1CNTH = 68, H_REGISTERS_T1CNTL = 69, H_REGISTERS_T1CAP1H = 70
+ , H_REGISTERS_T1CAP1L = 71, H_REGISTERS_T1CAP2H = 72, H_REGISTERS_T1CMP2H = 72, H_REGISTERS_T1CAP2L = 73
+ , H_REGISTERS_T1CMP2L = 73, H_REGISTERS_T1CMP1H = 74, H_REGISTERS_T1CMP1L = 75, H_REGISTERS_T1CFG1H = 76
+ , H_REGISTERS_T1CFG1L = 77, H_REGISTERS_T1CFG2H = 78, H_REGISTERS_T1CFG2L = 79, H_REGISTERS_ADCH = 80
+ , H_REGISTERS_ADCL = 81, H_REGISTERS_ADCCFG = 82, H_REGISTERS_ADCTMR = 83, H_REGISTERS_T2CNTH = 84
+ , H_REGISTERS_T2CNTL = 85, H_REGISTERS_T2CAP1H = 86, H_REGISTERS_T2CAP1L = 87, H_REGISTERS_T2CAP2H = 88
+ , H_REGISTERS_T2CMP2H = 88, H_REGISTERS_T2CAP2L = 89, H_REGISTERS_T2CMP2L = 89, H_REGISTERS_T2CMP1H = 90
+ , H_REGISTERS_T2CMP1L = 91, H_REGISTERS_T2CFG1H = 92, H_REGISTERS_T2CFG1L = 93, H_REGISTERS_T2CFG2H = 94
+ , H_REGISTERS_T2CFG2L = 95, H_REGISTERS_S1TMRH = 96, H_REGISTERS_S1TMRL = 97, H_REGISTERS_S1TBUFH = 98
+ , H_REGISTERS_S1TBUFL = 99, H_REGISTERS_S1TCFG = 100, H_REGISTERS_S1RCNT = 101, H_REGISTERS_S1RBUFH = 102
+ , H_REGISTERS_S1RBUFL = 103, H_REGISTERS_S1RCFG = 104, H_REGISTERS_S1RSYNC = 105, H_REGISTERS_S1INTF = 106
+ , H_REGISTERS_S1INTE = 107, H_REGISTERS_S1MODE = 108, H_REGISTERS_S1SMASK = 109, H_REGISTERS_PSPCFG = 110
+ , H_REGISTERS_CMPCFG = 111, H_REGISTERS_S2TMRH = 112, H_REGISTERS_S2TMRL = 113, H_REGISTERS_S2TBUFH = 114
+ , H_REGISTERS_S2TBUFL = 115, H_REGISTERS_S2TCFG = 116, H_REGISTERS_S2RCNT = 117, H_REGISTERS_S2RBUFH = 118
+ , H_REGISTERS_S2RBUFL = 119, H_REGISTERS_S2RCFG = 120, H_REGISTERS_S2RSYNC = 121, H_REGISTERS_S2INTF = 122
+ , H_REGISTERS_S2INTE = 123, H_REGISTERS_S2MODE = 124, H_REGISTERS_S2SMASK = 125, H_REGISTERS_CALLH = 126
+ , H_REGISTERS_CALLL = 127
+} REGISTER_NAMES;
+
+/* Attributes. */
+
+/* Enum declaration for machine type selection. */
+typedef enum mach_attr {
+ MACH_BASE, MACH_IP2022, MACH_IP2022EXT, MACH_MAX
+} MACH_ATTR;
+
+/* Enum declaration for instruction set selection. */
+typedef enum isa_attr {
+ ISA_IP2K, ISA_MAX
+} ISA_ATTR;
+
+/* Number of architecture variants. */
+#define MAX_ISAS 1
+#define MAX_MACHS ((int) MACH_MAX)
+
+/* Ifield support. */
+
+extern const struct cgen_ifld ip2k_cgen_ifld_table[];
+
+/* Ifield attribute indices. */
+
+/* Enum declaration for cgen_ifld attrs. */
+typedef enum cgen_ifld_attr {
+ CGEN_IFLD_VIRTUAL, CGEN_IFLD_PCREL_ADDR, CGEN_IFLD_ABS_ADDR, CGEN_IFLD_RESERVED
+ , CGEN_IFLD_SIGN_OPT, CGEN_IFLD_SIGNED, CGEN_IFLD_END_BOOLS, CGEN_IFLD_START_NBOOLS = 31
+ , CGEN_IFLD_MACH, CGEN_IFLD_END_NBOOLS
+} CGEN_IFLD_ATTR;
+
+/* Number of non-boolean elements in cgen_ifld_attr. */
+#define CGEN_IFLD_NBOOL_ATTRS (CGEN_IFLD_END_NBOOLS - CGEN_IFLD_START_NBOOLS - 1)
+
+/* Enum declaration for ip2k ifield types. */
+typedef enum ifield_type {
+ IP2K_F_NIL, IP2K_F_ANYOF, IP2K_F_IMM8, IP2K_F_REG
+ , IP2K_F_ADDR16CJP, IP2K_F_DIR, IP2K_F_BITNO, IP2K_F_OP3
+ , IP2K_F_OP4, IP2K_F_OP4MID, IP2K_F_OP6, IP2K_F_OP8
+ , IP2K_F_OP6_10LOW, IP2K_F_OP6_7LOW, IP2K_F_RETI3, IP2K_F_SKIPB
+ , IP2K_F_PAGE3, IP2K_F_MAX
+} IFIELD_TYPE;
+
+#define MAX_IFLD ((int) IP2K_F_MAX)
+
+/* Hardware attribute indices. */
+
+/* Enum declaration for cgen_hw attrs. */
+typedef enum cgen_hw_attr {
+ CGEN_HW_VIRTUAL, CGEN_HW_CACHE_ADDR, CGEN_HW_PC, CGEN_HW_PROFILE
+ , CGEN_HW_END_BOOLS, CGEN_HW_START_NBOOLS = 31, CGEN_HW_MACH, CGEN_HW_END_NBOOLS
+} CGEN_HW_ATTR;
+
+/* Number of non-boolean elements in cgen_hw_attr. */
+#define CGEN_HW_NBOOL_ATTRS (CGEN_HW_END_NBOOLS - CGEN_HW_START_NBOOLS - 1)
+
+/* Enum declaration for ip2k hardware types. */
+typedef enum cgen_hw_type {
+ HW_H_MEMORY, HW_H_SINT, HW_H_UINT, HW_H_ADDR
+ , HW_H_IADDR, HW_H_SPR, HW_H_REGISTERS, HW_H_STACK
+ , HW_H_PABITS, HW_H_ZBIT, HW_H_CBIT, HW_H_DCBIT
+ , HW_H_PC, HW_MAX
+} CGEN_HW_TYPE;
+
+#define MAX_HW ((int) HW_MAX)
+
+/* Operand attribute indices. */
+
+/* Enum declaration for cgen_operand attrs. */
+typedef enum cgen_operand_attr {
+ CGEN_OPERAND_VIRTUAL, CGEN_OPERAND_PCREL_ADDR, CGEN_OPERAND_ABS_ADDR, CGEN_OPERAND_SIGN_OPT
+ , CGEN_OPERAND_SIGNED, CGEN_OPERAND_NEGATIVE, CGEN_OPERAND_RELAX, CGEN_OPERAND_SEM_ONLY
+ , CGEN_OPERAND_END_BOOLS, CGEN_OPERAND_START_NBOOLS = 31, CGEN_OPERAND_MACH, CGEN_OPERAND_END_NBOOLS
+} CGEN_OPERAND_ATTR;
+
+/* Number of non-boolean elements in cgen_operand_attr. */
+#define CGEN_OPERAND_NBOOL_ATTRS (CGEN_OPERAND_END_NBOOLS - CGEN_OPERAND_START_NBOOLS - 1)
+
+/* Enum declaration for ip2k operand types. */
+typedef enum cgen_operand_type {
+ IP2K_OPERAND_PC, IP2K_OPERAND_ADDR16CJP, IP2K_OPERAND_FR, IP2K_OPERAND_LIT8
+ , IP2K_OPERAND_BITNO, IP2K_OPERAND_ADDR16P, IP2K_OPERAND_ADDR16H, IP2K_OPERAND_ADDR16L
+ , IP2K_OPERAND_RETI3, IP2K_OPERAND_PABITS, IP2K_OPERAND_ZBIT, IP2K_OPERAND_CBIT
+ , IP2K_OPERAND_DCBIT, IP2K_OPERAND_MAX
+} CGEN_OPERAND_TYPE;
+
+/* Number of operands types. */
+#define MAX_OPERANDS 13
+
+/* Maximum number of operands referenced by any insn. */
+#define MAX_OPERAND_INSTANCES 8
+
+/* Insn attribute indices. */
+
+/* Enum declaration for cgen_insn attrs. */
+typedef enum cgen_insn_attr {
+ CGEN_INSN_ALIAS, CGEN_INSN_VIRTUAL, CGEN_INSN_UNCOND_CTI, CGEN_INSN_COND_CTI
+ , CGEN_INSN_SKIP_CTI, CGEN_INSN_DELAY_SLOT, CGEN_INSN_RELAXABLE, CGEN_INSN_RELAX
+ , CGEN_INSN_NO_DIS, CGEN_INSN_PBB, CGEN_INSN_EXT_SKIP_INSN, CGEN_INSN_SKIPA
+ , CGEN_INSN_END_BOOLS, CGEN_INSN_START_NBOOLS = 31, CGEN_INSN_MACH, CGEN_INSN_END_NBOOLS
+} CGEN_INSN_ATTR;
+
+/* Number of non-boolean elements in cgen_insn_attr. */
+#define CGEN_INSN_NBOOL_ATTRS (CGEN_INSN_END_NBOOLS - CGEN_INSN_START_NBOOLS - 1)
+
+/* cgen.h uses things we just defined. */
+#include "opcode/cgen.h"
+
+/* Attributes. */
+extern const CGEN_ATTR_TABLE ip2k_cgen_hardware_attr_table[];
+extern const CGEN_ATTR_TABLE ip2k_cgen_ifield_attr_table[];
+extern const CGEN_ATTR_TABLE ip2k_cgen_operand_attr_table[];
+extern const CGEN_ATTR_TABLE ip2k_cgen_insn_attr_table[];
+
+/* Hardware decls. */
+
+
+
+
+
+#endif /* IP2K_CPU_H */
--- /dev/null
+/* Disassembler interface for targets using CGEN. -*- C -*-
+ CGEN: Cpu tools GENerator
+
+THIS FILE IS MACHINE GENERATED WITH CGEN.
+- the resultant file is machine generated, cgen-dis.in isn't
+
+Copyright 1996, 1997, 1998, 1999, 2000, 2001 Free Software Foundation, Inc.
+
+This file is part of the GNU Binutils and GDB, the GNU debugger.
+
+This program is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2, or (at your option)
+any later version.
+
+This program is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with this program; if not, write to the Free Software Foundation, Inc.,
+59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
+
+/* ??? Eventually more and more of this stuff can go to cpu-independent files.
+ Keep that in mind. */
+
+#include "sysdep.h"
+#include <stdio.h>
+#include "ansidecl.h"
+#include "dis-asm.h"
+#include "bfd.h"
+#include "symcat.h"
+#include "ip2k-desc.h"
+#include "ip2k-opc.h"
+#include "opintl.h"
+
+/* Default text to print if an instruction isn't recognized. */
+#define UNKNOWN_INSN_MSG _("*unknown*")
+
+static void print_normal
+ PARAMS ((CGEN_CPU_DESC, PTR, long, unsigned int, bfd_vma, int));
+static void print_address
+ PARAMS ((CGEN_CPU_DESC, PTR, bfd_vma, unsigned int, bfd_vma, int));
+static void print_keyword
+ PARAMS ((CGEN_CPU_DESC, PTR, CGEN_KEYWORD *, long, unsigned int));
+static void print_insn_normal
+ PARAMS ((CGEN_CPU_DESC, PTR, const CGEN_INSN *, CGEN_FIELDS *,
+ bfd_vma, int));
+static int print_insn
+ PARAMS ((CGEN_CPU_DESC, bfd_vma, disassemble_info *, char *, unsigned));
+static int default_print_insn
+ PARAMS ((CGEN_CPU_DESC, bfd_vma, disassemble_info *));
+static int read_insn
+ PARAMS ((CGEN_CPU_DESC, bfd_vma, disassemble_info *, char *, int,
+ CGEN_EXTRACT_INFO *, unsigned long *));
+\f
+/* -- disassembler routines inserted here */
+
+/* -- dis.c */
+
+static void
+print_fr (cd, dis_info, value, attrs, pc, length)
+ CGEN_CPU_DESC cd;
+ PTR dis_info;
+ long value;
+ unsigned int attrs;
+ bfd_vma pc;
+ int length;
+{
+ disassemble_info *info = (disassemble_info *) dis_info;
+ const CGEN_KEYWORD_ENTRY *ke;
+ extern CGEN_KEYWORD ip2k_cgen_opval_register_names;
+ long offsettest;
+ long offsetvalue;
+
+ if ( value == 0 ) /* This is (IP) */
+ {
+ (*info->fprintf_func) (info->stream, "%s", "(IP)");
+ return;
+ }
+
+ offsettest = value >> 7;
+ offsetvalue = value & 0x7F;
+
+ /* Check to see if first two bits are 10 -> (DP) */
+ if ( offsettest == 2 )
+ {
+ if ( offsetvalue == 0 )
+ (*info->fprintf_func) (info->stream, "%s","(DP)");
+ else
+ (*info->fprintf_func) (info->stream, "$%x%s",offsetvalue, "(DP)");
+ return;
+ }
+
+ /* Check to see if first two bits are 11 -> (SP) */
+ if ( offsettest == 3 )
+ {
+ if ( offsetvalue == 0 )
+ (*info->fprintf_func) (info->stream, "%s", "(SP)");
+ else
+ (*info->fprintf_func) (info->stream, "$%x%s", offsetvalue,"(SP)");
+ return;
+ }
+
+ /* Attempt to print as a register keyword. */
+ ke = cgen_keyword_lookup_value (& ip2k_cgen_opval_register_names, value);
+ if (ke != NULL)
+ {
+ (*info->fprintf_func) (info->stream, "%s", ke->name);
+ return;
+ }
+
+ /* Print as an address literal. */
+ (*info->fprintf_func) (info->stream, "$%02x", value);
+}
+
+static void
+print_dollarhex (cd, dis_info, value, attrs, pc, length)
+ CGEN_CPU_DESC cd;
+ PTR dis_info;
+ long value;
+ unsigned int attrs;
+ bfd_vma pc;
+ int length;
+{
+ disassemble_info *info = (disassemble_info *) dis_info;
+
+ (*info->fprintf_func) (info->stream, "$%x", value);
+}
+
+static void
+print_dollarhex8 (cd, dis_info, value, attrs, pc, length)
+ CGEN_CPU_DESC cd;
+ PTR dis_info;
+ long value;
+ unsigned int attrs;
+ bfd_vma pc;
+ int length;
+{
+ disassemble_info *info = (disassemble_info *) dis_info;
+
+ (*info->fprintf_func) (info->stream, "$%02x", value);
+}
+
+static void
+print_dollarhex16 (cd, dis_info, value, attrs, pc, length)
+ CGEN_CPU_DESC cd;
+ PTR dis_info;
+ long value;
+ unsigned int attrs;
+ bfd_vma pc;
+ int length;
+{
+ disassemble_info *info = (disassemble_info *) dis_info;
+
+ (*info->fprintf_func) (info->stream, "$%04x", value);
+}
+
+static void
+print_dollarhex_addr16h (cd, dis_info, value, attrs, pc, length)
+ CGEN_CPU_DESC cd;
+ PTR dis_info;
+ long value;
+ unsigned int attrs;
+ bfd_vma pc;
+ int length;
+{
+ disassemble_info *info = (disassemble_info *) dis_info;
+
+ /* This is a loadh instruction. Shift the value to the left */
+ /* by 8 bits so that disassembled code will reassemble properly. */
+ value = ((value << 8) & 0xFF00);
+
+ (*info->fprintf_func) (info->stream, "$%04x", value);
+}
+
+static void
+print_dollarhex_addr16l (cd, dis_info, value, attrs, pc, length)
+ CGEN_CPU_DESC cd;
+ PTR dis_info;
+ long value;
+ unsigned int attrs;
+ bfd_vma pc;
+ int length;
+{
+ disassemble_info *info = (disassemble_info *) dis_info;
+
+ (*info->fprintf_func) (info->stream, "$%04x", value);
+}
+
+static void
+print_dollarhex_p (cd, dis_info, value, attrs, pc, length)
+ CGEN_CPU_DESC cd;
+ PTR dis_info;
+ long value;
+ unsigned int attrs;
+ bfd_vma pc;
+ int length;
+{
+ disassemble_info *info = (disassemble_info *) dis_info;
+
+ value = ((value << 14) & 0x1C000);
+ ;value = (value & 0x1FFFF);
+ (*info->fprintf_func) (info->stream, "$%05x", value);
+}
+
+static void
+print_dollarhex_cj (cd, dis_info, value, attrs, pc, length)
+ CGEN_CPU_DESC cd;
+ PTR dis_info;
+ long value;
+ unsigned int attrs;
+ bfd_vma pc;
+ int length;
+{
+ disassemble_info *info = (disassemble_info *) dis_info;
+
+ value = ((value << 1) & 0x1FFFF);
+ (*info->fprintf_func) (info->stream, "$%05x", value);
+}
+
+
+static void
+print_decimal (cd, dis_info, value, attrs, pc, length)
+ CGEN_CPU_DESC cd;
+ PTR dis_info;
+ long value;
+ unsigned int attrs;
+ bfd_vma pc;
+ int length;
+{
+ disassemble_info *info = (disassemble_info *) dis_info;
+
+ (*info->fprintf_func) (info->stream, "%d", value);
+}
+
+
+
+/* -- */
+
+void ip2k_cgen_print_operand
+ PARAMS ((CGEN_CPU_DESC, int, PTR, CGEN_FIELDS *,
+ void const *, bfd_vma, int));
+
+/* Main entry point for printing operands.
+ XINFO is a `void *' and not a `disassemble_info *' to not put a requirement
+ of dis-asm.h on cgen.h.
+
+ This function is basically just a big switch statement. Earlier versions
+ used tables to look up the function to use, but
+ - if the table contains both assembler and disassembler functions then
+ the disassembler contains much of the assembler and vice-versa,
+ - there's a lot of inlining possibilities as things grow,
+ - using a switch statement avoids the function call overhead.
+
+ This function could be moved into `print_insn_normal', but keeping it
+ separate makes clear the interface between `print_insn_normal' and each of
+ the handlers. */
+
+void
+ip2k_cgen_print_operand (cd, opindex, xinfo, fields, attrs, pc, length)
+ CGEN_CPU_DESC cd;
+ int opindex;
+ PTR xinfo;
+ CGEN_FIELDS *fields;
+ void const *attrs ATTRIBUTE_UNUSED;
+ bfd_vma pc;
+ int length;
+{
+ disassemble_info *info = (disassemble_info *) xinfo;
+
+ switch (opindex)
+ {
+ case IP2K_OPERAND_ADDR16CJP :
+ print_dollarhex_cj (cd, info, fields->f_addr16cjp, 0|(1<<CGEN_OPERAND_ABS_ADDR), pc, length);
+ break;
+ case IP2K_OPERAND_ADDR16H :
+ print_dollarhex_addr16h (cd, info, fields->f_imm8, 0, pc, length);
+ break;
+ case IP2K_OPERAND_ADDR16L :
+ print_dollarhex_addr16l (cd, info, fields->f_imm8, 0, pc, length);
+ break;
+ case IP2K_OPERAND_ADDR16P :
+ print_dollarhex_p (cd, info, fields->f_page3, 0, pc, length);
+ break;
+ case IP2K_OPERAND_BITNO :
+ print_decimal (cd, info, fields->f_bitno, 0, pc, length);
+ break;
+ case IP2K_OPERAND_CBIT :
+ print_normal (cd, info, 0, 0, pc, length);
+ break;
+ case IP2K_OPERAND_DCBIT :
+ print_normal (cd, info, 0, 0, pc, length);
+ break;
+ case IP2K_OPERAND_FR :
+ print_fr (cd, info, fields->f_reg, 0|(1<<CGEN_OPERAND_ABS_ADDR), pc, length);
+ break;
+ case IP2K_OPERAND_LIT8 :
+ print_dollarhex8 (cd, info, fields->f_imm8, 0|(1<<CGEN_OPERAND_SIGNED), pc, length);
+ break;
+ case IP2K_OPERAND_PABITS :
+ print_normal (cd, info, 0, 0, pc, length);
+ break;
+ case IP2K_OPERAND_RETI3 :
+ print_dollarhex (cd, info, fields->f_reti3, 0, pc, length);
+ break;
+ case IP2K_OPERAND_ZBIT :
+ print_normal (cd, info, 0, 0, pc, length);
+ break;
+
+ default :
+ /* xgettext:c-format */
+ fprintf (stderr, _("Unrecognized field %d while printing insn.\n"),
+ opindex);
+ abort ();
+ }
+}
+
+cgen_print_fn * const ip2k_cgen_print_handlers[] =
+{
+ print_insn_normal,
+};
+
+
+void
+ip2k_cgen_init_dis (cd)
+ CGEN_CPU_DESC cd;
+{
+ ip2k_cgen_init_opcode_table (cd);
+ ip2k_cgen_init_ibld_table (cd);
+ cd->print_handlers = & ip2k_cgen_print_handlers[0];
+ cd->print_operand = ip2k_cgen_print_operand;
+}
+
+\f
+/* Default print handler. */
+
+static void
+print_normal (cd, dis_info, value, attrs, pc, length)
+ CGEN_CPU_DESC cd ATTRIBUTE_UNUSED;
+ PTR dis_info;
+ long value;
+ unsigned int attrs;
+ bfd_vma pc ATTRIBUTE_UNUSED;
+ int length ATTRIBUTE_UNUSED;
+{
+ disassemble_info *info = (disassemble_info *) dis_info;
+
+#ifdef CGEN_PRINT_NORMAL
+ CGEN_PRINT_NORMAL (cd, info, value, attrs, pc, length);
+#endif
+
+ /* Print the operand as directed by the attributes. */
+ if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SEM_ONLY))
+ ; /* nothing to do */
+ else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SIGNED))
+ (*info->fprintf_func) (info->stream, "%ld", value);
+ else
+ (*info->fprintf_func) (info->stream, "0x%lx", value);
+}
+
+/* Default address handler. */
+
+static void
+print_address (cd, dis_info, value, attrs, pc, length)
+ CGEN_CPU_DESC cd ATTRIBUTE_UNUSED;
+ PTR dis_info;
+ bfd_vma value;
+ unsigned int attrs;
+ bfd_vma pc ATTRIBUTE_UNUSED;
+ int length ATTRIBUTE_UNUSED;
+{
+ disassemble_info *info = (disassemble_info *) dis_info;
+
+#ifdef CGEN_PRINT_ADDRESS
+ CGEN_PRINT_ADDRESS (cd, info, value, attrs, pc, length);
+#endif
+
+ /* Print the operand as directed by the attributes. */
+ if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SEM_ONLY))
+ ; /* nothing to do */
+ else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_PCREL_ADDR))
+ (*info->print_address_func) (value, info);
+ else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_ABS_ADDR))
+ (*info->print_address_func) (value, info);
+ else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SIGNED))
+ (*info->fprintf_func) (info->stream, "%ld", (long) value);
+ else
+ (*info->fprintf_func) (info->stream, "0x%lx", (long) value);
+}
+
+/* Keyword print handler. */
+
+static void
+print_keyword (cd, dis_info, keyword_table, value, attrs)
+ CGEN_CPU_DESC cd ATTRIBUTE_UNUSED;
+ PTR dis_info;
+ CGEN_KEYWORD *keyword_table;
+ long value;
+ unsigned int attrs ATTRIBUTE_UNUSED;
+{
+ disassemble_info *info = (disassemble_info *) dis_info;
+ const CGEN_KEYWORD_ENTRY *ke;
+
+ ke = cgen_keyword_lookup_value (keyword_table, value);
+ if (ke != NULL)
+ (*info->fprintf_func) (info->stream, "%s", ke->name);
+ else
+ (*info->fprintf_func) (info->stream, "???");
+}
+\f
+/* Default insn printer.
+
+ DIS_INFO is defined as `PTR' so the disassembler needn't know anything
+ about disassemble_info. */
+
+static void
+print_insn_normal (cd, dis_info, insn, fields, pc, length)
+ CGEN_CPU_DESC cd;
+ PTR dis_info;
+ const CGEN_INSN *insn;
+ CGEN_FIELDS *fields;
+ bfd_vma pc;
+ int length;
+{
+ const CGEN_SYNTAX *syntax = CGEN_INSN_SYNTAX (insn);
+ disassemble_info *info = (disassemble_info *) dis_info;
+ const CGEN_SYNTAX_CHAR_TYPE *syn;
+
+ CGEN_INIT_PRINT (cd);
+
+ for (syn = CGEN_SYNTAX_STRING (syntax); *syn; ++syn)
+ {
+ if (CGEN_SYNTAX_MNEMONIC_P (*syn))
+ {
+ (*info->fprintf_func) (info->stream, "%s", CGEN_INSN_MNEMONIC (insn));
+ continue;
+ }
+ if (CGEN_SYNTAX_CHAR_P (*syn))
+ {
+ (*info->fprintf_func) (info->stream, "%c", CGEN_SYNTAX_CHAR (*syn));
+ continue;
+ }
+
+ /* We have an operand. */
+ ip2k_cgen_print_operand (cd, CGEN_SYNTAX_FIELD (*syn), info,
+ fields, CGEN_INSN_ATTRS (insn), pc, length);
+ }
+}
+\f
+/* Subroutine of print_insn. Reads an insn into the given buffers and updates
+ the extract info.
+ Returns 0 if all is well, non-zero otherwise. */
+
+static int
+read_insn (cd, pc, info, buf, buflen, ex_info, insn_value)
+ CGEN_CPU_DESC cd ATTRIBUTE_UNUSED;
+ bfd_vma pc;
+ disassemble_info *info;
+ char *buf;
+ int buflen;
+ CGEN_EXTRACT_INFO *ex_info;
+ unsigned long *insn_value;
+{
+ int status = (*info->read_memory_func) (pc, buf, buflen, info);
+ if (status != 0)
+ {
+ (*info->memory_error_func) (status, pc, info);
+ return -1;
+ }
+
+ ex_info->dis_info = info;
+ ex_info->valid = (1 << buflen) - 1;
+ ex_info->insn_bytes = buf;
+
+ *insn_value = bfd_get_bits (buf, buflen * 8, info->endian == BFD_ENDIAN_BIG);
+ return 0;
+}
+
+/* Utility to print an insn.
+ BUF is the base part of the insn, target byte order, BUFLEN bytes long.
+ The result is the size of the insn in bytes or zero for an unknown insn
+ or -1 if an error occurs fetching data (memory_error_func will have
+ been called). */
+
+static int
+print_insn (cd, pc, info, buf, buflen)
+ CGEN_CPU_DESC cd;
+ bfd_vma pc;
+ disassemble_info *info;
+ char *buf;
+ unsigned int buflen;
+{
+ CGEN_INSN_INT insn_value;
+ const CGEN_INSN_LIST *insn_list;
+ CGEN_EXTRACT_INFO ex_info;
+ int basesize;
+
+ /* Extract base part of instruction, just in case CGEN_DIS_* uses it. */
+ basesize = cd->base_insn_bitsize < buflen * 8 ?
+ cd->base_insn_bitsize : buflen * 8;
+ insn_value = cgen_get_insn_value (cd, buf, basesize);
+
+
+ /* Fill in ex_info fields like read_insn would. Don't actually call
+ read_insn, since the incoming buffer is already read (and possibly
+ modified a la m32r). */
+ ex_info.valid = (1 << buflen) - 1;
+ ex_info.dis_info = info;
+ ex_info.insn_bytes = buf;
+
+ /* The instructions are stored in hash lists.
+ Pick the first one and keep trying until we find the right one. */
+
+ insn_list = CGEN_DIS_LOOKUP_INSN (cd, buf, insn_value);
+ while (insn_list != NULL)
+ {
+ const CGEN_INSN *insn = insn_list->insn;
+ CGEN_FIELDS fields;
+ int length;
+ unsigned long insn_value_cropped;
+
+#ifdef CGEN_VALIDATE_INSN_SUPPORTED
+ /* Not needed as insn shouldn't be in hash lists if not supported. */
+ /* Supported by this cpu? */
+ if (! ip2k_cgen_insn_supported (cd, insn))
+ {
+ insn_list = CGEN_DIS_NEXT_INSN (insn_list);
+ continue;
+ }
+#endif
+
+ /* Basic bit mask must be correct. */
+ /* ??? May wish to allow target to defer this check until the extract
+ handler. */
+
+ /* Base size may exceed this instruction's size. Extract the
+ relevant part from the buffer. */
+ if ((unsigned) (CGEN_INSN_BITSIZE (insn) / 8) < buflen &&
+ (unsigned) (CGEN_INSN_BITSIZE (insn) / 8) <= sizeof (unsigned long))
+ insn_value_cropped = bfd_get_bits (buf, CGEN_INSN_BITSIZE (insn),
+ info->endian == BFD_ENDIAN_BIG);
+ else
+ insn_value_cropped = insn_value;
+
+ if ((insn_value_cropped & CGEN_INSN_BASE_MASK (insn))
+ == CGEN_INSN_BASE_VALUE (insn))
+ {
+ /* Printing is handled in two passes. The first pass parses the
+ machine insn and extracts the fields. The second pass prints
+ them. */
+
+ /* Make sure the entire insn is loaded into insn_value, if it
+ can fit. */
+ if (((unsigned) CGEN_INSN_BITSIZE (insn) > cd->base_insn_bitsize) &&
+ (unsigned) (CGEN_INSN_BITSIZE (insn) / 8) <= sizeof (unsigned long))
+ {
+ unsigned long full_insn_value;
+ int rc = read_insn (cd, pc, info, buf,
+ CGEN_INSN_BITSIZE (insn) / 8,
+ & ex_info, & full_insn_value);
+ if (rc != 0)
+ return rc;
+ length = CGEN_EXTRACT_FN (cd, insn)
+ (cd, insn, &ex_info, full_insn_value, &fields, pc);
+ }
+ else
+ length = CGEN_EXTRACT_FN (cd, insn)
+ (cd, insn, &ex_info, insn_value_cropped, &fields, pc);
+
+ /* length < 0 -> error */
+ if (length < 0)
+ return length;
+ if (length > 0)
+ {
+ CGEN_PRINT_FN (cd, insn) (cd, info, insn, &fields, pc, length);
+ /* length is in bits, result is in bytes */
+ return length / 8;
+ }
+ }
+
+ insn_list = CGEN_DIS_NEXT_INSN (insn_list);
+ }
+
+ return 0;
+}
+
+/* Default value for CGEN_PRINT_INSN.
+ The result is the size of the insn in bytes or zero for an unknown insn
+ or -1 if an error occured fetching bytes. */
+
+#ifndef CGEN_PRINT_INSN
+#define CGEN_PRINT_INSN default_print_insn
+#endif
+
+static int
+default_print_insn (cd, pc, info)
+ CGEN_CPU_DESC cd;
+ bfd_vma pc;
+ disassemble_info *info;
+{
+ char buf[CGEN_MAX_INSN_SIZE];
+ int buflen;
+ int status;
+
+ /* Attempt to read the base part of the insn. */
+ buflen = cd->base_insn_bitsize / 8;
+ status = (*info->read_memory_func) (pc, buf, buflen, info);
+
+ /* Try again with the minimum part, if min < base. */
+ if (status != 0 && (cd->min_insn_bitsize < cd->base_insn_bitsize))
+ {
+ buflen = cd->min_insn_bitsize / 8;
+ status = (*info->read_memory_func) (pc, buf, buflen, info);
+ }
+
+ if (status != 0)
+ {
+ (*info->memory_error_func) (status, pc, info);
+ return -1;
+ }
+
+ return print_insn (cd, pc, info, buf, buflen);
+}
+
+/* Main entry point.
+ Print one instruction from PC on INFO->STREAM.
+ Return the size of the instruction (in bytes). */
+
+typedef struct cpu_desc_list {
+ struct cpu_desc_list *next;
+ int isa;
+ int mach;
+ int endian;
+ CGEN_CPU_DESC cd;
+} cpu_desc_list;
+
+int
+print_insn_ip2k (pc, info)
+ bfd_vma pc;
+ disassemble_info *info;
+{
+ static cpu_desc_list *cd_list = 0;
+ cpu_desc_list *cl = 0;
+ static CGEN_CPU_DESC cd = 0;
+ static int prev_isa;
+ static int prev_mach;
+ static int prev_endian;
+ int length;
+ int isa,mach;
+ int endian = (info->endian == BFD_ENDIAN_BIG
+ ? CGEN_ENDIAN_BIG
+ : CGEN_ENDIAN_LITTLE);
+ enum bfd_architecture arch;
+
+ /* ??? gdb will set mach but leave the architecture as "unknown" */
+#ifndef CGEN_BFD_ARCH
+#define CGEN_BFD_ARCH bfd_arch_ip2k
+#endif
+ arch = info->arch;
+ if (arch == bfd_arch_unknown)
+ arch = CGEN_BFD_ARCH;
+
+ /* There's no standard way to compute the machine or isa number
+ so we leave it to the target. */
+#ifdef CGEN_COMPUTE_MACH
+ mach = CGEN_COMPUTE_MACH (info);
+#else
+ mach = info->mach;
+#endif
+
+#ifdef CGEN_COMPUTE_ISA
+ isa = CGEN_COMPUTE_ISA (info);
+#else
+ isa = info->insn_sets;
+#endif
+
+ /* If we've switched cpu's, try to find a handle we've used before */
+ if (cd
+ && (isa != prev_isa
+ || mach != prev_mach
+ || endian != prev_endian))
+ {
+ cd = 0;
+ for (cl = cd_list; cl; cl = cl->next)
+ {
+ if (cl->isa == isa &&
+ cl->mach == mach &&
+ cl->endian == endian)
+ {
+ cd = cl->cd;
+ break;
+ }
+ }
+ }
+
+ /* If we haven't initialized yet, initialize the opcode table. */
+ if (! cd)
+ {
+ const bfd_arch_info_type *arch_type = bfd_lookup_arch (arch, mach);
+ const char *mach_name;
+
+ if (!arch_type)
+ abort ();
+ mach_name = arch_type->printable_name;
+
+ prev_isa = isa;
+ prev_mach = mach;
+ prev_endian = endian;
+ cd = ip2k_cgen_cpu_open (CGEN_CPU_OPEN_ISAS, prev_isa,
+ CGEN_CPU_OPEN_BFDMACH, mach_name,
+ CGEN_CPU_OPEN_ENDIAN, prev_endian,
+ CGEN_CPU_OPEN_END);
+ if (!cd)
+ abort ();
+
+ /* save this away for future reference */
+ cl = xmalloc (sizeof (struct cpu_desc_list));
+ cl->cd = cd;
+ cl->isa = isa;
+ cl->mach = mach;
+ cl->endian = endian;
+ cl->next = cd_list;
+ cd_list = cl;
+
+ ip2k_cgen_init_dis (cd);
+ }
+
+ /* We try to have as much common code as possible.
+ But at this point some targets need to take over. */
+ /* ??? Some targets may need a hook elsewhere. Try to avoid this,
+ but if not possible try to move this hook elsewhere rather than
+ have two hooks. */
+ length = CGEN_PRINT_INSN (cd, pc, info);
+ if (length > 0)
+ return length;
+ if (length < 0)
+ return -1;
+
+ (*info->fprintf_func) (info->stream, UNKNOWN_INSN_MSG);
+ return cd->default_insn_bitsize / 8;
+}
--- /dev/null
+/* Instruction building/extraction support for ip2k. -*- C -*-
+
+THIS FILE IS MACHINE GENERATED WITH CGEN: Cpu tools GENerator.
+- the resultant file is machine generated, cgen-ibld.in isn't
+
+Copyright 1996, 1997, 1998, 1999, 2000, 2001 Free Software Foundation, Inc.
+
+This file is part of the GNU Binutils and GDB, the GNU debugger.
+
+This program is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2, or (at your option)
+any later version.
+
+This program is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with this program; if not, write to the Free Software Foundation, Inc.,
+59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
+
+/* ??? Eventually more and more of this stuff can go to cpu-independent files.
+ Keep that in mind. */
+
+#include "sysdep.h"
+#include <stdio.h>
+#include "ansidecl.h"
+#include "dis-asm.h"
+#include "bfd.h"
+#include "symcat.h"
+#include "ip2k-desc.h"
+#include "ip2k-opc.h"
+#include "opintl.h"
+#include "safe-ctype.h"
+
+#undef min
+#define min(a,b) ((a) < (b) ? (a) : (b))
+#undef max
+#define max(a,b) ((a) > (b) ? (a) : (b))
+
+/* Used by the ifield rtx function. */
+#define FLD(f) (fields->f)
+
+static const char * insert_normal
+ PARAMS ((CGEN_CPU_DESC, long, unsigned int, unsigned int, unsigned int,
+ unsigned int, unsigned int, unsigned int, CGEN_INSN_BYTES_PTR));
+static const char * insert_insn_normal
+ PARAMS ((CGEN_CPU_DESC, const CGEN_INSN *,
+ CGEN_FIELDS *, CGEN_INSN_BYTES_PTR, bfd_vma));
+static int extract_normal
+ PARAMS ((CGEN_CPU_DESC, CGEN_EXTRACT_INFO *, CGEN_INSN_INT,
+ unsigned int, unsigned int, unsigned int, unsigned int,
+ unsigned int, unsigned int, bfd_vma, long *));
+static int extract_insn_normal
+ PARAMS ((CGEN_CPU_DESC, const CGEN_INSN *, CGEN_EXTRACT_INFO *,
+ CGEN_INSN_INT, CGEN_FIELDS *, bfd_vma));
+#if CGEN_INT_INSN_P
+static void put_insn_int_value
+ PARAMS ((CGEN_CPU_DESC, CGEN_INSN_BYTES_PTR, int, int, CGEN_INSN_INT));
+#endif
+#if ! CGEN_INT_INSN_P
+static CGEN_INLINE void insert_1
+ PARAMS ((CGEN_CPU_DESC, unsigned long, int, int, int, unsigned char *));
+static CGEN_INLINE int fill_cache
+ PARAMS ((CGEN_CPU_DESC, CGEN_EXTRACT_INFO *, int, int, bfd_vma));
+static CGEN_INLINE long extract_1
+ PARAMS ((CGEN_CPU_DESC, CGEN_EXTRACT_INFO *, int, int, int,
+ unsigned char *, bfd_vma));
+#endif
+\f
+/* Operand insertion. */
+
+#if ! CGEN_INT_INSN_P
+
+/* Subroutine of insert_normal. */
+
+static CGEN_INLINE void
+insert_1 (cd, value, start, length, word_length, bufp)
+ CGEN_CPU_DESC cd;
+ unsigned long value;
+ int start,length,word_length;
+ unsigned char *bufp;
+{
+ unsigned long x,mask;
+ int shift;
+
+ x = cgen_get_insn_value (cd, bufp, word_length);
+
+ /* Written this way to avoid undefined behaviour. */
+ mask = (((1L << (length - 1)) - 1) << 1) | 1;
+ if (CGEN_INSN_LSB0_P)
+ shift = (start + 1) - length;
+ else
+ shift = (word_length - (start + length));
+ x = (x & ~(mask << shift)) | ((value & mask) << shift);
+
+ cgen_put_insn_value (cd, bufp, word_length, (bfd_vma) x);
+}
+
+#endif /* ! CGEN_INT_INSN_P */
+
+/* Default insertion routine.
+
+ ATTRS is a mask of the boolean attributes.
+ WORD_OFFSET is the offset in bits from the start of the insn of the value.
+ WORD_LENGTH is the length of the word in bits in which the value resides.
+ START is the starting bit number in the word, architecture origin.
+ LENGTH is the length of VALUE in bits.
+ TOTAL_LENGTH is the total length of the insn in bits.
+
+ The result is an error message or NULL if success. */
+
+/* ??? This duplicates functionality with bfd's howto table and
+ bfd_install_relocation. */
+/* ??? This doesn't handle bfd_vma's. Create another function when
+ necessary. */
+
+static const char *
+insert_normal (cd, value, attrs, word_offset, start, length, word_length,
+ total_length, buffer)
+ CGEN_CPU_DESC cd;
+ long value;
+ unsigned int attrs;
+ unsigned int word_offset, start, length, word_length, total_length;
+ CGEN_INSN_BYTES_PTR buffer;
+{
+ static char errbuf[100];
+ /* Written this way to avoid undefined behaviour. */
+ unsigned long mask = (((1L << (length - 1)) - 1) << 1) | 1;
+
+ /* If LENGTH is zero, this operand doesn't contribute to the value. */
+ if (length == 0)
+ return NULL;
+
+#if 0
+ if (CGEN_INT_INSN_P
+ && word_offset != 0)
+ abort ();
+#endif
+
+ if (word_length > 32)
+ abort ();
+
+ /* For architectures with insns smaller than the base-insn-bitsize,
+ word_length may be too big. */
+ if (cd->min_insn_bitsize < cd->base_insn_bitsize)
+ {
+ if (word_offset == 0
+ && word_length > total_length)
+ word_length = total_length;
+ }
+
+ /* Ensure VALUE will fit. */
+ if (CGEN_BOOL_ATTR (attrs, CGEN_IFLD_SIGN_OPT))
+ {
+ long minval = - (1L << (length - 1));
+ unsigned long maxval = mask;
+
+ if ((value > 0 && (unsigned long) value > maxval)
+ || value < minval)
+ {
+ /* xgettext:c-format */
+ sprintf (errbuf,
+ _("operand out of range (%ld not between %ld and %lu)"),
+ value, minval, maxval);
+ return errbuf;
+ }
+ }
+ else if (! CGEN_BOOL_ATTR (attrs, CGEN_IFLD_SIGNED))
+ {
+ unsigned long maxval = mask;
+
+ if ((unsigned long) value > maxval)
+ {
+ /* xgettext:c-format */
+ sprintf (errbuf,
+ _("operand out of range (%lu not between 0 and %lu)"),
+ value, maxval);
+ return errbuf;
+ }
+ }
+ else
+ {
+ if (! cgen_signed_overflow_ok_p (cd))
+ {
+ long minval = - (1L << (length - 1));
+ long maxval = (1L << (length - 1)) - 1;
+
+ if (value < minval || value > maxval)
+ {
+ sprintf
+ /* xgettext:c-format */
+ (errbuf, _("operand out of range (%ld not between %ld and %ld)"),
+ value, minval, maxval);
+ return errbuf;
+ }
+ }
+ }
+
+#if CGEN_INT_INSN_P
+
+ {
+ int shift;
+
+ if (CGEN_INSN_LSB0_P)
+ shift = (word_offset + start + 1) - length;
+ else
+ shift = total_length - (word_offset + start + length);
+ *buffer = (*buffer & ~(mask << shift)) | ((value & mask) << shift);
+ }
+
+#else /* ! CGEN_INT_INSN_P */
+
+ {
+ unsigned char *bufp = (unsigned char *) buffer + word_offset / 8;
+
+ insert_1 (cd, value, start, length, word_length, bufp);
+ }
+
+#endif /* ! CGEN_INT_INSN_P */
+
+ return NULL;
+}
+
+/* Default insn builder (insert handler).
+ The instruction is recorded in CGEN_INT_INSN_P byte order (meaning
+ that if CGEN_INSN_BYTES_PTR is an int * and thus, the value is
+ recorded in host byte order, otherwise BUFFER is an array of bytes
+ and the value is recorded in target byte order).
+ The result is an error message or NULL if success. */
+
+static const char *
+insert_insn_normal (cd, insn, fields, buffer, pc)
+ CGEN_CPU_DESC cd;
+ const CGEN_INSN * insn;
+ CGEN_FIELDS * fields;
+ CGEN_INSN_BYTES_PTR buffer;
+ bfd_vma pc;
+{
+ const CGEN_SYNTAX *syntax = CGEN_INSN_SYNTAX (insn);
+ unsigned long value;
+ const CGEN_SYNTAX_CHAR_TYPE * syn;
+
+ CGEN_INIT_INSERT (cd);
+ value = CGEN_INSN_BASE_VALUE (insn);
+
+ /* If we're recording insns as numbers (rather than a string of bytes),
+ target byte order handling is deferred until later. */
+
+#if CGEN_INT_INSN_P
+
+ put_insn_int_value (cd, buffer, cd->base_insn_bitsize,
+ CGEN_FIELDS_BITSIZE (fields), value);
+
+#else
+
+ cgen_put_insn_value (cd, buffer, min ((unsigned) cd->base_insn_bitsize,
+ (unsigned) CGEN_FIELDS_BITSIZE (fields)),
+ value);
+
+#endif /* ! CGEN_INT_INSN_P */
+
+ /* ??? It would be better to scan the format's fields.
+ Still need to be able to insert a value based on the operand though;
+ e.g. storing a branch displacement that got resolved later.
+ Needs more thought first. */
+
+ for (syn = CGEN_SYNTAX_STRING (syntax); * syn; ++ syn)
+ {
+ const char *errmsg;
+
+ if (CGEN_SYNTAX_CHAR_P (* syn))
+ continue;
+
+ errmsg = (* cd->insert_operand) (cd, CGEN_SYNTAX_FIELD (*syn),
+ fields, buffer, pc);
+ if (errmsg)
+ return errmsg;
+ }
+
+ return NULL;
+}
+
+#if CGEN_INT_INSN_P
+/* Cover function to store an insn value into an integral insn. Must go here
+ because it needs <prefix>-desc.h for CGEN_INT_INSN_P. */
+
+static void
+put_insn_int_value (cd, buf, length, insn_length, value)
+ CGEN_CPU_DESC cd ATTRIBUTE_UNUSED;
+ CGEN_INSN_BYTES_PTR buf;
+ int length;
+ int insn_length;
+ CGEN_INSN_INT value;
+{
+ /* For architectures with insns smaller than the base-insn-bitsize,
+ length may be too big. */
+ if (length > insn_length)
+ *buf = value;
+ else
+ {
+ int shift = insn_length - length;
+ /* Written this way to avoid undefined behaviour. */
+ CGEN_INSN_INT mask = (((1L << (length - 1)) - 1) << 1) | 1;
+ *buf = (*buf & ~(mask << shift)) | ((value & mask) << shift);
+ }
+}
+#endif
+\f
+/* Operand extraction. */
+
+#if ! CGEN_INT_INSN_P
+
+/* Subroutine of extract_normal.
+ Ensure sufficient bytes are cached in EX_INFO.
+ OFFSET is the offset in bytes from the start of the insn of the value.
+ BYTES is the length of the needed value.
+ Returns 1 for success, 0 for failure. */
+
+static CGEN_INLINE int
+fill_cache (cd, ex_info, offset, bytes, pc)
+ CGEN_CPU_DESC cd ATTRIBUTE_UNUSED;
+ CGEN_EXTRACT_INFO *ex_info;
+ int offset, bytes;
+ bfd_vma pc;
+{
+ /* It's doubtful that the middle part has already been fetched so
+ we don't optimize that case. kiss. */
+ unsigned int mask;
+ disassemble_info *info = (disassemble_info *) ex_info->dis_info;
+
+ /* First do a quick check. */
+ mask = (1 << bytes) - 1;
+ if (((ex_info->valid >> offset) & mask) == mask)
+ return 1;
+
+ /* Search for the first byte we need to read. */
+ for (mask = 1 << offset; bytes > 0; --bytes, ++offset, mask <<= 1)
+ if (! (mask & ex_info->valid))
+ break;
+
+ if (bytes)
+ {
+ int status;
+
+ pc += offset;
+ status = (*info->read_memory_func)
+ (pc, ex_info->insn_bytes + offset, bytes, info);
+
+ if (status != 0)
+ {
+ (*info->memory_error_func) (status, pc, info);
+ return 0;
+ }
+
+ ex_info->valid |= ((1 << bytes) - 1) << offset;
+ }
+
+ return 1;
+}
+
+/* Subroutine of extract_normal. */
+
+static CGEN_INLINE long
+extract_1 (cd, ex_info, start, length, word_length, bufp, pc)
+ CGEN_CPU_DESC cd;
+ CGEN_EXTRACT_INFO *ex_info ATTRIBUTE_UNUSED;
+ int start,length,word_length;
+ unsigned char *bufp;
+ bfd_vma pc ATTRIBUTE_UNUSED;
+{
+ unsigned long x;
+ int shift;
+#if 0
+ int big_p = CGEN_CPU_INSN_ENDIAN (cd) == CGEN_ENDIAN_BIG;
+#endif
+ x = cgen_get_insn_value (cd, bufp, word_length);
+
+ if (CGEN_INSN_LSB0_P)
+ shift = (start + 1) - length;
+ else
+ shift = (word_length - (start + length));
+ return x >> shift;
+}
+
+#endif /* ! CGEN_INT_INSN_P */
+
+/* Default extraction routine.
+
+ INSN_VALUE is the first base_insn_bitsize bits of the insn in host order,
+ or sometimes less for cases like the m32r where the base insn size is 32
+ but some insns are 16 bits.
+ ATTRS is a mask of the boolean attributes. We only need `SIGNED',
+ but for generality we take a bitmask of all of them.
+ WORD_OFFSET is the offset in bits from the start of the insn of the value.
+ WORD_LENGTH is the length of the word in bits in which the value resides.
+ START is the starting bit number in the word, architecture origin.
+ LENGTH is the length of VALUE in bits.
+ TOTAL_LENGTH is the total length of the insn in bits.
+
+ Returns 1 for success, 0 for failure. */
+
+/* ??? The return code isn't properly used. wip. */
+
+/* ??? This doesn't handle bfd_vma's. Create another function when
+ necessary. */
+
+static int
+extract_normal (cd, ex_info, insn_value, attrs, word_offset, start, length,
+ word_length, total_length, pc, valuep)
+ CGEN_CPU_DESC cd;
+#if ! CGEN_INT_INSN_P
+ CGEN_EXTRACT_INFO *ex_info;
+#else
+ CGEN_EXTRACT_INFO *ex_info ATTRIBUTE_UNUSED;
+#endif
+ CGEN_INSN_INT insn_value;
+ unsigned int attrs;
+ unsigned int word_offset, start, length, word_length, total_length;
+#if ! CGEN_INT_INSN_P
+ bfd_vma pc;
+#else
+ bfd_vma pc ATTRIBUTE_UNUSED;
+#endif
+ long *valuep;
+{
+ long value, mask;
+
+ /* If LENGTH is zero, this operand doesn't contribute to the value
+ so give it a standard value of zero. */
+ if (length == 0)
+ {
+ *valuep = 0;
+ return 1;
+ }
+
+#if 0
+ if (CGEN_INT_INSN_P
+ && word_offset != 0)
+ abort ();
+#endif
+
+ if (word_length > 32)
+ abort ();
+
+ /* For architectures with insns smaller than the insn-base-bitsize,
+ word_length may be too big. */
+ if (cd->min_insn_bitsize < cd->base_insn_bitsize)
+ {
+ if (word_offset == 0
+ && word_length > total_length)
+ word_length = total_length;
+ }
+
+ /* Does the value reside in INSN_VALUE, and at the right alignment? */
+
+ if (CGEN_INT_INSN_P || (word_offset == 0 && word_length == total_length))
+ {
+ if (CGEN_INSN_LSB0_P)
+ value = insn_value >> ((word_offset + start + 1) - length);
+ else
+ value = insn_value >> (total_length - ( word_offset + start + length));
+ }
+
+#if ! CGEN_INT_INSN_P
+
+ else
+ {
+ unsigned char *bufp = ex_info->insn_bytes + word_offset / 8;
+
+ if (word_length > 32)
+ abort ();
+
+ if (fill_cache (cd, ex_info, word_offset / 8, word_length / 8, pc) == 0)
+ return 0;
+
+ value = extract_1 (cd, ex_info, start, length, word_length, bufp, pc);
+ }
+
+#endif /* ! CGEN_INT_INSN_P */
+
+ /* Written this way to avoid undefined behaviour. */
+ mask = (((1L << (length - 1)) - 1) << 1) | 1;
+
+ value &= mask;
+ /* sign extend? */
+ if (CGEN_BOOL_ATTR (attrs, CGEN_IFLD_SIGNED)
+ && (value & (1L << (length - 1))))
+ value |= ~mask;
+
+ *valuep = value;
+
+ return 1;
+}
+
+/* Default insn extractor.
+
+ INSN_VALUE is the first base_insn_bitsize bits, translated to host order.
+ The extracted fields are stored in FIELDS.
+ EX_INFO is used to handle reading variable length insns.
+ Return the length of the insn in bits, or 0 if no match,
+ or -1 if an error occurs fetching data (memory_error_func will have
+ been called). */
+
+static int
+extract_insn_normal (cd, insn, ex_info, insn_value, fields, pc)
+ CGEN_CPU_DESC cd;
+ const CGEN_INSN *insn;
+ CGEN_EXTRACT_INFO *ex_info;
+ CGEN_INSN_INT insn_value;
+ CGEN_FIELDS *fields;
+ bfd_vma pc;
+{
+ const CGEN_SYNTAX *syntax = CGEN_INSN_SYNTAX (insn);
+ const CGEN_SYNTAX_CHAR_TYPE *syn;
+
+ CGEN_FIELDS_BITSIZE (fields) = CGEN_INSN_BITSIZE (insn);
+
+ CGEN_INIT_EXTRACT (cd);
+
+ for (syn = CGEN_SYNTAX_STRING (syntax); *syn; ++syn)
+ {
+ int length;
+
+ if (CGEN_SYNTAX_CHAR_P (*syn))
+ continue;
+
+ length = (* cd->extract_operand) (cd, CGEN_SYNTAX_FIELD (*syn),
+ ex_info, insn_value, fields, pc);
+ if (length <= 0)
+ return length;
+ }
+
+ /* We recognized and successfully extracted this insn. */
+ return CGEN_INSN_BITSIZE (insn);
+}
+\f
+/* machine generated code added here */
+
+const char * ip2k_cgen_insert_operand
+ PARAMS ((CGEN_CPU_DESC, int, CGEN_FIELDS *, CGEN_INSN_BYTES_PTR, bfd_vma));
+
+/* Main entry point for operand insertion.
+
+ This function is basically just a big switch statement. Earlier versions
+ used tables to look up the function to use, but
+ - if the table contains both assembler and disassembler functions then
+ the disassembler contains much of the assembler and vice-versa,
+ - there's a lot of inlining possibilities as things grow,
+ - using a switch statement avoids the function call overhead.
+
+ This function could be moved into `parse_insn_normal', but keeping it
+ separate makes clear the interface between `parse_insn_normal' and each of
+ the handlers. It's also needed by GAS to insert operands that couldn't be
+ resolved during parsing. */
+
+const char *
+ip2k_cgen_insert_operand (cd, opindex, fields, buffer, pc)
+ CGEN_CPU_DESC cd;
+ int opindex;
+ CGEN_FIELDS * fields;
+ CGEN_INSN_BYTES_PTR buffer;
+ bfd_vma pc ATTRIBUTE_UNUSED;
+{
+ const char * errmsg = NULL;
+ unsigned int total_length = CGEN_FIELDS_BITSIZE (fields);
+
+ switch (opindex)
+ {
+ case IP2K_OPERAND_ADDR16CJP :
+ errmsg = insert_normal (cd, fields->f_addr16cjp, 0|(1<<CGEN_IFLD_ABS_ADDR), 0, 12, 13, 16, total_length, buffer);
+ break;
+ case IP2K_OPERAND_ADDR16H :
+ errmsg = insert_normal (cd, fields->f_imm8, 0, 0, 7, 8, 16, total_length, buffer);
+ break;
+ case IP2K_OPERAND_ADDR16L :
+ errmsg = insert_normal (cd, fields->f_imm8, 0, 0, 7, 8, 16, total_length, buffer);
+ break;
+ case IP2K_OPERAND_ADDR16P :
+ errmsg = insert_normal (cd, fields->f_page3, 0, 0, 2, 3, 16, total_length, buffer);
+ break;
+ case IP2K_OPERAND_BITNO :
+ errmsg = insert_normal (cd, fields->f_bitno, 0, 0, 11, 3, 16, total_length, buffer);
+ break;
+ case IP2K_OPERAND_CBIT :
+ break;
+ case IP2K_OPERAND_DCBIT :
+ break;
+ case IP2K_OPERAND_FR :
+ errmsg = insert_normal (cd, fields->f_reg, 0|(1<<CGEN_IFLD_ABS_ADDR), 0, 8, 9, 16, total_length, buffer);
+ break;
+ case IP2K_OPERAND_LIT8 :
+ errmsg = insert_normal (cd, fields->f_imm8, 0, 0, 7, 8, 16, total_length, buffer);
+ break;
+ case IP2K_OPERAND_PABITS :
+ break;
+ case IP2K_OPERAND_RETI3 :
+ errmsg = insert_normal (cd, fields->f_reti3, 0, 0, 2, 3, 16, total_length, buffer);
+ break;
+ case IP2K_OPERAND_ZBIT :
+ break;
+
+ default :
+ /* xgettext:c-format */
+ fprintf (stderr, _("Unrecognized field %d while building insn.\n"),
+ opindex);
+ abort ();
+ }
+
+ return errmsg;
+}
+
+int ip2k_cgen_extract_operand
+ PARAMS ((CGEN_CPU_DESC, int, CGEN_EXTRACT_INFO *, CGEN_INSN_INT,
+ CGEN_FIELDS *, bfd_vma));
+
+/* Main entry point for operand extraction.
+ The result is <= 0 for error, >0 for success.
+ ??? Actual values aren't well defined right now.
+
+ This function is basically just a big switch statement. Earlier versions
+ used tables to look up the function to use, but
+ - if the table contains both assembler and disassembler functions then
+ the disassembler contains much of the assembler and vice-versa,
+ - there's a lot of inlining possibilities as things grow,
+ - using a switch statement avoids the function call overhead.
+
+ This function could be moved into `print_insn_normal', but keeping it
+ separate makes clear the interface between `print_insn_normal' and each of
+ the handlers. */
+
+int
+ip2k_cgen_extract_operand (cd, opindex, ex_info, insn_value, fields, pc)
+ CGEN_CPU_DESC cd;
+ int opindex;
+ CGEN_EXTRACT_INFO *ex_info;
+ CGEN_INSN_INT insn_value;
+ CGEN_FIELDS * fields;
+ bfd_vma pc;
+{
+ /* Assume success (for those operands that are nops). */
+ int length = 1;
+ unsigned int total_length = CGEN_FIELDS_BITSIZE (fields);
+
+ switch (opindex)
+ {
+ case IP2K_OPERAND_ADDR16CJP :
+ length = extract_normal (cd, ex_info, insn_value, 0|(1<<CGEN_IFLD_ABS_ADDR), 0, 12, 13, 16, total_length, pc, & fields->f_addr16cjp);
+ break;
+ case IP2K_OPERAND_ADDR16H :
+ length = extract_normal (cd, ex_info, insn_value, 0, 0, 7, 8, 16, total_length, pc, & fields->f_imm8);
+ break;
+ case IP2K_OPERAND_ADDR16L :
+ length = extract_normal (cd, ex_info, insn_value, 0, 0, 7, 8, 16, total_length, pc, & fields->f_imm8);
+ break;
+ case IP2K_OPERAND_ADDR16P :
+ length = extract_normal (cd, ex_info, insn_value, 0, 0, 2, 3, 16, total_length, pc, & fields->f_page3);
+ break;
+ case IP2K_OPERAND_BITNO :
+ length = extract_normal (cd, ex_info, insn_value, 0, 0, 11, 3, 16, total_length, pc, & fields->f_bitno);
+ break;
+ case IP2K_OPERAND_CBIT :
+ break;
+ case IP2K_OPERAND_DCBIT :
+ break;
+ case IP2K_OPERAND_FR :
+ length = extract_normal (cd, ex_info, insn_value, 0|(1<<CGEN_IFLD_ABS_ADDR), 0, 8, 9, 16, total_length, pc, & fields->f_reg);
+ break;
+ case IP2K_OPERAND_LIT8 :
+ length = extract_normal (cd, ex_info, insn_value, 0, 0, 7, 8, 16, total_length, pc, & fields->f_imm8);
+ break;
+ case IP2K_OPERAND_PABITS :
+ break;
+ case IP2K_OPERAND_RETI3 :
+ length = extract_normal (cd, ex_info, insn_value, 0, 0, 2, 3, 16, total_length, pc, & fields->f_reti3);
+ break;
+ case IP2K_OPERAND_ZBIT :
+ break;
+
+ default :
+ /* xgettext:c-format */
+ fprintf (stderr, _("Unrecognized field %d while decoding insn.\n"),
+ opindex);
+ abort ();
+ }
+
+ return length;
+}
+
+cgen_insert_fn * const ip2k_cgen_insert_handlers[] =
+{
+ insert_insn_normal,
+};
+
+cgen_extract_fn * const ip2k_cgen_extract_handlers[] =
+{
+ extract_insn_normal,
+};
+
+int ip2k_cgen_get_int_operand
+ PARAMS ((CGEN_CPU_DESC, int, const CGEN_FIELDS *));
+bfd_vma ip2k_cgen_get_vma_operand
+ PARAMS ((CGEN_CPU_DESC, int, const CGEN_FIELDS *));
+
+/* Getting values from cgen_fields is handled by a collection of functions.
+ They are distinguished by the type of the VALUE argument they return.
+ TODO: floating point, inlining support, remove cases where result type
+ not appropriate. */
+
+int
+ip2k_cgen_get_int_operand (cd, opindex, fields)
+ CGEN_CPU_DESC cd ATTRIBUTE_UNUSED;
+ int opindex;
+ const CGEN_FIELDS * fields;
+{
+ int value;
+
+ switch (opindex)
+ {
+ case IP2K_OPERAND_ADDR16CJP :
+ value = fields->f_addr16cjp;
+ break;
+ case IP2K_OPERAND_ADDR16H :
+ value = fields->f_imm8;
+ break;
+ case IP2K_OPERAND_ADDR16L :
+ value = fields->f_imm8;
+ break;
+ case IP2K_OPERAND_ADDR16P :
+ value = fields->f_page3;
+ break;
+ case IP2K_OPERAND_BITNO :
+ value = fields->f_bitno;
+ break;
+ case IP2K_OPERAND_CBIT :
+ value = 0;
+ break;
+ case IP2K_OPERAND_DCBIT :
+ value = 0;
+ break;
+ case IP2K_OPERAND_FR :
+ value = fields->f_reg;
+ break;
+ case IP2K_OPERAND_LIT8 :
+ value = fields->f_imm8;
+ break;
+ case IP2K_OPERAND_PABITS :
+ value = 0;
+ break;
+ case IP2K_OPERAND_RETI3 :
+ value = fields->f_reti3;
+ break;
+ case IP2K_OPERAND_ZBIT :
+ value = 0;
+ break;
+
+ default :
+ /* xgettext:c-format */
+ fprintf (stderr, _("Unrecognized field %d while getting int operand.\n"),
+ opindex);
+ abort ();
+ }
+
+ return value;
+}
+
+bfd_vma
+ip2k_cgen_get_vma_operand (cd, opindex, fields)
+ CGEN_CPU_DESC cd ATTRIBUTE_UNUSED;
+ int opindex;
+ const CGEN_FIELDS * fields;
+{
+ bfd_vma value;
+
+ switch (opindex)
+ {
+ case IP2K_OPERAND_ADDR16CJP :
+ value = fields->f_addr16cjp;
+ break;
+ case IP2K_OPERAND_ADDR16H :
+ value = fields->f_imm8;
+ break;
+ case IP2K_OPERAND_ADDR16L :
+ value = fields->f_imm8;
+ break;
+ case IP2K_OPERAND_ADDR16P :
+ value = fields->f_page3;
+ break;
+ case IP2K_OPERAND_BITNO :
+ value = fields->f_bitno;
+ break;
+ case IP2K_OPERAND_CBIT :
+ value = 0;
+ break;
+ case IP2K_OPERAND_DCBIT :
+ value = 0;
+ break;
+ case IP2K_OPERAND_FR :
+ value = fields->f_reg;
+ break;
+ case IP2K_OPERAND_LIT8 :
+ value = fields->f_imm8;
+ break;
+ case IP2K_OPERAND_PABITS :
+ value = 0;
+ break;
+ case IP2K_OPERAND_RETI3 :
+ value = fields->f_reti3;
+ break;
+ case IP2K_OPERAND_ZBIT :
+ value = 0;
+ break;
+
+ default :
+ /* xgettext:c-format */
+ fprintf (stderr, _("Unrecognized field %d while getting vma operand.\n"),
+ opindex);
+ abort ();
+ }
+
+ return value;
+}
+
+void ip2k_cgen_set_int_operand
+ PARAMS ((CGEN_CPU_DESC, int, CGEN_FIELDS *, int));
+void ip2k_cgen_set_vma_operand
+ PARAMS ((CGEN_CPU_DESC, int, CGEN_FIELDS *, bfd_vma));
+
+/* Stuffing values in cgen_fields is handled by a collection of functions.
+ They are distinguished by the type of the VALUE argument they accept.
+ TODO: floating point, inlining support, remove cases where argument type
+ not appropriate. */
+
+void
+ip2k_cgen_set_int_operand (cd, opindex, fields, value)
+ CGEN_CPU_DESC cd ATTRIBUTE_UNUSED;
+ int opindex;
+ CGEN_FIELDS * fields;
+ int value;
+{
+ switch (opindex)
+ {
+ case IP2K_OPERAND_ADDR16CJP :
+ fields->f_addr16cjp = value;
+ break;
+ case IP2K_OPERAND_ADDR16H :
+ fields->f_imm8 = value;
+ break;
+ case IP2K_OPERAND_ADDR16L :
+ fields->f_imm8 = value;
+ break;
+ case IP2K_OPERAND_ADDR16P :
+ fields->f_page3 = value;
+ break;
+ case IP2K_OPERAND_BITNO :
+ fields->f_bitno = value;
+ break;
+ case IP2K_OPERAND_CBIT :
+ break;
+ case IP2K_OPERAND_DCBIT :
+ break;
+ case IP2K_OPERAND_FR :
+ fields->f_reg = value;
+ break;
+ case IP2K_OPERAND_LIT8 :
+ fields->f_imm8 = value;
+ break;
+ case IP2K_OPERAND_PABITS :
+ break;
+ case IP2K_OPERAND_RETI3 :
+ fields->f_reti3 = value;
+ break;
+ case IP2K_OPERAND_ZBIT :
+ break;
+
+ default :
+ /* xgettext:c-format */
+ fprintf (stderr, _("Unrecognized field %d while setting int operand.\n"),
+ opindex);
+ abort ();
+ }
+}
+
+void
+ip2k_cgen_set_vma_operand (cd, opindex, fields, value)
+ CGEN_CPU_DESC cd ATTRIBUTE_UNUSED;
+ int opindex;
+ CGEN_FIELDS * fields;
+ bfd_vma value;
+{
+ switch (opindex)
+ {
+ case IP2K_OPERAND_ADDR16CJP :
+ fields->f_addr16cjp = value;
+ break;
+ case IP2K_OPERAND_ADDR16H :
+ fields->f_imm8 = value;
+ break;
+ case IP2K_OPERAND_ADDR16L :
+ fields->f_imm8 = value;
+ break;
+ case IP2K_OPERAND_ADDR16P :
+ fields->f_page3 = value;
+ break;
+ case IP2K_OPERAND_BITNO :
+ fields->f_bitno = value;
+ break;
+ case IP2K_OPERAND_CBIT :
+ break;
+ case IP2K_OPERAND_DCBIT :
+ break;
+ case IP2K_OPERAND_FR :
+ fields->f_reg = value;
+ break;
+ case IP2K_OPERAND_LIT8 :
+ fields->f_imm8 = value;
+ break;
+ case IP2K_OPERAND_PABITS :
+ break;
+ case IP2K_OPERAND_RETI3 :
+ fields->f_reti3 = value;
+ break;
+ case IP2K_OPERAND_ZBIT :
+ break;
+
+ default :
+ /* xgettext:c-format */
+ fprintf (stderr, _("Unrecognized field %d while setting vma operand.\n"),
+ opindex);
+ abort ();
+ }
+}
+
+/* Function to call before using the instruction builder tables. */
+
+void
+ip2k_cgen_init_ibld_table (cd)
+ CGEN_CPU_DESC cd;
+{
+ cd->insert_handlers = & ip2k_cgen_insert_handlers[0];
+ cd->extract_handlers = & ip2k_cgen_extract_handlers[0];
+
+ cd->insert_operand = ip2k_cgen_insert_operand;
+ cd->extract_operand = ip2k_cgen_extract_operand;
+
+ cd->get_int_operand = ip2k_cgen_get_int_operand;
+ cd->set_int_operand = ip2k_cgen_set_int_operand;
+ cd->get_vma_operand = ip2k_cgen_get_vma_operand;
+ cd->set_vma_operand = ip2k_cgen_set_vma_operand;
+}
--- /dev/null
+/* Instruction opcode table for ip2k.
+
+THIS FILE IS MACHINE GENERATED WITH CGEN.
+
+Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc.
+
+This file is part of the GNU Binutils and/or GDB, the GNU debugger.
+
+This program is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2, or (at your option)
+any later version.
+
+This program is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License along
+with this program; if not, write to the Free Software Foundation, Inc.,
+59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+
+*/
+
+#include "sysdep.h"
+#include "ansidecl.h"
+#include "bfd.h"
+#include "symcat.h"
+#include "ip2k-desc.h"
+#include "ip2k-opc.h"
+#include "libiberty.h"
+
+/* -- opc.c */
+
+/* A better hash function for instruction mnemonics. */
+unsigned int
+ip2k_asm_hash (insn)
+ const char* insn;
+{
+ unsigned int hash;
+ const char* m = insn;
+
+ for (hash = 0; *m && !isspace(*m); m++)
+ hash = (hash * 23) ^ (0x1F & tolower(*m));
+
+ /* printf ("%s %d\n", insn, (hash % CGEN_ASM_HASH_SIZE)); */
+
+ return hash % CGEN_ASM_HASH_SIZE;
+}
+
+
+
+\f
+/* -- asm.c */
+/* The hash functions are recorded here to help keep assembler code out of
+ the disassembler and vice versa. */
+
+static int asm_hash_insn_p PARAMS ((const CGEN_INSN *));
+static unsigned int asm_hash_insn PARAMS ((const char *));
+static int dis_hash_insn_p PARAMS ((const CGEN_INSN *));
+static unsigned int dis_hash_insn PARAMS ((const char *, CGEN_INSN_INT));
+
+/* Instruction formats. */
+
+#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
+#define F(f) & ip2k_cgen_ifld_table[IP2K_##f]
+#else
+#define F(f) & ip2k_cgen_ifld_table[IP2K_/**/f]
+#endif
+static const CGEN_IFMT ifmt_empty = {
+ 0, 0, 0x0, { { 0 } }
+};
+
+static const CGEN_IFMT ifmt_jmp = {
+ 16, 16, 0xe000, { { F (F_OP3) }, { F (F_ADDR16CJP) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_sb = {
+ 16, 16, 0xf000, { { F (F_OP4) }, { F (F_BITNO) }, { F (F_REG) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_xorw_l = {
+ 16, 16, 0xff00, { { F (F_OP4) }, { F (F_OP4MID) }, { F (F_IMM8) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_loadl_a = {
+ 16, 16, 0xff00, { { F (F_OP4) }, { F (F_OP4MID) }, { F (F_IMM8) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_loadh_a = {
+ 16, 16, 0xff00, { { F (F_OP4) }, { F (F_OP4MID) }, { F (F_IMM8) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_addcfr_w = {
+ 16, 16, 0xfe00, { { F (F_OP6) }, { F (F_DIR) }, { F (F_REG) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_speed = {
+ 16, 16, 0xff00, { { F (F_OP8) }, { F (F_IMM8) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_ireadi = {
+ 16, 16, 0xffff, { { F (F_OP6) }, { F (F_OP6_10LOW) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_page = {
+ 16, 16, 0xfff8, { { F (F_OP6) }, { F (F_OP6_7LOW) }, { F (F_PAGE3) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_reti = {
+ 16, 16, 0xfff8, { { F (F_OP6) }, { F (F_OP6_7LOW) }, { F (F_RETI3) }, { 0 } }
+};
+
+#undef F
+
+#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
+#define A(a) (1 << CGEN_INSN_##a)
+#else
+#define A(a) (1 << CGEN_INSN_/**/a)
+#endif
+#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
+#define OPERAND(op) IP2K_OPERAND_##op
+#else
+#define OPERAND(op) IP2K_OPERAND_/**/op
+#endif
+#define MNEM CGEN_SYNTAX_MNEMONIC /* syntax value for mnemonic */
+#define OP(field) CGEN_SYNTAX_MAKE_FIELD (OPERAND (field))
+
+/* The instruction table. */
+
+static const CGEN_OPCODE ip2k_cgen_insn_opcode_table[MAX_INSNS] =
+{
+ /* Special null first entry.
+ A `num' value of zero is thus invalid.
+ Also, the special `invalid' insn resides here. */
+ { { 0, 0, 0, 0 }, {{0}}, 0, {0}},
+/* jmp $addr16cjp */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (ADDR16CJP), 0 } },
+ & ifmt_jmp, { 0xe000 }
+ },
+/* call $addr16cjp */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (ADDR16CJP), 0 } },
+ & ifmt_jmp, { 0xc000 }
+ },
+/* sb $fr,$bitno */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (FR), ',', OP (BITNO), 0 } },
+ & ifmt_sb, { 0xb000 }
+ },
+/* snb $fr,$bitno */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (FR), ',', OP (BITNO), 0 } },
+ & ifmt_sb, { 0xa000 }
+ },
+/* setb $fr,$bitno */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (FR), ',', OP (BITNO), 0 } },
+ & ifmt_sb, { 0x9000 }
+ },
+/* clrb $fr,$bitno */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (FR), ',', OP (BITNO), 0 } },
+ & ifmt_sb, { 0x8000 }
+ },
+/* xor W,#$lit8 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', 'W', ',', '#', OP (LIT8), 0 } },
+ & ifmt_xorw_l, { 0x7f00 }
+ },
+/* and W,#$lit8 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', 'W', ',', '#', OP (LIT8), 0 } },
+ & ifmt_xorw_l, { 0x7e00 }
+ },
+/* or W,#$lit8 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', 'W', ',', '#', OP (LIT8), 0 } },
+ & ifmt_xorw_l, { 0x7d00 }
+ },
+/* add W,#$lit8 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', 'W', ',', '#', OP (LIT8), 0 } },
+ & ifmt_xorw_l, { 0x7b00 }
+ },
+/* sub W,#$lit8 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', 'W', ',', '#', OP (LIT8), 0 } },
+ & ifmt_xorw_l, { 0x7a00 }
+ },
+/* cmp W,#$lit8 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', 'W', ',', '#', OP (LIT8), 0 } },
+ & ifmt_xorw_l, { 0x7900 }
+ },
+/* retw #$lit8 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', '#', OP (LIT8), 0 } },
+ & ifmt_xorw_l, { 0x7800 }
+ },
+/* cse W,#$lit8 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', 'W', ',', '#', OP (LIT8), 0 } },
+ & ifmt_xorw_l, { 0x7700 }
+ },
+/* csne W,#$lit8 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', 'W', ',', '#', OP (LIT8), 0 } },
+ & ifmt_xorw_l, { 0x7600 }
+ },
+/* push #$lit8 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', '#', OP (LIT8), 0 } },
+ & ifmt_xorw_l, { 0x7400 }
+ },
+/* muls W,#$lit8 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', 'W', ',', '#', OP (LIT8), 0 } },
+ & ifmt_xorw_l, { 0x7300 }
+ },
+/* mulu W,#$lit8 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', 'W', ',', '#', OP (LIT8), 0 } },
+ & ifmt_xorw_l, { 0x7200 }
+ },
+/* loadl #$lit8 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', '#', OP (LIT8), 0 } },
+ & ifmt_xorw_l, { 0x7100 }
+ },
+/* loadh #$lit8 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', '#', OP (LIT8), 0 } },
+ & ifmt_xorw_l, { 0x7000 }
+ },
+/* loadl $addr16l */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (ADDR16L), 0 } },
+ & ifmt_loadl_a, { 0x7100 }
+ },
+/* loadh $addr16h */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (ADDR16H), 0 } },
+ & ifmt_loadh_a, { 0x7000 }
+ },
+/* addc $fr,W */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (FR), ',', 'W', 0 } },
+ & ifmt_addcfr_w, { 0x5e00 }
+ },
+/* addc W,$fr */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', 'W', ',', OP (FR), 0 } },
+ & ifmt_addcfr_w, { 0x5c00 }
+ },
+/* incsnz $fr */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (FR), 0 } },
+ & ifmt_addcfr_w, { 0x5a00 }
+ },
+/* incsnz W,$fr */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', 'W', ',', OP (FR), 0 } },
+ & ifmt_addcfr_w, { 0x5800 }
+ },
+/* muls W,$fr */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', 'W', ',', OP (FR), 0 } },
+ & ifmt_addcfr_w, { 0x5400 }
+ },
+/* mulu W,$fr */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', 'W', ',', OP (FR), 0 } },
+ & ifmt_addcfr_w, { 0x5000 }
+ },
+/* decsnz $fr */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (FR), 0 } },
+ & ifmt_addcfr_w, { 0x4e00 }
+ },
+/* decsnz W,$fr */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', 'W', ',', OP (FR), 0 } },
+ & ifmt_addcfr_w, { 0x4c00 }
+ },
+/* subc W,$fr */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', 'W', ',', OP (FR), 0 } },
+ & ifmt_addcfr_w, { 0x4800 }
+ },
+/* subc $fr,W */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (FR), ',', 'W', 0 } },
+ & ifmt_addcfr_w, { 0x4a00 }
+ },
+/* pop $fr */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (FR), 0 } },
+ & ifmt_addcfr_w, { 0x4600 }
+ },
+/* push $fr */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (FR), 0 } },
+ & ifmt_addcfr_w, { 0x4400 }
+ },
+/* cse W,$fr */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', 'W', ',', OP (FR), 0 } },
+ & ifmt_addcfr_w, { 0x4200 }
+ },
+/* csne W,$fr */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', 'W', ',', OP (FR), 0 } },
+ & ifmt_addcfr_w, { 0x4000 }
+ },
+/* incsz $fr */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (FR), 0 } },
+ & ifmt_addcfr_w, { 0x3e00 }
+ },
+/* incsz W,$fr */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', 'W', ',', OP (FR), 0 } },
+ & ifmt_addcfr_w, { 0x3c00 }
+ },
+/* swap $fr */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (FR), 0 } },
+ & ifmt_addcfr_w, { 0x3a00 }
+ },
+/* swap W,$fr */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', 'W', ',', OP (FR), 0 } },
+ & ifmt_addcfr_w, { 0x3800 }
+ },
+/* rl $fr */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (FR), 0 } },
+ & ifmt_addcfr_w, { 0x3600 }
+ },
+/* rl W,$fr */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', 'W', ',', OP (FR), 0 } },
+ & ifmt_addcfr_w, { 0x3400 }
+ },
+/* rr $fr */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (FR), 0 } },
+ & ifmt_addcfr_w, { 0x3200 }
+ },
+/* rr W,$fr */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', 'W', ',', OP (FR), 0 } },
+ & ifmt_addcfr_w, { 0x3000 }
+ },
+/* decsz $fr */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (FR), 0 } },
+ & ifmt_addcfr_w, { 0x2e00 }
+ },
+/* decsz W,$fr */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', 'W', ',', OP (FR), 0 } },
+ & ifmt_addcfr_w, { 0x2c00 }
+ },
+/* inc $fr */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (FR), 0 } },
+ & ifmt_addcfr_w, { 0x2a00 }
+ },
+/* inc W,$fr */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', 'W', ',', OP (FR), 0 } },
+ & ifmt_addcfr_w, { 0x2800 }
+ },
+/* not $fr */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (FR), 0 } },
+ & ifmt_addcfr_w, { 0x2600 }
+ },
+/* not W,$fr */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', 'W', ',', OP (FR), 0 } },
+ & ifmt_addcfr_w, { 0x2400 }
+ },
+/* test $fr */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (FR), 0 } },
+ & ifmt_addcfr_w, { 0x2200 }
+ },
+/* mov W,#$lit8 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', 'W', ',', '#', OP (LIT8), 0 } },
+ & ifmt_xorw_l, { 0x7c00 }
+ },
+/* mov $fr,W */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (FR), ',', 'W', 0 } },
+ & ifmt_addcfr_w, { 0x200 }
+ },
+/* mov W,$fr */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', 'W', ',', OP (FR), 0 } },
+ & ifmt_addcfr_w, { 0x2000 }
+ },
+/* add $fr,W */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (FR), ',', 'W', 0 } },
+ & ifmt_addcfr_w, { 0x1e00 }
+ },
+/* add W,$fr */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', 'W', ',', OP (FR), 0 } },
+ & ifmt_addcfr_w, { 0x1c00 }
+ },
+/* xor $fr,W */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (FR), ',', 'W', 0 } },
+ & ifmt_addcfr_w, { 0x1a00 }
+ },
+/* xor W,$fr */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', 'W', ',', OP (FR), 0 } },
+ & ifmt_addcfr_w, { 0x1800 }
+ },
+/* and $fr,W */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (FR), ',', 'W', 0 } },
+ & ifmt_addcfr_w, { 0x1600 }
+ },
+/* and W,$fr */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', 'W', ',', OP (FR), 0 } },
+ & ifmt_addcfr_w, { 0x1400 }
+ },
+/* or $fr,W */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (FR), ',', 'W', 0 } },
+ & ifmt_addcfr_w, { 0x1200 }
+ },
+/* or W,$fr */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', 'W', ',', OP (FR), 0 } },
+ & ifmt_addcfr_w, { 0x1000 }
+ },
+/* dec $fr */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (FR), 0 } },
+ & ifmt_addcfr_w, { 0xe00 }
+ },
+/* dec W,$fr */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', 'W', ',', OP (FR), 0 } },
+ & ifmt_addcfr_w, { 0xc00 }
+ },
+/* sub $fr,W */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (FR), ',', 'W', 0 } },
+ & ifmt_addcfr_w, { 0xa00 }
+ },
+/* sub W,$fr */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', 'W', ',', OP (FR), 0 } },
+ & ifmt_addcfr_w, { 0x800 }
+ },
+/* clr $fr */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (FR), 0 } },
+ & ifmt_addcfr_w, { 0x600 }
+ },
+/* cmp W,$fr */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', 'W', ',', OP (FR), 0 } },
+ & ifmt_addcfr_w, { 0x400 }
+ },
+/* speed #$lit8 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', '#', OP (LIT8), 0 } },
+ & ifmt_speed, { 0x100 }
+ },
+/* ireadi */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, 0 } },
+ & ifmt_ireadi, { 0x1d }
+ },
+/* iwritei */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, 0 } },
+ & ifmt_ireadi, { 0x1c }
+ },
+/* fread */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, 0 } },
+ & ifmt_ireadi, { 0x1b }
+ },
+/* fwrite */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, 0 } },
+ & ifmt_ireadi, { 0x1a }
+ },
+/* iread */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, 0 } },
+ & ifmt_ireadi, { 0x19 }
+ },
+/* iwrite */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, 0 } },
+ & ifmt_ireadi, { 0x18 }
+ },
+/* page $addr16p */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (ADDR16P), 0 } },
+ & ifmt_page, { 0x10 }
+ },
+/* system */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, 0 } },
+ & ifmt_ireadi, { 0xff }
+ },
+/* reti #$reti3 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', '#', OP (RETI3), 0 } },
+ & ifmt_reti, { 0x8 }
+ },
+/* ret */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, 0 } },
+ & ifmt_ireadi, { 0x7 }
+ },
+/* int */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, 0 } },
+ & ifmt_ireadi, { 0x6 }
+ },
+/* breakx */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, 0 } },
+ & ifmt_ireadi, { 0x5 }
+ },
+/* cwdt */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, 0 } },
+ & ifmt_ireadi, { 0x4 }
+ },
+/* ferase */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, 0 } },
+ & ifmt_ireadi, { 0x3 }
+ },
+/* retnp */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, 0 } },
+ & ifmt_ireadi, { 0x2 }
+ },
+/* break */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, 0 } },
+ & ifmt_ireadi, { 0x1 }
+ },
+/* nop */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, 0 } },
+ & ifmt_ireadi, { 0x0 }
+ },
+};
+
+#undef A
+#undef OPERAND
+#undef MNEM
+#undef OP
+
+/* Formats for ALIAS macro-insns. */
+
+#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
+#define F(f) & ip2k_cgen_ifld_table[IP2K_##f]
+#else
+#define F(f) & ip2k_cgen_ifld_table[IP2K_/**/f]
+#endif
+static const CGEN_IFMT ifmt_sc = {
+ 16, 16, 0xffff, { { F (F_OP4) }, { F (F_BITNO) }, { F (F_REG) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_snc = {
+ 16, 16, 0xffff, { { F (F_OP4) }, { F (F_BITNO) }, { F (F_REG) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_sz = {
+ 16, 16, 0xffff, { { F (F_OP4) }, { F (F_BITNO) }, { F (F_REG) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_snz = {
+ 16, 16, 0xffff, { { F (F_OP4) }, { F (F_BITNO) }, { F (F_REG) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_skip = {
+ 16, 16, 0xffff, { { F (F_OP4) }, { F (F_BITNO) }, { F (F_REG) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_skipb = {
+ 16, 16, 0xffff, { { F (F_OP4) }, { F (F_BITNO) }, { F (F_REG) }, { 0 } }
+};
+
+#undef F
+
+/* Each non-simple macro entry points to an array of expansion possibilities. */
+
+#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
+#define A(a) (1 << CGEN_INSN_##a)
+#else
+#define A(a) (1 << CGEN_INSN_/**/a)
+#endif
+#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
+#define OPERAND(op) IP2K_OPERAND_##op
+#else
+#define OPERAND(op) IP2K_OPERAND_/**/op
+#endif
+#define MNEM CGEN_SYNTAX_MNEMONIC /* syntax value for mnemonic */
+#define OP(field) CGEN_SYNTAX_MAKE_FIELD (OPERAND (field))
+
+/* The macro instruction table. */
+
+static const CGEN_IBASE ip2k_cgen_macro_insn_table[] =
+{
+/* sc */
+ {
+ -1, "sc", "sc", 16,
+ { 0|A(ALIAS), { (1<<MACH_BASE) } }
+ },
+/* snc */
+ {
+ -1, "snc", "snc", 16,
+ { 0|A(ALIAS), { (1<<MACH_BASE) } }
+ },
+/* sz */
+ {
+ -1, "sz", "sz", 16,
+ { 0|A(ALIAS), { (1<<MACH_BASE) } }
+ },
+/* snz */
+ {
+ -1, "snz", "snz", 16,
+ { 0|A(ALIAS), { (1<<MACH_BASE) } }
+ },
+/* skip */
+ {
+ -1, "skip", "skip", 16,
+ { 0|A(SKIPA)|A(ALIAS), { (1<<MACH_BASE) } }
+ },
+/* skip */
+ {
+ -1, "skipb", "skip", 16,
+ { 0|A(SKIPA)|A(ALIAS), { (1<<MACH_BASE) } }
+ },
+};
+
+/* The macro instruction opcode table. */
+
+static const CGEN_OPCODE ip2k_cgen_macro_insn_opcode_table[] =
+{
+/* sc */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, 0 } },
+ & ifmt_sc, { 0xb00b }
+ },
+/* snc */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, 0 } },
+ & ifmt_snc, { 0xa00b }
+ },
+/* sz */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, 0 } },
+ & ifmt_sz, { 0xb40b }
+ },
+/* snz */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, 0 } },
+ & ifmt_snz, { 0xa40b }
+ },
+/* skip */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, 0 } },
+ & ifmt_skip, { 0xa009 }
+ },
+/* skip */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, 0 } },
+ & ifmt_skipb, { 0xb009 }
+ },
+};
+
+#undef A
+#undef OPERAND
+#undef MNEM
+#undef OP
+
+#ifndef CGEN_ASM_HASH_P
+#define CGEN_ASM_HASH_P(insn) 1
+#endif
+
+#ifndef CGEN_DIS_HASH_P
+#define CGEN_DIS_HASH_P(insn) 1
+#endif
+
+/* Return non-zero if INSN is to be added to the hash table.
+ Targets are free to override CGEN_{ASM,DIS}_HASH_P in the .opc file. */
+
+static int
+asm_hash_insn_p (insn)
+ const CGEN_INSN *insn ATTRIBUTE_UNUSED;
+{
+ return CGEN_ASM_HASH_P (insn);
+}
+
+static int
+dis_hash_insn_p (insn)
+ const CGEN_INSN *insn;
+{
+ /* If building the hash table and the NO-DIS attribute is present,
+ ignore. */
+ if (CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_NO_DIS))
+ return 0;
+ return CGEN_DIS_HASH_P (insn);
+}
+
+#ifndef CGEN_ASM_HASH
+#define CGEN_ASM_HASH_SIZE 127
+#ifdef CGEN_MNEMONIC_OPERANDS
+#define CGEN_ASM_HASH(mnem) (*(unsigned char *) (mnem) % CGEN_ASM_HASH_SIZE)
+#else
+#define CGEN_ASM_HASH(mnem) (*(unsigned char *) (mnem) % CGEN_ASM_HASH_SIZE) /*FIXME*/
+#endif
+#endif
+
+/* It doesn't make much sense to provide a default here,
+ but while this is under development we do.
+ BUFFER is a pointer to the bytes of the insn, target order.
+ VALUE is the first base_insn_bitsize bits as an int in host order. */
+
+#ifndef CGEN_DIS_HASH
+#define CGEN_DIS_HASH_SIZE 256
+#define CGEN_DIS_HASH(buf, value) (*(unsigned char *) (buf))
+#endif
+
+/* The result is the hash value of the insn.
+ Targets are free to override CGEN_{ASM,DIS}_HASH in the .opc file. */
+
+static unsigned int
+asm_hash_insn (mnem)
+ const char * mnem;
+{
+ return CGEN_ASM_HASH (mnem);
+}
+
+/* BUF is a pointer to the bytes of the insn, target order.
+ VALUE is the first base_insn_bitsize bits as an int in host order. */
+
+static unsigned int
+dis_hash_insn (buf, value)
+ const char * buf ATTRIBUTE_UNUSED;
+ CGEN_INSN_INT value ATTRIBUTE_UNUSED;
+{
+ return CGEN_DIS_HASH (buf, value);
+}
+
+static void set_fields_bitsize PARAMS ((CGEN_FIELDS *, int));
+
+/* Set the recorded length of the insn in the CGEN_FIELDS struct. */
+
+static void
+set_fields_bitsize (fields, size)
+ CGEN_FIELDS *fields;
+ int size;
+{
+ CGEN_FIELDS_BITSIZE (fields) = size;
+}
+
+/* Function to call before using the operand instance table.
+ This plugs the opcode entries and macro instructions into the cpu table. */
+
+void
+ip2k_cgen_init_opcode_table (cd)
+ CGEN_CPU_DESC cd;
+{
+ int i;
+ int num_macros = (sizeof (ip2k_cgen_macro_insn_table) /
+ sizeof (ip2k_cgen_macro_insn_table[0]));
+ const CGEN_IBASE *ib = & ip2k_cgen_macro_insn_table[0];
+ const CGEN_OPCODE *oc = & ip2k_cgen_macro_insn_opcode_table[0];
+ CGEN_INSN *insns = (CGEN_INSN *) xmalloc (num_macros * sizeof (CGEN_INSN));
+ memset (insns, 0, num_macros * sizeof (CGEN_INSN));
+ for (i = 0; i < num_macros; ++i)
+ {
+ insns[i].base = &ib[i];
+ insns[i].opcode = &oc[i];
+ ip2k_cgen_build_insn_regex (& insns[i]);
+ }
+ cd->macro_insn_table.init_entries = insns;
+ cd->macro_insn_table.entry_size = sizeof (CGEN_IBASE);
+ cd->macro_insn_table.num_init_entries = num_macros;
+
+ oc = & ip2k_cgen_insn_opcode_table[0];
+ insns = (CGEN_INSN *) cd->insn_table.init_entries;
+ for (i = 0; i < MAX_INSNS; ++i)
+ {
+ insns[i].opcode = &oc[i];
+ ip2k_cgen_build_insn_regex (& insns[i]);
+ }
+
+ cd->sizeof_fields = sizeof (CGEN_FIELDS);
+ cd->set_fields_bitsize = set_fields_bitsize;
+
+ cd->asm_hash_p = asm_hash_insn_p;
+ cd->asm_hash = asm_hash_insn;
+ cd->asm_hash_size = CGEN_ASM_HASH_SIZE;
+
+ cd->dis_hash_p = dis_hash_insn_p;
+ cd->dis_hash = dis_hash_insn;
+ cd->dis_hash_size = CGEN_DIS_HASH_SIZE;
+}
--- /dev/null
+/* Instruction opcode header for ip2k.
+
+THIS FILE IS MACHINE GENERATED WITH CGEN.
+
+Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc.
+
+This file is part of the GNU Binutils and/or GDB, the GNU debugger.
+
+This program is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2, or (at your option)
+any later version.
+
+This program is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License along
+with this program; if not, write to the Free Software Foundation, Inc.,
+59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+
+*/
+
+#ifndef IP2K_OPC_H
+#define IP2K_OPC_H
+
+/* -- opc.h */
+
+/* Check applicability of instructions against machines. */
+#define CGEN_VALIDATE_INSN_SUPPORTED
+
+/* Allows reason codes to be output when assembler errors occur. */
+#define CGEN_VERBOSE_ASSEMBLER_ERRORS
+
+/* Override disassembly hashing - there are variable bits in the top
+ byte of these instructions. */
+#define CGEN_DIS_HASH_SIZE 8
+#define CGEN_DIS_HASH(buf,value) (((* (unsigned char*) (buf)) >> 5) % CGEN_DIS_HASH_SIZE)
+
+#define CGEN_ASM_HASH_SIZE 127
+#define CGEN_ASM_HASH(insn) ip2k_asm_hash(insn)
+
+extern unsigned int ip2k_asm_hash (const char *insn);
+
+
+/* Special check to ensure that instruction exists for given machine. */
+static int
+ip2k_cgen_insn_supported (cd, insn)
+ CGEN_CPU_DESC cd;
+ CGEN_INSN *insn;
+{
+ int machs = CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_MACH);
+
+ /* No mach attribute? Assume it's supported for all machs. */
+ if (machs == 0)
+ return 1;
+
+ return ((machs & cd->machs) != 0);
+}
+
+\f
+/* -- opc.c */
+/* Enum declaration for ip2k instruction types. */
+typedef enum cgen_insn_type {
+ IP2K_INSN_INVALID, IP2K_INSN_JMP, IP2K_INSN_CALL, IP2K_INSN_SB
+ , IP2K_INSN_SNB, IP2K_INSN_SETB, IP2K_INSN_CLRB, IP2K_INSN_XORW_L
+ , IP2K_INSN_ANDW_L, IP2K_INSN_ORW_L, IP2K_INSN_ADDW_L, IP2K_INSN_SUBW_L
+ , IP2K_INSN_CMPW_L, IP2K_INSN_RETW_L, IP2K_INSN_CSEW_L, IP2K_INSN_CSNEW_L
+ , IP2K_INSN_PUSH_L, IP2K_INSN_MULSW_L, IP2K_INSN_MULUW_L, IP2K_INSN_LOADL_L
+ , IP2K_INSN_LOADH_L, IP2K_INSN_LOADL_A, IP2K_INSN_LOADH_A, IP2K_INSN_ADDCFR_W
+ , IP2K_INSN_ADDCW_FR, IP2K_INSN_INCSNZ_FR, IP2K_INSN_INCSNZW_FR, IP2K_INSN_MULSW_FR
+ , IP2K_INSN_MULUW_FR, IP2K_INSN_DECSNZ_FR, IP2K_INSN_DECSNZW_FR, IP2K_INSN_SUBCW_FR
+ , IP2K_INSN_SUBCFR_W, IP2K_INSN_POP_FR, IP2K_INSN_PUSH_FR, IP2K_INSN_CSEW_FR
+ , IP2K_INSN_CSNEW_FR, IP2K_INSN_INCSZ_FR, IP2K_INSN_INCSZW_FR, IP2K_INSN_SWAP_FR
+ , IP2K_INSN_SWAPW_FR, IP2K_INSN_RL_FR, IP2K_INSN_RLW_FR, IP2K_INSN_RR_FR
+ , IP2K_INSN_RRW_FR, IP2K_INSN_DECSZ_FR, IP2K_INSN_DECSZW_FR, IP2K_INSN_INC_FR
+ , IP2K_INSN_INCW_FR, IP2K_INSN_NOT_FR, IP2K_INSN_NOTW_FR, IP2K_INSN_TEST_FR
+ , IP2K_INSN_MOVW_L, IP2K_INSN_MOVFR_W, IP2K_INSN_MOVW_FR, IP2K_INSN_ADDFR_W
+ , IP2K_INSN_ADDW_FR, IP2K_INSN_XORFR_W, IP2K_INSN_XORW_FR, IP2K_INSN_ANDFR_W
+ , IP2K_INSN_ANDW_FR, IP2K_INSN_ORFR_W, IP2K_INSN_ORW_FR, IP2K_INSN_DEC_FR
+ , IP2K_INSN_DECW_FR, IP2K_INSN_SUBFR_W, IP2K_INSN_SUBW_FR, IP2K_INSN_CLR_FR
+ , IP2K_INSN_CMPW_FR, IP2K_INSN_SPEED, IP2K_INSN_IREADI, IP2K_INSN_IWRITEI
+ , IP2K_INSN_FREAD, IP2K_INSN_FWRITE, IP2K_INSN_IREAD, IP2K_INSN_IWRITE
+ , IP2K_INSN_PAGE, IP2K_INSN_SYSTEM, IP2K_INSN_RETI, IP2K_INSN_RET
+ , IP2K_INSN_INT, IP2K_INSN_BREAKX, IP2K_INSN_CWDT, IP2K_INSN_FERASE
+ , IP2K_INSN_RETNP, IP2K_INSN_BREAK, IP2K_INSN_NOP
+} CGEN_INSN_TYPE;
+
+/* Index of `invalid' insn place holder. */
+#define CGEN_INSN_INVALID IP2K_INSN_INVALID
+
+/* Total number of insns in table. */
+#define MAX_INSNS ((int) IP2K_INSN_NOP + 1)
+
+/* This struct records data prior to insertion or after extraction. */
+struct cgen_fields
+{
+ int length;
+ long f_nil;
+ long f_anyof;
+ long f_imm8;
+ long f_reg;
+ long f_addr16cjp;
+ long f_dir;
+ long f_bitno;
+ long f_op3;
+ long f_op4;
+ long f_op4mid;
+ long f_op6;
+ long f_op8;
+ long f_op6_10low;
+ long f_op6_7low;
+ long f_reti3;
+ long f_skipb;
+ long f_page3;
+};
+
+#define CGEN_INIT_PARSE(od) \
+{\
+}
+#define CGEN_INIT_INSERT(od) \
+{\
+}
+#define CGEN_INIT_EXTRACT(od) \
+{\
+}
+#define CGEN_INIT_PRINT(od) \
+{\
+}
+
+
+#endif /* IP2K_OPC_H */
projects / thirdparty / binutils-gdb.git / commitdiff
