]> git.ipfire.org Git - thirdparty/openwrt.git/commitdiff
realtek: refactor GS1900-8HP variants to have common definitions
authorPeter Putzer <openwrt@mundschenk.at>
Sat, 25 Jul 2026 10:10:42 +0000 (10:10 +0000)
committerJonas Jelonek <jelonek.jonas@gmail.com>
Mon, 27 Jul 2026 20:54:32 +0000 (22:54 +0200)
Moves common definitions to separate include file.

Signed-off-by: Peter Putzer <openwrt@mundschenk.at>
Link: https://github.com/openwrt/openwrt/pull/24418
Signed-off-by: Jonas Jelonek <jelonek.jonas@gmail.com>
target/linux/realtek/dts/rtl8380_zyxel_gs1900-8hp-a1.dts
target/linux/realtek/dts/rtl8380_zyxel_gs1900-8hp-b1.dts
target/linux/realtek/dts/rtl8380_zyxel_gs1900-8hp.dtsi [new file with mode: 0644]

index 88e76c9774a4195d50b64106fe52ce2d6d681710..1ebc76310146af3b500007b1acd1ecee6c600057 100644 (file)
@@ -1,41 +1,13 @@
 // SPDX-License-Identifier: GPL-2.0-or-later
 
-#include "rtl8380_zyxel_gs1900.dtsi"
-#include "rtl8380_zyxel_gs1900_gpio.dtsi"
+#include "rtl8380_zyxel_gs1900-8hp.dtsi"
 
 / {
        compatible = "zyxel,gs1900-8hp-a1", "realtek,rtl838x-soc";
        model = "Zyxel GS1900-8HP A1 Switch";
 };
 
-&uart1 {
-       status = "okay";
-
-       pse: ethernet-pse {
-               compatible = "zyxel,gs1900-8hp-a1-pse", "realtek,pse-mcu-gen1";
-               current-speed = <19200>;
-
-               pse-pis {
-                       #address-cells = <1>;
-                       #size-cells = <0>;
-
-                       PSE_PI(0)
-                       PSE_PI(1)
-                       PSE_PI(2)
-                       PSE_PI(3)
-                       PSE_PI(4)
-                       PSE_PI(5)
-                       PSE_PI(6)
-                       PSE_PI(7)
-               };
-       };
+&pse {
+       compatible = "zyxel,gs1900-8hp-a1-pse", "realtek,pse-mcu-gen1";
+       current-speed = <19200>;
 };
-
-&phy8 { pses = <&pse_pi0>; };
-&phy9 { pses = <&pse_pi1>; };
-&phy10 { pses = <&pse_pi2>; };
-&phy11 { pses = <&pse_pi3>; };
-&phy12 { pses = <&pse_pi4>; };
-&phy13 { pses = <&pse_pi5>; };
-&phy14 { pses = <&pse_pi6>; };
-&phy15 { pses = <&pse_pi7>; };
index 8987fd1d736823c17bafd43f026b6bf58237dbf9..8ee34dc699ba134e18dce3e3ad9d2eb17b6de45a 100644 (file)
@@ -1,41 +1,13 @@
 // SPDX-License-Identifier: GPL-2.0-or-later
 
-#include "rtl8380_zyxel_gs1900.dtsi"
-#include "rtl8380_zyxel_gs1900_gpio.dtsi"
+#include "rtl8380_zyxel_gs1900-8hp.dtsi"
 
 / {
        compatible = "zyxel,gs1900-8hp-b1", "realtek,rtl838x-soc";
        model = "Zyxel GS1900-8HP B1 Switch";
 };
 
-&uart1 {
-       status = "okay";
-
-       pse: ethernet-pse {
-               compatible = "zyxel,gs1900-8hp-b1-pse", "realtek,pse-mcu-gen1";
-               current-speed = <19200>;
-
-               pse-pis {
-                       #address-cells = <1>;
-                       #size-cells = <0>;
-
-                       PSE_PI(0)
-                       PSE_PI(1)
-                       PSE_PI(2)
-                       PSE_PI(3)
-                       PSE_PI(4)
-                       PSE_PI(5)
-                       PSE_PI(6)
-                       PSE_PI(7)
-               };
-       };
+&pse {
+       compatible = "zyxel,gs1900-8hp-b1-pse", "realtek,pse-mcu-gen1";
+       current-speed = <19200>;
 };
-
-&phy8 { pses = <&pse_pi0>; };
-&phy9 { pses = <&pse_pi1>; };
-&phy10 { pses = <&pse_pi2>; };
-&phy11 { pses = <&pse_pi3>; };
-&phy12 { pses = <&pse_pi4>; };
-&phy13 { pses = <&pse_pi5>; };
-&phy14 { pses = <&pse_pi6>; };
-&phy15 { pses = <&pse_pi7>; };
diff --git a/target/linux/realtek/dts/rtl8380_zyxel_gs1900-8hp.dtsi b/target/linux/realtek/dts/rtl8380_zyxel_gs1900-8hp.dtsi
new file mode 100644 (file)
index 0000000..1eab58f
--- /dev/null
@@ -0,0 +1,34 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+
+#include "rtl8380_zyxel_gs1900.dtsi"
+#include "rtl8380_zyxel_gs1900_gpio.dtsi"
+
+&uart1 {
+       status = "okay";
+
+       /* PoE MCU; compatible and current-speed are set per variant */
+       pse: ethernet-pse {
+               pse-pis {
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+
+                       PSE_PI(0)
+                       PSE_PI(1)
+                       PSE_PI(2)
+                       PSE_PI(3)
+                       PSE_PI(4)
+                       PSE_PI(5)
+                       PSE_PI(6)
+                       PSE_PI(7)
+               };
+       };
+};
+
+&phy8 { pses = <&pse_pi0>; };
+&phy9 { pses = <&pse_pi1>; };
+&phy10 { pses = <&pse_pi2>; };
+&phy11 { pses = <&pse_pi3>; };
+&phy12 { pses = <&pse_pi4>; };
+&phy13 { pses = <&pse_pi5>; };
+&phy14 { pses = <&pse_pi6>; };
+&phy15 { pses = <&pse_pi7>; };