spi: atmel-quadspi: Create `atmel_qspi_ops` to support newer SoC families

[ Upstream commit c0a0203cf57963792d59b3e4317a1d07b73df42a ]

Refactor the code to introduce an ops struct, to prepare for merging
support for later SoCs, such as SAMA7G5. This code was based on the
vendor's kernel (linux4microchip). Cc'ing original contributors.

Signed-off-by: Csókás, Bence <csokas.bence@prolan.hu>
Link: https://patch.msgid.link/20241128174316.3209354-2-csokas.bence@prolan.hu
Signed-off-by: Mark Brown <broonie@kernel.org>
Stable-dep-of: be92ab2de0ee ("spi: atmel-qspi: Memory barriers after memory-mapped I/O")
Signed-off-by: Sasha Levin <sashal@kernel.org>

diff --git a/drivers/spi/atmel-quadspi.c b/drivers/spi/atmel-quadspi.c
index bc6dfb6d865467ba0b40d86845bc45fe972e4550..32fcab2a1188527c15d88dfb8a579c05296732a6 100644 (file)
--- a/drivers/spi/atmel-quadspi.c
+++ b/drivers/spi/atmel-quadspi.c
@@ -138,11 +138,15 @@
 #define QSPI_WPSR_WPVSRC_MASK           GENMASK(15, 8)
 #define QSPI_WPSR_WPVSRC(src)           (((src) << 8) & QSPI_WPSR_WPVSRC)
 
+#define ATMEL_QSPI_TIMEOUT             1000    /* ms */
+
 struct atmel_qspi_caps {
        bool has_qspick;
        bool has_ricr;
 };
 
+struct atmel_qspi_ops;
+
 struct atmel_qspi {
        void __iomem            *regs;
        void __iomem            *mem;
@@ -150,13 +154,22 @@ struct atmel_qspi {
        struct clk              *qspick;
        struct platform_device  *pdev;
        const struct atmel_qspi_caps *caps;
+       const struct atmel_qspi_ops *ops;
        resource_size_t         mmap_size;
        u32                     pending;
+       u32                     irq_mask;
        u32                     mr;
        u32                     scr;
        struct completion       cmd_completion;
 };
 
+struct atmel_qspi_ops {
+       int (*set_cfg)(struct atmel_qspi *aq, const struct spi_mem_op *op,
+                      u32 *offset);
+       int (*transfer)(struct spi_mem *mem, const struct spi_mem_op *op,
+                       u32 offset);
+};
+
 struct atmel_qspi_mode {
        u8 cmd_buswidth;
        u8 addr_buswidth;
@@ -404,10 +417,60 @@ static int atmel_qspi_set_cfg(struct atmel_qspi *aq,
        return 0;
 }
 
+static int atmel_qspi_wait_for_completion(struct atmel_qspi *aq, u32 irq_mask)
+{
+       int err = 0;
+       u32 sr;
+
+       /* Poll INSTRuction End status */
+       sr = atmel_qspi_read(aq, QSPI_SR);
+       if ((sr & irq_mask) == irq_mask)
+               return 0;
+
+       /* Wait for INSTRuction End interrupt */
+       reinit_completion(&aq->cmd_completion);
+       aq->pending = sr & irq_mask;
+       aq->irq_mask = irq_mask;
+       atmel_qspi_write(irq_mask, aq, QSPI_IER);
+       if (!wait_for_completion_timeout(&aq->cmd_completion,
+                                        msecs_to_jiffies(ATMEL_QSPI_TIMEOUT)))
+               err = -ETIMEDOUT;
+       atmel_qspi_write(irq_mask, aq, QSPI_IDR);
+
+       return err;
+}
+
+static int atmel_qspi_transfer(struct spi_mem *mem,
+                              const struct spi_mem_op *op, u32 offset)
+{
+       struct atmel_qspi *aq = spi_controller_get_devdata(mem->spi->controller);
+
+       /* Skip to the final steps if there is no data */
+       if (!op->data.nbytes)
+               return atmel_qspi_wait_for_completion(aq,
+                                                     QSPI_SR_CMD_COMPLETED);
+
+       /* Dummy read of QSPI_IFR to synchronize APB and AHB accesses */
+       (void)atmel_qspi_read(aq, QSPI_IFR);
+
+       /* Send/Receive data */
+       if (op->data.dir == SPI_MEM_DATA_IN)
+               memcpy_fromio(op->data.buf.in, aq->mem + offset,
+                             op->data.nbytes);
+       else
+               memcpy_toio(aq->mem + offset, op->data.buf.out,
+                           op->data.nbytes);
+
+       /* Release the chip-select */
+       atmel_qspi_write(QSPI_CR_LASTXFER, aq, QSPI_CR);
+
+       return atmel_qspi_wait_for_completion(aq, QSPI_SR_CMD_COMPLETED);
+}
+
 static int atmel_qspi_exec_op(struct spi_mem *mem, const struct spi_mem_op *op)
 {
        struct atmel_qspi *aq = spi_controller_get_devdata(mem->spi->controller);
-       u32 sr, offset;
+       u32 offset;
        int err;
 
        /*
@@ -416,46 +479,20 @@ static int atmel_qspi_exec_op(struct spi_mem *mem, const struct spi_mem_op *op)
         * when the flash memories overrun the controller's memory space.
         */
        if (op->addr.val + op->data.nbytes > aq->mmap_size)
-               return -ENOTSUPP;
+               return -EOPNOTSUPP;
+
+       if (op->addr.nbytes > 4)
+               return -EOPNOTSUPP;
 
        err = pm_runtime_resume_and_get(&aq->pdev->dev);
        if (err < 0)
                return err;
 
-       err = atmel_qspi_set_cfg(aq, op, &offset);
+       err = aq->ops->set_cfg(aq, op, &offset);
        if (err)
                goto pm_runtime_put;
 
-       /* Skip to the final steps if there is no data */
-       if (op->data.nbytes) {
-               /* Dummy read of QSPI_IFR to synchronize APB and AHB accesses */
-               (void)atmel_qspi_read(aq, QSPI_IFR);
-
-               /* Send/Receive data */
-               if (op->data.dir == SPI_MEM_DATA_IN)
-                       memcpy_fromio(op->data.buf.in, aq->mem + offset,
-                                     op->data.nbytes);
-               else
-                       memcpy_toio(aq->mem + offset, op->data.buf.out,
-                                   op->data.nbytes);
-
-               /* Release the chip-select */
-               atmel_qspi_write(QSPI_CR_LASTXFER, aq, QSPI_CR);
-       }
-
-       /* Poll INSTRuction End status */
-       sr = atmel_qspi_read(aq, QSPI_SR);
-       if ((sr & QSPI_SR_CMD_COMPLETED) == QSPI_SR_CMD_COMPLETED)
-               goto pm_runtime_put;
-
-       /* Wait for INSTRuction End interrupt */
-       reinit_completion(&aq->cmd_completion);
-       aq->pending = sr & QSPI_SR_CMD_COMPLETED;
-       atmel_qspi_write(QSPI_SR_CMD_COMPLETED, aq, QSPI_IER);
-       if (!wait_for_completion_timeout(&aq->cmd_completion,
-                                        msecs_to_jiffies(1000)))
-               err = -ETIMEDOUT;
-       atmel_qspi_write(QSPI_SR_CMD_COMPLETED, aq, QSPI_IDR);
+       err = aq->ops->transfer(mem, op, offset);
 
 pm_runtime_put:
        pm_runtime_mark_last_busy(&aq->pdev->dev);
@@ -569,12 +606,17 @@ static irqreturn_t atmel_qspi_interrupt(int irq, void *dev_id)
                return IRQ_NONE;
 
        aq->pending |= pending;
-       if ((aq->pending & QSPI_SR_CMD_COMPLETED) == QSPI_SR_CMD_COMPLETED)
+       if ((aq->pending & aq->irq_mask) == aq->irq_mask)
                complete(&aq->cmd_completion);
 
        return IRQ_HANDLED;
 }
 
+static const struct atmel_qspi_ops atmel_qspi_ops = {
+       .set_cfg = atmel_qspi_set_cfg,
+       .transfer = atmel_qspi_transfer,
+};
+
 static int atmel_qspi_probe(struct platform_device *pdev)
 {
        struct spi_controller *ctrl;
@@ -599,6 +641,7 @@ static int atmel_qspi_probe(struct platform_device *pdev)
 
        init_completion(&aq->cmd_completion);
        aq->pdev = pdev;
+       aq->ops = &atmel_qspi_ops;
 
        /* Map the registers */
        res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "qspi_base");