clk: at91: sam9x7: update pll clk ranges

Update the min, max ranges of the PLL clocks according to the latest
datasheet to be coherent in the driver. This patch solves the issues in
configuring the clocks related to peripherals with the desired frequency
within the range.

Fixes: 33013b43e271 ("clk: at91: sam9x7: add sam9x7 pmc driver")
Suggested-by: Patrice Vilchez <Patrice.Vilchez@microchip.com>
Signed-off-by: Varshini Rajendran <varshini.rajendran@microchip.com>
Link: https://lore.kernel.org/r/20250714093512.29944-1-varshini.rajendran@microchip.com
Signed-off-by: Claudiu Beznea <claudiu.beznea@tuxon.dev>

diff --git a/drivers/clk/at91/sam9x7.c b/drivers/clk/at91/sam9x7.c
index cbb8b220f16bcde25ae34c74b9708809691473c1..ffab32b047a017e5c6e42a2bc301c93d8b12ea4c 100644 (file)
--- a/drivers/clk/at91/sam9x7.c
+++ b/drivers/clk/at91/sam9x7.c
@@ -61,44 +61,44 @@ static const struct clk_master_layout sam9x7_master_layout = {
 
 /* Fractional PLL core output range. */
 static const struct clk_range plla_core_outputs[] = {
-       { .min = 375000000, .max = 1600000000 },
+       { .min = 800000000, .max = 1600000000 },
 };
 
 static const struct clk_range upll_core_outputs[] = {
-       { .min = 600000000, .max = 1200000000 },
+       { .min = 600000000, .max = 960000000 },
 };
 
 static const struct clk_range lvdspll_core_outputs[] = {
-       { .min = 400000000, .max = 800000000 },
+       { .min = 600000000, .max = 1200000000 },
 };
 
 static const struct clk_range audiopll_core_outputs[] = {
-       { .min = 400000000, .max = 800000000 },
+       { .min = 600000000, .max = 1200000000 },
 };
 
 static const struct clk_range plladiv2_core_outputs[] = {
-       { .min = 375000000, .max = 1600000000 },
+       { .min = 800000000, .max = 1600000000 },
 };
 
 /* Fractional PLL output range. */
 static const struct clk_range plla_outputs[] = {
-       { .min = 732421, .max = 800000000 },
+       { .min = 400000000, .max = 800000000 },
 };
 
 static const struct clk_range upll_outputs[] = {
-       { .min = 300000000, .max = 600000000 },
+       { .min = 300000000, .max = 480000000 },
 };
 
 static const struct clk_range lvdspll_outputs[] = {
-       { .min = 10000000, .max = 800000000 },
+       { .min = 175000000, .max = 550000000 },
 };
 
 static const struct clk_range audiopll_outputs[] = {
-       { .min = 10000000, .max = 800000000 },
+       { .min = 0, .max = 300000000 },
 };
 
 static const struct clk_range plladiv2_outputs[] = {
-       { .min = 366210, .max = 400000000 },
+       { .min = 200000000, .max = 400000000 },
 };
 
 /* PLL characteristics. */