aarch64: Support multiple variants including up to 3

On some of the Qualcomm's SoC that includes oryon-1 core, the variant
will be different on the cores due to big.little config. Though
the difference between big and little is not significant enough
to have seperate cost/scheduling models for them and the feature set
is the same across all variants.

Also on some SoCs, there are 3 variants of the core, big.middle.little
so this increases the support there for up to 3 cores and 3 variants
in the original parsing loop but it does not change the support for max
of 2 different cores.

After this patch and the patch that adds oryon-1, -mcpu=native works
on the SoCs I am working with.

Bootstrapped and tested on aarch64-linux-gnu with no regressions.

gcc/ChangeLog:

	* config/aarch64/driver-aarch64.cc (host_detect_local_cpu): Support
	3 cores and 3 variants. If there is one core but multiple variant,
	then treat the variant as being all.

gcc/testsuite/ChangeLog:

	* gcc.target/aarch64/cpunative/info_25: New file.
	* gcc.target/aarch64/cpunative/info_26: New file.
	* gcc.target/aarch64/cpunative/native_cpu_25.c: New test.
	* gcc.target/aarch64/cpunative/native_cpu_26.c: New test.

Signed-off-by: Andrew Pinski <quic_apinski@quicinc.com>

diff --git a/gcc/config/aarch64/driver-aarch64.cc b/gcc/config/aarch64/driver-aarch64.cc
index b620351e572038d84da5d401a9c295fe19797b4e..abe6e7df7dc69cb8c435e5348463b93fa56986d1 100644 (file)
--- a/gcc/config/aarch64/driver-aarch64.cc
+++ b/gcc/config/aarch64/driver-aarch64.cc
@@ -256,9 +256,9 @@ host_detect_local_cpu (int argc, const char **argv)
   bool cpu = false;
   unsigned int i = 0;
   unsigned char imp = INVALID_IMP;
-  unsigned int cores[2] = { INVALID_CORE, INVALID_CORE };
+  unsigned int cores[3] = { INVALID_CORE, INVALID_CORE, INVALID_CORE };
   unsigned int n_cores = 0;
-  unsigned int variants[2] = { ALL_VARIANTS, ALL_VARIANTS };
+  unsigned int variants[3] = { ALL_VARIANTS, ALL_VARIANTS, ALL_VARIANTS };
   unsigned int n_variants = 0;
   bool processed_exts = false;
   aarch64_feature_flags extension_flags = 0;
@@ -314,7 +314,7 @@ host_detect_local_cpu (int argc, const char **argv)
          unsigned cvariant = parse_field (buf);
          if (!contains_core_p (variants, cvariant))
            {
-              if (n_variants == 2)
+             if (n_variants == 3)
                 goto not_found;
 
               variants[n_variants++] = cvariant;
@@ -326,7 +326,7 @@ host_detect_local_cpu (int argc, const char **argv)
          unsigned ccore = parse_field (buf);
          if (!contains_core_p (cores, ccore))
            {
-             if (n_cores == 2)
+             if (n_cores == 3)
                goto not_found;
 
              cores[n_cores++] = ccore;
@@ -383,11 +383,15 @@ host_detect_local_cpu (int argc, const char **argv)
   /* Weird cpuinfo format that we don't know how to handle.  */
   if (n_cores == 0
       || n_cores > 2
-      || (n_cores == 1 && n_variants != 1)
       || imp == INVALID_IMP
       || !processed_exts)
     goto not_found;
 
+  /* If we have one core type but multiple variants, consider
+     that as one variant with ALL_VARIANTS instead.  */
+  if (n_cores == 1 && n_variants != 1)
+    variants[0] = ALL_VARIANTS;
+
   /* Simple case, one core type or just looking for the arch. */
   if (n_cores == 1 || arch)
     {

diff --git a/gcc/testsuite/gcc.target/aarch64/cpunative/info_25 b/gcc/testsuite/gcc.target/aarch64/cpunative/info_25
new file mode 100644 (file)
index 0000000..d6e83cc
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/cpunative/info_25
@@ -0,0 +1,17 @@
+processor      : 0
+BogoMIPS       : 38.40
+Features       : fp asimd evtstrm aes pmull sha1 sha2 crc32 atomics fphp asimdhp cpuid asimdrdm jscvt fcma lrcpc dcpop sha3 sm3 sm4 asimddp sha512 asimdfhm dit uscat ilrcpc flagm ssbs sb paca pacg dcpodp flagm2 frint i8mm bf16 rng bti ecv afp rpres
+CPU implementer        : 0x51
+CPU architecture: 8
+CPU variant    : 0x2
+CPU part       : 0x001
+CPU revision   : 1
+
+processor      : 1
+BogoMIPS       : 38.40
+Features       : fp asimd evtstrm aes pmull sha1 sha2 crc32 atomics fphp asimdhp cpuid asimdrdm jscvt fcma lrcpc dcpop sha3 sm3 sm4 asimddp sha512 asimdfhm dit uscat ilrcpc flagm ssbs sb paca pacg dcpodp flagm2 frint i8mm bf16 rng bti ecv afp rpres
+CPU implementer        : 0x51
+CPU architecture: 8
+CPU variant    : 0x1
+CPU part       : 0x001
+CPU revision   : 1
\ No newline at end of file

diff --git a/gcc/testsuite/gcc.target/aarch64/cpunative/info_26 b/gcc/testsuite/gcc.target/aarch64/cpunative/info_26
new file mode 100644 (file)
index 0000000..7631baf
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/cpunative/info_26
@@ -0,0 +1,26 @@
+processor      : 0
+BogoMIPS       : 38.40
+Features       : fp asimd evtstrm aes pmull sha1 sha2 crc32 atomics fphp asimdhp cpuid asimdrdm jscvt fcma lrcpc dcpop sha3 sm3 sm4 asimddp sha512 asimdfhm dit uscat ilrcpc flagm ssbs sb paca pacg dcpodp flagm2 frint i8mm bf16 rng bti ecv afp rpres
+CPU implementer        : 0x51
+CPU architecture: 8
+CPU variant    : 0x2
+CPU part       : 0x001
+CPU revision   : 1
+
+processor      : 1
+BogoMIPS       : 38.40
+Features       : fp asimd evtstrm aes pmull sha1 sha2 crc32 atomics fphp asimdhp cpuid asimdrdm jscvt fcma lrcpc dcpop sha3 sm3 sm4 asimddp sha512 asimdfhm dit uscat ilrcpc flagm ssbs sb paca pacg dcpodp flagm2 frint i8mm bf16 rng bti ecv afp rpres
+CPU implementer        : 0x51
+CPU architecture: 8
+CPU variant    : 0x1
+CPU part       : 0x001
+CPU revision   : 1
+
+processor      : 2
+BogoMIPS       : 38.40
+Features       : fp asimd evtstrm aes pmull sha1 sha2 crc32 atomics fphp asimdhp cpuid asimdrdm jscvt fcma lrcpc dcpop sha3 sm3 sm4 asimddp sha512 asimdfhm dit uscat ilrcpc flagm ssbs sb paca pacg dcpodp flagm2 frint i8mm bf16 rng bti ecv afp rpres
+CPU implementer        : 0x51
+CPU architecture: 8
+CPU variant    : 0x2
+CPU part       : 0x001
+CPU revision   : 1
\ No newline at end of file

diff --git a/gcc/testsuite/gcc.target/aarch64/cpunative/native_cpu_25.c b/gcc/testsuite/gcc.target/aarch64/cpunative/native_cpu_25.c
new file mode 100644 (file)
index 0000000..05c88a2
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/cpunative/native_cpu_25.c
@@ -0,0 +1,11 @@
+/* { dg-do compile { target { { aarch64*-*-linux*} && native } } } */
+/* { dg-set-compiler-env-var GCC_CPUINFO "$srcdir/gcc.target/aarch64/cpunative/info_25" } */
+/* { dg-additional-options "-mcpu=native --save-temps " } */
+
+int main()
+{
+  return 0;
+}
+
+/* { dg-final { scan-assembler {\.arch armv8.6-a\+rng\+sm4\+crc\+aes\+sha3\+fp16} } } */
+/* Test that SoC with cores of 2 variants work.  */

diff --git a/gcc/testsuite/gcc.target/aarch64/cpunative/native_cpu_26.c b/gcc/testsuite/gcc.target/aarch64/cpunative/native_cpu_26.c
new file mode 100644 (file)
index 0000000..4eb943d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/cpunative/native_cpu_26.c
@@ -0,0 +1,11 @@
+/* { dg-do compile { target { { aarch64*-*-linux*} && native } } } */
+/* { dg-set-compiler-env-var GCC_CPUINFO "$srcdir/gcc.target/aarch64/cpunative/info_26" } */
+/* { dg-additional-options "-mcpu=native --save-temps " } */
+
+int main()
+{
+  return 0;
+}
+
+/* { dg-final { scan-assembler {\.arch armv8.6-a\+rng\+sm4\+crc\+aes\+sha3\+fp16} } } */
+/* Test that SoC with cores of 3 variants work.  */
\ No newline at end of file