arm64: dts: freescale: imx93-var-som: Add support for WM8904 audio codec

The VAR-SOM-MX93 can integrate the WM8904, a high-performance
ultra-low-power stereo codec optimized for portable audio applications.

This patch adds the WM8904 device to the appropriate I2C bus, enables
the SAI peripheral, and introduces the sound node to expose the
sound card to the system.

Signed-off-by: Stefano Radaelli <stefano.radaelli21@gmail.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>

diff --git a/arch/arm64/boot/dts/freescale/imx93-var-som.dtsi b/arch/arm64/boot/dts/freescale/imx93-var-som.dtsi
index 85fd9c9c9372f393cdbb4d9c72aa4c573be92c31..0b7f6740e5adee6c58867b81603b763fcabcc5cc 100644 (file)
--- a/arch/arm64/boot/dts/freescale/imx93-var-som.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx93-var-som.dtsi
@@ -12,6 +12,34 @@
        model = "Variscite VAR-SOM-MX93 module";
        compatible = "variscite,var-som-mx93", "fsl,imx93";
 
+       sound {
+               compatible = "simple-audio-card";
+               simple-audio-card,bitclock-master = <&codec_dai>;
+               simple-audio-card,format = "i2s";
+               simple-audio-card,frame-master = <&codec_dai>;
+               simple-audio-card,name = "wm8904-audio";
+               simple-audio-card,routing =
+                       "Headphone Jack", "HPOUTL",
+                       "Headphone Jack", "HPOUTR",
+                       "IN2L", "Line In Jack",
+                       "IN2R", "Line In Jack",
+                       "IN1L", "Microphone Jack",
+                       "IN1R", "Microphone Jack";
+               simple-audio-card,widgets =
+                       "Microphone", "Microphone Jack",
+                       "Headphone", "Headphone Jack",
+                       "Line", "Line In Jack";
+               simple-audio-card,mclk-fs = <256>;
+
+               codec_dai: simple-audio-card,codec {
+                       sound-dai = <&wm8904>;
+               };
+
+               simple-audio-card,cpu {
+                       sound-dai = <&sai1>;
+               };
+       };
+
        usdhc3_pwrseq: mmc-pwrseq {
                compatible = "mmc-pwrseq-simple";
                post-power-on-delay-ms = <100>;
@@ -152,6 +180,36 @@
                        };
                };
        };
+
+       wm8904: audio-codec@1a {
+               compatible = "wlf,wm8904";
+               reg = <0x1a>;
+               #sound-dai-cells = <0>;
+               clocks = <&clk IMX93_CLK_SAI1_GATE>;
+               clock-names = "mclk";
+               AVDD-supply = <&buck5>;
+               CPVDD-supply = <&buck5>;
+               DBVDD-supply = <&buck4>;
+               DCVDD-supply = <&buck5>;
+               MICVDD-supply = <&buck5>;
+               wlf,drc-cfg-names = "default", "peaklimiter", "tradition",
+                                   "soft", "music";
+               /*
+                * Config registers per name, respectively:
+                * KNEE_IP = 0,   KNEE_OP = 0,     HI_COMP = 1,   LO_COMP = 1
+                * KNEE_IP = -24, KNEE_OP = -6,    HI_COMP = 1/4, LO_COMP = 1
+                * KNEE_IP = -42, KNEE_OP = -3,    HI_COMP = 0,   LO_COMP = 1
+                * KNEE_IP = -45, KNEE_OP = -9,    HI_COMP = 1/8, LO_COMP = 1
+                * KNEE_IP = -30, KNEE_OP = -10.5, HI_COMP = 1/4, LO_COMP = 1
+                */
+               wlf,drc-cfg-regs = /bits/ 16 <0x01af 0x3248 0x0000 0x0000>,
+                                  /bits/ 16 <0x04af 0x324b 0x0010 0x0408>,
+                                  /bits/ 16 <0x04af 0x324b 0x0028 0x0704>,
+                                  /bits/ 16 <0x04af 0x324b 0x0018 0x078c>,
+                                  /bits/ 16 <0x04af 0x324b 0x0010 0x050e>;
+               /* GPIO1 = DMIC_CLK, don't touch others */
+               wlf,gpio-cfg = <0x0018>, <0xffff>, <0xffff>, <0xffff>;
+       };
 };
 
 /* BT module */
@@ -166,6 +224,17 @@
        };
 };
 
+&sai1 {
+       pinctrl-names = "default", "sleep";
+       pinctrl-0 = <&pinctrl_sai1>;
+       pinctrl-1 = <&pinctrl_sai1_sleep>;
+       assigned-clocks = <&clk IMX93_CLK_SAI1>;
+       assigned-clock-parents = <&clk IMX93_CLK_AUDIO_PLL>;
+       assigned-clock-rates = <12288000>;
+       fsl,sai-mclk-direction-output;
+       status = "okay";
+};
+
 /* eMMC */
 &usdhc1 {
        pinctrl-names = "default", "state_100mhz", "state_200mhz";
@@ -247,6 +316,30 @@
                >;
        };
 
+       pinctrl_sai1: sai1grp {
+               fsl,pins = <
+                       MX93_PAD_SAI1_TXC__SAI1_TX_BCLK         0x31e
+                       MX93_PAD_SAI1_TXFS__SAI1_TX_SYNC        0x31e
+                       MX93_PAD_SAI1_TXD0__SAI1_TX_DATA00      0x31e
+                       MX93_PAD_SAI1_RXD0__SAI1_RX_DATA00      0x31e
+                       MX93_PAD_I2C2_SDA__SAI1_RX_BCLK         0x31e
+                       MX93_PAD_I2C2_SCL__SAI1_RX_SYNC         0x31e
+                       MX93_PAD_UART2_RXD__SAI1_MCLK           0x31e
+               >;
+       };
+
+       pinctrl_sai1_sleep: sai1-sleepgrp {
+               fsl,pins = <
+                       MX93_PAD_SAI1_TXC__GPIO1_IO12           0x31e
+                       MX93_PAD_SAI1_TXFS__GPIO1_IO11          0x31e
+                       MX93_PAD_SAI1_TXD0__GPIO1_IO13          0x31e
+                       MX93_PAD_SAI1_RXD0__GPIO1_IO14          0x31e
+                       MX93_PAD_UART2_RXD__GPIO1_IO06          0x31e
+                       MX93_PAD_I2C2_SDA__GPIO1_IO03           0x31e
+                       MX93_PAD_I2C2_SCL__GPIO1_IO02           0x31e
+               >;
+       };
+
        pinctrl_usdhc1: usdhc1grp {
                fsl,pins = <
                        MX93_PAD_SD1_CLK__USDHC1_CLK            0x15fe