arm64: dts: rockchip: Fix gmac0 reset pin for NanoPi R5S

According to the NanoPi R5S 2204 schematic on page 6, GPIO0_C4 is for
GMAC0_INT/PMEB_GPIO0_C4, while GPIO0_C5 is for GMAC0_RSTn_GPIO0_C5.
While the 'reset-gpios' property was set correctly, the corresponding
pinctrl didn't match that.

Next to fixing the pinctrl definition, also change the node name and
phandle to match what is used in the schematic.

Fixes: c6629b9a6738 ("arm64: dts: rockchip: Add FriendlyElec Nanopi R5S")
Signed-off-by: Diederik de Haas <diederik@cknow-tech.com>
Link: https://patch.msgid.link/20260401131551.734456-2-diederik@cknow-tech.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>

diff --git a/arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5s.dts b/arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5s.dts
index 718d1a2da8e5686d82cf67730855b581782819a7..90ce6f0e1dcff7d0cb08a4f4195c47c67e5a439c 100644 (file)
--- a/arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5s.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5s.dts
@@ -98,7 +98,7 @@
        rgmii_phy0: ethernet-phy@1 {
                compatible = "ethernet-phy-ieee802.3-c22";
                reg = <1>;
-               pinctrl-0 = <&eth_phy0_reset_pin>;
+               pinctrl-0 = <&gmac0_rstn_gpio0_c5_pin>;
                pinctrl-names = "default";
        };
 };
@@ -132,8 +132,8 @@
 
 &pinctrl {
        gmac0 {
-               eth_phy0_reset_pin: eth-phy0-reset-pin {
-                       rockchip,pins = <0 RK_PC4 RK_FUNC_GPIO &pcfg_pull_up>;
+               gmac0_rstn_gpio0_c5_pin: gmac0-rstn-gpio0-c5-pin {
+                       rockchip,pins = <0 RK_PC5 RK_FUNC_GPIO &pcfg_pull_up>;
                };
        };