pwm: mediatek: correct mt7628 clock source setting

PWMCON register Bit(3) is used to configure whether to pre divide
the clock source. Most revisions clear this bit to disable frequency
division. However, mt7628 needs to set this bit. Hence, we introduce
a new clksel_fixup flag to correctly configure the clock source for
mt7628.

Signed-off-by: Shiji Yang <yangshiji66@outlook.com>
Link: https://patch.msgid.link/OS7PR01MB136020DA816E8D601D5BA8BF4BC74A@OS7PR01MB13602.jpnprd01.prod.outlook.com
Signed-off-by: Uwe Kleine-König <ukleinek@kernel.org>

diff --git a/drivers/pwm/pwm-mediatek.c b/drivers/pwm/pwm-mediatek.c
index dee61e7caf8944e49018d385866e111043af2000..992137a2775013a5a4993340b78ddd321be6e8ea 100644 (file)
--- a/drivers/pwm/pwm-mediatek.c
+++ b/drivers/pwm/pwm-mediatek.c
@@ -23,6 +23,8 @@
 /* PWM registers and bits definitions */
 #define PWMCON                 0x00
 #define PWMCON_CLKDIV                  GENMASK(2, 0)
+#define PWMCON_CLKSEL                  BIT(3)
+#define PWMCON_OLD_PWM_MODE            BIT(15)
 #define PWMHDUR                        0x04
 #define PWMLDUR                        0x08
 #define PWMGDUR                        0x0c
@@ -38,6 +40,7 @@
 
 struct pwm_mediatek_of_data {
        unsigned int num_pwms;
+       bool clksel_fixup;
        bool pwm45_fixup;
        u16 pwm_ck_26m_sel_reg;
        unsigned int chanreg_base;
@@ -337,6 +340,7 @@ static int pwm_mediatek_write_waveform(struct pwm_chip *chip,
 
        if (wfhw->enable) {
                u32 reg_width = PWMDWIDTH, reg_thres = PWMTHRES;
+               u32 con_val = PWMCON_OLD_PWM_MODE | wfhw->con;
 
                if (pc->soc->pwm45_fixup && pwm->hwpwm > 2) {
                        /*
@@ -364,7 +368,11 @@ static int pwm_mediatek_write_waveform(struct pwm_chip *chip,
                if (pc->soc->pwm_ck_26m_sel_reg)
                        writel(0, pc->regs + pc->soc->pwm_ck_26m_sel_reg);
 
-               pwm_mediatek_writel(pc, pwm->hwpwm, PWMCON, BIT(15) | wfhw->con);
+               /* Set BIT(3) to disable clock division */
+               if (pc->soc->clksel_fixup)
+                       con_val |= PWMCON_CLKSEL;
+
+               pwm_mediatek_writel(pc, pwm->hwpwm, PWMCON, con_val);
                pwm_mediatek_writel(pc, pwm->hwpwm, reg_width, wfhw->width);
                pwm_mediatek_writel(pc, pwm->hwpwm, reg_thres, wfhw->thres);
        } else {
@@ -496,6 +504,7 @@ static int pwm_mediatek_probe(struct platform_device *pdev)
 
 static const struct pwm_mediatek_of_data mt2712_pwm_data = {
        .num_pwms = 8,
+       .clksel_fixup = false,
        .pwm45_fixup = false,
        .chanreg_base = 0x10,
        .chanreg_width = 0x40,
@@ -503,6 +512,7 @@ static const struct pwm_mediatek_of_data mt2712_pwm_data = {
 
 static const struct pwm_mediatek_of_data mt6795_pwm_data = {
        .num_pwms = 7,
+       .clksel_fixup = false,
        .pwm45_fixup = false,
        .chanreg_base = 0x10,
        .chanreg_width = 0x40,
@@ -510,6 +520,7 @@ static const struct pwm_mediatek_of_data mt6795_pwm_data = {
 
 static const struct pwm_mediatek_of_data mt7622_pwm_data = {
        .num_pwms = 6,
+       .clksel_fixup = false,
        .pwm45_fixup = false,
        .pwm_ck_26m_sel_reg = PWM_CK_26M_SEL,
        .chanreg_base = 0x10,
@@ -518,6 +529,7 @@ static const struct pwm_mediatek_of_data mt7622_pwm_data = {
 
 static const struct pwm_mediatek_of_data mt7623_pwm_data = {
        .num_pwms = 5,
+       .clksel_fixup = false,
        .pwm45_fixup = true,
        .chanreg_base = 0x10,
        .chanreg_width = 0x40,
@@ -525,6 +537,7 @@ static const struct pwm_mediatek_of_data mt7623_pwm_data = {
 
 static const struct pwm_mediatek_of_data mt7628_pwm_data = {
        .num_pwms = 4,
+       .clksel_fixup = true,
        .pwm45_fixup = false,
        .chanreg_base = 0x10,
        .chanreg_width = 0x40,
@@ -532,6 +545,7 @@ static const struct pwm_mediatek_of_data mt7628_pwm_data = {
 
 static const struct pwm_mediatek_of_data mt7629_pwm_data = {
        .num_pwms = 1,
+       .clksel_fixup = false,
        .pwm45_fixup = false,
        .chanreg_base = 0x10,
        .chanreg_width = 0x40,
@@ -539,6 +553,7 @@ static const struct pwm_mediatek_of_data mt7629_pwm_data = {
 
 static const struct pwm_mediatek_of_data mt7981_pwm_data = {
        .num_pwms = 3,
+       .clksel_fixup = false,
        .pwm45_fixup = false,
        .pwm_ck_26m_sel_reg = PWM_CK_26M_SEL,
        .chanreg_base = 0x80,
@@ -547,6 +562,7 @@ static const struct pwm_mediatek_of_data mt7981_pwm_data = {
 
 static const struct pwm_mediatek_of_data mt7986_pwm_data = {
        .num_pwms = 2,
+       .clksel_fixup = false,
        .pwm45_fixup = false,
        .pwm_ck_26m_sel_reg = PWM_CK_26M_SEL,
        .chanreg_base = 0x10,
@@ -555,6 +571,7 @@ static const struct pwm_mediatek_of_data mt7986_pwm_data = {
 
 static const struct pwm_mediatek_of_data mt7988_pwm_data = {
        .num_pwms = 8,
+       .clksel_fixup = false,
        .pwm45_fixup = false,
        .chanreg_base = 0x80,
        .chanreg_width = 0x40,
@@ -562,6 +579,7 @@ static const struct pwm_mediatek_of_data mt7988_pwm_data = {
 
 static const struct pwm_mediatek_of_data mt8183_pwm_data = {
        .num_pwms = 4,
+       .clksel_fixup = false,
        .pwm45_fixup = false,
        .pwm_ck_26m_sel_reg = PWM_CK_26M_SEL,
        .chanreg_base = 0x10,
@@ -570,6 +588,7 @@ static const struct pwm_mediatek_of_data mt8183_pwm_data = {
 
 static const struct pwm_mediatek_of_data mt8365_pwm_data = {
        .num_pwms = 3,
+       .clksel_fixup = false,
        .pwm45_fixup = false,
        .pwm_ck_26m_sel_reg = PWM_CK_26M_SEL,
        .chanreg_base = 0x10,
@@ -578,6 +597,7 @@ static const struct pwm_mediatek_of_data mt8365_pwm_data = {
 
 static const struct pwm_mediatek_of_data mt8516_pwm_data = {
        .num_pwms = 5,
+       .clksel_fixup = false,
        .pwm45_fixup = false,
        .pwm_ck_26m_sel_reg = PWM_CK_26M_SEL,
        .chanreg_base = 0x10,
@@ -586,6 +606,7 @@ static const struct pwm_mediatek_of_data mt8516_pwm_data = {
 
 static const struct pwm_mediatek_of_data mt6991_pwm_data = {
        .num_pwms = 4,
+       .clksel_fixup = false,
        .pwm45_fixup = false,
        .pwm_ck_26m_sel_reg = PWM_CK_26M_SEL_V3,
        .chanreg_base = 0x100,