clk: renesas: r9a09g056: Add clock and reset entries for RTC

Add module clock and reset entries for the RTC module on the Renesas
RZ/V2N (R9A09G056) SoC.

Signed-off-by: Ovidiu Panait <ovidiu.panait.rb@renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://patch.msgid.link/20260125192706.27099-3-ovidiu.panait.rb@renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

diff --git a/drivers/clk/renesas/r9a09g056-cpg.c b/drivers/clk/renesas/r9a09g056-cpg.c
index 70de6bb929b912f8ed3d6c0471035b8d94188b9f..549c882f9a18d1303be9f7797d751c42b7ede6fb 100644 (file)
--- a/drivers/clk/renesas/r9a09g056-cpg.c
+++ b/drivers/clk/renesas/r9a09g056-cpg.c
@@ -289,6 +289,8 @@ static const struct rzv2h_mod_clk r9a09g056_mod_clks[] __initconst = {
                                                BUS_MSTOP(5, BIT(13))),
        DEF_MOD("wdt_3_clk_loco",               CLK_QEXTAL, 5, 2, 2, 18,
                                                BUS_MSTOP(5, BIT(13))),
+       DEF_MOD("rtc_0_clk_rtc",                CLK_PLLCM33_DIV16, 5, 3, 2, 19,
+                                               BUS_MSTOP(3, BIT(11) | BIT(12))),
        DEF_MOD("rspi_0_pclk",                  CLK_PLLCLN_DIV8, 5, 4, 2, 20,
                                                BUS_MSTOP(11, BIT(0))),
        DEF_MOD("rspi_0_pclk_sfr",              CLK_PLLCLN_DIV8, 5, 5, 2, 21,
@@ -593,6 +595,8 @@ static const struct rzv2h_reset r9a09g056_resets[] __initconst = {
        DEF_RST(9, 2, 4, 3),            /* RSCI8_TRESETN */
        DEF_RST(9, 3, 4, 4),            /* RSCI9_PRESETN */
        DEF_RST(9, 4, 4, 5),            /* RSCI9_TRESETN */
+       DEF_RST(7, 9, 3, 10),           /* RTC_0_RST_RTC */
+       DEF_RST(7, 10, 3, 11),          /* RTC_0_RST_RTC_V */
        DEF_RST(7, 11, 3, 12),          /* RSPI_0_PRESETN */
        DEF_RST(7, 12, 3, 13),          /* RSPI_0_TRESETN */
        DEF_RST(7, 13, 3, 14),          /* RSPI_1_PRESETN */