Daily bump.

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 1bfe6cf5d1dcc118ae3a8487abf532f420d4ccae..a54b549618ac6236142e3ba064d043a9bca03f45 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,183 @@
+2020-06-24  Peter Bergner  <bergner@linux.ibm.com>
+
+       Backported from master:
+       2020-06-21  Peter Bergner  <bergner@linux.ibm.com>
+
+       * config/rs6000/predicates.md (mma_assemble_input_operand): New.
+       * config/rs6000/rs6000-builtin.def (BU_MMA_1, BU_MMA_V2, BU_MMA_3,
+       BU_MMA_5, BU_MMA_6, BU_VSX_1): Add support macros for defining MMA
+       built-in functions.
+       (ASSEMBLE_ACC, ASSEMBLE_PAIR, DISASSEMBLE_ACC, DISASSEMBLE_PAIR,
+       PMXVBF16GER2, PMXVBF16GER2NN, PMXVBF16GER2NP, PMXVBF16GER2PN,
+       PMXVBF16GER2PP, PMXVF16GER2, PMXVF16GER2NN, PMXVF16GER2NP,
+       PMXVF16GER2PN, PMXVF16GER2PP, PMXVF32GER, PMXVF32GERNN,
+       PMXVF32GERNP, PMXVF32GERPN, PMXVF32GERPP, PMXVF64GER, PMXVF64GERNN,
+       PMXVF64GERNP, PMXVF64GERPN, PMXVF64GERPP, PMXVI16GER2, PMXVI16GER2PP,
+       PMXVI16GER2S, PMXVI16GER2SPP, PMXVI4GER8, PMXVI4GER8PP, PMXVI8GER4,
+       PMXVI8GER4PP, PMXVI8GER4SPP, XVBF16GER2, XVBF16GER2NN, XVBF16GER2NP,
+       XVBF16GER2PN, XVBF16GER2PP, XVCVBF16SP, XVCVSPBF16, XVF16GER2,
+       XVF16GER2NN, XVF16GER2NP, XVF16GER2PN, XVF16GER2PP, XVF32GER,
+       XVF32GERNN, XVF32GERNP, XVF32GERPN, XVF32GERPP, XVF64GER, XVF64GERNN,
+       XVF64GERNP, XVF64GERPN, XVF64GERPP, XVI16GER2, XVI16GER2PP, XVI16GER2S,
+       XVI16GER2SPP, XVI4GER8, XVI4GER8PP, XVI8GER4, XVI8GER4PP, XVI8GER4SPP,
+       XXMFACC, XXMTACC, XXSETACCZ): Add MMA built-ins.
+       * config/rs6000/rs6000.c (rs6000_emit_move): Use CONST_INT_P.
+       Allow zero constants.
+       (print_operand) <case 'A'>: New output modifier.
+       (rs6000_split_multireg_move): Add support for inserting accumulator
+       priming and depriming instructions.  Add support for splitting an
+       assemble accumulator pattern.
+       * config/rs6000/rs6000-call.c (mma_init_builtins, mma_expand_builtin,
+       rs6000_gimple_fold_mma_builtin): New functions.
+       (RS6000_BUILTIN_M): New macro.
+       (def_builtin): Handle RS6000_BTC_QUAD and RS6000_BTC_PAIR attributes.
+       (bdesc_mma): Add new MMA built-in support.
+       (htm_expand_builtin): Use RS6000_BTC_OPND_MASK.
+       (rs6000_invalid_builtin): Add handling of RS6000_BTM_FUTURE and
+       RS6000_BTM_MMA.
+       (rs6000_builtin_valid_without_lhs): Handle RS6000_BTC_VOID attribute.
+       (rs6000_gimple_fold_builtin): Call rs6000_builtin_is_supported_p
+       and rs6000_gimple_fold_mma_builtin.
+       (rs6000_expand_builtin): Call mma_expand_builtin.
+       Use RS6000_BTC_OPND_MASK.
+       (rs6000_init_builtins): Adjust comment.  Call mma_init_builtins.
+       (htm_init_builtins): Use RS6000_BTC_OPND_MASK.
+       (builtin_function_type): Handle VSX_BUILTIN_XVCVSPBF16 and
+       VSX_BUILTIN_XVCVBF16SP.
+       * config/rs6000/rs6000.h (RS6000_BTC_QUINARY, RS6000_BTC_SENARY,
+       RS6000_BTC_OPND_MASK, RS6000_BTC_QUAD, RS6000_BTC_PAIR,
+       RS6000_BTC_QUADPAIR, RS6000_BTC_GIMPLE): New defines.
+       (RS6000_BTC_PREDICATE, RS6000_BTC_ABS, RS6000_BTC_DST,
+       RS6000_BTC_TYPE_MASK, RS6000_BTC_ATTR_MASK): Adjust values.
+       * config/rs6000/mma.md (MAX_MMA_OPERANDS): New define_constant.
+       (UNSPEC_MMA_ASSEMBLE_ACC, UNSPEC_MMA_PMXVBF16GER2,
+       UNSPEC_MMA_PMXVBF16GER2NN, UNSPEC_MMA_PMXVBF16GER2NP,
+       UNSPEC_MMA_PMXVBF16GER2PN, UNSPEC_MMA_PMXVBF16GER2PP,
+       UNSPEC_MMA_PMXVF16GER2, UNSPEC_MMA_PMXVF16GER2NN,
+       UNSPEC_MMA_PMXVF16GER2NP, UNSPEC_MMA_PMXVF16GER2PN,
+       UNSPEC_MMA_PMXVF16GER2PP, UNSPEC_MMA_PMXVF32GER,
+       UNSPEC_MMA_PMXVF32GERNN, UNSPEC_MMA_PMXVF32GERNP,
+       UNSPEC_MMA_PMXVF32GERPN, UNSPEC_MMA_PMXVF32GERPP,
+       UNSPEC_MMA_PMXVF64GER, UNSPEC_MMA_PMXVF64GERNN,
+       UNSPEC_MMA_PMXVF64GERNP, UNSPEC_MMA_PMXVF64GERPN,
+       UNSPEC_MMA_PMXVF64GERPP, UNSPEC_MMA_PMXVI16GER2,
+       UNSPEC_MMA_PMXVI16GER2PP, UNSPEC_MMA_PMXVI16GER2S,
+       UNSPEC_MMA_PMXVI16GER2SPP, UNSPEC_MMA_PMXVI4GER8,
+       UNSPEC_MMA_PMXVI4GER8PP, UNSPEC_MMA_PMXVI8GER4,
+       UNSPEC_MMA_PMXVI8GER4PP, UNSPEC_MMA_PMXVI8GER4SPP,
+       UNSPEC_MMA_XVBF16GER2, UNSPEC_MMA_XVBF16GER2NN,
+       UNSPEC_MMA_XVBF16GER2NP, UNSPEC_MMA_XVBF16GER2PN,
+       UNSPEC_MMA_XVBF16GER2PP, UNSPEC_MMA_XVF16GER2, UNSPEC_MMA_XVF16GER2NN,
+       UNSPEC_MMA_XVF16GER2NP, UNSPEC_MMA_XVF16GER2PN, UNSPEC_MMA_XVF16GER2PP,
+       UNSPEC_MMA_XVF32GER, UNSPEC_MMA_XVF32GERNN, UNSPEC_MMA_XVF32GERNP,
+       UNSPEC_MMA_XVF32GERPN, UNSPEC_MMA_XVF32GERPP, UNSPEC_MMA_XVF64GER,
+       UNSPEC_MMA_XVF64GERNN, UNSPEC_MMA_XVF64GERNP, UNSPEC_MMA_XVF64GERPN,
+       UNSPEC_MMA_XVF64GERPP, UNSPEC_MMA_XVI16GER2, UNSPEC_MMA_XVI16GER2PP,
+       UNSPEC_MMA_XVI16GER2S, UNSPEC_MMA_XVI16GER2SPP, UNSPEC_MMA_XVI4GER8,
+       UNSPEC_MMA_XVI4GER8PP, UNSPEC_MMA_XVI8GER4, UNSPEC_MMA_XVI8GER4PP,
+       UNSPEC_MMA_XVI8GER4SPP, UNSPEC_MMA_XXMFACC, UNSPEC_MMA_XXMTACC): New.
+       (MMA_ACC, MMA_VV, MMA_AVV, MMA_PV, MMA_APV, MMA_VVI4I4I8,
+       MMA_AVVI4I4I8, MMA_VVI4I4I2, MMA_AVVI4I4I2, MMA_VVI4I4,
+       MMA_AVVI4I4, MMA_PVI4I2, MMA_APVI4I2, MMA_VVI4I4I4,
+       MMA_AVVI4I4I4): New define_int_iterator.
+       (acc, vv, avv, pv, apv, vvi4i4i8, avvi4i4i8, vvi4i4i2,
+       avvi4i4i2, vvi4i4, avvi4i4, pvi4i2, apvi4i2, vvi4i4i4,
+       avvi4i4i4): New define_int_attr.
+       (*movpxi): Add zero constant alternative.
+       (mma_assemble_pair, mma_assemble_acc): New define_expand.
+       (*mma_assemble_acc): New define_insn_and_split.
+       (mma_<acc>, mma_xxsetaccz, mma_<vv>, mma_<avv>, mma_<pv>, mma_<apv>,
+       mma_<vvi4i4i8>, mma_<avvi4i4i8>, mma_<vvi4i4i2>, mma_<avvi4i4i2>,
+       mma_<vvi4i4>, mma_<avvi4i4>, mma_<pvi4i2>, mma_<apvi4i2>,
+       mma_<vvi4i4i4>, mma_<avvi4i4i4>): New define_insn.
+       * config/rs6000/rs6000.md (define_attr "type"): New type mma.
+       * config/rs6000/vsx.md (UNSPEC_VSX_XVCVBF16SP): New.
+       (UNSPEC_VSX_XVCVSPBF16): Likewise.
+       (XVCVBF16): New define_int_iterator.
+       (xvcvbf16): New define_int_attr.
+       (vsx_<xvcvbf16>): New define_insn.
+       * doc/extend.texi: Document the mma built-ins.
+
+2020-06-24  Kelvin Nilsen  <wschmidt@linux.ibm.com>
+
+       * config/rs6000/predicates.md (u8bit_cint_operand): New predicate.
+
+2020-06-24  Peter Bergner  <bergner@linux.ibm.com>
+
+       Backported from master:
+       2020-06-21  Peter Bergner  <bergner@linux.ibm.com>
+                   Michael Meissner  <meissner@linux.ibm.com>
+
+       * config/rs6000/mma.md: New file.
+       * config/rs6000/rs6000-c.c (rs6000_target_modify_macros): Define
+       __MMA__ for mma.
+       * config/rs6000/rs6000-call.c (rs6000_init_builtins): Add support
+       for __vector_pair and __vector_quad types.
+       * config/rs6000/rs6000-cpus.def (OTHER_FUTURE_MASKS): Add
+       OPTION_MASK_MMA.
+       (POWERPC_MASKS): Likewise.
+       * config/rs6000/rs6000-modes.def (OI, XI): New integer modes.
+       (POI, PXI): New partial integer modes.
+       * config/rs6000/rs6000.c (TARGET_INVALID_CONVERSION): Define.
+       (rs6000_hard_regno_nregs_internal): Use VECTOR_ALIGNMENT_P.
+       (rs6000_hard_regno_mode_ok_uncached): Likewise.
+       Add support for POImode being allowed in VSX registers and PXImode
+       being allowed in FP registers.
+       (rs6000_modes_tieable_p): Adjust comment.
+       Add support for POImode and PXImode.
+       (rs6000_debug_reg_global) <print_tieable_modes>: Add OImode, POImode
+       XImode, PXImode, V2SImode, V2SFmode and CCFPmode..
+       (rs6000_setup_reg_addr_masks): Use VECTOR_ALIGNMENT_P.
+       Set up appropriate addr_masks for vector pair and vector quad addresses.
+       (rs6000_init_hard_regno_mode_ok): Add support for vector pair and
+       vector quad registers.  Setup reload handlers for POImode and PXImode.
+       (rs6000_builtin_mask_calculate): Add support for RS6000_BTM_MMA.
+       (rs6000_option_override_internal): Error if -mmma is specified
+       without -mcpu=future.
+       (rs6000_slow_unaligned_access): Use VECTOR_ALIGNMENT_P.
+       (quad_address_p): Change size test to less than 16 bytes.
+       (reg_offset_addressing_ok_p): Add support for ISA 3.1 vector pair
+       and vector quad instructions.
+       (avoiding_indexed_address_p): Likewise.
+       (rs6000_emit_move): Disallow POImode and PXImode moves involving
+       constants.
+       (rs6000_preferred_reload_class): Prefer VSX registers for POImode
+       and FP registers for PXImode.
+       (rs6000_split_multireg_move): Support splitting POImode and PXImode
+       move instructions.
+       (rs6000_mangle_type): Adjust comment.  Add support for mangling
+       __vector_pair and __vector_quad types.
+       (rs6000_opt_masks): Add entry for mma.
+       (rs6000_builtin_mask_names): Add RS6000_BTM_MMA and RS6000_BTM_FUTURE.
+       (rs6000_function_value): Use VECTOR_ALIGNMENT_P.
+       (address_to_insn_form): Likewise.
+       (reg_to_non_prefixed): Likewise.
+       (rs6000_invalid_conversion): New function.
+       * config/rs6000/rs6000.h (MASK_MMA): Define.
+       (BIGGEST_ALIGNMENT): Set to 512 if MMA support is enabled.
+       (VECTOR_ALIGNMENT_P): New helper macro.
+       (ALTIVEC_VECTOR_MODE): Use VECTOR_ALIGNMENT_P.
+       (RS6000_BTM_MMA): Define.
+       (RS6000_BTM_COMMON): Add RS6000_BTM_MMA and RS6000_BTM_FUTURE.
+       (rs6000_builtin_type_index): Add RS6000_BTI_vector_pair and
+       RS6000_BTI_vector_quad.
+       (vector_pair_type_node): New.
+       (vector_quad_type_node): New.
+       * config/rs6000/rs6000.md: Include mma.md.
+       (define_mode_iterator RELOAD): Add POI and PXI.
+       * config/rs6000/t-rs6000 (MD_INCLUDES): Add mma.md.
+       * config/rs6000/rs6000.opt (-mmma): New.
+       * doc/invoke.texi: Document -mmma.
+
+2020-06-24  Richard Biener  <rguenther@suse.de>
+
+       Backported from master:
+       2020-06-17  Richard Biener  <rguenther@suse.de>
+
+       PR tree-optimization/95717
+       * tree-vect-loop-manip.c (slpeel_tree_duplicate_loop_to_edge_cfg):
+       Move BB SSA updating before exit/latch PHI current def copying.
+
 2020-06-23  Richard Biener  <rguenther@suse.de>
 
        PR middle-end/95493

diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP
index 1e6790229fe6231eee114d508e9eff5126cced79..ab7687c5b0de40a371f1f4ce721091e759036a31 100644 (file)
--- a/gcc/DATESTAMP
+++ b/gcc/DATESTAMP
@@ -1 +1 @@
-20200624
+20200625

diff --git a/gcc/cp/ChangeLog b/gcc/cp/ChangeLog
index 0faa5bda7e314bf4dcc6f4b83c64827217c51829..a8f21f9bc3899d6b6a1a778fa1bedce69cf4811f 100644 (file)
--- a/gcc/cp/ChangeLog
+++ b/gcc/cp/ChangeLog
@@ -1,3 +1,12 @@
+2020-06-24  Jason Merrill  <jason@redhat.com>
+
+       Backported from master:
+       2020-06-24  Jason Merrill  <jason@redhat.com>
+
+       PR c++/95719
+       * call.c (build_over_call): Look up the overrider in base_binfo.
+       * class.c (lookup_vfn_in_binfo): Look through BINFO_PRIMARY_P.
+
 2020-06-22  Jason Merrill  <jason@redhat.com>
 
        * call.c (joust): Only compare constraints for non-template

diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index ab8c7c9775931bab9cf0a924944f5109a406efb5..252faa9f831577bf74341434e72e1ee004b3738b 100644 (file)
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,31 @@
+2020-06-24  Peter Bergner  <bergner@linux.ibm.com>
+
+       Backported from master:
+       2020-06-21  Peter Bergner  <bergner@linux.ibm.com>
+
+       * gcc.target/powerpc/mma-builtin-1.c: New test.
+       * gcc.target/powerpc/mma-builtin-2.c: New test.
+       * gcc.target/powerpc/mma-builtin-3.c: New test.
+       * gcc.target/powerpc/mma-builtin-4.c: New test.
+       * gcc.target/powerpc/mma-builtin-5.c: New test.
+       * gcc.target/powerpc/mma-builtin-6.c: New test.
+
+2020-06-24  Jason Merrill  <jason@redhat.com>
+
+       Backported from master:
+       2020-06-24  Jason Merrill  <jason@redhat.com>
+
+       PR c++/95719
+       * g++.dg/tree-ssa/final4.C: New test.
+
+2020-06-24  Richard Biener  <rguenther@suse.de>
+
+       Backported from master:
+       2020-06-17  Richard Biener  <rguenther@suse.de>
+
+       PR tree-optimization/95717
+       * g++.dg/torture/pr95717.C: New testcase.
+
 2020-06-23  Thomas Koenig  <tkoenig@gcc.gnu.org>
 
        Backported from master:

diff --git a/libstdc++-v3/ChangeLog b/libstdc++-v3/ChangeLog
index 5b3e04c9ca0ddcd529b46ee16577c11a1d264c35..681071334f3a043daff26b8082a574d685d03982 100644 (file)
--- a/libstdc++-v3/ChangeLog
+++ b/libstdc++-v3/ChangeLog
@@ -1,3 +1,32 @@
+2020-06-24  Jonathan Wakely  <jwakely@redhat.com>
+
+       Backported from master:
+       2020-06-24  Jonathan Wakely  <jwakely@redhat.com>
+
+       * include/std/charconv (__from_chars_binary): Ignore leading zeros.
+       * testsuite/20_util/from_chars/1.cc: Check "0x1" for all bases,
+       not just 10 and 16.
+       * testsuite/20_util/from_chars/3.cc: New test.
+
+2020-06-24  Jonathan Wakely  <jwakely@redhat.com>
+
+       Backported from master:
+       2020-06-24  Jonathan Wakely  <jwakely@redhat.com>
+
+       * include/bits/stl_algobase.h (__find_if): Add FALLTHRU markers.
+       * include/std/charconv (__detail::__to_chars): Avoid
+       -Wsign-compare warning.
+
+2020-06-24  Jonathan Wakely  <jwakely@redhat.com>
+
+       Backported from master:
+       2020-06-24  Jonathan Wakely  <jwakely@redhat.com>
+
+       PR libstdc++/95851
+       * include/std/charconv (__to_chars_i): Check for zero-sized
+       buffer unconditionally.
+       * testsuite/20_util/to_chars/95851.cc: New test.
+
 2020-06-22  Jason Merrill  <jason@redhat.com>
 
        * testsuite/24_iterators/move_iterator/rel_ops_c++20.cc: