]> git.ipfire.org Git - thirdparty/kernel/linux.git/commitdiff
fpga: altera-cvp: Use pci_find_vsec_capability() when probing FPGA device
authorAndy Shevchenko <andriy.shevchenko@linux.intel.com>
Sun, 9 Nov 2025 20:16:37 +0000 (21:16 +0100)
committerXu Yilun <yilun.xu@linux.intel.com>
Mon, 10 Nov 2025 07:03:13 +0000 (15:03 +0800)
Currently altera_cvp_probe() open-codes pci_find_vsec_capability().
Refactor the former to use the latter.

With that done:
- use the VSEC ID as per datasheet [1]
- update the error message accordingly

Link: https://www.intel.com/content/www/us/en/docs/programmable/683763/23-1/vendor-specific-header-register.html
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Link: https://lore.kernel.org/r/20251109201729.3220460-1-andriy.shevchenko@linux.intel.com
Reviewed-by: Xu Yilun <yilun.xu@intel.com>
Signed-off-by: Xu Yilun <yilun.xu@linux.intel.com>
drivers/fpga/altera-cvp.c

index 5af0bd33890c0bae4654203f01fa3d828dace1b9..44badfd11e1b0ae5ff3d38c2d8d318a95f5515bc 100644 (file)
@@ -22,9 +22,6 @@
 #define TIMEOUT_US     2000    /* CVP STATUS timeout for USERMODE polling */
 
 /* Vendor Specific Extended Capability Registers */
-#define VSE_PCIE_EXT_CAP_ID            0x0
-#define VSE_PCIE_EXT_CAP_ID_VAL                0x000b  /* 16bit */
-
 #define VSE_CVP_STATUS                 0x1c    /* 32bit */
 #define VSE_CVP_STATUS_CFG_RDY         BIT(18) /* CVP_CONFIG_READY */
 #define VSE_CVP_STATUS_CFG_ERR         BIT(19) /* CVP_CONFIG_ERROR */
@@ -577,25 +574,18 @@ static int altera_cvp_probe(struct pci_dev *pdev,
 {
        struct altera_cvp_conf *conf;
        struct fpga_manager *mgr;
-       int ret, offset;
-       u16 cmd, val;
+       u16 cmd, offset;
        u32 regval;
-
-       /* Discover the Vendor Specific Offset for this device */
-       offset = pci_find_next_ext_capability(pdev, 0, PCI_EXT_CAP_ID_VNDR);
-       if (!offset) {
-               dev_err(&pdev->dev, "No Vendor Specific Offset.\n");
-               return -ENODEV;
-       }
+       int ret;
 
        /*
         * First check if this is the expected FPGA device. PCI config
         * space access works without enabling the PCI device, memory
         * space access is enabled further down.
         */
-       pci_read_config_word(pdev, offset + VSE_PCIE_EXT_CAP_ID, &val);
-       if (val != VSE_PCIE_EXT_CAP_ID_VAL) {
-               dev_err(&pdev->dev, "Wrong EXT_CAP_ID value 0x%x\n", val);
+       offset = pci_find_vsec_capability(pdev, PCI_VENDOR_ID_ALTERA, 0x1172);
+       if (!offset) {
+               dev_err(&pdev->dev, "Wrong VSEC ID value\n");
                return -ENODEV;
        }