clk: renesas: r9a09g047: Add I3C0 clocks and resets

Add I3C0 clock and reset support to the Renesas RZ/G3E R9A09G047 CPG
driver.

Signed-off-by: Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com>
Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20250611093934.4208-3-wsa+renesas@sang-engineering.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

diff --git a/drivers/clk/renesas/r9a09g047-cpg.c b/drivers/clk/renesas/r9a09g047-cpg.c
index 21699999cedded8a2336c8c92f62c8c81fd03802..3e50447ed9f3d1003d0e8fcf118da71dea1bcb6f 100644 (file)
--- a/drivers/clk/renesas/r9a09g047-cpg.c
+++ b/drivers/clk/renesas/r9a09g047-cpg.c
@@ -160,6 +160,12 @@ static const struct rzv2h_mod_clk r9a09g047_mod_clks[] __initconst = {
                                                BUS_MSTOP(5, BIT(13))),
        DEF_MOD("scif_0_clk_pck",               CLK_PLLCM33_DIV16, 8, 15, 4, 15,
                                                BUS_MSTOP(3, BIT(14))),
+       DEF_MOD("i3c_0_pclkrw",                 CLK_PLLCLN_DIV16, 9, 0, 4, 16,
+                                               BUS_MSTOP(10, BIT(15))),
+       DEF_MOD("i3c_0_pclk",                   CLK_PLLCLN_DIV16, 9, 1, 4, 17,
+                                               BUS_MSTOP(10, BIT(15))),
+       DEF_MOD("i3c_0_tclk",                   CLK_PLLCLN_DIV8, 9, 2, 4, 18,
+                                               BUS_MSTOP(10, BIT(15))),
        DEF_MOD("riic_8_ckm",                   CLK_PLLCM33_DIV16, 9, 3, 4, 19,
                                                BUS_MSTOP(3, BIT(13))),
        DEF_MOD("riic_0_ckm",                   CLK_PLLCLN_DIV16, 9, 4, 4, 20,
@@ -239,6 +245,8 @@ static const struct rzv2h_reset r9a09g047_resets[] __initconst = {
        DEF_RST(7, 7, 3, 8),            /* WDT_2_RESET */
        DEF_RST(7, 8, 3, 9),            /* WDT_3_RESET */
        DEF_RST(9, 5, 4, 6),            /* SCIF_0_RST_SYSTEM_N */
+       DEF_RST(9, 6, 4, 7),            /* I3C_0_PRESETN */
+       DEF_RST(9, 7, 4, 8),            /* I3C_0_TRESETN */
        DEF_RST(9, 8, 4, 9),            /* RIIC_0_MRST */
        DEF_RST(9, 9, 4, 10),           /* RIIC_1_MRST */
        DEF_RST(9, 10, 4, 11),          /* RIIC_2_MRST */