clk: renesas: rzg2l: Rename RZG3L-prefixed PLL macros to CPG-prefixed ones

Rename RZG3L_PLL_STBY_OFFSET(), RZG3L_PLL_STBY_RESETB,
RZG3L_PLL_STBY_RESETB_WEN, RZG3L_PLL_MON_OFFSET(), RZG3L_PLL_MON_RESETB,
and RZG3L_PLL_MON_LOCK to their CPG_PLL_* equivalents to reflect that
these macros are not RZG3L-specific and are shared across SoCs.

Also fold CPG_PLL_MON_OFFSET() into rzg2l-cpg.c alongside the other
CPG_PLL_*_OFFSET() helpers introduced in previous patches.

No functional changes.

Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Link: https://patch.msgid.link/20260519141518.389670-4-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

diff --git a/drivers/clk/renesas/rzg2l-cpg.c b/drivers/clk/renesas/rzg2l-cpg.c
index 096901e25317886286e59b330955db6701ea8ade..0abe00e2960ba386d2152d04f8d5a386e020ea6a 100644 (file)
--- a/drivers/clk/renesas/rzg2l-cpg.c
+++ b/drivers/clk/renesas/rzg2l-cpg.c
@@ -60,15 +60,13 @@
 
 #define CPG_PLL1_SETTING_OFFSET(conf)  FIELD_GET(GENMASK(11, 0), (conf))
 #define CPG_PLL_STBY_OFFSET(conf)      FIELD_GET(GENMASK(23, 12), (conf))
+#define CPG_PLL_STBY_RESETB_WEN                BIT(16)
+#define CPG_PLL_STBY_RESETB            BIT(0)
 #define CPG_PLL_CLK1_OFFSET(x)         (CPG_PLL_STBY_OFFSET(x) + 0x4)
 #define CPG_PLL_CLK2_OFFSET(x)         (CPG_PLL_STBY_OFFSET(x) + 0x8)
-
-#define RZG3L_PLL_STBY_OFFSET(x)       (CPG_PLL_STBY_OFFSET(x))
-#define RZG3L_PLL_STBY_RESETB          BIT(0)
-#define RZG3L_PLL_STBY_RESETB_WEN      BIT(16)
-#define RZG3L_PLL_MON_OFFSET(x)                (CPG_PLL_STBY_OFFSET(x) + 0xc)
-#define RZG3L_PLL_MON_RESETB           BIT(0)
-#define RZG3L_PLL_MON_LOCK             BIT(4)
+#define CPG_PLL_MON_OFFSET(x)          (CPG_PLL_STBY_OFFSET(x) + 0xc)
+#define CPG_PLL_MON_LOCK               BIT(4)
+#define CPG_PLL_MON_RESETB             BIT(0)
 
 #define CLK_ON_R(reg)          (reg)
 #define CLK_MON_R(reg)         (0x180 + (reg))
@@ -1188,8 +1186,8 @@ static int rzg3l_cpg_pll_clk_is_enabled(struct clk_hw *hw)
 {
        struct pll_clk *pll_clk = to_pll(hw);
        struct rzg2l_cpg_priv *priv = pll_clk->priv;
-       u32 val = readl(priv->base + RZG3L_PLL_MON_OFFSET(pll_clk->conf));
-       u32 mon_val = RZG3L_PLL_MON_RESETB | RZG3L_PLL_MON_LOCK;
+       u32 val = readl(priv->base + CPG_PLL_MON_OFFSET(pll_clk->conf));
+       u32 mon_val = CPG_PLL_MON_RESETB | CPG_PLL_MON_LOCK;
 
        /* Ensure both RESETB and LOCK bits are set */
        return (mon_val == (val & mon_val));
@@ -1199,17 +1197,17 @@ static int rzg3l_cpg_pll_clk_endisable(struct clk_hw *hw, bool enable)
 {
        struct pll_clk *pll_clk = to_pll(hw);
        struct rzg2l_cpg_priv *priv = pll_clk->priv;
-       u32 mon_mask = RZG3L_PLL_MON_RESETB | RZG3L_PLL_MON_LOCK;
-       u32 val = RZG3L_PLL_STBY_RESETB_WEN;
+       u32 mon_mask = CPG_PLL_MON_RESETB | CPG_PLL_MON_LOCK;
+       u32 val = CPG_PLL_STBY_RESETB_WEN;
        u32 stby_offset, mon_offset;
        u32 mon_val = 0;
        int ret;
 
-       stby_offset = RZG3L_PLL_STBY_OFFSET(pll_clk->conf);
-       mon_offset = RZG3L_PLL_MON_OFFSET(pll_clk->conf);
+       stby_offset = CPG_PLL_STBY_OFFSET(pll_clk->conf);
+       mon_offset = CPG_PLL_MON_OFFSET(pll_clk->conf);
 
        if (enable) {
-               val |= RZG3L_PLL_STBY_RESETB;
+               val |= CPG_PLL_STBY_RESETB;
                mon_val = mon_mask;
        }