drm/xe: Consolidate workaround entries for Wa_16028005424

Wa_16028005424 applies to all media IPs from 13.01 to 35.00 (inclusive)
and all graphics IPs from 30.00 and 30.05 (inclusive).  Conslidate the
multiple RTP entries into a single range-based entry.

Reviewed-by: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com>
Link: https://patch.msgid.link/20260220-forupstream-wa_cleanup-v2-6-b12005a05af6@intel.com
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>

diff --git a/drivers/gpu/drm/xe/xe_wa.c b/drivers/gpu/drm/xe/xe_wa.c
index 33e7e33db83175953361ee13dd40af8954c6d838..4009323da8021cf5791a96e119b7b71b64eb4431 100644 (file)
--- a/drivers/gpu/drm/xe/xe_wa.c
+++ b/drivers/gpu/drm/xe/xe_wa.c
@@ -159,6 +159,11 @@ static const struct xe_rtp_entry_sr gt_was[] = {
          XE_RTP_ACTIONS(SET(VDBOX_CGCTL3F08(0), CG3DDISHRS_CLKGATE_DIS)),
          XE_RTP_ENTRY_FLAG(FOREACH_ENGINE),
        },
+       { XE_RTP_NAME("16028005424"),
+         XE_RTP_RULES(GRAPHICS_VERSION_RANGE(3000, 3005), OR,
+                      MEDIA_VERSION_RANGE(1301, 3500)),
+         XE_RTP_ACTIONS(SET(GUC_INTR_CHICKEN, DISABLE_SIGNALING_ENGINES))
+       },
 
        /* DG1 */
 
@@ -239,10 +244,6 @@ static const struct xe_rtp_entry_sr gt_was[] = {
          XE_RTP_ACTIONS(SET(VDBOX_CGCTL3F10(0), IECPUNIT_CLKGATE_DIS)),
          XE_RTP_ENTRY_FLAG(FOREACH_ENGINE),
        },
-       { XE_RTP_NAME("16028005424"),
-         XE_RTP_RULES(MEDIA_VERSION(2000)),
-         XE_RTP_ACTIONS(SET(GUC_INTR_CHICKEN, DISABLE_SIGNALING_ENGINES))
-       },
 
        /* Xe2_HPG */
 
@@ -256,23 +257,12 @@ static const struct xe_rtp_entry_sr gt_was[] = {
                             LSN_DIM_Z_WGT(1)))
        },
 
-       /* Xe2_HPM */
-
-       { XE_RTP_NAME("16028005424"),
-         XE_RTP_RULES(MEDIA_VERSION(1301)),
-         XE_RTP_ACTIONS(SET(GUC_INTR_CHICKEN, DISABLE_SIGNALING_ENGINES))
-       },
-
        /* Xe3_LPG */
 
        { XE_RTP_NAME("14021871409"),
          XE_RTP_RULES(GRAPHICS_VERSION(3000), GRAPHICS_STEP(A0, B0)),
          XE_RTP_ACTIONS(SET(UNSLCGCTL9454, LSCFE_CLKGATE_DIS))
        },
-       { XE_RTP_NAME("16028005424"),
-         XE_RTP_RULES(GRAPHICS_VERSION_RANGE(3000, 3005)),
-         XE_RTP_ACTIONS(SET(GUC_INTR_CHICKEN, DISABLE_SIGNALING_ENGINES))
-       },
 
        /* Xe3_LPM */
 
@@ -294,17 +284,6 @@ static const struct xe_rtp_entry_sr gt_was[] = {
          XE_RTP_ACTIONS(SET(VDBOX_CGCTL3F10(0), RAMDFTUNIT_CLKGATE_DIS)),
          XE_RTP_ENTRY_FLAG(FOREACH_ENGINE),
        },
-       { XE_RTP_NAME("16028005424"),
-         XE_RTP_RULES(MEDIA_VERSION_RANGE(3000, 3002)),
-         XE_RTP_ACTIONS(SET(GUC_INTR_CHICKEN, DISABLE_SIGNALING_ENGINES))
-       },
-
-       /* Xe3p_LPM */
-
-       { XE_RTP_NAME("16028005424"),
-         XE_RTP_RULES(MEDIA_VERSION(3500)),
-         XE_RTP_ACTIONS(SET(GUC_INTR_CHICKEN, DISABLE_SIGNALING_ENGINES))
-       },
 
        /* Xe3P_LPG */