arm64: dts: qcom: sm8650: add cpu interconnect nodes

Add the interconnect entry for each cpu, with 3 different paths:
- CPU to Last Level Cache Controller (LLCC)
- Last Level Cache Controller (LLCC) to DDR
- L3 Cache from CPU to DDR interface

Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
Link: https://lore.kernel.org/r/20250211-topic-sm8650-ddr-bw-scaling-v2-2-a0c950540e68@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>

diff --git a/arch/arm64/boot/dts/qcom/sm8650.dtsi b/arch/arm64/boot/dts/qcom/sm8650.dtsi
index bc09e879c1440873a52daf3fc7a38f451f1f972c..e194a95cdcc0f0f692e62b942331cd9e07a4eae0 100644 (file)
--- a/arch/arm64/boot/dts/qcom/sm8650.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8650.dtsi
@@ -15,6 +15,7 @@
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/interconnect/qcom,icc.h>
 #include <dt-bindings/interconnect/qcom,sm8650-rpmh.h>
+#include <dt-bindings/interconnect/qcom,osm-l3.h>
 #include <dt-bindings/interrupt-controller/arm-gic.h>
 #include <dt-bindings/mailbox/qcom-ipcc.h>
 #include <dt-bindings/phy/phy-qcom-qmp.h>
@@ -85,6 +86,13 @@
 
                        qcom,freq-domain = <&cpufreq_hw 0>;
 
+                       interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+                                        &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>,
+                                       <&mc_virt MASTER_LLCC QCOM_ICC_TAG_ACTIVE_ONLY
+                                        &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>,
+                                       <&epss_l3 MASTER_EPSS_L3_APPS
+                                        &epss_l3 SLAVE_EPSS_L3_SHARED>;
+
                        #cooling-cells = <2>;
 
                        l2_0: l2-cache {
@@ -118,6 +126,13 @@
 
                        qcom,freq-domain = <&cpufreq_hw 0>;
 
+                       interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+                                        &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>,
+                                       <&mc_virt MASTER_LLCC QCOM_ICC_TAG_ACTIVE_ONLY
+                                        &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>,
+                                       <&epss_l3 MASTER_EPSS_L3_APPS
+                                        &epss_l3 SLAVE_EPSS_L3_SHARED>;
+
                        #cooling-cells = <2>;
                };
 
@@ -138,6 +153,13 @@
 
                        qcom,freq-domain = <&cpufreq_hw 3>;
 
+                       interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+                                        &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>,
+                                       <&mc_virt MASTER_LLCC QCOM_ICC_TAG_ACTIVE_ONLY
+                                        &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>,
+                                       <&epss_l3 MASTER_EPSS_L3_APPS
+                                        &epss_l3 SLAVE_EPSS_L3_SHARED>;
+
                        #cooling-cells = <2>;
 
                        l2_200: l2-cache {
@@ -165,6 +187,13 @@
 
                        qcom,freq-domain = <&cpufreq_hw 3>;
 
+                       interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+                                        &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>,
+                                       <&mc_virt MASTER_LLCC QCOM_ICC_TAG_ACTIVE_ONLY
+                                        &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>,
+                                       <&epss_l3 MASTER_EPSS_L3_APPS
+                                        &epss_l3 SLAVE_EPSS_L3_SHARED>;
+
                        #cooling-cells = <2>;
                };
 
@@ -185,6 +214,13 @@
 
                        qcom,freq-domain = <&cpufreq_hw 3>;
 
+                       interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+                                        &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>,
+                                       <&mc_virt MASTER_LLCC QCOM_ICC_TAG_ACTIVE_ONLY
+                                        &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>,
+                                       <&epss_l3 MASTER_EPSS_L3_APPS
+                                        &epss_l3 SLAVE_EPSS_L3_SHARED>;
+
                        #cooling-cells = <2>;
 
                        l2_400: l2-cache {
@@ -212,6 +248,13 @@
 
                        qcom,freq-domain = <&cpufreq_hw 1>;
 
+                       interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+                                        &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>,
+                                       <&mc_virt MASTER_LLCC QCOM_ICC_TAG_ACTIVE_ONLY
+                                        &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>,
+                                       <&epss_l3 MASTER_EPSS_L3_APPS
+                                        &epss_l3 SLAVE_EPSS_L3_SHARED>;
+
                        #cooling-cells = <2>;
 
                        l2_500: l2-cache {
@@ -239,6 +282,13 @@
 
                        qcom,freq-domain = <&cpufreq_hw 1>;
 
+                       interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+                                        &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>,
+                                       <&mc_virt MASTER_LLCC QCOM_ICC_TAG_ACTIVE_ONLY
+                                        &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>,
+                                       <&epss_l3 MASTER_EPSS_L3_APPS
+                                        &epss_l3 SLAVE_EPSS_L3_SHARED>;
+
                        #cooling-cells = <2>;
 
                        l2_600: l2-cache {
@@ -266,6 +316,13 @@
 
                        qcom,freq-domain = <&cpufreq_hw 2>;
 
+                       interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+                                        &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>,
+                                       <&mc_virt MASTER_LLCC QCOM_ICC_TAG_ACTIVE_ONLY
+                                        &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>,
+                                       <&epss_l3 MASTER_EPSS_L3_APPS
+                                        &epss_l3 SLAVE_EPSS_L3_SHARED>;
+
                        #cooling-cells = <2>;
 
                        l2_700: l2-cache {