]> git.ipfire.org Git - thirdparty/kernel/stable.git/commitdiff
drm/msm/dpu: drop the regdma configuration
authorDmitry Baryshkov <dmitry.baryshkov@linaro.org>
Thu, 20 Apr 2023 22:25:57 +0000 (01:25 +0300)
committerGreg Kroah-Hartman <gregkh@linuxfoundation.org>
Wed, 13 Sep 2023 07:48:15 +0000 (09:48 +0200)
[ Upstream commit 078f766e165097c03629cc1a8f7e1a7b7ec0e79b ]

The regdma is currently not used by the current driver. We have no way
to practically verify that the regdma is described correctly. Drop it
now.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Marijn Suijten <marijn.suijten@somainline.org>
Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com>
Patchwork: https://patchwork.freedesktop.org/patch/533148/
Link: https://lore.kernel.org/r/20230420222558.1208887-1-dmitry.baryshkov@linaro.org
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Stable-dep-of: 42d0d253ed03 ("drm/msm/dpu: increase memtype count to 16 for sm8550")
Signed-off-by: Sasha Levin <sashal@kernel.org>
12 files changed:
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h

index ff9ccf72a4bf9a046a64656d94c1adc04f05f947..6560eeef00143ed4711b4f7fcd08acd99adf2d40 100644 (file)
@@ -195,7 +195,6 @@ const struct dpu_mdss_cfg dpu_msm8998_cfg = {
        .intf = msm8998_intf,
        .vbif_count = ARRAY_SIZE(msm8998_vbif),
        .vbif = msm8998_vbif,
-       .reg_dma_count = 0,
        .perf = &msm8998_perf_data,
        .mdss_irqs = BIT(MDP_SSPP_TOP0_INTR) | \
                     BIT(MDP_SSPP_TOP0_INTR2) | \
index 5b9b3b99f1b5f99ca80076e943ee083980d61085..84159f8cbdaeb36a691887f264f4c2f7a174094b 100644 (file)
@@ -193,8 +193,6 @@ const struct dpu_mdss_cfg dpu_sdm845_cfg = {
        .intf = sdm845_intf,
        .vbif_count = ARRAY_SIZE(sdm845_vbif),
        .vbif = sdm845_vbif,
-       .reg_dma_count = 1,
-       .dma_cfg = &sdm845_regdma,
        .perf = &sdm845_perf_data,
        .mdss_irqs = BIT(MDP_SSPP_TOP0_INTR) | \
                     BIT(MDP_SSPP_TOP0_INTR2) | \
index 074ba54d420f4469b1019850f227ed294f64d01a..266c525f8daaf29352f07401782bab24bfc84975 100644 (file)
@@ -220,8 +220,6 @@ const struct dpu_mdss_cfg dpu_sm8150_cfg = {
        .intf = sm8150_intf,
        .vbif_count = ARRAY_SIZE(sdm845_vbif),
        .vbif = sdm845_vbif,
-       .reg_dma_count = 1,
-       .dma_cfg = &sm8150_regdma,
        .perf = &sm8150_perf_data,
        .mdss_irqs = BIT(MDP_SSPP_TOP0_INTR) | \
                     BIT(MDP_SSPP_TOP0_INTR2) | \
index 0540d218108576c0f8934ad31a095f8c34a6c280..76c5745c2fa1f359d0521de5d6ab4adda34fea15 100644 (file)
@@ -198,8 +198,6 @@ const struct dpu_mdss_cfg dpu_sc8180x_cfg = {
        .intf = sc8180x_intf,
        .vbif_count = ARRAY_SIZE(sdm845_vbif),
        .vbif = sdm845_vbif,
-       .reg_dma_count = 1,
-       .dma_cfg = &sm8150_regdma,
        .perf = &sc8180x_perf_data,
        .mdss_irqs = BIT(MDP_SSPP_TOP0_INTR) | \
                     BIT(MDP_SSPP_TOP0_INTR2) | \
index b3284de35b8fa6d7413c1f709810cbc751f3a174..8660d04d0f5893a324c11f06255996c676ad4663 100644 (file)
@@ -228,8 +228,6 @@ const struct dpu_mdss_cfg dpu_sm8250_cfg = {
        .vbif = sdm845_vbif,
        .wb_count = ARRAY_SIZE(sm8250_wb),
        .wb = sm8250_wb,
-       .reg_dma_count = 1,
-       .dma_cfg = &sm8250_regdma,
        .perf = &sm8250_perf_data,
        .mdss_irqs = BIT(MDP_SSPP_TOP0_INTR) | \
                     BIT(MDP_SSPP_TOP0_INTR2) | \
index 88c211876516a209cf1618e1629c20c7b5ad7233..9631116f99e9bb62a576824e12d98d7078a50f64 100644 (file)
@@ -147,8 +147,6 @@ const struct dpu_mdss_cfg dpu_sc7180_cfg = {
        .wb = sc7180_wb,
        .vbif_count = ARRAY_SIZE(sdm845_vbif),
        .vbif = sdm845_vbif,
-       .reg_dma_count = 1,
-       .dma_cfg = &sdm845_regdma,
        .perf = &sc7180_perf_data,
        .mdss_irqs = BIT(MDP_SSPP_TOP0_INTR) | \
                     BIT(MDP_SSPP_TOP0_INTR2) | \
index 4f6a965bcd90b187a99146d74bdc9f3c4ca32dd6..9e8d6632a1927adf2c0cdb3b9937c819a7512960 100644 (file)
@@ -211,8 +211,6 @@ const struct dpu_mdss_cfg dpu_sm8350_cfg = {
        .intf = sm8350_intf,
        .vbif_count = ARRAY_SIZE(sdm845_vbif),
        .vbif = sdm845_vbif,
-       .reg_dma_count = 1,
-       .dma_cfg = &sm8350_regdma,
        .perf = &sm8350_perf_data,
        .mdss_irqs = BIT(MDP_SSPP_TOP0_INTR) | \
                     BIT(MDP_SSPP_TOP0_INTR2) | \
index 706d0f13b598e53772eafeb1b6a455c2ee488dff..cb58b4ec97db4b37ef3726be7b974d19c33e62f5 100644 (file)
@@ -202,8 +202,6 @@ const struct dpu_mdss_cfg dpu_sc8280xp_cfg = {
        .intf = sc8280xp_intf,
        .vbif_count = ARRAY_SIZE(sdm845_vbif),
        .vbif = sdm845_vbif,
-       .reg_dma_count = 1,
-       .dma_cfg = &sc8280xp_regdma,
        .perf = &sc8280xp_perf_data,
        .mdss_irqs = BIT(MDP_SSPP_TOP0_INTR) | \
                     BIT(MDP_SSPP_TOP0_INTR2) | \
index 8bd4bb97e639c24d5e34d3a7da502dd66e5dc5f4..905b403ffb0fb9a63126e785eaf0bc8d50f4763b 100644 (file)
@@ -219,8 +219,6 @@ const struct dpu_mdss_cfg dpu_sm8450_cfg = {
        .intf = sm8450_intf,
        .vbif_count = ARRAY_SIZE(sdm845_vbif),
        .vbif = sdm845_vbif,
-       .reg_dma_count = 1,
-       .dma_cfg = &sm8450_regdma,
        .perf = &sm8450_perf_data,
        .mdss_irqs = BIT(MDP_SSPP_TOP0_INTR) | \
                     BIT(MDP_SSPP_TOP0_INTR2) | \
index d0ab351b6a8b934226fded7bdcf9db3ee30ac80a..be2f37728aa0cf0a15caaf8009d99f2c5a55e384 100644 (file)
@@ -224,8 +224,6 @@ const struct dpu_mdss_cfg dpu_sm8550_cfg = {
        .intf = sm8550_intf,
        .vbif_count = ARRAY_SIZE(sdm845_vbif),
        .vbif = sdm845_vbif,
-       .reg_dma_count = 1,
-       .dma_cfg = &sm8450_regdma,
        .perf = &sm8550_perf_data,
        .mdss_irqs = BIT(MDP_SSPP_TOP0_INTR) | \
                     BIT(MDP_SSPP_TOP0_INTR2) | \
index 0b604f31197bb5548747084e24f5732128b5d250..fc9d2c56d0e1109146aace02d6a22c68e6973ca0 100644 (file)
@@ -642,46 +642,6 @@ static const struct dpu_vbif_cfg sdm845_vbif[] = {
        },
 };
 
-static const struct dpu_reg_dma_cfg sc8280xp_regdma = {
-       .base = 0x0,
-       .version = 0x00020000,
-       .trigger_sel_off = 0x119c,
-       .xin_id = 7,
-       .clk_ctrl = DPU_CLK_CTRL_REG_DMA,
-};
-
-static const struct dpu_reg_dma_cfg sdm845_regdma = {
-       .base = 0x0, .version = 0x1, .trigger_sel_off = 0x119c
-};
-
-static const struct dpu_reg_dma_cfg sm8150_regdma = {
-       .base = 0x0, .version = 0x00010001, .trigger_sel_off = 0x119c
-};
-
-static const struct dpu_reg_dma_cfg sm8250_regdma = {
-       .base = 0x0,
-       .version = 0x00010002,
-       .trigger_sel_off = 0x119c,
-       .xin_id = 7,
-       .clk_ctrl = DPU_CLK_CTRL_REG_DMA,
-};
-
-static const struct dpu_reg_dma_cfg sm8350_regdma = {
-       .base = 0x400,
-       .version = 0x00020000,
-       .trigger_sel_off = 0x119c,
-       .xin_id = 7,
-       .clk_ctrl = DPU_CLK_CTRL_REG_DMA,
-};
-
-static const struct dpu_reg_dma_cfg sm8450_regdma = {
-       .base = 0x0,
-       .version = 0x00020000,
-       .trigger_sel_off = 0x119c,
-       .xin_id = 7,
-       .clk_ctrl = DPU_CLK_CTRL_REG_DMA,
-};
-
 /*************************************************************
  * PERF data config
  *************************************************************/
index 71584cd56fd759c2a2a6a792f7d76c42f2babb2e..8d62c21b051a8f70a547a485c36a6357efe9b54c 100644 (file)
@@ -720,21 +720,6 @@ struct dpu_vbif_cfg {
        u32 memtype_count;
        u32 memtype[MAX_XIN_COUNT];
 };
-/**
- * struct dpu_reg_dma_cfg - information of lut dma blocks
- * @id                 enum identifying this block
- * @base               register offset of this block
- * @features           bit mask identifying sub-blocks/features
- * @version            version of lutdma hw block
- * @trigger_sel_off    offset to trigger select registers of lutdma
- */
-struct dpu_reg_dma_cfg {
-       DPU_HW_BLK_INFO;
-       u32 version;
-       u32 trigger_sel_off;
-       u32 xin_id;
-       enum dpu_clk_ctrl_type clk_ctrl;
-};
 
 /**
  * Define CDP use cases
@@ -850,9 +835,6 @@ struct dpu_mdss_cfg {
        u32 wb_count;
        const struct dpu_wb_cfg *wb;
 
-       u32 reg_dma_count;
-       const struct dpu_reg_dma_cfg *dma_cfg;
-
        u32 ad_count;
 
        u32 dspp_count;