-From 4e7d472b61625804f585035a54364a6620bf803a Mon Sep 17 00:00:00 2001
+From be29cd958f5393004a24cd7b5b1da88dd90a651b Mon Sep 17 00:00:00 2001
From: Jonas Karlman <jonas@kwiboo.se>
-Date: Wed, 23 Jul 2025 12:23:00 +0000
-Subject: [PATCH] phy: rockchip: inno-usb2: Simplify rockchip,usbgrf handling
+Date: Tue, 5 May 2026 19:04:07 +0200
+Subject: [PATCH] phy: rockchip: inno-usb2: Simplify rockchip,usbgrf
+ handling
The logic to decide if usbgrf or grf should be used is more complex than
it needs to be. For RK3568, RV1108 and soon RK3528 we can assign the
because of an addition of a of_property_present() check.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
+Link: https://patch.msgid.link/20260505170410.3265305-3-heiko@sntech.de
+Signed-off-by: Vinod Koul <vkoul@kernel.org>
---
drivers/phy/rockchip/phy-rockchip-inno-usb2.c | 68 +++++--------------
1 file changed, 18 insertions(+), 50 deletions(-)
-From 6b767459cf9295f10ee95b8ab78fbce5991132ed Mon Sep 17 00:00:00 2001
+From 2775541de0580ab1cd077dfef710e6316563d567 Mon Sep 17 00:00:00 2001
From: Jonas Karlman <jonas@kwiboo.se>
-Date: Wed, 23 Jul 2025 12:23:02 +0000
+Date: Tue, 5 May 2026 19:04:09 +0200
Subject: [PATCH] phy: rockchip: inno-usb2: Add clkout_ctl_phy support
The 480m clk is controlled using regs in the PHY address space and not
clk on these SoCs.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
+Link: https://patch.msgid.link/20260505170410.3265305-5-heiko@sntech.de
+Signed-off-by: Vinod Koul <vkoul@kernel.org>
---
drivers/phy/rockchip/phy-rockchip-inno-usb2.c | 47 +++++++++++++++----
1 file changed, 38 insertions(+), 9 deletions(-)
-From 8faac4ef6206a1c771e1c016e205dcee8164d618 Mon Sep 17 00:00:00 2001
+From 864b3617df827865a95a06f06f09a8d57a795b91 Mon Sep 17 00:00:00 2001
From: Jianwei Zheng <jianwei.zheng@rock-chips.com>
-Date: Wed, 23 Jul 2025 12:23:03 +0000
+Date: Tue, 5 May 2026 19:04:10 +0200
Subject: [PATCH] phy: rockchip: inno-usb2: Add support for RK3528
The RK3528 has a single USB2PHY with a otg and host port.
which uses dwc3 controller to improve fs/ls devices compatibility with
long cables.
-This is based on vendor kernel linux-stan-6.1-rkr5 tag.
+Undocumented magic-values are based on the linux-stan-6.1-rkr5 tag of
+the vendor-kernel.
Signed-off-by: Jianwei Zheng <jianwei.zheng@rock-chips.com>
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
+Link: https://patch.msgid.link/20260505170410.3265305-6-heiko@sntech.de
+Signed-off-by: Vinod Koul <vkoul@kernel.org>
---
- drivers/phy/rockchip/phy-rockchip-inno-usb2.c | 74 +++++++++++++++++++
- 1 file changed, 74 insertions(+)
+ drivers/phy/rockchip/phy-rockchip-inno-usb2.c | 84 +++++++++++++++++++
+ 1 file changed, 84 insertions(+)
--- a/drivers/phy/rockchip/phy-rockchip-inno-usb2.c
+++ b/drivers/phy/rockchip/phy-rockchip-inno-usb2.c
-@@ -1511,6 +1511,28 @@ static int rk3128_usb2phy_tuning(struct
+@@ -1511,6 +1511,38 @@ static int rk3128_usb2phy_tuning(struct
BIT(2) << BIT_WRITEABLE_SHIFT | 0);
}
+static int rk3528_usb2phy_tuning(struct rockchip_usb2phy *rphy)
+{
-+ int ret = 0;
++ int ret;
+
+ /* Turn off otg port differential receiver in suspend mode */
-+ ret |= regmap_write(rphy->phy_base, 0x30, BIT(18) | 0x0000);
++ ret = regmap_write(rphy->phy_base, 0x30, BIT(18) | 0x0000);
++ if (ret)
++ return ret;
+
+ /* Turn off host port differential receiver in suspend mode */
-+ ret |= regmap_write(rphy->phy_base, 0x430, BIT(18) | 0x0000);
++ ret = regmap_write(rphy->phy_base, 0x430, BIT(18) | 0x0000);
++ if (ret)
++ return ret;
+
+ /* Set otg port HS eye height to 400mv (default is 450mv) */
-+ ret |= regmap_write(rphy->phy_base, 0x30, GENMASK(22, 20) | 0x0000);
++ ret = regmap_write(rphy->phy_base, 0x30, GENMASK(22, 20) | 0x0000);
++ if (ret)
++ return ret;
+
+ /* Set host port HS eye height to 400mv (default is 450mv) */
-+ ret |= regmap_write(rphy->phy_base, 0x430, GENMASK(22, 20) | 0x0000);
++ ret = regmap_write(rphy->phy_base, 0x430, GENMASK(22, 20) | 0x0000);
++ if (ret)
++ return ret;
+
+ /* Choose the Tx fs/ls data as linestate from TX driver for otg port */
-+ ret |= regmap_write(rphy->phy_base, 0x94, GENMASK(22, 19) | 0x0018);
++ ret = regmap_write(rphy->phy_base, 0x94, GENMASK(22, 19) | 0x0018);
++ if (ret)
++ return ret;
+
-+ return ret;
++ return 0;
+}
+
static int rk3576_usb2phy_tuning(struct rockchip_usb2phy *rphy)
{
int ret;
-@@ -1924,6 +1946,57 @@ static const struct rockchip_usb2phy_cfg
+@@ -1924,6 +1956,57 @@ static const struct rockchip_usb2phy_cfg
{ /* sentinel */ }
};
static const struct rockchip_usb2phy_cfg rk3562_phy_cfgs[] = {
{
.reg = 0xff740000,
-@@ -2291,6 +2364,7 @@ static const struct of_device_id rockchi
+@@ -2291,6 +2374,7 @@ static const struct of_device_id rockchi
{ .compatible = "rockchip,rk3328-usb2phy", .data = &rk3328_phy_cfgs },
{ .compatible = "rockchip,rk3366-usb2phy", .data = &rk3366_phy_cfgs },
{ .compatible = "rockchip,rk3399-usb2phy", .data = &rk3399_phy_cfgs },
-From a41519d8b438adc154debd433c3a1436ebb93a10 Mon Sep 17 00:00:00 2001
+From 5f3ae9b12a6c523992a7216bbc4420ac33450b79 Mon Sep 17 00:00:00 2001
From: Jonas Karlman <jonas@kwiboo.se>
-Date: Wed, 23 Jul 2025 12:23:05 +0000
+Date: Fri, 29 May 2026 21:03:51 +0200
Subject: [PATCH] arm64: dts: rockchip: Add USB nodes for RK3528
-Rockchip RK3528 has one USB 3.0 DWC3 controller, a USB 2.0 EHCI/OHCI
-controller and uses a USB2PHY for USB 2.0. The DWC3 controller may also
-use the Naneng Combo PHY for USB3.
+Rockchip RK3528 has one USB 3.0 DWC3 controller and oneUSB 2.0 EHCI/OHCI
+controller and uses an Innosilicon-USB2PHY for USB 2.0. The DWC3
+controller additionally uses the Naneng Combo PHY for USB3.
Add device tree nodes to describe these USB controllers along with the
USB 2.0 PHYs.
+[moved snps,dis_u2_susphy_quirk here from individual boards,
+ describe both usb2+3 default phy connections, usb2 boards can override]
+
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+Link: https://patch.msgid.link/20260529190355.4148175-2-heiko@sntech.de
---
- arch/arm64/boot/dts/rockchip/rk3528.dtsi | 77 ++++++++++++++++++++++++
- 1 file changed, 77 insertions(+)
+ arch/arm64/boot/dts/rockchip/rk3528.dtsi | 80 ++++++++++++++++++++++++
+ 1 file changed, 80 insertions(+)
--- a/arch/arm64/boot/dts/rockchip/rk3528.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3528.dtsi
-@@ -336,6 +336,30 @@
+@@ -336,6 +336,33 @@
};
};
+ power-domains = <&power RK3528_PD_VPU>;
+ resets = <&cru SRST_A_USB3OTG>;
+ dr_mode = "otg";
++ phys = <&usb2phy_otg>, <&combphy PHY_TYPE_USB3>;
++ phy-names = "usb2-phy", "usb3-phy";
+ phy_type = "utmi_wide";
+ snps,dis_enblslpm_quirk;
+ snps,dis_rxdet_inp3_quirk;
+ snps,dis-u1-entry-quirk;
+ snps,dis-u2-entry-quirk;
+ snps,dis-u2-freeclk-exists-quirk;
++ snps,dis_u2_susphy_quirk;
+ snps,parkmode-disable-hs-quirk;
+ snps,parkmode-disable-ss-quirk;
+ status = "disabled";
gic: interrupt-controller@fed01000 {
compatible = "arm,gic-400";
reg = <0x0 0xfed01000 0 0x1000>,
-@@ -349,6 +373,30 @@
+@@ -349,6 +376,30 @@
#interrupt-cells = <3>;
};
qos_crypto_a: qos@ff200000 {
compatible = "rockchip,rk3528-qos", "syscon";
reg = <0x0 0xff200000 0x0 0x20>;
-@@ -1275,6 +1323,35 @@
+@@ -1273,6 +1324,35 @@
rockchip,pipe-phy-grf = <&pipe_phy_grf>;
status = "disabled";
};
-From d78af3aa816344d6e76dd77fbaf410fcbfa58bef Mon Sep 17 00:00:00 2001
+From e897bcf81dd920bf80ace6d98ec6f9645c5b50f2 Mon Sep 17 00:00:00 2001
From: Jonas Karlman <jonas@kwiboo.se>
-Date: Wed, 23 Jul 2025 12:23:06 +0000
+Date: Fri, 29 May 2026 21:03:52 +0200
Subject: [PATCH] arm64: dts: rockchip: Enable USB 2.0 ports on Radxa E20C
-The Radxa E20C has one USB2.0 Type-A HOST port and one USB2.0 Type-C OTG
-port.
+The Radxa E20C has one USB2.0 Type-A HOST port and one USB2.0 Type-C port.
+
+The Type-C port is conneced to a FE1.1s_QFN USB hub on the board, with its
+ports being connected to the XHCI usb controller and an usb-uart bridge.
+
+This also means, the XHCI controller can only be used in device-mode.
Add support for using the USB 2.0 ports on Radxa E20C.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
+[set xhci to peripheral and add comment about the outward-facing hub]
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+Link: https://patch.msgid.link/20260529190355.4148175-3-heiko@sntech.de
---
- .../boot/dts/rockchip/rk3528-radxa-e20c.dts | 48 +++++++++++++++++++
- 1 file changed, 48 insertions(+)
+ .../boot/dts/rockchip/rk3528-radxa-e20c.dts | 60 +++++++++++++++++++
+ 1 file changed, 60 insertions(+)
--- a/arch/arm64/boot/dts/rockchip/rk3528-radxa-e20c.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3528-radxa-e20c.dts
-@@ -136,6 +136,18 @@
+@@ -134,6 +134,18 @@
regulator-max-microvolt = <5000000>;
};
vccio_sd: regulator-vccio-sd {
compatible = "regulator-gpio";
gpios = <&gpio4 RK_PB6 GPIO_ACTIVE_HIGH>;
-@@ -275,6 +287,12 @@
+@@ -273,6 +285,12 @@
rockchip,pins = <4 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
};
&pwm1 {
-@@ -322,3 +340,33 @@
+@@ -320,3 +338,45 @@
pinctrl-0 = <&uart0m0_xfer>;
status = "okay";
};
+ status = "okay";
+};
+
++/*
++ * The usb controller can only work in peripheral mode, as it is
++ * connected to one of the ports of an outward-facing usb hub.
++ *
++ * type_c-port (hub-input)
++ * |
++ * usb-hub
++ * | |
++ * uart-usb usb-host0
++ * |
++ * uart0
++ */
+&usb_host0_xhci {
++ dr_mode = "peripheral";
+ extcon = <&usb2phy>;
+ maximum-speed = "high-speed";
+ phys = <&usb2phy_otg>;
+ phy-names = "usb2-phy";
-+ snps,dis_u2_susphy_quirk;
+ status = "okay";
+};
+
timer {
compatible = "arm,armv8-timer";
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
-@@ -689,6 +739,7 @@
+@@ -692,6 +742,7 @@
assigned-clock-rates = <297000000>, <300000000>;
clocks = <&cru ACLK_GPU_MALI>, <&scmi_clk SCMI_CLK_GPU>;
clock-names = "bus", "core";
interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>,
-@@ -1031,6 +1082,33 @@
+@@ -1034,6 +1085,33 @@
status = "disabled";
};
projects / thirdparty / openwrt.git / commitdiff
