]> git.ipfire.org Git - thirdparty/gcc.git/commitdiff
mips.c (mips_output_division): Use the division instruction to fill the delay slot...
authorRichard Sandiford <rsandifo@redhat.com>
Mon, 1 Mar 2004 18:17:35 +0000 (18:17 +0000)
committerRichard Sandiford <rsandifo@gcc.gnu.org>
Mon, 1 Mar 2004 18:17:35 +0000 (18:17 +0000)
* config/mips/mips.c (mips_output_division): Use the division
instruction to fill the delay slot of a zero check.
(mips_idiv_insns): Adjust accordingly.

From-SVN: r78712

gcc/ChangeLog
gcc/config/mips/mips.c

index 266145c430c5f932676cdb49a4bbd68cdcdffa45..512467ba5276c74167897e33d6430e45b7966bb9 100644 (file)
@@ -1,3 +1,9 @@
+2004-03-01  Richard Sandiford  <rsandifo@redhat.com>
+
+       * config/mips/mips.c (mips_output_division): Use the division
+       instruction to fill the delay slot of a zero check.
+       (mips_idiv_insns): Adjust accordingly.
+
 2004-03-01  Nathanael Nerode  <neroden@gcc.gnu.org>
 
        * config.gcc: Create a default tmake_file for linux, and use
index 8fdd97918d81639391a259c0f1adb2c1377059b7..c200af7f1509a1535cbfae69f80775e73e12eb40 100644 (file)
@@ -1359,12 +1359,7 @@ mips_idiv_insns (void)
 
   count = 1;
   if (TARGET_CHECK_ZERO_DIV)
-    {
-      if (TARGET_MIPS16)
-       count += 2;
-      else
-       count += 3;
-    }
+    count += 2;
   if (TARGET_FIX_R4000)
     count++;
   return count;
@@ -9225,16 +9220,22 @@ mips_output_conditional_branch (rtx insn, rtx *operands, int two_operands_p,
 const char *
 mips_output_division (const char *division, rtx *operands)
 {
-  const char *s = division;
+  const char *s;
 
+  s = division;
   if (TARGET_CHECK_ZERO_DIV)
     {
-      output_asm_insn (s, operands);
-
       if (TARGET_MIPS16)
-       s = "bnez\t%2,1f\n\tbreak\t7\n1:";
+       {
+         output_asm_insn (s, operands);
+         s = "bnez\t%2,1f\n\tbreak\t7\n1:";
+       }
       else
-       s = "bne\t%2,%.,1f%#\n\tbreak\t7\n1:";
+       {
+         output_asm_insn ("%(bne\t%2,%.,1f", operands);
+         output_asm_insn (s, operands);
+         s = "break\t7%)\n1:";
+       }
     }
   if (TARGET_FIX_R4000)
     {