smp2p-adsp {
compatible = "qcom,smp2p";
qcom,smem = <443>, <429>;
- interrupts = <GIC_SPI 172 IRQ_TYPE_EDGE_RISING>;
+ interrupts = <GIC_SPI 172 IRQ_TYPE_EDGE_RISING 0>;
/* On this platform, bit 26 (normally SLPI) is repurposed for ADSP */
mboxes = <&apss_shared 26>;
smp2p-cdsp {
compatible = "qcom,smp2p";
qcom,smem = <94>, <432>;
- interrupts = <GIC_SPI 576 IRQ_TYPE_EDGE_RISING>;
+ interrupts = <GIC_SPI 576 IRQ_TYPE_EDGE_RISING 0>;
mboxes = <&apss_shared 6>;
qcom,local-pid = <0>;
"cqhci",
"ice";
- interrupts = <GIC_SPI 641 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 644 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 641 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 644 IRQ_TYPE_LEVEL_HIGH 0>;
interrupt-names = "hc_irq",
"pwr_irq";
compatible = "qcom,qcs615-gpi-dma", "qcom,sdm845-gpi-dma";
reg = <0x0 0x800000 0x0 0x60000>;
#dma-cells = <3>;
- interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH 0>;
dma-channels = <8>;
dma-channel-mask = <0xf>;
iommus = <&apps_smmu 0xd6 0x0>;
clock-names = "se";
pinctrl-0 = <&qup_uart0_tx>, <&qup_uart0_rx>;
pinctrl-names = "default";
- interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH 0>;
interconnects = <&aggre1_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
reg = <0x0 0x884000 0x0 0x4000>;
#address-cells = <1>;
#size-cells = <0>;
- interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
clock-names = "se";
pinctrl-0 = <&qup_i2c1_data_clk>;
reg = <0x0 0x888000 0x0 0x4000>;
#address-cells = <1>;
#size-cells = <0>;
- interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
clock-names = "se";
pinctrl-0 = <&qup_i2c2_data_clk>;
spi2: spi@888000 {
compatible = "qcom,geni-spi";
reg = <0x0 0x00888000 0x0 0x4000>;
- interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
clock-names = "se";
pinctrl-0 = <&qup_spi2_data_clk>, <&qup_spi2_cs>;
uart2: serial@888000 {
compatible = "qcom,geni-uart";
reg = <0x0 0x00888000 0x0 0x4000>;
- interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
clock-names = "se";
pinctrl-0 = <&qup_uart2_cts>, <&qup_uart2_rts>,
reg = <0x0 0x88c000 0x0 0x4000>;
#address-cells = <1>;
#size-cells = <0>;
- interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
clock-names = "se";
pinctrl-0 = <&qup_i2c3_data_clk>;
compatible = "qcom,qcs615-gpi-dma", "qcom,sdm845-gpi-dma";
reg = <0x0 0xa00000 0x0 0x60000>;
#dma-cells = <3>;
- interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH 0>;
dma-channels = <8>;
dma-channel-mask = <0xf>;
iommus = <&apps_smmu 0x376 0x0>;
clock-names = "se";
pinctrl-0 = <&qup_i2c4_data_clk>;
pinctrl-names = "default";
- interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH 0>;
#address-cells = <1>;
#size-cells = <0>;
interconnects = <&aggre1_noc MASTER_BLSP_1 QCOM_ICC_TAG_ALWAYS
clock-names = "se";
pinctrl-0 = <&qup_spi4_data_clk>, <&qup_spi4_cs>;
pinctrl-names = "default";
- interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH 0>;
#address-cells = <1>;
#size-cells = <0>;
interconnects = <&aggre1_noc MASTER_BLSP_1 QCOM_ICC_TAG_ALWAYS
pinctrl-0 = <&qup_uart4_cts>, <&qup_uart4_rts>,
<&qup_uart4_tx>, <&qup_uart4_rx>;
pinctrl-names = "default";
- interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH 0>;
interconnects = <&aggre1_noc MASTER_BLSP_1 QCOM_ICC_TAG_ALWAYS
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
clock-names = "se";
pinctrl-0 = <&qup_i2c5_data_clk>;
pinctrl-names = "default";
- interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH 0>;
#address-cells = <1>;
#size-cells = <0>;
interconnects = <&aggre1_noc MASTER_BLSP_1 QCOM_ICC_TAG_ALWAYS
clock-names = "se";
pinctrl-0 = <&qup_i2c6_data_clk>;
pinctrl-names = "default";
- interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH 0>;
#address-cells = <1>;
#size-cells = <0>;
interconnects = <&aggre1_noc MASTER_BLSP_1 QCOM_ICC_TAG_ALWAYS
clock-names = "se";
pinctrl-0 = <&qup_spi6_data_clk>, <&qup_spi6_cs>;
pinctrl-names = "default";
- interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH 0>;
#address-cells = <1>;
#size-cells = <0>;
interconnects = <&aggre1_noc MASTER_BLSP_1 QCOM_ICC_TAG_ALWAYS
pinctrl-0 = <&qup_uart6_cts>, <&qup_uart6_rts>,
<&qup_uart6_tx>, <&qup_uart6_rx>;
pinctrl-names = "default";
- interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH 0>;
interconnects = <&aggre1_noc MASTER_BLSP_1 QCOM_ICC_TAG_ALWAYS
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
clock-names = "se";
pinctrl-0 = <&qup_i2c7_data_clk>;
pinctrl-names = "default";
- interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH 0>;
#address-cells = <1>;
#size-cells = <0>;
interconnects = <&aggre1_noc MASTER_BLSP_1 QCOM_ICC_TAG_ALWAYS
clock-names = "se";
pinctrl-0 = <&qup_spi7_data_clk>, <&qup_spi7_cs>;
pinctrl-names = "default";
- interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH 0>;
#address-cells = <1>;
#size-cells = <0>;
interconnects = <&aggre1_noc MASTER_BLSP_1 QCOM_ICC_TAG_ALWAYS
pinctrl-0 = <&qup_uart7_cts>, <&qup_uart7_rts>,
<&qup_uart7_tx>, <&qup_uart7_rx>;
pinctrl-names = "default";
- interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH 0>;
interconnects = <&aggre1_noc MASTER_BLSP_1 QCOM_ICC_TAG_ALWAYS
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
linux,pci-domain = <0>;
num-lanes = <1>;
- interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH 0>;
interrupt-names = "msi0",
"msi1",
"msi2",
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 0x7>;
- interrupt-map = <0 0 0 1 &intc GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
- <0 0 0 2 &intc GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>,
- <0 0 0 3 &intc GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>,
- <0 0 0 4 &intc GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-map = <0 0 0 1 &intc GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH 0>,
+ <0 0 0 2 &intc GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH 0>,
+ <0 0 0 3 &intc GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH 0>,
+ <0 0 0 4 &intc GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&gcc GCC_PCIE_0_PIPE_CLK>,
<&gcc GCC_PCIE_0_AUX_CLK>,
reg-names = "std",
"ice";
- interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&gcc GCC_UFS_PHY_AXI_CLK>,
<&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
cryptobam: dma-controller@1dc4000 {
compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0";
reg = <0x0 0x01dc4000 0x0 0x24000>;
- interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH 0>;
#dma-cells = <1>;
qcom,ee = <0>;
qcom,controlled-remotely;
reg-names = "east",
"west",
"south";
- interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH 0>;
gpio-ranges = <&tlmm 0 0 124>;
gpio-controller;
#gpio-cells = <2>;
compatible = "qcom,qcs615-cdsp-pas", "qcom,sm8150-cdsp-pas";
reg = <0x0 0x08300000 0x0 0x4040>;
- interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>,
+ interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING 0>,
<&cdsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
<&cdsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
<&cdsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
status = "disabled";
glink-edge {
- interrupts = <GIC_SPI 574 IRQ_TYPE_EDGE_RISING>;
+ interrupts = <GIC_SPI 574 IRQ_TYPE_EDGE_RISING 0>;
mboxes = <&apss_shared 4>;
label = "cdsp";
qcom,remote-pid = <5>;
pmu@90b6300 {
compatible = "qcom,qcs615-cpu-bwmon", "qcom,sdm845-bwmon";
reg = <0x0 0x090b6300 0x0 0x600>;
- interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH 0>;
interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
&gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>;
pmu@90cd000 {
compatible = "qcom,qcs615-llcc-bwmon", "qcom,sc7280-llcc-bwmon";
reg = <0x0 0x090cd000 0x0 0x1000>;
- interrupts = <GIC_SPI 667 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 667 IRQ_TYPE_LEVEL_HIGH 0>;
interconnects = <&mc_virt MASTER_LLCC QCOM_ICC_TAG_ACTIVE_ONLY
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>;
reg = <0x0 0x08804000 0x0 0x1000>;
reg-names = "hc";
- interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH 0>;
interrupt-names = "hc_irq",
"pwr_irq";
venus: video-codec@aa00000 {
compatible = "qcom,qcs615-venus", "qcom,sc7180-venus";
reg = <0x0 0x0aa00000 0x0 0x100000>;
- interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&videocc VIDEO_CC_VENUS_CTL_CORE_CLK>,
<&videocc VIDEO_CC_VENUS_AHB_CLK>,
<&gcc GCC_DISP_HF_AXI_CLK>,
<&dispcc DISP_CC_MDSS_MDP_CLK>;
- interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH 0>;
interrupt-controller;
#interrupt-cells = <1>;
aoss_qmp: power-management@c300000 {
compatible = "qcom,qcs615-aoss-qmp", "qcom,aoss-qmp";
reg = <0x0 0x0c300000 0x0 0x400>;
- interrupts = <GIC_SPI 389 IRQ_TYPE_EDGE_RISING>;
+ interrupts = <GIC_SPI 389 IRQ_TYPE_EDGE_RISING 0>;
mboxes = <&apss_shared 0>;
#clock-cells = <0>;
#global-interrupts = <1>;
dma-coherent;
- interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH 0>;
};
spmi_bus: spmi@c440000 {
compatible = "arm,gic-v3";
reg = <0x0 0x17a00000 0x0 0x10000>, /* GICD */
<0x0 0x17a60000 0x0 0x100000>; /* GICR * 8 */
- interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>;
#address-cells = <0>;
- #interrupt-cells = <3>;
+ #interrupt-cells = <4>;
interrupt-controller;
#redistributor-regions = <1>;
redistributor-stride = <0x0 0x20000>;
watchdog: watchdog@17c10000 {
compatible = "qcom,apss-wdt-qcs615", "qcom,kpss-wdt";
reg = <0x0 0x17c10000 0x0 0x1000>;
- interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&sleep_clk>;
};
reg = <0x17c21000 0x1000>,
<0x17c22000 0x1000>;
frame-number = <0>;
- interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH 0>;
};
frame@17c23000 {
reg = <0x17c23000 0x1000>;
frame-number = <1>;
- interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH 0>;
status = "disabled";
};
frame@17c25000 {
reg = <0x17c25000 0x1000>;
frame-number = <2>;
- interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH 0>;
status = "disabled";
};
frame@17c27000 {
reg = <0x17c27000 0x1000>;
frame-number = <3>;
- interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH 0>;
status = "disabled";
};
frame@17c29000 {
reg = <0x17c29000 0x1000>;
frame-number = <4>;
- interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH 0>;
status = "disabled";
};
frame@17c2b000 {
reg = <0x17c2b000 0x1000>;
frame-number = <5>;
- interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH 0>;
status = "disabled";
};
frame@17c2d000 {
reg = <0x17c2d000 0x1000>;
frame-number = <6>;
- interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH 0>;
status = "disabled";
};
};
"drv-1",
"drv-2";
- interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH 0>;
qcom,drv-id = <2>;
qcom,tcs-offset = <0xd00>;
<&gcc GCC_USB30_PRIM_MASTER_CLK>;
assigned-clock-rates = <19200000>, <200000000>;
- interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
- <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
+ interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH 0>,
+ <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH 0>,
<&pdc 9 IRQ_TYPE_EDGE_BOTH>,
<&pdc 8 IRQ_TYPE_EDGE_BOTH>,
<&pdc 6 IRQ_TYPE_LEVEL_HIGH>;
reg = <0x0 0x0a600000 0x0 0xcd00>;
iommus = <&apps_smmu 0x140 0x0>;
- interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH 0>;
phys = <&usb_1_hsphy>, <&usb_qmpphy>;
phy-names = "usb2-phy", "usb3-phy";
<&gcc GCC_USB20_SEC_MASTER_CLK>;
assigned-clock-rates = <19200000>, <200000000>;
- interrupts-extended = <&intc GIC_SPI 663 IRQ_TYPE_LEVEL_HIGH>,
- <&intc GIC_SPI 662 IRQ_TYPE_LEVEL_HIGH>,
+ interrupts-extended = <&intc GIC_SPI 663 IRQ_TYPE_LEVEL_HIGH 0>,
+ <&intc GIC_SPI 662 IRQ_TYPE_LEVEL_HIGH 0>,
<&pdc 11 IRQ_TYPE_EDGE_BOTH>,
<&pdc 10 IRQ_TYPE_EDGE_BOTH>;
interrupt-names = "pwr_event",
reg = <0x0 0x0a800000 0x0 0xcd00>;
iommus = <&apps_smmu 0xe0 0x0>;
- interrupts = <GIC_SPI 664 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 664 IRQ_TYPE_LEVEL_HIGH 0>;
phys = <&usb_hsphy_2>;
phy-names = "usb2-phy";
compatible = "qcom,qcs615-tsens", "qcom,tsens-v2";
reg = <0x0 0x0c263000 0x0 0x1000>,
<0x0 0x0c222000 0x0 0x1000>;
- interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH 0>;
interrupt-names = "uplow", "critical";
#qcom,sensors = <16>;
#thermal-sensor-cells = <1>;
compatible = "qcom,qcs615-adsp-pas", "qcom,sm8150-adsp-pas";
reg = <0x0 0x62400000 0x0 0x4040>;
- interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>,
+ interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING 0>,
<&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
<&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
<&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
status = "disabled";
glink_edge: glink-edge {
- interrupts = <GIC_SPI 170 IRQ_TYPE_EDGE_RISING>;
+ interrupts = <GIC_SPI 170 IRQ_TYPE_EDGE_RISING 0>;
mboxes = <&apss_shared 24>;
label = "lpass";
qcom,remote-pid = <2>;
arch_timer: timer {
compatible = "arm,armv8-timer";
- interrupts = <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
- <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
- <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
- <GIC_PPI 0 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
+ interrupts = <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW) 0>,
+ <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW) 0>,
+ <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW) 0>,
+ <GIC_PPI 0 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW) 0>;
};
thermal-zones {
projects / thirdparty / kernel / linux.git / commitdiff
