(umulsi3_highpart, const_umulsi3_highpart): New expander and matcher.

(smulsi3_highpart, const_smulsi3_highpart): Likewise.

From-SVN: r7593

diff --git a/gcc/config/m68k/m68k.md b/gcc/config/m68k/m68k.md
index e17752a8136458dc862731dcf1efb65519be2689..9e5494a4a81073a203e067e90519dc37e158ed54 100644 (file)
--- a/gcc/config/m68k/m68k.md
+++ b/gcc/config/m68k/m68k.md
@@ -2531,6 +2531,94 @@
    && INTVAL (operands[2]) >= -0x80000000"
   "muls%.l %2,%3:%0")
 
+(define_expand "umulsi3_highpart"
+  [(parallel
+    [(set (match_operand:SI 0 "register_operand" "")
+         (truncate:SI
+          (lshiftrt:DI
+           (mult:DI (zero_extend:DI (match_operand:SI 1 "register_operand" ""))
+                    (zero_extend:DI (match_operand:SI 2 "general_operand" "")))
+           (const_int 32))))
+     (clobber (match_dup 3))])]
+  "TARGET_68020"
+  "
+{
+  operands[3] = gen_reg_rtx (SImode);
+  if (CONSTANT_P (operands[2]))
+    {
+      /* We have to rearrange the operand order for the matching constraints.  */
+      emit_insn (gen_const_umulsi3_highpart (operands[0], operands[3],
+                                            operands[1], operands[2]));
+      DONE;
+    }
+}")
+
+(define_insn ""
+  [(set (match_operand:SI 0 "register_operand" "=r")
+       (truncate:SI
+        (lshiftrt:DI
+         (mult:DI (zero_extend:DI (match_operand:SI 2 "register_operand" "%1"))
+                  (zero_extend:DI (match_operand:SI 3 "nonimmediate_operand" "dm")))
+         (const_int 32))))
+   (clobber (match_operand:SI 1 "register_operand" "=d"))]
+  "TARGET_68020"
+  "mulu%.l %3,%0:%1")
+
+(define_insn "const_umulsi3_highpart"
+  [(set (match_operand:SI 0 "register_operand" "=r")
+       (truncate:SI
+        (lshiftrt:DI
+         (mult:DI (zero_extend:DI (match_operand:SI 2 "register_operand" "1"))
+                  (match_operand:DI 3 "immediate_operand" "i"))
+         (const_int 32))))
+   (clobber (match_operand:SI 1 "register_operand" "=d"))]
+  "TARGET_68020"
+  "mulu%.l %3,%0:%1")
+
+(define_expand "smulsi3_highpart"
+  [(parallel
+    [(set (match_operand:SI 0 "register_operand" "")
+         (truncate:SI
+          (lshiftrt:DI
+           (mult:DI (sign_extend:DI (match_operand:SI 1 "register_operand" ""))
+                    (sign_extend:DI (match_operand:SI 2 "general_operand" "")))
+           (const_int 32))))
+     (clobber (match_dup 3))])]
+  "TARGET_68020"
+  "
+{
+  operands[3] = gen_reg_rtx (SImode);
+  if (CONSTANT_P (operands[2]))
+    {
+      /* We have to rearrange the operand order for the matching constraints.  */
+      emit_insn (gen_const_smulsi3_highpart (operands[0], operands[3],
+                                            operands[1], operands[2]));
+      DONE;
+    }
+}")
+
+(define_insn ""
+  [(set (match_operand:SI 0 "register_operand" "=r")
+       (truncate:SI
+        (lshiftrt:DI
+         (mult:DI (sign_extend:DI (match_operand:SI 2 "register_operand" "%1"))
+                  (sign_extend:DI (match_operand:SI 3 "nonimmediate_operand" "dm")))
+         (const_int 32))))
+   (clobber (match_operand:SI 1 "register_operand" "=d"))]
+  "TARGET_68020"
+  "muls%.l %3,%0:%1")
+
+(define_insn "const_smulsi3_highpart"
+  [(set (match_operand:SI 0 "register_operand" "=r")
+       (truncate:SI
+        (lshiftrt:DI
+         (mult:DI (sign_extend:DI (match_operand:SI 2 "register_operand" "1"))
+                  (match_operand:DI 3 "immediate_operand" "i"))
+         (const_int 32))))
+   (clobber (match_operand:SI 1 "register_operand" "=d"))]
+  "TARGET_68020"
+  "muls%.l %3,%0:%1")
+
 (define_expand "muldf3"
   [(set (match_operand:DF 0 "general_operand" "")
        (mult:DF (match_operand:DF 1 "general_operand" "")