--- /dev/null
+/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */
+/dts-v1/;
+/plugin/;
+
+#include <dt-bindings/gpio/gpio.h>
+
+/ {
+ compatible = "mediatek,mt7981-rfb", "mediatek,mt7981";
+
+ fragment@0 {
+ target = <&gmac1>;
+ __overlay__ {
+ phy-mode = "2500base-x";
+ phy-handle = <&phy5>;
+ };
+ };
+
+ fragment@1 {
+ target = <&mdio_bus>;
+ __overlay__ {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reset-gpios = <&pio 14 GPIO_ACTIVE_LOW>;
+ reset-delay-us = <600>;
+ reset-post-delay-us = <20000>;
+
+ phy5: ethernet-phy@5 {
+ reg = <5>;
+ compatible = "ethernet-phy-ieee802.3-c45";
+ phy-mode = "2500base-x";
+ };
+ };
+ };
+};
--- /dev/null
+/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */
+/dts-v1/;
+/plugin/;
+
+#include <dt-bindings/gpio/gpio.h>
+
+/ {
+ compatible = "mediatek,mt7981-rfb", "mediatek,mt7981";
+
+ fragment@0 {
+ target = <&sw_p5>;
+ __overlay__ {
+ phy-mode = "2500base-x";
+ phy-handle = <&phy5>;
+ status = "okay";
+ };
+ };
+
+ fragment@1 {
+ target = <&mdio_bus>;
+ __overlay__ {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reset-gpios = <&pio 14 GPIO_ACTIVE_LOW>;
+ reset-delay-us = <600>;
+ reset-post-delay-us = <20000>;
+
+ phy5: ethernet-phy@5 {
+ reg = <5>;
+ compatible = "ethernet-phy-ieee802.3-c45";
+ phy-mode = "2500base-x";
+ };
+ };
+ };
+};
--- /dev/null
+/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */
+/dts-v1/;
+/plugin/;
+
+/ {
+ compatible = "mediatek,mt7981-rfb", "mediatek,mt7981";
+
+ fragment@0 {
+ target = <&chosen>;
+ rootdisk-spim-nand = <&ubi_rootdisk>;
+ };
+
+ fragment@1 {
+ target = <&spi0>;
+ __overlay__ {
+ status = "okay";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ spi_nand: spi_nand@1 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "spi-nand";
+ reg = <1>;
+ spi-max-frequency = <10000000>;
+ spi-tx-bus-width = <4>;
+ spi-rx-bus-width = <4>;
+
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ partition@0 {
+ label = "BL2";
+ reg = <0x00000 0x0100000>;
+ read-only;
+ };
+
+ partition@100000 {
+ label = "u-boot-env";
+ reg = <0x0100000 0x0080000>;
+ };
+
+ factory: partition@180000 {
+ label = "Factory";
+ reg = <0x180000 0x0200000>;
+ };
+
+ partition@380000 {
+ label = "FIP";
+ reg = <0x380000 0x0200000>;
+ };
+
+ partition@580000 {
+ label = "ubi";
+ reg = <0x580000 0x4000000>;
+ compatible = "linux,ubi";
+
+ volumes {
+ ubi_rootdisk: ubi-volume-fit {
+ volname = "fit";
+ };
+ };
+ };
+ };
+ };
+ };
+ };
+
+ fragment@2 {
+ target = <&wifi>;
+ __overlay__ {
+ mediatek,mtd-eeprom = <&factory 0x0>;
+ status = "okay";
+ };
+ };
+};
--- /dev/null
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright (C) 2022 MediaTek Inc.
+ * Author: Sam.Shih <sam.shih@mediatek.com>
+ */
+
+/dts-v1/;
+#include "mt7981b.dtsi"
+
+/ {
+ model = "MediaTek MT7981 RFB";
+ compatible = "mediatek,mt7981-rfb", "mediatek,mt7981";
+
+ aliases {
+ serial0 = &uart0;
+ };
+
+ chosen: chosen {
+ stdout-path = "serial0:115200n8";
+ bootargs-append = " root=/dev/fit0 rootwait";
+ };
+
+ memory {
+ reg = <0 0x40000000 0 0x20000000>;
+ };
+
+ reg_3p3v: regulator-3p3v {
+ compatible = "regulator-fixed";
+ regulator-name = "fixed-3.3V";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ reg_5v: regulator-5v {
+ compatible = "regulator-fixed";
+ regulator-name = "fixed-5V";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ gpio-keys {
+ compatible = "gpio-keys";
+ reset {
+ label = "reset";
+ linux,code = <KEY_RESTART>;
+ gpios = <&pio 1 GPIO_ACTIVE_LOW>;
+ };
+ wps {
+ label = "wps";
+ linux,code = <KEY_WPS_BUTTON>;
+ gpios = <&pio 0 GPIO_ACTIVE_HIGH>;
+ };
+ };
+};
+
+ð {
+ status = "okay";
+
+ gmac0: mac@0 {
+ compatible = "mediatek,eth-mac";
+ reg = <0>;
+ phy-mode = "2500base-x";
+
+ fixed-link {
+ speed = <2500>;
+ full-duplex;
+ pause;
+ };
+ };
+
+ gmac1: mac@1 {
+ compatible = "mediatek,eth-mac";
+ reg = <1>;
+ phy-mode = "gmii";
+ phy-handle = <&int_gbe_phy>;
+ };
+};
+
+&mdio_bus {
+ switch: switch@1f {
+ compatible = "mediatek,mt7531";
+ reg = <31>;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ interrupt-parent = <&pio>;
+ interrupts = <38 IRQ_TYPE_LEVEL_HIGH>;
+ reset-gpios = <&pio 5 GPIO_ACTIVE_HIGH>;
+ };
+};
+
+&crypto {
+ status = "okay";
+};
+
+&pio {
+ spi0_flash_pins: spi0-pins {
+ mux {
+ function = "spi";
+ groups = "spi0", "spi0_wp_hold";
+ };
+ conf-pu {
+ pins = "SPI0_CS", "SPI0_HOLD", "SPI0_WP";
+ drive-strength = <MTK_DRIVE_8mA>;
+ bias-pull-up = <MTK_PUPD_SET_R1R0_11>;
+ };
+ conf-pd {
+ pins = "SPI0_CLK", "SPI0_MOSI", "SPI0_MISO";
+ drive-strength = <MTK_DRIVE_8mA>;
+ bias-pull-down = <MTK_PUPD_SET_R1R0_11>;
+ };
+ };
+
+};
+
+&spi0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&spi0_flash_pins>;
+ cs-gpios = <0>, <0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+};
+
+&switch {
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ label = "lan1";
+ };
+
+ port@1 {
+ reg = <1>;
+ label = "lan2";
+ };
+
+ port@2 {
+ reg = <2>;
+ label = "lan3";
+ };
+
+ port@3 {
+ reg = <3>;
+ label = "lan4";
+ };
+
+ sw_p5: port@5 {
+ reg = <5>;
+ label = "lan5";
+ status = "disabled";
+ };
+
+ port@6 {
+ reg = <6>;
+ ethernet = <&gmac0>;
+ phy-mode = "2500base-x";
+
+ fixed-link {
+ speed = <2500>;
+ full-duplex;
+ pause;
+ };
+ };
+ };
+};
+
+&xhci {
+ vusb33-supply = <®_3p3v>;
+ vbus-supply = <®_5v>;
+ status = "okay";
+};
+
+&uart0 {
+ status = "okay";
+};
+
+&usb_phy {
+ status = "okay";
+};
+
+&watchdog {
+ status = "okay";
+};
--- /dev/null
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright (c) 2020 MediaTek Inc.
+ * Author: Sam.Shih <sam.shih@mediatek.com>
+ * Author: Jianhui Zhao <zhaojh329@gmail.com>
+ */
+
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/phy/phy.h>
+#include <dt-bindings/clock/mediatek,mt7981-clk.h>
+#include <dt-bindings/reset/mt7986-resets.h>
+#include <dt-bindings/pinctrl/mt65xx.h>
+#include <dt-bindings/leds/common.h>
+#include <dt-bindings/input/linux-event-codes.h>
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/mux/mux.h>
+
+/ {
+ compatible = "mediatek,mt7981";
+ interrupt-parent = <&gic>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu@0 {
+ compatible = "arm,cortex-a53";
+ reg = <0x0>;
+ device_type = "cpu";
+ enable-method = "psci";
+ };
+
+ cpu@1 {
+ compatible = "arm,cortex-a53";
+ reg = <0x1>;
+ device_type = "cpu";
+ enable-method = "psci";
+ };
+ };
+
+ ice: ice_debug {
+ compatible = "mediatek,mt7981-ice_debug", "mediatek,mt2701-ice_debug";
+ clocks = <&infracfg CLK_INFRA_DBG_CK>;
+ clock-names = "ice_dbg";
+ };
+
+ clk40m: oscillator-40m {
+ compatible = "fixed-clock";
+ clock-frequency = <40000000>;
+ clock-output-names = "clkxtal";
+ #clock-cells = <0>;
+ };
+
+ psci {
+ compatible = "arm,psci-0.2";
+ method = "smc";
+ };
+
+ fan: pwm-fan {
+ compatible = "pwm-fan";
+ /* cooling level (0, 1, 2, 3, 4, 5, 6, 7) : (0%/25%/37.5%/50%/62.5%/75%/87.5%/100% duty) */
+ cooling-levels = <0 63 95 127 159 191 223 255>;
+ #cooling-cells = <2>;
+ status = "disabled";
+ };
+
+ reg_3p3v: regulator-3p3v {
+ compatible = "regulator-fixed";
+ regulator-name = "fixed-3.3V";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ reserved-memory {
+ ranges;
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ /* 64 KiB reserved for ramoops/pstore */
+ ramoops@42ff0000 {
+ compatible = "ramoops";
+ reg = <0 0x42ff0000 0 0x10000>;
+ record-size = <0x1000>;
+ };
+
+ /* 192 KiB reserved for ARM Trusted Firmware (BL31) */
+ secmon_reserved: secmon@43000000 {
+ reg = <0 0x43000000 0 0x30000>;
+ no-map;
+ };
+
+ wmcpu_emi: wmcpu-reserved@47c80000 {
+ reg = <0 0x47c80000 0 0x100000>;
+ no-map;
+ };
+
+ wo_emi0: wo-emi@47d80000 {
+ reg = <0 0x47d80000 0 0x40000>;
+ no-map;
+ };
+
+ wo_data: wo-data@47dc0000 {
+ reg = <0 0x47dc0000 0 0x240000>;
+ no-map;
+ };
+ };
+
+ soc {
+ compatible = "simple-bus";
+ ranges;
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ gic: interrupt-controller@c000000 {
+ compatible = "arm,gic-v3";
+ reg = <0 0x0c000000 0 0x40000>, /* GICD */
+ <0 0x0c080000 0 0x200000>; /* GICR */
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-controller;
+ #interrupt-cells = <3>;
+ };
+
+ consys: consys@10000000 {
+ compatible = "mediatek,mt7981-consys";
+ reg = <0 0x10000000 0 0x8600000>;
+ memory-region = <&wmcpu_emi>;
+ };
+
+ infracfg: clock-controller@10001000 {
+ compatible = "mediatek,mt7981-infracfg", "syscon";
+ reg = <0 0x10001000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ wed_pcie: wed_pcie@10003000 {
+ compatible = "mediatek,wed_pcie";
+ reg = <0 0x10003000 0 0x10>;
+ };
+
+ topckgen: clock-controller@1001b000 {
+ compatible = "mediatek,mt7981-topckgen", "syscon";
+ reg = <0 0x1001b000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ watchdog: watchdog@1001c000 {
+ compatible = "mediatek,mt7986-wdt",
+ "mediatek,mt6589-wdt";
+ reg = <0 0x1001c000 0 0x1000>;
+ interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
+ #reset-cells = <1>;
+ status = "disabled";
+ };
+
+ apmixedsys: clock-controller@1001e000 {
+ compatible = "mediatek,mt7981-apmixedsys", "syscon";
+ reg = <0 0x1001e000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ pwm: pwm@10048000 {
+ compatible = "mediatek,mt7981-pwm";
+ reg = <0 0x10048000 0 0x1000>;
+ clocks = <&infracfg CLK_INFRA_PWM_STA>,
+ <&infracfg CLK_INFRA_PWM_HCK>,
+ <&infracfg CLK_INFRA_PWM1_CK>,
+ <&infracfg CLK_INFRA_PWM2_CK>,
+ <&infracfg CLK_INFRA_PWM3_CK>;
+ clock-names = "top", "main", "pwm1", "pwm2", "pwm3";
+ #pwm-cells = <2>;
+ };
+
+ sgmiisys0: syscon@10060000 {
+ compatible = "mediatek,mt7981-sgmiisys_0", "syscon";
+ reg = <0 0x10060000 0 0x1000>;
+ mediatek,pnswap;
+ #clock-cells = <1>;
+ };
+
+ sgmiisys1: syscon@10070000 {
+ compatible = "mediatek,mt7981-sgmiisys_1", "syscon";
+ reg = <0 0x10070000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ crypto: crypto@10320000 {
+ compatible = "inside-secure,safexcel-eip97";
+ reg = <0 0x10320000 0 0x40000>;
+ interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "ring0", "ring1", "ring2", "ring3";
+ clocks = <&topckgen CLK_TOP_EIP97B>;
+ clock-names = "top_eip97_ck";
+ assigned-clocks = <&topckgen CLK_TOP_EIP97B_SEL>;
+ assigned-clock-parents = <&topckgen CLK_TOP_CB_NET1_D5>;
+ };
+
+ uart0: serial@11002000 {
+ compatible = "mediatek,mt6577-uart";
+ reg = <0 0x11002000 0 0x400>;
+ interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&infracfg CLK_INFRA_UART0_SEL>,
+ <&infracfg CLK_INFRA_UART0_CK>;
+ clock-names = "baud", "bus";
+ assigned-clocks = <&topckgen CLK_TOP_UART_SEL>,
+ <&infracfg CLK_INFRA_UART0_SEL>;
+ assigned-clock-parents = <&topckgen CLK_TOP_CB_CKSQ_40M>,
+ <&topckgen CLK_TOP_UART_SEL>;
+ pinctrl-0 = <&uart0_pins>;
+ pinctrl-names = "default";
+ status = "disabled";
+ };
+
+ uart1: serial@11003000 {
+ compatible = "mediatek,mt6577-uart";
+ reg = <0 0x11003000 0 0x400>;
+ interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&infracfg CLK_INFRA_UART1_SEL>,
+ <&infracfg CLK_INFRA_UART1_CK>;
+ clock-names = "baud", "bus";
+ assigned-clocks = <&topckgen CLK_TOP_UART_SEL>,
+ <&infracfg CLK_INFRA_UART1_SEL>;
+ assigned-clock-parents = <&topckgen CLK_TOP_CB_CKSQ_40M>,
+ <&topckgen CLK_TOP_UART_SEL>;
+ status = "disabled";
+ };
+
+ uart2: serial@11004000 {
+ compatible = "mediatek,mt6577-uart";
+ reg = <0 0x11004000 0 0x400>;
+ interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&infracfg CLK_INFRA_UART2_SEL>,
+ <&infracfg CLK_INFRA_UART2_CK>;
+ clock-names = "baud", "bus";
+ assigned-clocks = <&topckgen CLK_TOP_UART_SEL>,
+ <&infracfg CLK_INFRA_UART2_SEL>;
+ assigned-clock-parents = <&topckgen CLK_TOP_CB_CKSQ_40M>,
+ <&topckgen CLK_TOP_UART_SEL>;
+ status = "disabled";
+ };
+
+ snand: snfi@11005000 {
+ compatible = "mediatek,mt7986-snand";
+ reg = <0 0x11005000 0 0x1000>, <0 0x11006000 0 0x1000>;
+ reg-names = "nfi", "ecc";
+ interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&infracfg CLK_INFRA_SPINFI1_CK>,
+ <&infracfg CLK_INFRA_NFI1_CK>,
+ <&infracfg CLK_INFRA_NFI_HCK_CK>;
+ clock-names = "pad_clk", "nfi_clk", "nfi_hclk";
+ assigned-clocks = <&topckgen CLK_TOP_SPINFI_SEL>,
+ <&topckgen CLK_TOP_NFI1X_SEL>;
+ assigned-clock-parents = <&topckgen CLK_TOP_CB_M_D8>,
+ <&topckgen CLK_TOP_CB_M_D8>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c0: i2c@11007000 {
+ compatible = "mediatek,mt7981-i2c";
+ reg = <0 0x11007000 0 0x1000>,
+ <0 0x10217080 0 0x80>;
+ interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
+ clock-div = <1>;
+ clocks = <&infracfg CLK_INFRA_I2C0_CK>,
+ <&infracfg CLK_INFRA_AP_DMA_CK>,
+ <&infracfg CLK_INFRA_I2C_MCK_CK>,
+ <&infracfg CLK_INFRA_I2C_PCK_CK>;
+ clock-names = "main", "dma", "arb", "pmic";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ spi2: spi@11009000 {
+ compatible = "mediatek,mt7986-spi-ipm", "mediatek,spi-ipm";
+ reg = <0 0x11009000 0 0x100>;
+ interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&topckgen CLK_TOP_CB_M_D2>,
+ <&topckgen CLK_TOP_SPI_SEL>,
+ <&infracfg CLK_INFRA_SPI2_CK>,
+ <&infracfg CLK_INFRA_SPI2_HCK_CK>;
+ clock-names = "parent-clk", "sel-clk", "spi-clk", "hclk";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ spi0: spi@1100a000 {
+ compatible = "mediatek,mt7986-spi-ipm", "mediatek,spi-ipm";
+ reg = <0 0x1100a000 0 0x100>;
+ interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&topckgen CLK_TOP_CB_M_D2>,
+ <&topckgen CLK_TOP_SPI_SEL>,
+ <&infracfg CLK_INFRA_SPI0_CK>,
+ <&infracfg CLK_INFRA_SPI0_HCK_CK>;
+ clock-names = "parent-clk", "sel-clk", "spi-clk", "hclk";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ spi1: spi@1100b000 {
+ compatible = "mediatek,mt7986-spi-ipm", "mediatek,spi-ipm";
+ reg = <0 0x1100b000 0 0x100>;
+ interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&topckgen CLK_TOP_CB_M_D2>,
+ <&topckgen CLK_TOP_SPIM_MST_SEL>,
+ <&infracfg CLK_INFRA_SPI1_CK>,
+ <&infracfg CLK_INFRA_SPI1_HCK_CK>;
+ clock-names = "parent-clk", "sel-clk", "spi-clk", "hclk";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ thermal: thermal@1100c800 {
+ compatible = "mediatek,mt7981-thermal", "mediatek,mt7986-thermal";
+ reg = <0 0x1100c800 0 0x800>;
+ interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&infracfg CLK_INFRA_THERM_CK>,
+ <&infracfg CLK_INFRA_ADC_26M_CK>;
+ clock-names = "therm", "auxadc";
+ nvmem-cells = <&thermal_calibration>;
+ nvmem-cell-names = "calibration-data";
+ #thermal-sensor-cells = <1>;
+ mediatek,auxadc = <&auxadc>;
+ mediatek,apmixedsys = <&apmixedsys>;
+ };
+
+ auxadc: adc@1100d000 {
+ compatible = "mediatek,mt7981-auxadc",
+ "mediatek,mt7986-auxadc",
+ "mediatek,mt7622-auxadc";
+ reg = <0 0x1100d000 0 0x1000>;
+ clocks = <&infracfg CLK_INFRA_ADC_26M_CK>,
+ <&infracfg CLK_INFRA_ADC_FRC_CK>;
+ clock-names = "main", "32k";
+ #io-channel-cells = <1>;
+ };
+
+ xhci: usb@11200000 {
+ compatible = "mediatek,mt7986-xhci",
+ "mediatek,mtk-xhci";
+ reg = <0 0x11200000 0 0x2e00>,
+ <0 0x11203e00 0 0x0100>;
+ reg-names = "mac", "ippc";
+ interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&infracfg CLK_INFRA_IUSB_SYS_CK>,
+ <&infracfg CLK_INFRA_IUSB_CK>,
+ <&infracfg CLK_INFRA_IUSB_133_CK>,
+ <&infracfg CLK_INFRA_IUSB_66M_CK>,
+ <&topckgen CLK_TOP_U2U3_XHCI_SEL>;
+ clock-names = "sys_ck",
+ "ref_ck",
+ "mcu_ck",
+ "dma_ck",
+ "xhci_ck";
+ phys = <&u2port0 PHY_TYPE_USB2>,
+ <&u3port0 PHY_TYPE_USB3>;
+ vusb33-supply = <®_3p3v>;
+ status = "disabled";
+ };
+
+ afe: audio-controller@11210000 {
+ compatible = "mediatek,mt79xx-audio";
+ reg = <0 0x11210000 0 0x9000>;
+ interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&infracfg CLK_INFRA_AUD_BUS_CK>,
+ <&infracfg CLK_INFRA_AUD_26M_CK>,
+ <&infracfg CLK_INFRA_AUD_L_CK>,
+ <&infracfg CLK_INFRA_AUD_AUD_CK>,
+ <&infracfg CLK_INFRA_AUD_EG2_CK>,
+ <&topckgen CLK_TOP_AUD_SEL>;
+ clock-names = "aud_bus_ck",
+ "aud_26m_ck",
+ "aud_l_ck",
+ "aud_aud_ck",
+ "aud_eg2_ck",
+ "aud_sel";
+ assigned-clocks = <&topckgen CLK_TOP_AUD_SEL>,
+ <&topckgen CLK_TOP_A1SYS_SEL>,
+ <&topckgen CLK_TOP_AUD_L_SEL>,
+ <&topckgen CLK_TOP_A_TUNER_SEL>;
+ assigned-clock-parents = <&topckgen CLK_TOP_CB_APLL2_196M>,
+ <&topckgen CLK_TOP_APLL2_D4>,
+ <&topckgen CLK_TOP_CB_APLL2_196M>,
+ <&topckgen CLK_TOP_APLL2_D4>;
+ status = "disabled";
+ };
+
+ mmc0: mmc@11230000 {
+ compatible = "mediatek,mt7986-mmc", "mediatek,mt7981-mmc";
+ reg = <0 0x11230000 0 0x1000>, <0 0x11c20000 0 0x1000>;
+ interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&infracfg CLK_INFRA_MSDC_CK>,
+ <&infracfg CLK_INFRA_MSDC_HCK_CK>,
+ <&infracfg CLK_INFRA_MSDC_66M_CK>,
+ <&infracfg CLK_INFRA_MSDC_133M_CK>;
+ assigned-clocks = <&topckgen CLK_TOP_EMMC_208M_SEL>,
+ <&topckgen CLK_TOP_EMMC_400M_SEL>;
+ assigned-clock-parents = <&topckgen CLK_TOP_CB_M_D2>,
+ <&topckgen CLK_TOP_CB_NET2_D2>;
+ clock-names = "source", "hclk", "axi_cg", "ahb_cg";
+ status = "disabled";
+ };
+
+ pcie: pcie@11280000 {
+ compatible = "mediatek,mt7981-pcie",
+ "mediatek,mt8192-pcie";
+ reg = <0 0x11280000 0 0x4000>;
+ reg-names = "pcie-mac";
+ ranges = <0x82000000 0 0x20000000
+ 0x0 0x20000000 0 0x10000000>;
+ device_type = "pci";
+ interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
+ bus-range = <0x00 0xff>;
+ clocks = <&infracfg CLK_INFRA_IPCIE_CK>,
+ <&infracfg CLK_INFRA_IPCIE_PIPE_CK>,
+ <&infracfg CLK_INFRA_IPCIER_CK>,
+ <&infracfg CLK_INFRA_IPCIEB_CK>;
+ phys = <&u3port0 PHY_TYPE_PCIE>;
+ phy-names = "pcie-phy";
+ interrupt-map-mask = <0 0 0 7>;
+ interrupt-map = <0 0 0 1 &pcie_intc 0>,
+ <0 0 0 2 &pcie_intc 1>,
+ <0 0 0 3 &pcie_intc 2>,
+ <0 0 0 4 &pcie_intc 3>;
+ #interrupt-cells = <1>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ status = "disabled";
+
+ pcie_intc: interrupt-controller {
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ #address-cells = <0>;
+ };
+ };
+
+ pio: pinctrl@11d00000 {
+ compatible = "mediatek,mt7981-pinctrl";
+ reg = <0 0x11d00000 0 0x1000>,
+ <0 0x11c00000 0 0x1000>,
+ <0 0x11c10000 0 0x1000>,
+ <0 0x11d20000 0 0x1000>,
+ <0 0x11e00000 0 0x1000>,
+ <0 0x11e20000 0 0x1000>,
+ <0 0x11f00000 0 0x1000>,
+ <0 0x11f10000 0 0x1000>,
+ <0 0x1000b000 0 0x1000>;
+ reg-names = "gpio", "iocfg_rt", "iocfg_rm",
+ "iocfg_rb", "iocfg_lb", "iocfg_bl",
+ "iocfg_tm", "iocfg_tl", "eint";
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&pio 0 0 56>;
+ interrupt-controller;
+ interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-parent = <&gic>;
+ #interrupt-cells = <2>;
+
+ mdio_pins: mdc-mdio-pins {
+ mux {
+ function = "eth";
+ groups = "smi_mdc_mdio";
+ };
+ };
+
+ uart0_pins: uart0-pins {
+ mux {
+ function = "uart";
+ groups = "uart0";
+ };
+ };
+
+ wifi_dbdc_pins: wifi-dbdc-pins {
+ mux {
+ function = "eth";
+ groups = "wf0_mode1";
+ };
+
+ conf {
+ pins = "WF_HB1", "WF_HB2", "WF_HB3", "WF_HB4",
+ "WF_HB0", "WF_HB0_B", "WF_HB5", "WF_HB6",
+ "WF_HB7", "WF_HB8", "WF_HB9", "WF_HB10",
+ "WF_TOP_CLK", "WF_TOP_DATA", "WF_XO_REQ",
+ "WF_CBA_RESETB", "WF_DIG_RESETB";
+ drive-strength = <4>;
+ };
+ };
+
+ gbe_led0_pins: gbe-led0-pins {
+ mux {
+ function = "led";
+ groups = "gbe_led0";
+ };
+ };
+
+ gbe_led1_pins: gbe-led1-pins {
+ mux {
+ function = "led";
+ groups = "gbe_led1";
+ };
+ };
+ };
+
+ topmisc: topmisc@11d10000 {
+ compatible = "mediatek,mt7981-topmisc", "syscon";
+ reg = <0 0x11d10000 0 0x10000>;
+ #clock-cells = <1>;
+ };
+
+ usb_phy: usb-phy@11e10000 {
+ compatible = "mediatek,mt7981",
+ "mediatek,generic-tphy-v2";
+ ranges = <0 0 0x11e10000 0x1700>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ status = "disabled";
+
+ u2port0: usb-phy@0 {
+ reg = <0x0 0x700>;
+ clocks = <&topckgen CLK_TOP_USB_FRMCNT_SEL>;
+ clock-names = "ref";
+ #phy-cells = <1>;
+ };
+
+ u3port0: usb-phy@700 {
+ reg = <0x700 0x900>;
+ clocks = <&topckgen CLK_TOP_USB3_PHY_SEL>;
+ clock-names = "ref";
+ #phy-cells = <1>;
+ mediatek,syscon-type = <&topmisc 0x218 0>;
+ status = "okay";
+ };
+ };
+
+ efuse: efuse@11f20000 {
+ compatible = "mediatek,mt7981-efuse",
+ "mediatek,efuse";
+ reg = <0 0x11f20000 0 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ status = "okay";
+
+ thermal_calibration: thermal-calib@274 {
+ reg = <0x274 0xc>;
+ };
+
+ phy_calibration: phy-calib@8dc {
+ reg = <0x8dc 0x10>;
+ };
+
+ comb_rx_imp_p0: usb3-rx-imp@8c8 {
+ reg = <0x8c8 1>;
+ bits = <0 5>;
+ };
+
+ comb_tx_imp_p0: usb3-tx-imp@8c8 {
+ reg = <0x8c8 2>;
+ bits = <5 5>;
+ };
+
+ comb_intr_p0: usb3-intr@8c9 {
+ reg = <0x8c9 1>;
+ bits = <2 6>;
+ };
+ };
+
+ ethsys: clock-controller@15000000 {
+ compatible = "mediatek,mt7981-ethsys",
+ "syscon";
+ reg = <0 0x15000000 0 0x1000>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ };
+
+ wed: wed@15010000 {
+ compatible = "mediatek,mt7981-wed",
+ "mediatek,mt7986-wed",
+ "syscon";
+ reg = <0 0x15010000 0 0x1000>;
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>;
+ memory-region = <&wo_emi0>, <&wo_data>;
+ memory-region-names = "wo-emi", "wo-data";
+ mediatek,wo-ccif = <&wo_ccif0>;
+ mediatek,wo-ilm = <&wo_ilm0>;
+ mediatek,wo-dlm = <&wo_dlm0>;
+ mediatek,wo-cpuboot = <&wo_cpuboot>;
+ };
+
+ eth: ethernet@15100000 {
+ compatible = "mediatek,mt7981-eth";
+ reg = <0 0x15100000 0 0x80000>;
+ interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <ðsys CLK_ETH_FE_EN>,
+ <ðsys CLK_ETH_GP2_EN>,
+ <ðsys CLK_ETH_GP1_EN>,
+ <ðsys CLK_ETH_WOCPU0_EN>,
+ <&sgmiisys0 CLK_SGM0_TX_EN>,
+ <&sgmiisys0 CLK_SGM0_RX_EN>,
+ <&sgmiisys0 CLK_SGM0_CK0_EN>,
+ <&sgmiisys0 CLK_SGM0_CDR_CK0_EN>,
+ <&sgmiisys1 CLK_SGM1_TX_EN>,
+ <&sgmiisys1 CLK_SGM1_RX_EN>,
+ <&sgmiisys1 CLK_SGM1_CK1_EN>,
+ <&sgmiisys1 CLK_SGM1_CDR_CK1_EN>,
+ <&topckgen CLK_TOP_SGM_REG>,
+ <&topckgen CLK_TOP_NETSYS_SEL>,
+ <&topckgen CLK_TOP_NETSYS_500M_SEL>;
+ clock-names = "fe", "gp2", "gp1", "wocpu0",
+ "sgmii_tx250m", "sgmii_rx250m",
+ "sgmii_cdr_ref", "sgmii_cdr_fb",
+ "sgmii2_tx250m", "sgmii2_rx250m",
+ "sgmii2_cdr_ref", "sgmii2_cdr_fb",
+ "sgmii_ck", "netsys0", "netsys1";
+ assigned-clocks = <&topckgen CLK_TOP_NETSYS_2X_SEL>,
+ <&topckgen CLK_TOP_SGM_325M_SEL>;
+ assigned-clock-parents = <&topckgen CLK_TOP_CB_NET2_800M>,
+ <&topckgen CLK_TOP_CB_SGM_325M>;
+ mediatek,ethsys = <ðsys>;
+ mediatek,sgmiisys = <&sgmiisys0>, <&sgmiisys1>;
+ mediatek,infracfg = <&topmisc>;
+ mediatek,wed = <&wed>;
+ #reset-cells = <1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+
+ mdio_bus: mdio-bus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ int_gbe_phy: ethernet-phy@0 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <0>;
+ phy-mode = "gmii";
+ phy-is-integrated;
+ nvmem-cells = <&phy_calibration>;
+ nvmem-cell-names = "phy-cal-data";
+
+ leds {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ int_gbe_phy_led0: int-gbe-phy-led0@0 {
+ reg = <0>;
+ function = LED_FUNCTION_LAN;
+ status = "disabled";
+ };
+
+ int_gbe_phy_led1: int-gbe-phy-led1@1 {
+ reg = <1>;
+ function = LED_FUNCTION_LAN;
+ status = "disabled";
+ };
+ };
+ };
+ };
+ };
+
+ wdma: wdma@15104800 {
+ compatible = "mediatek,wed-wdma";
+ reg = <0 0x15104800 0 0x400>,
+ <0 0x15104c00 0 0x400>;
+ };
+
+ wo_cpuboot: syscon@15194000 {
+ compatible = "mediatek,mt7986-wo-cpuboot", "syscon";
+ reg = <0 0x15194000 0 0x1000>;
+ };
+
+ ap2woccif: ap2woccif@151a5000 {
+ compatible = "mediatek,ap2woccif";
+ reg = <0 0x151a5000 0 0x1000>,
+ <0 0x151ad000 0 0x1000>;
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ wo_ccif0: syscon@151a5000 {
+ compatible = "mediatek,mt7986-wo-ccif", "syscon";
+ reg = <0 0x151a5000 0 0x1000>;
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ wo_ilm0: syscon@151e0000 {
+ compatible = "mediatek,mt7986-wo-ilm", "syscon";
+ reg = <0 0x151e0000 0 0x8000>;
+ };
+
+ wo_dlm0: syscon@151e8000 {
+ compatible = "mediatek,mt7986-wo-dlm", "syscon";
+ reg = <0 0x151e8000 0 0x2000>;
+ };
+
+ wifi: wifi@18000000 {
+ compatible = "mediatek,mt7981-wmac";
+ reg = <0 0x18000000 0 0x1000000>,
+ <0 0x10003000 0 0x1000>,
+ <0 0x11d10000 0 0x1000>;
+ resets = <&watchdog MT7986_TOPRGU_CONSYS_SW_RST>;
+ reset-names = "consys";
+ pinctrl-0 = <&wifi_dbdc_pins>;
+ pinctrl-names = "dbdc";
+ clocks = <&topckgen CLK_TOP_NETSYS_MCU_SEL>,
+ <&topckgen CLK_TOP_AP2CNN_HOST_SEL>;
+ clock-names = "mcu", "ap2conn";
+ interrupts = <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>;
+ memory-region = <&wmcpu_emi>;
+ status = "disabled";
+ };
+ };
+
+ thermal-zones {
+ cpu_thermal: cpu-thermal {
+ polling-delay-passive = <1000>;
+ polling-delay = <1000>;
+ thermal-sensors = <&thermal 0>;
+
+ trips {
+ cpu_trip_active_highest: active-highest {
+ temperature = <70000>;
+ hysteresis = <2000>;
+ type = "active";
+ };
+
+ cpu_trip_active_high: active-high {
+ temperature = <60000>;
+ hysteresis = <2000>;
+ type = "active";
+ };
+
+ cpu_trip_active_med: active-med {
+ temperature = <50000>;
+ hysteresis = <2000>;
+ type = "active";
+ };
+
+ cpu_trip_active_low: active-low {
+ temperature = <45000>;
+ hysteresis = <2000>;
+ type = "active";
+ };
+
+ cpu_trip_active_lowest: active-lowest {
+ temperature = <40000>;
+ hysteresis = <2000>;
+ type = "active";
+ };
+ };
+
+ cooling-maps {
+ cpu-active-highest {
+ /* active: set fan to cooling level 7 */
+ cooling-device = <&fan 7 7>;
+ trip = <&cpu_trip_active_highest>;
+ };
+
+ cpu-active-high {
+ /* active: set fan to cooling level 5 */
+ cooling-device = <&fan 5 5>;
+ trip = <&cpu_trip_active_high>;
+ };
+
+ cpu-active-med {
+ /* active: set fan to cooling level 3 */
+ cooling-device = <&fan 3 3>;
+ trip = <&cpu_trip_active_med>;
+ };
+
+ cpu-active-low {
+ /* active: set fan to cooling level 2 */
+ cooling-device = <&fan 2 2>;
+ trip = <&cpu_trip_active_low>;
+ };
+
+ cpu-active-lowest {
+ /* active: set fan to cooling level 1 */
+ cooling-device = <&fan 1 1>;
+ trip = <&cpu_trip_active_lowest>;
+ };
+ };
+ };
+ };
+
+ timer {
+ compatible = "arm,armv8-timer";
+ interrupt-parent = <&gic>;
+ clock-frequency = <13000000>;
+ interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
+
+ };
+
+ trng {
+ compatible = "mediatek,mt7981-rng";
+ };
+};
--- /dev/null
+/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */
+
+#include "mt7986a-rfb.dtsi"
+
+/ {
+ compatible = "mediatek,mt7986a-rfb-snand";
+};
+
+&spi0 {
+ status = "okay";
+
+ spi_nand: spi_nand@1 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "spi-nand";
+ reg = <1>;
+ spi-max-frequency = <10000000>;
+ spi-tx-bus-width = <4>;
+ spi-rx-bus-width = <4>;
+
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ partition@0 {
+ label = "BL2";
+ reg = <0x00000 0x0100000>;
+ read-only;
+ };
+ partition@100000 {
+ label = "u-boot-env";
+ reg = <0x0100000 0x0080000>;
+ };
+ factory: partition@180000 {
+ label = "Factory";
+ reg = <0x180000 0x0200000>;
+ };
+ partition@380000 {
+ label = "FIP";
+ reg = <0x380000 0x0200000>;
+ };
+ partition@580000 {
+ label = "ubi";
+ reg = <0x580000 0x4000000>;
+ };
+ };
+ };
+};
+
+&wifi {
+ mediatek,mtd-eeprom = <&factory 0>;
+};
--- /dev/null
+/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */
+
+#include "mt7986a-rfb.dtsi"
+
+/ {
+ compatible = "mediatek,mt7986a-rfb-snor";
+};
+
+&spi0 {
+ status = "okay";
+
+ spi_nor: spi_nor@0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "jedec,spi-nor";
+ reg = <0>;
+ spi-max-frequency = <52000000>;
+ spi-tx-bus-width = <4>;
+ spi-rx-bus-width = <4>;
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ partition@00000 {
+ label = "BL2";
+ reg = <0x00000 0x0040000>;
+ };
+ partition@40000 {
+ label = "u-boot-env";
+ reg = <0x40000 0x0010000>;
+ };
+ factory: partition@50000 {
+ label = "Factory";
+ reg = <0x50000 0x00B0000>;
+ };
+ partition@100000 {
+ label = "FIP";
+ reg = <0x100000 0x0080000>;
+ };
+ partition@180000 {
+ label = "firmware";
+ reg = <0x180000 0xE00000>;
+ };
+ };
+ };
+};
+
+&wifi {
+ mediatek,mtd-eeprom = <&factory 0>;
+};
--- /dev/null
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright (C) 2021 MediaTek Inc.
+ * Author: Sam.Shih <sam.shih@mediatek.com>
+ */
+
+/dts-v1/;
+#include "mt7986a.dtsi"
+
+/ {
+ model = "MediaTek MT7986a RFB";
+ compatible = "mediatek,mt7986a-rfb";
+
+ aliases {
+ serial0 = &uart0;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ memory {
+ reg = <0 0x40000000 0 0x40000000>;
+ };
+
+ reg_1p8v: regulator-1p8v {
+ compatible = "regulator-fixed";
+ regulator-name = "fixed-1.8V";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ reg_3p3v: regulator-3p3v {
+ compatible = "regulator-fixed";
+ regulator-name = "fixed-3.3V";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ reg_5v: regulator-5v {
+ compatible = "regulator-fixed";
+ regulator-name = "fixed-5V";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+};
+
+ð {
+ status = "okay";
+
+ gmac0: mac@0 {
+ compatible = "mediatek,eth-mac";
+ reg = <0>;
+ phy-mode = "2500base-x";
+
+ fixed-link {
+ speed = <2500>;
+ full-duplex;
+ pause;
+ };
+ };
+
+ gmac1: mac@1 {
+ compatible = "mediatek,eth-mac";
+ reg = <1>;
+ phy-mode = "2500base-x";
+ };
+
+ mdio: mdio-bus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+};
+
+&wifi {
+ status = "okay";
+ pinctrl-names = "default", "dbdc";
+ pinctrl-0 = <&wf_2g_5g_pins>;
+ pinctrl-1 = <&wf_dbdc_pins>;
+};
+
+&mdio {
+ phy5: phy@5 {
+ compatible = "ethernet-phy-id67c9.de0a";
+ reg = <5>;
+
+ reset-gpios = <&pio 6 1>;
+ reset-deassert-us = <20000>;
+ };
+
+ phy6: phy@6 {
+ compatible = "ethernet-phy-id67c9.de0a";
+ reg = <6>;
+ };
+
+ switch: switch@1f {
+ compatible = "mediatek,mt7531";
+ reg = <31>;
+ reset-gpios = <&pio 5 0>;
+ };
+};
+
+&crypto {
+ status = "okay";
+};
+
+&mmc0 {
+ pinctrl-names = "default", "state_uhs";
+ pinctrl-0 = <&mmc0_pins_default>;
+ pinctrl-1 = <&mmc0_pins_uhs>;
+ bus-width = <8>;
+ max-frequency = <200000000>;
+ cap-mmc-highspeed;
+ mmc-hs200-1_8v;
+ mmc-hs400-1_8v;
+ hs400-ds-delay = <0x14014>;
+ vmmc-supply = <®_3p3v>;
+ vqmmc-supply = <®_1p8v>;
+ non-removable;
+ no-sd;
+ no-sdio;
+ status = "okay";
+};
+
+&pcie {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pcie_pins>;
+ status = "okay";
+};
+
+&pcie_phy {
+ status = "okay";
+};
+
+&pio {
+ mmc0_pins_default: mmc0-pins {
+ mux {
+ function = "emmc";
+ groups = "emmc_51";
+ };
+ conf-cmd-dat {
+ pins = "EMMC_DATA_0", "EMMC_DATA_1", "EMMC_DATA_2",
+ "EMMC_DATA_3", "EMMC_DATA_4", "EMMC_DATA_5",
+ "EMMC_DATA_6", "EMMC_DATA_7", "EMMC_CMD";
+ input-enable;
+ drive-strength = <4>;
+ mediatek,pull-up-adv = <1>; /* pull-up 10K */
+ };
+ conf-clk {
+ pins = "EMMC_CK";
+ drive-strength = <6>;
+ mediatek,pull-down-adv = <2>; /* pull-down 50K */
+ };
+ conf-ds {
+ pins = "EMMC_DSL";
+ mediatek,pull-down-adv = <2>; /* pull-down 50K */
+ };
+ conf-rst {
+ pins = "EMMC_RSTB";
+ drive-strength = <4>;
+ mediatek,pull-up-adv = <1>; /* pull-up 10K */
+ };
+ };
+
+ mmc0_pins_uhs: mmc0-uhs-pins {
+ mux {
+ function = "emmc";
+ groups = "emmc_51";
+ };
+ conf-cmd-dat {
+ pins = "EMMC_DATA_0", "EMMC_DATA_1", "EMMC_DATA_2",
+ "EMMC_DATA_3", "EMMC_DATA_4", "EMMC_DATA_5",
+ "EMMC_DATA_6", "EMMC_DATA_7", "EMMC_CMD";
+ input-enable;
+ drive-strength = <4>;
+ mediatek,pull-up-adv = <1>; /* pull-up 10K */
+ };
+ conf-clk {
+ pins = "EMMC_CK";
+ drive-strength = <6>;
+ mediatek,pull-down-adv = <2>; /* pull-down 50K */
+ };
+ conf-ds {
+ pins = "EMMC_DSL";
+ mediatek,pull-down-adv = <2>; /* pull-down 50K */
+ };
+ conf-rst {
+ pins = "EMMC_RSTB";
+ drive-strength = <4>;
+ mediatek,pull-up-adv = <1>; /* pull-up 10K */
+ };
+ };
+
+ pcie_pins: pcie-pins {
+ mux {
+ function = "pcie";
+ groups = "pcie_clk", "pcie_wake", "pcie_pereset";
+ };
+ };
+
+ spic_pins_g2: spic-pins-29-to-32 {
+ mux {
+ function = "spi";
+ groups = "spi1_2";
+ };
+ };
+
+ spi_flash_pins: spi-flash-pins-33-to-38 {
+ mux {
+ function = "spi";
+ groups = "spi0", "spi0_wp_hold";
+ };
+ conf-pu {
+ pins = "SPI2_CS", "SPI2_HOLD", "SPI2_WP";
+ drive-strength = <8>;
+ mediatek,pull-up-adv = <0>; /* bias-disable */
+ };
+ conf-pd {
+ pins = "SPI2_CLK", "SPI2_MOSI", "SPI2_MISO";
+ drive-strength = <8>;
+ mediatek,pull-down-adv = <0>; /* bias-disable */
+ };
+ };
+
+ uart1_pins: uart1-pins {
+ mux {
+ function = "uart";
+ groups = "uart1";
+ };
+ };
+
+ uart2_pins: uart2-pins {
+ mux {
+ function = "uart";
+ groups = "uart2";
+ };
+ };
+
+ wf_2g_5g_pins: wf_2g_5g-pins {
+ mux {
+ function = "wifi";
+ groups = "wf_2g", "wf_5g";
+ };
+ conf {
+ pins = "WF0_HB1", "WF0_HB2", "WF0_HB3", "WF0_HB4",
+ "WF0_HB0", "WF0_HB0_B", "WF0_HB5", "WF0_HB6",
+ "WF0_HB7", "WF0_HB8", "WF0_HB9", "WF0_HB10",
+ "WF0_TOP_CLK", "WF0_TOP_DATA", "WF1_HB1",
+ "WF1_HB2", "WF1_HB3", "WF1_HB4", "WF1_HB0",
+ "WF1_HB5", "WF1_HB6", "WF1_HB7", "WF1_HB8",
+ "WF1_TOP_CLK", "WF1_TOP_DATA";
+ drive-strength = <4>;
+ };
+ };
+
+ wf_dbdc_pins: wf_dbdc-pins {
+ mux {
+ function = "wifi";
+ groups = "wf_dbdc";
+ };
+ conf {
+ pins = "WF0_HB1", "WF0_HB2", "WF0_HB3", "WF0_HB4",
+ "WF0_HB0", "WF0_HB0_B", "WF0_HB5", "WF0_HB6",
+ "WF0_HB7", "WF0_HB8", "WF0_HB9", "WF0_HB10",
+ "WF0_TOP_CLK", "WF0_TOP_DATA", "WF1_HB1",
+ "WF1_HB2", "WF1_HB3", "WF1_HB4", "WF1_HB0",
+ "WF1_HB5", "WF1_HB6", "WF1_HB7", "WF1_HB8",
+ "WF1_TOP_CLK", "WF1_TOP_DATA";
+ drive-strength = <4>;
+ };
+ };
+};
+
+&spi0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&spi_flash_pins>;
+ cs-gpios = <0>, <0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+};
+
+&spi1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&spic_pins_g2>;
+ status = "okay";
+
+ proslic_spi: proslic_spi@0 {
+ compatible = "silabs,proslic_spi";
+ reg = <0>;
+ spi-max-frequency = <10000000>;
+ spi-cpha = <1>;
+ spi-cpol = <1>;
+ channel_count = <1>;
+ debug_level = <4>; /* 1 = TRC, 2 = DBG, 4 = ERR */
+ reset_gpio = <&pio 7 0>;
+ ig,enable-spi = <1>; /* 1: Enable, 0: Disable */
+ };
+};
+
+&gmac1 {
+ phy-mode = "2500base-x";
+ phy-connection-type = "2500base-x";
+ phy-handle = <&phy6>;
+};
+
+&switch {
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ label = "lan1";
+ };
+
+ port@1 {
+ reg = <1>;
+ label = "lan2";
+ };
+
+ port@2 {
+ reg = <2>;
+ label = "lan3";
+ };
+
+ port@3 {
+ reg = <3>;
+ label = "lan4";
+ };
+
+ port@4 {
+ reg = <4>;
+ label = "wan";
+ };
+
+ port@5 {
+ reg = <5>;
+ label = "lan6";
+
+ phy-mode = "2500base-x";
+ phy-handle = <&phy5>;
+ };
+
+ port@6 {
+ reg = <6>;
+ ethernet = <&gmac0>;
+ phy-mode = "2500base-x";
+
+ fixed-link {
+ speed = <2500>;
+ full-duplex;
+ pause;
+ };
+ };
+ };
+};
+
+&ssusb {
+ vusb33-supply = <®_3p3v>;
+ vbus-supply = <®_5v>;
+ status = "okay";
+};
+
+&uart0 {
+ status = "okay";
+};
+
+&uart1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart1_pins>;
+ status = "okay";
+};
+
+&uart2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart2_pins>;
+ status = "okay";
+};
+
+&usb_phy {
+ status = "okay";
+};
--- /dev/null
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright (C) 2021 MediaTek Inc.
+ * Author: Frank Wunderlich <frank-w@public-files.de>
+ */
+
+/dts-v1/;
+/plugin/;
+
+/ {
+ compatible = "bananapi,bpi-r4", "mediatek,mt7988a";
+
+ fragment@0 {
+ target-path = "/soc/mmc@11230000";
+ __overlay__ {
+ pinctrl-names = "default", "state_uhs";
+ pinctrl-0 = <&mmc0_pins_emmc_51>;
+ pinctrl-1 = <&mmc0_pins_emmc_51>;
+ bus-width = <8>;
+ max-frequency = <200000000>;
+ cap-mmc-highspeed;
+ mmc-hs200-1_8v;
+ mmc-hs400-1_8v;
+ hs400-ds-delay = <0x12814>;
+ vqmmc-supply = <®_1p8v>;
+ vmmc-supply = <®_3p3v>;
+ non-removable;
+ no-sd;
+ no-sdio;
+ status = "okay";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ card@0 {
+ compatible = "mmc-card";
+ reg = <0>;
+
+ block {
+ compatible = "block-device";
+ partitions {
+ block-partition-env {
+ partname = "ubootenv";
+
+ nvmem-layout {
+ compatible = "u-boot,env";
+ };
+ };
+ emmc_rootfs: block-partition-production {
+ partname = "production";
+ };
+ };
+ };
+ };
+ };
+ };
+
+ fragment@2 {
+ target-path = "/chosen";
+ __overlay__ {
+ rootdisk-emmc = <&emmc_rootfs>;
+ };
+ };
+};
--- /dev/null
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright (C) 2022 MediaTek Inc.
+ * Author: Sam.Shih <sam.shih@mediatek.com>
+ */
+
+#include "mt7988a-bananapi-bpi-r4.dtsi"
+
+/ {
+ model = "Bananapi BPI-R4 2.5GE PoE";
+ compatible = "bananapi,bpi-r4-poe",
+ "mediatek,mt7988a";
+};
+
+&gmac1 {
+ phy-mode = "internal";
+ phy-connection-type = "internal";
+ phy = <&int_2p5g_phy>;
+ status = "okay";
+ openwrt,netdev-name = "lan4";
+};
+
+&int_2p5g_phy {
+ pinctrl-names = "i2p5gbe-led";
+ pinctrl-0 = <&i2p5gbe_led0_pins>;
+};
--- /dev/null
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright (C) 2023
+ * Author: Daniel Golle <daniel@makrotopia.org>
+ */
+
+/dts-v1/;
+/plugin/;
+
+/ {
+ compatible = "bananapi,bpi-r4", "mediatek,mt7988a";
+
+ fragment@0 {
+ target = <&pcf8563>;
+ __overlay__ {
+ status = "okay";
+ };
+ };
+};
--- /dev/null
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright (C) 2023 MediaTek Inc.
+ * Author: Frank Wunderlich <frank-w@public-files.de>
+ */
+
+/dts-v1/;
+/plugin/;
+
+#include <dt-bindings/gpio/gpio.h>
+
+/ {
+ compatible = "bananapi,bpi-r4", "mediatek,mt7988a";
+
+ fragment@1 {
+ target-path = "/soc/mmc@11230000";
+ __overlay__ {
+ pinctrl-names = "default", "state_uhs";
+ pinctrl-0 = <&mmc0_pins_sdcard>;
+ pinctrl-1 = <&mmc0_pins_sdcard>;
+ cd-gpios = <&pio 12 GPIO_ACTIVE_LOW>;
+ bus-width = <4>;
+ max-frequency = <52000000>;
+ cap-sd-highspeed;
+ vmmc-supply = <®_3p3v>;
+ vqmmc-supply = <®_3p3v>;
+ no-mmc;
+ status = "okay";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ card@0 {
+ compatible = "mmc-card";
+ reg = <0>;
+
+ block {
+ compatible = "block-device";
+ partitions {
+ block-partition-env {
+ partname = "ubootenv";
+
+ nvmem-layout {
+ compatible = "u-boot,env";
+ };
+ };
+ sd_rootfs: block-partition-production {
+ partname = "production";
+ };
+ };
+ };
+ };
+ };
+ };
+
+ fragment@2 {
+ target-path = "/chosen";
+ __overlay__ {
+ rootdisk-sd = <&sd_rootfs>;
+ };
+ };
+};
--- /dev/null
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/dts-v1/;
+/plugin/;
+
+#include <dt-bindings/gpio/gpio.h>
+
+/ {
+ compatible = "bananapi,bpi-r4", "mediatek,mt7988a";
+
+ fragment@0 {
+ target-path = "/";
+ __overlay__ {
+ wifi_12v: regulator-wifi-12v {
+ compatible = "regulator-fixed";
+ regulator-name = "wifi";
+ regulator-min-microvolt = <12000000>;
+ regulator-max-microvolt = <12000000>;
+ gpios = <&pio 4 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ regulator-always-on;
+ };
+ };
+ };
+
+ fragment@1 {
+ target = <&i2c_wifi>;
+ __overlay__ {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ // 5G WIFI MAC Address EEPROM
+ wifi_eeprom@51 {
+ compatible = "atmel,24c02";
+ reg = <0x51>;
+ address-bits = <8>;
+ page-size = <8>;
+ size = <256>;
+
+ nvmem-layout {
+ compatible = "fixed-layout";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ macaddr_5g: macaddr@0 {
+ reg = <0x0 0x6>;
+ };
+ };
+ };
+
+ // 6G WIFI MAC Address EEPROM
+ wifi_eeprom@52 {
+ compatible = "atmel,24c02";
+ reg = <0x52>;
+ address-bits = <8>;
+ page-size = <8>;
+ size = <256>;
+
+ nvmem-layout {
+ compatible = "fixed-layout";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ macaddr_6g: macaddr@0 {
+ reg = <0x0 0x6>;
+ };
+ };
+ };
+ };
+ };
+
+ fragment@2 {
+ target = <&pcie0>;
+ __overlay__ {
+ #address-cells = <3>;
+ #size-cells = <2>;
+
+ pcie@0,0 {
+ #address-cells = <3>;
+ #size-cells = <2>;
+ reg = <0x0000 0 0 0 0>;
+
+ wifi@0,0 {
+ compatible = "mediatek,mt76";
+ reg = <0x0000 0 0 0 0>;
+ nvmem-cell-names = "mac-address";
+ nvmem-cells = <&macaddr_5g>;
+ };
+ };
+ };
+ };
+
+ fragment@3 {
+ target = <&pcie1>;
+ __overlay__ {
+ #address-cells = <3>;
+ #size-cells = <2>;
+
+ pcie@0,0 {
+ #address-cells = <3>;
+ #size-cells = <2>;
+ reg = <0x0000 0 0 0 0>;
+
+ wifi@0,0 {
+ compatible = "mediatek,mt76";
+ reg = <0x0000 0 0 0 0>;
+ nvmem-cell-names = "mac-address";
+ nvmem-cells = <&macaddr_6g>;
+ };
+ };
+ };
+ };
+};
--- /dev/null
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright (C) 2022 MediaTek Inc.
+ * Author: Sam.Shih <sam.shih@mediatek.com>
+ */
+
+#include "mt7988a-bananapi-bpi-r4.dtsi"
+
+/ {
+ model = "Bananapi BPI-R4";
+ compatible = "bananapi,bpi-r4",
+ "mediatek,mt7988a";
+
+ /* SFP2 cage (LAN) */
+ sfp2: sfp2 {
+ compatible = "sff,sfp";
+ i2c-bus = <&i2c_sfp2>;
+ los-gpios = <&pio 2 GPIO_ACTIVE_HIGH>;
+ mod-def0-gpios = <&pio 83 GPIO_ACTIVE_LOW>;
+ tx-disable-gpios = <&pio 0 GPIO_ACTIVE_HIGH>;
+ tx-fault-gpios = <&pio 1 GPIO_ACTIVE_HIGH>;
+ rate-select0-gpios = <&pio 3 GPIO_ACTIVE_LOW>;
+ maximum-power-milliwatt = <3000>;
+ };
+};
+
+&gmac1 {
+ sfp = <&sfp2>;
+ managed = "in-band-status";
+ phy-mode = "usxgmii";
+ status = "okay";
+ openwrt,netdev-name = "sfp-lan";
+};
+
+&pca9545 {
+ i2c_sfp2: i2c@2 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <2>;
+ };
+};
--- /dev/null
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright (C) 2022 MediaTek Inc.
+ * Author: Sam.Shih <sam.shih@mediatek.com>
+ */
+
+/dts-v1/;
+#include "mt7988a.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
+#include <dt-bindings/regulator/richtek,rt5190a-regulator.h>
+
+/ {
+ model = "Bananapi BPI-R4";
+ compatible = "bananapi,bpi-r4",
+ "mediatek,mt7988a";
+
+ aliases {
+ ethernet0 = &gmac0;
+ ethernet1 = &gmac1;
+ led-boot = &led_green;
+ led-failsafe = &led_green;
+ led-running = &led_green;
+ led-upgrade = &led_green;
+ serial0 = &serial0;
+ };
+
+ chosen {
+ stdout-path = &serial0;
+ bootargs = "console=ttyS0,115200n1 loglevel=8 pci=pcie_bus_perf ubi.block=0,fit root=/dev/fit0 rootwait";
+ rootdisk-spim-nand = <&ubi_rootfs>;
+ };
+
+ memory {
+ reg = <0x00 0x40000000 0x00 0x10000000>;
+ };
+
+ /* SFP1 cage (WAN) */
+ sfp1: sfp1 {
+ compatible = "sff,sfp";
+ i2c-bus = <&i2c_sfp1>;
+ los-gpios = <&pio 54 GPIO_ACTIVE_HIGH>;
+ mod-def0-gpios = <&pio 82 GPIO_ACTIVE_LOW>;
+ tx-disable-gpios = <&pio 70 GPIO_ACTIVE_HIGH>;
+ tx-fault-gpios = <&pio 69 GPIO_ACTIVE_HIGH>;
+ rate-select0-gpios = <&pio 21 GPIO_ACTIVE_LOW>;
+ maximum-power-milliwatt = <3000>;
+ };
+
+ gpio-keys {
+ compatible = "gpio-keys";
+
+ wps {
+ label = "WPS";
+ linux,code = <KEY_RESTART>;
+ gpios = <&pio 14 GPIO_ACTIVE_LOW>;
+ };
+ };
+
+ gpio-leds {
+ compatible = "gpio-leds";
+
+ led_green: led-green {
+ function = LED_FUNCTION_STATUS;
+ color = <LED_COLOR_ID_GREEN>;
+ gpios = <&pio 79 GPIO_ACTIVE_HIGH>;
+ default-state = "on";
+ };
+
+ led_blue: led-blue {
+ function = LED_FUNCTION_WPS;
+ color = <LED_COLOR_ID_BLUE>;
+ gpios = <&pio 63 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ };
+ };
+
+ reg_1p8v: regulator-1p8v {
+ compatible = "regulator-fixed";
+ regulator-name = "fixed-1.8V";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ reg_3p3v: regulator-3p3v {
+ compatible = "regulator-fixed";
+ regulator-name = "fixed-3.3V";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+};
+
+ð {
+ status = "okay";
+};
+
+&gmac0 {
+ status = "okay";
+};
+
+&gmac2 {
+ sfp = <&sfp1>;
+ managed = "in-band-status";
+ phy-mode = "usxgmii";
+ status = "okay";
+ openwrt,netdev-name = "sfp-wan";
+};
+
+&switch {
+ status = "okay";
+};
+
+&gsw_phy0 {
+ pinctrl-names = "gbe-led";
+ pinctrl-0 = <&gbe0_led0_pins>;
+};
+
+&gsw_port0 {
+ label = "wan";
+};
+
+&gsw_phy0_led0 {
+ status = "okay";
+ function = LED_FUNCTION_WAN;
+ color = <LED_COLOR_ID_GREEN>;
+};
+
+&gsw_phy1 {
+ pinctrl-names = "gbe-led";
+ pinctrl-0 = <&gbe1_led0_pins>;
+};
+
+&gsw_port1 {
+ label = "lan1";
+};
+
+&gsw_phy1_led0 {
+ status = "okay";
+ function = LED_FUNCTION_LAN;
+ color = <LED_COLOR_ID_GREEN>;
+};
+
+&gsw_phy2 {
+ pinctrl-names = "gbe-led";
+ pinctrl-0 = <&gbe2_led0_pins>;
+};
+
+&gsw_port2 {
+ label = "lan2";
+};
+
+&gsw_phy2_led0 {
+ status = "okay";
+ function = LED_FUNCTION_LAN;
+ color = <LED_COLOR_ID_GREEN>;
+};
+
+&gsw_phy3 {
+ pinctrl-names = "gbe-led";
+ pinctrl-0 = <&gbe3_led0_pins>;
+};
+
+&gsw_port3 {
+ label = "lan3";
+};
+
+&gsw_phy3_led0 {
+ status = "okay";
+ function = LED_FUNCTION_LAN;
+ color = <LED_COLOR_ID_GREEN>;
+};
+
+&cpu0 {
+ proc-supply = <&rt5190_buck3>;
+};
+
+&cpu1 {
+ proc-supply = <&rt5190_buck3>;
+};
+
+&cpu2 {
+ proc-supply = <&rt5190_buck3>;
+};
+
+&cpu3 {
+ proc-supply = <&rt5190_buck3>;
+};
+
+&cci {
+ proc-supply = <&rt5190_buck3>;
+};
+
+&i2c0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c0_pins>;
+ status = "okay";
+
+ rt5190a_64: rt5190a@64 {
+ compatible = "richtek,rt5190a";
+ reg = <0x64>;
+ vin2-supply = <&rt5190_buck1>;
+ vin3-supply = <&rt5190_buck1>;
+ vin4-supply = <&rt5190_buck1>;
+
+ regulators {
+ rt5190_buck1: buck1 {
+ regulator-name = "rt5190a-buck1";
+ regulator-min-microvolt = <5090000>;
+ regulator-max-microvolt = <5090000>;
+ regulator-allowed-modes =
+ <RT5190A_OPMODE_AUTO RT5190A_OPMODE_FPWM>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+ buck2 {
+ regulator-name = "vcore";
+ regulator-min-microvolt = <600000>;
+ regulator-max-microvolt = <1400000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+ rt5190_buck3: buck3 {
+ regulator-name = "vproc";
+ regulator-min-microvolt = <600000>;
+ regulator-max-microvolt = <1400000>;
+ regulator-boot-on;
+ };
+ buck4 {
+ regulator-name = "rt5190a-buck4";
+ regulator-min-microvolt = <850000>;
+ regulator-max-microvolt = <850000>;
+ regulator-allowed-modes =
+ <RT5190A_OPMODE_AUTO RT5190A_OPMODE_FPWM>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+ ldo {
+ regulator-name = "rt5190a-ldo";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+ };
+ };
+};
+
+&i2c2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c2_1_pins>;
+ status = "okay";
+
+ pca9545: i2c-switch@70 {
+ reg = <0x70>;
+ compatible = "nxp,pca9545";
+ reset-gpios = <&pio 5 GPIO_ACTIVE_LOW>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ i2c_rtc: i2c@0 { //eeprom,rtc,ngff
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+
+ eeprom@50 {
+ compatible = "atmel,24c02";
+ reg = <0x50>;
+ address-bits = <8>;
+ page-size = <8>;
+ size = <256>;
+ };
+
+ eeprom@57 {
+ compatible = "atmel,24c02";
+ reg = <0x57>;
+ address-bits = <8>;
+ page-size = <8>;
+ size = <256>;
+ };
+
+ pcf8563: rtc@51 {
+ compatible = "nxp,pcf8563";
+ reg = <0x51>;
+ status = "disabled";
+ };
+ };
+
+ i2c_sfp1: i2c@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+ };
+
+ i2c_wifi: i2c@3 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <3>;
+ };
+ };
+};
+
+/* mPCIe SIM2 */
+&pcie0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pcie0_pins>;
+ status = "okay";
+};
+
+/* mPCIe SIM3 */
+&pcie1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pcie1_pins>;
+ status = "okay";
+};
+
+/* M.2 key-B SIM1 */
+&pcie2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pcie2_pins>;
+ status = "okay";
+};
+
+/* M.2 key-M SSD */
+&pcie3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pcie3_pins>;
+ status = "okay";
+};
+
+&pio {
+ mdio0_pins: mdio0-pins {
+ mux {
+ function = "eth";
+ groups = "mdc_mdio0";
+ };
+
+ conf {
+ groups = "mdc_mdio0";
+ drive-strength = <MTK_DRIVE_8mA>;
+ };
+ };
+
+ i2c0_pins: i2c0-pins-g0 {
+ mux {
+ function = "i2c";
+ groups = "i2c0_1";
+ };
+ };
+
+ i2c2_1_pins: i2c2-pins-g1 {
+ mux {
+ function = "i2c";
+ groups = "i2c2_1";
+ };
+ };
+
+ gbe0_led0_pins: gbe0-led0-pins {
+ mux {
+ function = "led";
+ groups = "gbe0_led0";
+ };
+ };
+
+ gbe1_led0_pins: gbe1-led0-pins {
+ mux {
+ function = "led";
+ groups = "gbe1_led0";
+ };
+ };
+
+ gbe2_led0_pins: gbe2-led0-pins {
+ mux {
+ function = "led";
+ groups = "gbe2_led0";
+ };
+ };
+
+ gbe3_led0_pins: gbe3-led0-pins {
+ mux {
+ function = "led";
+ groups = "gbe3_led0";
+ };
+ };
+
+ i2p5gbe_led0_pins: 2p5gbe-led0-pins {
+ mux {
+ function = "led";
+ groups = "2p5gbe_led0";
+ };
+ };
+
+ mmc0_pins_emmc_51: mmc0-pins-emmc-51 {
+ mux {
+ function = "flash";
+ groups = "emmc_51";
+ };
+ };
+
+ mmc0_pins_sdcard: mmc0-pins-sdcard {
+ mux {
+ function = "flash";
+ groups = "sdcard";
+ };
+ };
+
+ pwm0_pins: pwm0-pins {
+ mux {
+ groups = "pwm0";
+ function = "pwm";
+ };
+ };
+
+ uart0_pins: uart0-pins {
+ mux {
+ function = "uart";
+ groups = "uart0";
+ };
+ };
+
+ uart1_2_lite_pins: uart1-2-lite-pins {
+ mux {
+ function = "uart";
+ groups = "uart1_2_lite";
+ };
+ };
+
+ uart2_3_pins: uart2-3-pins {
+ mux {
+ function = "uart";
+ groups = "uart2_3";
+ };
+ };
+
+ spi0_flash_pins: spi0-flash-pins {
+ mux {
+ function = "spi";
+ groups = "spi0", "spi0_wp_hold";
+ };
+ };
+
+ fan: pwm-fan {
+ compatible = "pwm-fan";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pwm0_pins>;
+ pwms = <&pwm 0 50000>;
+ /* cooling level (0, 1, 2, 3) : (0% duty, 30% duty, 50% duty, 100% duty) */
+ cooling-levels = <0 80 128 255>;
+ #cooling-cells = <2>;
+ #thermal-sensor-cells = <1>;
+
+ status = "okay";
+ };
+};
+
+&pwm {
+ status = "okay";
+};
+
+&cpu_thermal {
+ trips {
+ cpu_trip_hot: hot {
+ temperature = <120000>;
+ hysteresis = <2000>;
+ type = "hot";
+ };
+
+ cpu_trip_active_high: active-high {
+ temperature = <115000>;
+ hysteresis = <2000>;
+ type = "active";
+ };
+
+ cpu_trip_active_med: active-med {
+ temperature = <85000>;
+ hysteresis = <2000>;
+ type = "active";
+ };
+
+ cpu_trip_active_low: active-low {
+ temperature = <40000>;
+ hysteresis = <2000>;
+ type = "active";
+ };
+ };
+
+ cooling-maps {
+ cpu-active-high {
+ /* active: set fan to cooling level 2 */
+ cooling-device = <&fan 3 3>;
+ trip = <&cpu_trip_active_high>;
+ };
+
+ cpu-active-low {
+ /* active: set fan to cooling level 1 */
+ cooling-device = <&fan 2 2>;
+ trip = <&cpu_trip_active_med>;
+ };
+
+ cpu-passive {
+ /* passive: set fan to cooling level 0 */
+ cooling-device = <&fan 1 1>;
+ trip = <&cpu_trip_active_low>;
+ };
+ };
+};
+
+&ssusb1 {
+ status = "okay";
+};
+
+&tphy {
+ status = "okay";
+};
+
+&spi0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&spi0_flash_pins>;
+ status = "okay";
+
+ spi_nand: spi_nand@0 {
+ compatible = "spi-nand";
+ reg = <0>;
+ spi-max-frequency = <52000000>;
+ spi-tx-buswidth = <4>;
+ spi-rx-buswidth = <4>;
+ };
+};
+
+&spi_nand {
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ partition@0 {
+ label = "bl2";
+ reg = <0x0 0x200000>;
+ read-only;
+ };
+
+ partition@200000 {
+ label = "ubi";
+ reg = <0x200000 0x7e00000>;
+ compatible = "linux,ubi";
+
+ volumes {
+ ubi-volume-ubootenv {
+ volname = "ubootenv";
+ nvmem-layout {
+ compatible = "u-boot,env-redundant-bool";
+ };
+ };
+
+ ubi-volume-ubootenv2 {
+ volname = "ubootenv2";
+ nvmem-layout {
+ compatible = "u-boot,env-redundant-bool";
+ };
+ };
+
+ ubi_rootfs: ubi-volume-fit {
+ volname = "fit";
+ };
+ };
+ };
+ };
+};
+
+&serial0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0_pins>;
+ status = "okay";
+};
+
+&serial1 {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart1_2_lite_pins>;
+};
+
+&serial2 {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart2_3_pins>;
+};
+
+&watchdog {
+ status = "okay";
+};
+
+&xsphy {
+ status = "okay";
+};
--- /dev/null
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright (C) 2021 MediaTek Inc.
+ * Author: Frank Wunderlich <frank-w@public-files.de>
+ */
+
+/dts-v1/;
+/plugin/;
+
+/ {
+ compatible = "mediatek,mt7988a-rfb", "mediatek,mt7988a";
+
+ fragment@0 {
+ target = <&mmc0>;
+ __overlay__ {
+ pinctrl-names = "default", "state_uhs";
+ pinctrl-0 = <&mmc0_pins_emmc_51>;
+ pinctrl-1 = <&mmc0_pins_emmc_51>;
+ bus-width = <8>;
+ max-frequency = <200000000>;
+ cap-mmc-highspeed;
+ mmc-hs200-1_8v;
+ mmc-hs400-1_8v;
+ hs400-ds-delay = <0x12814>;
+ vqmmc-supply = <®_1p8v>;
+ vmmc-supply = <®_3p3v>;
+ non-removable;
+ no-sd;
+ no-sdio;
+ status = "okay";
+ };
+ };
+};
--- /dev/null
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright (C) 2022 MediaTek Inc.
+ * Author: Sam.Shih <sam.shih@mediatek.com>
+ */
+
+/dts-v1/;
+/plugin/;
+
+#include <dt-bindings/gpio/gpio.h>
+
+/ {
+ compatible = "mediatek,mt7988a-rfb", "mediatek,mt7988a";
+
+ fragment@0 {
+ target = <&mdio_bus>;
+ __overlay__ {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ /* external Aquantia AQR113C */
+ phy0: ethernet-phy@0 {
+ reg = <0>;
+ compatible = "ethernet-phy-ieee802.3-c45";
+ firmware-name = "AQR-G4_v5.7.0-AQR_EVB_Generic_X3410_StdCfg_MDISwap_USX_ID46316_VER2140.cld";
+ reset-gpios = <&pio 72 GPIO_ACTIVE_LOW>;
+ reset-assert-us = <100000>;
+ reset-deassert-us = <221000>;
+ };
+ };
+ };
+
+ fragment@1 {
+ target = <&gmac1>;
+ __overlay__ {
+ phy-mode = "usxgmii";
+ phy-connection-type = "usxgmii";
+ phy = <&phy0>;
+ status = "okay";
+ };
+ };
+};
--- /dev/null
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright (C) 2022 MediaTek Inc.
+ * Author: Sam.Shih <sam.shih@mediatek.com>
+ */
+
+/dts-v1/;
+/plugin/;
+
+/ {
+ compatible = "mediatek,mt7988a-rfb", "mediatek,mt7988a";
+
+ fragment@0 {
+ target = <&gmac1>;
+ __overlay__ {
+ phy-mode = "internal";
+ phy-connection-type = "internal";
+ phy = <&int_2p5g_phy>;
+ status = "okay";
+ };
+ };
+
+ fragment@1 {
+ target = <&int_2p5g_phy>;
+ __overlay__ {
+ pinctrl-names = "i2p5gbe-led";
+ pinctrl-0 = <&i2p5gbe_led0_pins>;
+ };
+ };
+};
--- /dev/null
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright (C) 2022 MediaTek Inc.
+ * Author: Sam.Shih <sam.shih@mediatek.com>
+ */
+
+/dts-v1/;
+/plugin/;
+
+#include <dt-bindings/gpio/gpio.h>
+
+/ {
+ compatible = "mediatek,mt7988a-rfb", "mediatek,mt7988a";
+
+ fragment@0 {
+ target = <&mdio_bus>;
+ __overlay__ {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ /* external Maxlinear GPY211C */
+ phy13: ethernet-phy@13 {
+ reg = <13>;
+ compatible = "ethernet-phy-ieee802.3-c45";
+ phy-mode = "2500base-x";
+ };
+ };
+ };
+
+ fragment@1 {
+ target = <&gmac1>;
+ __overlay__ {
+ phy-mode = "2500base-x";
+ phy-connection-type = "2500base-x";
+ phy = <&phy13>;
+ status = "okay";
+ };
+ };
+};
--- /dev/null
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright (C) 2022 MediaTek Inc.
+ * Author: Sam.Shih <sam.shih@mediatek.com>
+ */
+
+/dts-v1/;
+/plugin/;
+
+#include <dt-bindings/gpio/gpio.h>
+
+/ {
+ compatible = "mediatek,mt7988a-rfb", "mediatek,mt7988a";
+
+ fragment@0 {
+ target = <&i2c2>;
+ __overlay__ {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c2_0_pins>;
+ status = "okay";
+ };
+ };
+
+ fragment@1 {
+ target-path = "/";
+ __overlay__ {
+ sfp_esp1: sfp@1 {
+ compatible = "sff,sfp";
+ i2c-bus = <&i2c2>;
+ mod-def0-gpios = <&pio 82 GPIO_ACTIVE_LOW>;
+ los-gpios = <&pio 81 GPIO_ACTIVE_HIGH>;
+ tx-disable-gpios = <&pio 36 GPIO_ACTIVE_HIGH>;
+ maximum-power-milliwatt = <3000>;
+ };
+ };
+ };
+
+ fragment@2 {
+ target = <&gmac1>;
+ __overlay__ {
+ phy-mode = "10gbase-r";
+ managed = "in-band-status";
+ sfp = <&sfp_esp1>;
+ status = "okay";
+ };
+ };
+};
--- /dev/null
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright (C) 2022 MediaTek Inc.
+ * Author: Sam.Shih <sam.shih@mediatek.com>
+ */
+
+/dts-v1/;
+/plugin/;
+
+#include <dt-bindings/gpio/gpio.h>
+
+/ {
+ compatible = "mediatek,mt7988a-rfb", "mediatek,mt7988a";
+
+ fragment@0 {
+ target = <&mdio_bus>;
+ __overlay__ {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ /* external Aquantia AQR113C */
+ phy8: ethernet-phy@8 {
+ reg = <8>;
+ compatible = "ethernet-phy-ieee802.3-c45";
+ firmware-name = "AQR-G4_v5.7.0-AQR_EVB_Generic_X3410_StdCfg_MDISwap_USX_ID46316_VER2140.cld";
+ reset-gpios = <&pio 71 GPIO_ACTIVE_LOW>;
+ reset-assert-us = <100000>;
+ reset-deassert-us = <221000>;
+ };
+ };
+ };
+
+ fragment@1 {
+ target = <&gmac2>;
+ __overlay__ {
+ phy-mode = "usxgmii";
+ phy-connection-type = "usxgmii";
+ phy = <&phy8>;
+ status = "okay";
+ };
+ };
+};
--- /dev/null
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright (C) 2022 MediaTek Inc.
+ * Author: Sam.Shih <sam.shih@mediatek.com>
+ */
+
+/dts-v1/;
+/plugin/;
+
+#include <dt-bindings/gpio/gpio.h>
+
+/ {
+ compatible = "mediatek,mt7988a-rfb", "mediatek,mt7988a";
+
+ fragment@0 {
+ target = <&mdio_bus>;
+ __overlay__ {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ /* external Maxlinear GPY211C */
+ phy5: ethernet-phy@5 {
+ reg = <5>;
+ compatible = "ethernet-phy-ieee802.3-c45";
+ phy-mode = "2500base-x";
+ };
+ };
+ };
+
+ fragment@1 {
+ target = <&gmac2>;
+ __overlay__ {
+ phy-mode = "2500base-x";
+ phy-connection-type = "2500base-x";
+ phy = <&phy5>;
+ status = "okay";
+ };
+ };
+};
--- /dev/null
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright (C) 2022 MediaTek Inc.
+ * Author: Sam.Shih <sam.shih@mediatek.com>
+ */
+
+/dts-v1/;
+/plugin/;
+
+#include <dt-bindings/gpio/gpio.h>
+
+/ {
+ compatible = "mediatek,mt7988a-rfb", "mediatek,mt7988a";
+
+ fragment@0 {
+ target = <&i2c1>;
+ __overlay__ {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c1_sfp_pins>;
+ status = "okay";
+ };
+ };
+
+ fragment@1 {
+ target-path = "/";
+ __overlay__ {
+ sfp_esp0: sfp@0 {
+ compatible = "sff,sfp";
+ i2c-bus = <&i2c1>;
+ mod-def0-gpios = <&pio 35 GPIO_ACTIVE_LOW>;
+ los-gpios = <&pio 33 GPIO_ACTIVE_HIGH>;
+ tx-disable-gpios = <&pio 29 GPIO_ACTIVE_HIGH>;
+ maximum-power-milliwatt = <3000>;
+ };
+ };
+ };
+
+ fragment@2 {
+ target = <&gmac2>;
+ __overlay__ {
+ phy-mode = "10gbase-r";
+ managed = "in-band-status";
+ sfp = <&sfp_esp0>;
+ status = "okay";
+ };
+ };
+};
--- /dev/null
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright (C) 2023 MediaTek Inc.
+ * Author: Frank Wunderlich <frank-w@public-files.de>
+ */
+
+/dts-v1/;
+/plugin/;
+
+#include <dt-bindings/gpio/gpio.h>
+
+/ {
+ compatible = "mediatek,mt7988a-rfb", "mediatek,mt7988a";
+
+ fragment@1 {
+ target-path = <&mmc0>;
+ __overlay__ {
+ pinctrl-names = "default", "state_uhs";
+ pinctrl-0 = <&mmc0_pins_sdcard>;
+ pinctrl-1 = <&mmc0_pins_sdcard>;
+ cd-gpios = <&pio 69 GPIO_ACTIVE_LOW>;
+ bus-width = <4>;
+ max-frequency = <52000000>;
+ cap-sd-highspeed;
+ vmmc-supply = <®_3p3v>;
+ vqmmc-supply = <®_3p3v>;
+ no-mmc;
+ status = "okay";
+ };
+ };
+};
--- /dev/null
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright (C) 2022 MediaTek Inc.
+ * Author: Sam.Shih <sam.shih@mediatek.com>
+ */
+
+/dts-v1/;
+/plugin/;
+
+/ {
+ compatible = "mediatek,mt7988a-rfb", "mediatek,mt7988a";
+
+ fragment@0 {
+ target = <&snand>;
+ __overlay__ {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "okay";
+
+ flash@0 {
+ compatible = "spi-nand";
+ reg = <0>;
+ spi-max-frequency = <52000000>;
+ spi-tx-bus-width = <4>;
+ spi-rx-bus-width = <4>;
+ mediatek,nmbm;
+ mediatek,bmt-max-ratio = <1>;
+ mediatek,bmt-max-reserved-blocks = <64>;
+
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ partition@0 {
+ label = "BL2";
+ reg = <0x00000 0x0100000>;
+ read-only;
+ };
+
+ partition@100000 {
+ label = "u-boot-env";
+ reg = <0x0100000 0x0080000>;
+ };
+
+ partition@180000 {
+ label = "Factory";
+ reg = <0x180000 0x0400000>;
+ };
+
+ partition@580000 {
+ label = "FIP";
+ reg = <0x580000 0x0200000>;
+ };
+
+ partition@780000 {
+ label = "ubi";
+ reg = <0x780000 0x7080000>;
+ };
+ };
+ };
+ };
+ };
+
+ fragment@1 {
+ target = <&bch>;
+ __overlay__ {
+ status = "okay";
+ };
+ };
+};
--- /dev/null
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+
+/dts-v1/;
+/plugin/;
+
+/ {
+ compatible = "mediatek,mt7988a-rfb", "mediatek,mt7988a";
+
+ fragment@0 {
+ target = <&ubi_part>;
+
+ __overlay__ {
+ volumes {
+ ubi_factory: ubi-volume-factory {
+ volname = "factory";
+
+ nvmem-layout {
+ compatible = "fixed-layout";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ eeprom_wmac: eeprom@0 {
+ reg = <0x0 0x1e00>;
+ };
+
+ gmac2_mac: eeprom@fffee {
+ reg = <0xfffee 0x6>;
+ };
+
+ gmac1_mac: eeprom@ffff4 {
+ reg = <0xffff4 0x6>;
+ };
+
+ gmac0_mac: eeprom@ffffa {
+ reg = <0xffffa 0x6>;
+ };
+ };
+ };
+ };
+ };
+ };
+
+ fragment@1 {
+ target = <&pcie0>;
+ __overlay__ {
+ #address-cells = <3>;
+ #size-cells = <2>;
+
+ pcie@0,0 {
+ #address-cells = <3>;
+ #size-cells = <2>;
+ reg = <0x0000 0 0 0 0>;
+
+ wifi@0,0 {
+ compatible = "mediatek,mt76";
+ reg = <0x0000 0 0 0 0>;
+ nvmem-cell-names = "eeprom";
+ nvmem-cells = <&eeprom_wmac>;
+ };
+ };
+ };
+ };
+
+ fragment@2 {
+ target = <&gmac0>;
+ __overlay__ {
+ nvmem-cell-names = "mac-address";
+ nvmem-cells = <&gmac0_mac>;
+ };
+ };
+
+ fragment@3 {
+ target = <&gmac1>;
+ __overlay__ {
+ nvmem-cell-names = "mac-address";
+ nvmem-cells = <&gmac1_mac>;
+ };
+ };
+
+ fragment@4 {
+ target = <&gmac2>;
+ __overlay__ {
+ nvmem-cell-names = "mac-address";
+ nvmem-cells = <&gmac2_mac>;
+ };
+ };
+};
--- /dev/null
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright (C) 2022 MediaTek Inc.
+ * Author: Sam.Shih <sam.shih@mediatek.com>
+ */
+
+/dts-v1/;
+/plugin/;
+
+/ {
+ compatible = "mediatek,mt7988a-rfb", "mediatek,mt7988a";
+
+ fragment@0 {
+ target = <&spi0>;
+ __overlay__ {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&spi0_flash_pins>;
+ status = "okay";
+
+ flash@0 {
+ compatible = "spi-nand";
+ reg = <0>;
+ spi-max-frequency = <52000000>;
+ spi-tx-bus-width = <4>;
+ spi-rx-bus-width = <4>;
+
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ partition@0 {
+ label = "BL2";
+ reg = <0x00000 0x0200000>;
+ read-only;
+ };
+
+ ubi_part: partition@200000 {
+ label = "ubi";
+ reg = <0x0200000 0x7e00000>;
+ compatible = "linux,ubi";
+
+ volumes {
+ ubi-volume-ubootenv {
+ volname = "ubootenv";
+ nvmem-layout {
+ compatible = "u-boot,env-redundant-bool";
+ };
+ };
+
+ ubi-volume-ubootenv2 {
+ volname = "ubootenv2";
+ nvmem-layout {
+ compatible = "u-boot,env-redundant-bool";
+ };
+ };
+
+ ubi_root: ubi-volume-fit {
+ volname = "fit";
+ };
+
+ };
+ };
+ };
+ };
+ };
+ };
+
+ fragment@1 {
+ target-path = "/chosen";
+ __overlay__ {
+ rootdisk-spim-nand = <&ubi_root>;
+ };
+ };
+};
--- /dev/null
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright (C) 2022 MediaTek Inc.
+ * Author: Sam.Shih <sam.shih@mediatek.com>
+ */
+
+/dts-v1/;
+/plugin/;
+
+/ {
+ compatible = "mediatek,mt7988a-rfb", "mediatek,mt7988a";
+
+ fragment@0 {
+ target = <&spi2>;
+ __overlay__ {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&spi2_flash_pins>;
+ status = "okay";
+
+ flash@0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "jedec,spi-nor";
+ spi-cal-enable;
+ spi-cal-mode = "read-data";
+ spi-cal-datalen = <7>;
+ spi-cal-data = /bits/ 8 <
+ 0x53 0x46 0x5F 0x42 0x4F 0x4F 0x54>; /* SF_BOOT */
+ spi-cal-addrlen = <1>;
+ spi-cal-addr = /bits/ 32 <0x0>;
+ reg = <0>;
+ spi-max-frequency = <52000000>;
+ spi-tx-bus-width = <4>;
+ spi-rx-bus-width = <4>;
+
+ partition@0 {
+ label = "BL2";
+ reg = <0x00000 0x0040000>;
+ };
+ partition@40000 {
+ label = "u-boot-env";
+ reg = <0x40000 0x0010000>;
+ };
+ partition@50000 {
+ label = "Factory";
+ reg = <0x50000 0x0200000>;
+ };
+ partition@250000 {
+ label = "FIP";
+ reg = <0x250000 0x0080000>;
+ };
+ partition@2D0000 {
+ label = "firmware";
+ reg = <0x2D0000 0x1D30000>;
+ };
+ };
+ };
+ };
+};
--- /dev/null
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright (C) 2022 MediaTek Inc.
+ * Author: Sam.Shih <sam.shih@mediatek.com>
+ */
+
+/dts-v1/;
+#include "mt7988a.dtsi"
+#include <dt-bindings/pinctrl/mt65xx.h>
+#include <dt-bindings/leds/common.h>
+#include <dt-bindings/regulator/richtek,rt5190a-regulator.h>
+
+/ {
+ model = "MediaTek MT7988A Reference Board";
+ compatible = "mediatek,mt7988a-rfb",
+ "mediatek,mt7988a";
+
+ chosen {
+ bootargs = "console=ttyS0,115200n1 loglevel=8 \
+ earlycon=uart8250,mmio32,0x11000000 \
+ pci=pcie_bus_perf";
+ };
+
+ memory {
+ reg = <0 0x40000000 0 0x40000000>;
+ };
+
+ reg_1p8v: regulator-1p8v {
+ compatible = "regulator-fixed";
+ regulator-name = "fixed-1.8V";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ reg_3p3v: regulator-3p3v {
+ compatible = "regulator-fixed";
+ regulator-name = "fixed-3.3V";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+};
+
+&pio {
+ mdio0_pins: mdio0-pins {
+ mux {
+ function = "eth";
+ groups = "mdc_mdio0";
+ };
+
+ conf {
+ groups = "mdc_mdio0";
+ drive-strength = <MTK_DRIVE_8mA>;
+ };
+ };
+
+ gbe0_led0_pins: gbe0-led0-pins {
+ mux {
+ function = "led";
+ groups = "gbe0_led0";
+ };
+ };
+
+ gbe1_led0_pins: gbe1-led0-pins {
+ mux {
+ function = "led";
+ groups = "gbe1_led0";
+ };
+ };
+
+ gbe2_led0_pins: gbe2-led0-pins {
+ mux {
+ function = "led";
+ groups = "gbe2_led0";
+ };
+ };
+
+ gbe3_led0_pins: gbe3-led0-pins {
+ mux {
+ function = "led";
+ groups = "gbe3_led0";
+ };
+ };
+
+ i2c1_sfp_pins: i2c1-sfp-pins-g0 {
+ mux {
+ function = "i2c";
+ groups = "i2c1_sfp";
+ };
+ };
+
+ i2c2_0_pins: i2c2-pins-g0 {
+ mux {
+ function = "i2c";
+ groups = "i2c2_0";
+ };
+ };
+
+ i2c0_pins: i2c0-pins-g0 {
+ mux {
+ function = "i2c";
+ groups = "i2c0_1";
+ };
+ };
+
+ i2c1_pins: i2c1-pins-g0 {
+ mux {
+ function = "i2c";
+ groups = "i2c1_0";
+ };
+ };
+
+ i2p5gbe_led0_pins: 2p5gbe-led0-pins {
+ mux {
+ function = "led";
+ groups = "2p5gbe_led0";
+ };
+ };
+
+ mmc0_pins_emmc_51: mmc0-pins-emmc-51 {
+ mux {
+ function = "flash";
+ groups = "emmc_51";
+ };
+ };
+
+ mmc0_pins_sdcard: mmc0-pins-sdcard {
+ mux {
+ function = "flash";
+ groups = "sdcard";
+ };
+ };
+
+ uart0_pins: uart0-pins {
+ mux {
+ function = "uart";
+ groups = "uart0";
+ };
+ };
+
+ spi0_flash_pins: spi0-flash-pins {
+ mux {
+ function = "spi";
+ groups = "spi0", "spi0_wp_hold";
+ };
+ };
+
+ spi1_pins: spi1-pins {
+ mux {
+ function = "spi";
+ groups = "spi1";
+ };
+ };
+};
+
+ð {
+ pinctrl-0 = <&mdio0_pins>;
+ pinctrl-names = "default";
+};
+
+&gmac0 {
+ status = "okay";
+};
+
+&cpu0 {
+ proc-supply = <&rt5190_buck3>;
+};
+
+&cpu1 {
+ proc-supply = <&rt5190_buck3>;
+};
+
+&cpu2 {
+ proc-supply = <&rt5190_buck3>;
+};
+
+&cpu3 {
+ proc-supply = <&rt5190_buck3>;
+};
+
+&cci {
+ proc-supply = <&rt5190_buck3>;
+};
+
+ð {
+ status = "okay";
+};
+
+&switch {
+ status = "okay";
+};
+
+&gsw_phy0 {
+ pinctrl-names = "gbe-led";
+ pinctrl-0 = <&gbe0_led0_pins>;
+};
+
+&gsw_port0 {
+ label = "lan0";
+};
+
+&gsw_phy0_led0 {
+ status = "okay";
+ function = LED_FUNCTION_LAN;
+ color = <LED_COLOR_ID_GREEN>;
+};
+
+&gsw_phy1 {
+ pinctrl-names = "gbe-led";
+ pinctrl-0 = <&gbe1_led0_pins>;
+};
+
+&gsw_port1 {
+ label = "lan1";
+};
+
+&gsw_phy1_led0 {
+ status = "okay";
+ function = LED_FUNCTION_LAN;
+ color = <LED_COLOR_ID_GREEN>;
+};
+
+&gsw_phy2 {
+ pinctrl-names = "gbe-led";
+ pinctrl-0 = <&gbe2_led0_pins>;
+};
+
+&gsw_port2 {
+ label = "lan2";
+};
+
+&gsw_phy2_led0 {
+ status = "okay";
+ function = LED_FUNCTION_LAN;
+ color = <LED_COLOR_ID_GREEN>;
+};
+
+&gsw_phy3 {
+ pinctrl-names = "gbe-led";
+ pinctrl-0 = <&gbe3_led0_pins>;
+};
+
+&gsw_port3 {
+ label = "lan3";
+};
+
+&gsw_phy3_led0 {
+ status = "okay";
+ function = LED_FUNCTION_LAN;
+ color = <LED_COLOR_ID_GREEN>;
+};
+
+&i2c0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c0_pins>;
+ status = "okay";
+
+ rt5190a_64: rt5190a@64 {
+ compatible = "richtek,rt5190a";
+ reg = <0x64>;
+ /*interrupts-extended = <&gpio26 0 IRQ_TYPE_LEVEL_LOW>;*/
+ vin2-supply = <&rt5190_buck1>;
+ vin3-supply = <&rt5190_buck1>;
+ vin4-supply = <&rt5190_buck1>;
+
+ regulators {
+ rt5190_buck1: buck1 {
+ regulator-name = "rt5190a-buck1";
+ regulator-min-microvolt = <5090000>;
+ regulator-max-microvolt = <5090000>;
+ regulator-allowed-modes =
+ <RT5190A_OPMODE_AUTO RT5190A_OPMODE_FPWM>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+ buck2 {
+ regulator-name = "vcore";
+ regulator-min-microvolt = <600000>;
+ regulator-max-microvolt = <1400000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+ rt5190_buck3: buck3 {
+ regulator-name = "vproc";
+ regulator-min-microvolt = <600000>;
+ regulator-max-microvolt = <1400000>;
+ regulator-boot-on;
+ };
+ buck4 {
+ regulator-name = "rt5190a-buck4";
+ regulator-min-microvolt = <850000>;
+ regulator-max-microvolt = <850000>;
+ regulator-allowed-modes =
+ <RT5190A_OPMODE_AUTO RT5190A_OPMODE_FPWM>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+ ldo {
+ regulator-name = "rt5190a-ldo";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+ };
+ };
+};
+
+&pcie0 {
+ status = "okay";
+};
+
+&pcie1 {
+ status = "okay";
+};
+
+&pcie2 {
+ status = "disabled";
+};
+
+&pcie3 {
+ status = "okay";
+};
+
+&ssusb0 {
+ status = "okay";
+};
+
+&ssusb1 {
+ status = "okay";
+};
+
+&tphy {
+ status = "okay";
+};
+
+&serial0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0_pins>;
+ status = "okay";
+};
+
+&watchdog {
+ status = "okay";
+};
+
+&xsphy {
+ status = "okay";
+};
--- /dev/null
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright (C) 2023 MediaTek Inc.
+ * Author: Sam.Shih <sam.shih@mediatek.com>
+ */
+
+#include <dt-bindings/clock/mediatek,mt7988-clk.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/leds/common.h>
+#include <dt-bindings/phy/phy.h>
+#include <dt-bindings/pinctrl/mt65xx.h>
+#include <dt-bindings/reset/mediatek,mt7988-resets.h>
+#include <dt-bindings/thermal/thermal.h>
+
+/* TOPRGU resets */
+#define MT7988_TOPRGU_SGMII0_GRST 1
+#define MT7988_TOPRGU_SGMII1_GRST 2
+#define MT7988_TOPRGU_XFI0_GRST 12
+#define MT7988_TOPRGU_XFI1_GRST 13
+#define MT7988_TOPRGU_XFI_PEXTP0_GRST 14
+#define MT7988_TOPRGU_XFI_PEXTP1_GRST 15
+#define MT7988_TOPRGU_XFI_PLL_GRST 16
+
+/ {
+ compatible = "mediatek,mt7988a";
+ interrupt-parent = <&gic>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ cci: cci {
+ compatible = "mediatek,mt7988-cci",
+ "mediatek,mt8183-cci";
+ clocks = <&mcusys CLK_MCU_BUS_DIV_SEL>,
+ <&topckgen CLK_TOP_XTAL>;
+ clock-names = "cci", "intermediate";
+ operating-points-v2 = <&cci_opp>;
+ };
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu0: cpu@0 {
+ compatible = "arm,cortex-a73";
+ reg = <0x0>;
+ device_type = "cpu";
+ enable-method = "psci";
+ clocks = <&mcusys CLK_MCU_ARM_DIV_SEL>,
+ <&topckgen CLK_TOP_XTAL>;
+ clock-names = "cpu", "intermediate";
+ operating-points-v2 = <&cluster0_opp>;
+ mediatek,cci = <&cci>;
+ };
+
+ cpu1: cpu@1 {
+ compatible = "arm,cortex-a73";
+ reg = <0x1>;
+ device_type = "cpu";
+ enable-method = "psci";
+ clocks = <&mcusys CLK_MCU_ARM_DIV_SEL>,
+ <&topckgen CLK_TOP_XTAL>;
+ clock-names = "cpu", "intermediate";
+ operating-points-v2 = <&cluster0_opp>;
+ mediatek,cci = <&cci>;
+ };
+
+ cpu2: cpu@2 {
+ compatible = "arm,cortex-a73";
+ reg = <0x2>;
+ device_type = "cpu";
+ enable-method = "psci";
+ clocks = <&mcusys CLK_MCU_ARM_DIV_SEL>,
+ <&topckgen CLK_TOP_XTAL>;
+ clock-names = "cpu", "intermediate";
+ operating-points-v2 = <&cluster0_opp>;
+ mediatek,cci = <&cci>;
+ };
+
+ cpu3: cpu@3 {
+ compatible = "arm,cortex-a73";
+ reg = <0x3>;
+ device_type = "cpu";
+ enable-method = "psci";
+ clocks = <&mcusys CLK_MCU_ARM_DIV_SEL>,
+ <&topckgen CLK_TOP_XTAL>;
+ clock-names = "cpu", "intermediate";
+ operating-points-v2 = <&cluster0_opp>;
+ mediatek,cci = <&cci>;
+ };
+
+ cluster0_opp: opp_table0 {
+ compatible = "operating-points-v2";
+ opp-shared;
+
+ opp00 {
+ opp-hz = /bits/ 64 <800000000>;
+ opp-microvolt = <850000>;
+ };
+
+ opp01 {
+ opp-hz = /bits/ 64 <1100000000>;
+ opp-microvolt = <850000>;
+ };
+
+ opp02 {
+ opp-hz = /bits/ 64 <1500000000>;
+ opp-microvolt = <850000>;
+ };
+
+ opp03 {
+ opp-hz = /bits/ 64 <1800000000>;
+ opp-microvolt = <900000>;
+ };
+ };
+ };
+
+ cci_opp: opp_table_cci {
+ compatible = "operating-points-v2";
+ opp-shared;
+
+ opp00 {
+ opp-hz = /bits/ 64 <480000000>;
+ opp-microvolt = <850000>;
+ };
+
+ opp01 {
+ opp-hz = /bits/ 64 <660000000>;
+ opp-microvolt = <850000>;
+ };
+
+ opp02 {
+ opp-hz = /bits/ 64 <900000000>;
+ opp-microvolt = <850000>;
+ };
+
+ opp03 {
+ opp-hz = /bits/ 64 <1080000000>;
+ opp-microvolt = <900000>;
+ };
+ };
+
+ clk40m: oscillator@0 {
+ compatible = "fixed-clock";
+ clock-frequency = <40000000>;
+ #clock-cells = <0>;
+ clock-output-names = "clkxtal";
+ };
+
+ pmu {
+ compatible = "arm,cortex-a73-pmu";
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
+ };
+
+ psci {
+ compatible = "arm,psci-0.2";
+ method = "smc";
+ };
+
+ reserved-memory {
+ ranges;
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ /* 320 KiB reserved for ARM Trusted Firmware (BL31 and BL32) */
+ secmon_reserved: secmon@43000000 {
+ reg = <0 0x43000000 0 0x50000>;
+ no-map;
+ };
+
+ wmcpu_emi: wmcpu-reserved@47cc0000 {
+ reg = <0 0x47cc0000 0 0x00100000>;
+ no-map;
+ };
+
+ wo_emi0: wo-emi@4f600000 {
+ reg = <0 0x4f600000 0 0x40000>;
+ no-map;
+ };
+
+ wo_emi1: wo-emi@4f640000 {
+ reg = <0 0x4f640000 0 0x40000>;
+ no-map;
+ };
+
+ wo_emi2: wo-emi@4f680000 {
+ reg = <0 0x4f680000 0 0x40000>;
+ no-map;
+ };
+
+ wo_data: wo-data@4f700000 {
+ reg = <0 0x4f700000 0 0x800000>;
+ no-map;
+ shared = <1>;
+ };
+ };
+
+ soc {
+ compatible = "simple-bus";
+ ranges;
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ gic: interrupt-controller@c000000 {
+ compatible = "arm,gic-v3";
+ reg = <0 0x0c000000 0 0x40000>, /* GICD */
+ <0 0x0c080000 0 0x200000>, /* GICR */
+ <0 0x0c400000 0 0x2000>, /* GICC */
+ <0 0x0c410000 0 0x1000>, /* GICH */
+ <0 0x0c420000 0 0x2000>; /* GICV */
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-controller;
+ #interrupt-cells = <3>;
+ };
+
+ phyfw: phy-firmware@f000000 {
+ compatible = "mediatek,2p5gphy-fw";
+ reg = <0 0x0f100000 0 0x20000>,
+ <0 0x0f0f0018 0 0x20>;
+ };
+
+ infracfg: infracfg@10001000 {
+ compatible = "mediatek,mt7988-infracfg", "syscon";
+ reg = <0 0x10001000 0 0x1000>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ };
+
+ topckgen: topckgen@1001b000 {
+ compatible = "mediatek,mt7988-topckgen", "syscon";
+ reg = <0 0x1001b000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ watchdog: watchdog@1001c000 {
+ compatible = "mediatek,mt7988-wdt",
+ "mediatek,mt6589-wdt",
+ "syscon";
+ reg = <0 0x1001c000 0 0x1000>;
+ interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
+ #reset-cells = <1>;
+ };
+
+ apmixedsys: apmixedsys@1001e000 {
+ compatible = "mediatek,mt7988-apmixedsys";
+ reg = <0 0x1001e000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ pio: pinctrl@1001f000 {
+ compatible = "mediatek,mt7988-pinctrl", "syscon";
+ reg = <0 0x1001f000 0 0x1000>,
+ <0 0x11c10000 0 0x1000>,
+ <0 0x11d00000 0 0x1000>,
+ <0 0x11d20000 0 0x1000>,
+ <0 0x11e00000 0 0x1000>,
+ <0 0x11f00000 0 0x1000>,
+ <0 0x1000b000 0 0x1000>;
+ reg-names = "gpio_base", "iocfg_tr_base",
+ "iocfg_br_base", "iocfg_rb_base",
+ "iocfg_lb_base", "iocfg_tl_base", "eint";
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&pio 0 0 84>;
+ interrupt-controller;
+ interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-parent = <&gic>;
+ #interrupt-cells = <2>;
+
+ pcie0_pins: pcie0-pins {
+ mux {
+ function = "pcie";
+ groups = "pcie_2l_0_pereset", "pcie_clk_req_n0_0",
+ "pcie_wake_n0_0";
+ };
+ };
+
+ pcie1_pins: pcie1-pins {
+ mux {
+ function = "pcie";
+ groups = "pcie_2l_1_pereset", "pcie_clk_req_n1",
+ "pcie_wake_n1_0";
+ };
+ };
+
+ pcie2_pins: pcie2-pins {
+ mux {
+ function = "pcie";
+ groups = "pcie_1l_0_pereset", "pcie_clk_req_n2_0",
+ "pcie_wake_n2_0";
+ };
+ };
+
+ pcie3_pins: pcie3-pins {
+ mux {
+ function = "pcie";
+ groups = "pcie_1l_1_pereset", "pcie_clk_req_n3",
+ "pcie_wake_n3_0";
+ };
+ };
+
+ snfi_pins: snfi-pins {
+ mux {
+ function = "flash";
+ groups = "snfi";
+ };
+ };
+ };
+
+ pwm: pwm@10048000 {
+ compatible = "mediatek,mt7988-pwm";
+ reg = <0 0x10048000 0 0x1000>;
+ #pwm-cells = <2>;
+ clocks = <&infracfg CLK_INFRA_66M_PWM_BCK>,
+ <&infracfg CLK_INFRA_66M_PWM_HCK>,
+ <&infracfg CLK_INFRA_66M_PWM_CK1>,
+ <&infracfg CLK_INFRA_66M_PWM_CK2>,
+ <&infracfg CLK_INFRA_66M_PWM_CK3>,
+ <&infracfg CLK_INFRA_66M_PWM_CK4>,
+ <&infracfg CLK_INFRA_66M_PWM_CK5>,
+ <&infracfg CLK_INFRA_66M_PWM_CK6>,
+ <&infracfg CLK_INFRA_66M_PWM_CK7>,
+ <&infracfg CLK_INFRA_66M_PWM_CK8>;
+ clock-names = "top", "main", "pwm1", "pwm2", "pwm3",
+ "pwm4","pwm5","pwm6","pwm7","pwm8";
+ status = "disabled";
+ };
+
+ sgmiisys0: syscon@10060000 {
+ compatible = "mediatek,mt7988-sgmiisys",
+ "mediatek,mt7988-sgmiisys0",
+ "syscon",
+ "simple-mfd";
+ reg = <0 0x10060000 0 0x1000>;
+ resets = <&watchdog MT7988_TOPRGU_SGMII0_GRST>;
+ #clock-cells = <1>;
+
+ sgmiipcs0: pcs {
+ compatible = "mediatek,mt7988-sgmii";
+ clocks = <&topckgen CLK_TOP_SGM_0_SEL>,
+ <&sgmiisys0 CLK_SGM0_TX_EN>,
+ <&sgmiisys0 CLK_SGM0_RX_EN>;
+ clock-names = "sgmii_sel", "sgmii_tx", "sgmii_rx";
+ };
+ };
+
+ sgmiisys1: syscon@10070000 {
+ compatible = "mediatek,mt7988-sgmiisys",
+ "mediatek,mt7988-sgmiisys1",
+ "syscon",
+ "simple-mfd";
+ reg = <0 0x10070000 0 0x1000>;
+ resets = <&watchdog MT7988_TOPRGU_SGMII1_GRST>;
+ #clock-cells = <1>;
+
+ sgmiipcs1: pcs {
+ compatible = "mediatek,mt7988-sgmii";
+ clocks = <&topckgen CLK_TOP_SGM_1_SEL>,
+ <&sgmiisys1 CLK_SGM1_TX_EN>,
+ <&sgmiisys1 CLK_SGM1_RX_EN>;
+ clock-names = "sgmii_sel", "sgmii_tx", "sgmii_rx";
+ };
+ };
+
+ usxgmiisys0: pcs@10080000 {
+ compatible = "mediatek,mt7988-usxgmiisys";
+ reg = <0 0x10080000 0 0x1000>;
+ resets = <&watchdog MT7988_TOPRGU_XFI0_GRST>;
+ clocks = <&topckgen CLK_TOP_USXGMII_SBUS_0_SEL>;
+ };
+
+ usxgmiisys1: pcs@10081000 {
+ compatible = "mediatek,mt7988-usxgmiisys";
+ reg = <0 0x10081000 0 0x1000>;
+ resets = <&watchdog MT7988_TOPRGU_XFI1_GRST>;
+ clocks = <&topckgen CLK_TOP_USXGMII_SBUS_1_SEL>;
+ };
+
+ mcusys: mcusys@100e0000 {
+ compatible = "mediatek,mt7988-mcusys", "syscon";
+ reg = <0 0x100e0000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ serial0: serial@11000000 {
+ compatible = "mediatek,mt7986-uart",
+ "mediatek,mt6577-uart";
+ reg = <0 0x11000000 0 0x100>;
+ interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
+ /*
+ * 8250-mtk driver don't control "baud" clock since commit
+ * e32a83c70cf9 (kernel v5.7), but both "baud" and "bus" clocks
+ * still need to be passed to the driver to prevent probe fail
+ */
+ clocks = <&topckgen CLK_TOP_UART_SEL>,
+ <&infracfg CLK_INFRA_52M_UART0_CK>;
+ clock-names = "baud", "bus";
+ assigned-clocks = <&topckgen CLK_TOP_UART_SEL>,
+ <&infracfg CLK_INFRA_MUX_UART0_SEL>;
+ assigned-clock-parents = <&topckgen CLK_TOP_XTAL>,
+ <&topckgen CLK_TOP_UART_SEL>;
+ status = "disabled";
+ };
+
+ serial1: serial@11000100 {
+ compatible = "mediatek,mt7986-uart",
+ "mediatek,mt6577-uart";
+ reg = <0 0x11000100 0 0x100>;
+ interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
+ /*
+ * 8250-mtk driver don't control "baud" clock since commit
+ * e32a83c70cf9 (kernel v5.7), but both "baud" and "bus" clocks
+ * still need to be passed to the driver to prevent probe fail
+ */
+ clocks = <&topckgen CLK_TOP_UART_SEL>,
+ <&infracfg CLK_INFRA_52M_UART1_CK>;
+ clock-names = "baud", "bus";
+ assigned-clocks = <&topckgen CLK_TOP_UART_SEL>,
+ <&infracfg CLK_INFRA_MUX_UART1_SEL>;
+ assigned-clock-parents = <&topckgen CLK_TOP_XTAL>,
+ <&topckgen CLK_TOP_UART_SEL>;
+ status = "disabled";
+ };
+
+ serial2: serial@11000200 {
+ compatible = "mediatek,mt7986-uart",
+ "mediatek,mt6577-uart";
+ reg = <0 0x11000200 0 0x100>;
+ interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
+ /*
+ * 8250-mtk driver don't control "baud" clock since commit
+ * e32a83c70cf9 (kernel v5.7), but both "baud" and "bus" clocks
+ * still need to be passed to the driver to prevent probe fail
+ */
+ clocks = <&topckgen CLK_TOP_UART_SEL>,
+ <&infracfg CLK_INFRA_52M_UART2_CK>;
+ clock-names = "baud", "bus";
+ assigned-clocks = <&topckgen CLK_TOP_UART_SEL>,
+ <&infracfg CLK_INFRA_MUX_UART2_SEL>;
+ assigned-clock-parents = <&topckgen CLK_TOP_XTAL>,
+ <&topckgen CLK_TOP_UART_SEL>;
+ status = "disabled";
+ };
+
+ snand: spi@11001000 {
+ compatible = "mediatek,mt7986-snand";
+ reg = <0 0x11001000 0 0x1000>;
+ interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&infracfg CLK_INFRA_SPINFI>,
+ <&infracfg CLK_INFRA_NFI>;
+ clock-names = "pad_clk", "nfi_clk";
+ assigned-clocks = <&topckgen CLK_TOP_SPINFI_SEL>,
+ <&topckgen CLK_TOP_NFI1X_SEL>;
+ assigned-clock-parents = <&topckgen CLK_TOP_MPLL_D8>,
+ <&topckgen CLK_TOP_MPLL_D8>;
+ nand-ecc-engine = <&bch>;
+ mediatek,quad-spi;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&snfi_pins>;
+ status = "disabled";
+ };
+
+ bch: ecc@11002000 {
+ compatible = "mediatek,mt7686-ecc";
+ reg = <0 0x11002000 0 0x1000>;
+ interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&topckgen CLK_TOP_NFI1X_SEL>;
+ clock-names = "nfiecc_clk";
+ status = "disabled";
+ };
+
+ i2c0: i2c@11003000 {
+ compatible = "mediatek,mt7988-i2c",
+ "mediatek,mt7981-i2c";
+ reg = <0 0x11003000 0 0x1000>,
+ <0 0x10217080 0 0x80>;
+ interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
+ clock-div = <1>;
+ clocks = <&infracfg CLK_INFRA_I2C_BCK>,
+ <&infracfg CLK_INFRA_66M_AP_DMA_BCK>;
+ clock-names = "main", "dma";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c1: i2c@11004000 {
+ compatible = "mediatek,mt7988-i2c",
+ "mediatek,mt7981-i2c";
+ reg = <0 0x11004000 0 0x1000>,
+ <0 0x10217100 0 0x80>;
+ interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
+ clock-div = <1>;
+ clocks = <&infracfg CLK_INFRA_I2C_BCK>,
+ <&infracfg CLK_INFRA_66M_AP_DMA_BCK>;
+ clock-names = "main", "dma";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c2: i2c@11005000 {
+ compatible = "mediatek,mt7988-i2c",
+ "mediatek,mt7981-i2c";
+ reg = <0 0x11005000 0 0x1000>,
+ <0 0x10217180 0 0x80>;
+ interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
+ clock-div = <1>;
+ clocks = <&infracfg CLK_INFRA_I2C_BCK>,
+ <&infracfg CLK_INFRA_66M_AP_DMA_BCK>;
+ clock-names = "main", "dma";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ spi0: spi@11007000 {
+ compatible = "mediatek,ipm-spi-quad", "mediatek,spi-ipm";
+ reg = <0 0x11007000 0 0x100>;
+ interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&topckgen CLK_TOP_MPLL_D2>,
+ <&topckgen CLK_TOP_SPI_SEL>,
+ <&infracfg CLK_INFRA_104M_SPI0>,
+ <&infracfg CLK_INFRA_66M_SPI0_HCK>;
+ clock-names = "parent-clk", "sel-clk", "spi-clk",
+ "hclk";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ spi1: spi@11008000 {
+ compatible = "mediatek,ipm-spi-single", "mediatek,spi-ipm";
+ reg = <0 0x11008000 0 0x100>;
+ interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&topckgen CLK_TOP_MPLL_D2>,
+ <&topckgen CLK_TOP_SPIM_MST_SEL>,
+ <&infracfg CLK_INFRA_104M_SPI1>,
+ <&infracfg CLK_INFRA_66M_SPI1_HCK>;
+ clock-names = "parent-clk", "sel-clk", "spi-clk",
+ "hclk";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ spi2: spi@11009000 {
+ compatible = "mediatek,ipm-spi-quad", "mediatek,spi-ipm";
+ reg = <0 0x11009000 0 0x100>;
+ interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&topckgen CLK_TOP_MPLL_D2>,
+ <&topckgen CLK_TOP_SPI_SEL>,
+ <&infracfg CLK_INFRA_104M_SPI2_BCK>,
+ <&infracfg CLK_INFRA_66M_SPI2_HCK>;
+ clock-names = "parent-clk", "sel-clk", "spi-clk",
+ "hclk";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ lvts: lvts@1100a000 {
+ compatible = "mediatek,mt7988-lvts-ap";
+ reg = <0 0x1100a000 0 0x1000>;
+ clocks = <&infracfg CLK_INFRA_26M_THERM_SYSTEM>;
+ clock-names = "lvts_clk";
+ interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
+ resets = <&infracfg MT7988_INFRA_RST1_THERM_CTRL_SWRST>;
+ nvmem-cells = <&lvts_calibration>;
+ nvmem-cell-names = "lvts-calib-data-1";
+ #thermal-sensor-cells = <1>;
+ };
+
+ ssusb0: usb@11190000 {
+ compatible = "mediatek,mt7988-xhci",
+ "mediatek,mtk-xhci";
+ reg = <0 0x11190000 0 0x2e00>,
+ <0 0x11193e00 0 0x0100>;
+ reg-names = "mac", "ippc";
+ interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
+ phys = <&xphyu2port0 PHY_TYPE_USB2>,
+ <&xphyu3port0 PHY_TYPE_USB3>;
+ clocks = <&infracfg CLK_INFRA_USB_SYS>,
+ <&infracfg CLK_INFRA_USB_XHCI>,
+ <&infracfg CLK_INFRA_USB_REF>,
+ <&infracfg CLK_INFRA_66M_USB_HCK>,
+ <&infracfg CLK_INFRA_133M_USB_HCK>;
+ clock-names = "sys_ck",
+ "xhci_ck",
+ "ref_ck",
+ "mcu_ck",
+ "dma_ck";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ mediatek,p0_speed_fixup;
+ status = "disabled";
+ };
+
+ ssusb1: usb@11200000 {
+ compatible = "mediatek,mt7988-xhci",
+ "mediatek,mtk-xhci";
+ reg = <0 0x11200000 0 0x2e00>,
+ <0 0x11203e00 0 0x0100>;
+ reg-names = "mac", "ippc";
+ interrupts = <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>;
+ phys = <&tphyu2port0 PHY_TYPE_USB2>,
+ <&tphyu3port0 PHY_TYPE_USB3>;
+ clocks = <&infracfg CLK_INFRA_USB_SYS_CK_P1>,
+ <&infracfg CLK_INFRA_USB_XHCI_CK_P1>,
+ <&infracfg CLK_INFRA_USB_CK_P1>,
+ <&infracfg CLK_INFRA_66M_USB_HCK_CK_P1>,
+ <&infracfg CLK_INFRA_133M_USB_HCK_CK_P1>;
+ clock-names = "sys_ck",
+ "xhci_ck",
+ "ref_ck",
+ "mcu_ck",
+ "dma_ck";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ status = "disabled";
+ };
+
+ afe: audio-controller@11210000 {
+ compatible = "mediatek,mt79xx-audio";
+ reg = <0 0x11210000 0 0x9000>;
+ interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&infracfg CLK_INFRA_66M_AUD_SLV_BCK>,
+ <&infracfg CLK_INFRA_AUD_26M>,
+ <&infracfg CLK_INFRA_AUD_L>,
+ <&infracfg CLK_INFRA_AUD_AUD>,
+ <&infracfg CLK_INFRA_AUD_EG2>,
+ <&topckgen CLK_TOP_AUD_SEL>,
+ <&topckgen CLK_TOP_AUD_I2S_M>;
+ clock-names = "aud_bus_ck",
+ "aud_26m_ck",
+ "aud_l_ck",
+ "aud_aud_ck",
+ "aud_eg2_ck",
+ "aud_sel",
+ "aud_i2s_m";
+ assigned-clocks = <&topckgen CLK_TOP_AUD_SEL>,
+ <&topckgen CLK_TOP_A1SYS_SEL>,
+ <&topckgen CLK_TOP_AUD_L_SEL>,
+ <&topckgen CLK_TOP_A_TUNER_SEL>;
+ assigned-clock-parents = <&apmixedsys CLK_APMIXED_APLL2>,
+ <&topckgen CLK_TOP_APLL2_D4>,
+ <&apmixedsys CLK_APMIXED_APLL2>,
+ <&topckgen CLK_TOP_APLL2_D4>;
+ status = "disabled";
+ };
+
+ mmc0: mmc@11230000 {
+ compatible = "mediatek,mt7986-mmc",
+ "mediatek,mt7981-mmc";
+ reg = <0 0x11230000 0 0x1000>,
+ <0 0x11D60000 0 0x1000>;
+ interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&infracfg CLK_INFRA_MSDC400>,
+ <&infracfg CLK_INFRA_MSDC2_HCK>,
+ <&infracfg CLK_INFRA_66M_MSDC_0_HCK>,
+ <&infracfg CLK_INFRA_133M_MSDC_0_HCK>;
+ assigned-clocks = <&topckgen CLK_TOP_EMMC_250M_SEL>,
+ <&topckgen CLK_TOP_EMMC_400M_SEL>;
+ assigned-clock-parents = <&topckgen CLK_TOP_NET1PLL_D5_D2>,
+ <&apmixedsys CLK_APMIXED_MSDCPLL>;
+ clock-names = "source",
+ "hclk",
+ "axi_cg",
+ "ahb_cg";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ pcie2: pcie@11280000 {
+ compatible = "mediatek,mt7988-pcie",
+ "mediatek,mt7986-pcie",
+ "mediatek,mt8192-pcie";
+ reg = <0 0x11280000 0 0x2000>;
+ reg-names = "pcie-mac";
+ ranges = <0x81000000 0x00 0x20000000 0x00
+ 0x20000000 0x00 0x00200000>,
+ <0x82000000 0x00 0x20200000 0x00
+ 0x20200000 0x00 0x07e00000>;
+ device_type = "pci";
+ linux,pci-domain = <3>;
+ interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>;
+ bus-range = <0x00 0xff>;
+ clocks = <&infracfg CLK_INFRA_PCIE_PIPE_P2>,
+ <&infracfg CLK_INFRA_PCIE_GFMUX_TL_P2>,
+ <&infracfg CLK_INFRA_PCIE_PERI_26M_CK_P2>,
+ <&infracfg CLK_INFRA_133M_PCIE_CK_P2>,
+ <&topckgen CLK_TOP_PEXTP_P2_SEL>;
+ clock-names = "pl_250m", "tl_26m", "peri_26m",
+ "top_133m", "pextp_clk";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pcie2_pins>;
+ phys = <&xphyu3port0 PHY_TYPE_PCIE>;
+ phy-names = "pcie-phy";
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 0x7>;
+ interrupt-map = <0 0 0 1 &pcie_intc2 0>,
+ <0 0 0 2 &pcie_intc2 1>,
+ <0 0 0 3 &pcie_intc2 2>,
+ <0 0 0 4 &pcie_intc2 3>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ status = "disabled";
+
+ pcie_intc2: interrupt-controller {
+ #address-cells = <0>;
+ #interrupt-cells = <1>;
+ interrupt-controller;
+ };
+ };
+
+ pcie3: pcie@11290000 {
+ compatible = "mediatek,mt7988-pcie",
+ "mediatek,mt7986-pcie",
+ "mediatek,mt8192-pcie";
+ reg = <0 0x11290000 0 0x2000>;
+ reg-names = "pcie-mac";
+ ranges = <0x81000000 0x00 0x28000000 0x00
+ 0x28000000 0x00 0x00200000>,
+ <0x82000000 0x00 0x28200000 0x00
+ 0x28200000 0x00 0x07e00000>;
+ device_type = "pci";
+ linux,pci-domain = <2>;
+ interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>;
+ bus-range = <0x00 0xff>;
+ clocks = <&infracfg CLK_INFRA_PCIE_PIPE_P3>,
+ <&infracfg CLK_INFRA_PCIE_GFMUX_TL_P3>,
+ <&infracfg CLK_INFRA_PCIE_PERI_26M_CK_P3>,
+ <&infracfg CLK_INFRA_133M_PCIE_CK_P3>,
+ <&topckgen CLK_TOP_PEXTP_P3_SEL>;
+ clock-names = "pl_250m", "tl_26m", "peri_26m",
+ "top_133m", "pextp_clk";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pcie3_pins>;
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 0x7>;
+ interrupt-map = <0 0 0 1 &pcie_intc3 0>,
+ <0 0 0 2 &pcie_intc3 1>,
+ <0 0 0 3 &pcie_intc3 2>,
+ <0 0 0 4 &pcie_intc3 3>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ status = "disabled";
+
+ pcie_intc3: interrupt-controller {
+ #address-cells = <0>;
+ #interrupt-cells = <1>;
+ interrupt-controller;
+ };
+ };
+
+ pcie0: pcie@11300000 {
+ compatible = "mediatek,mt7988-pcie",
+ "mediatek,mt7986-pcie",
+ "mediatek,mt8192-pcie";
+ reg = <0 0x11300000 0 0x2000>;
+ reg-names = "pcie-mac";
+ ranges = <0x81000000 0x00 0x30000000 0x00
+ 0x30000000 0x00 0x00200000>,
+ <0x82000000 0x00 0x30200000 0x00
+ 0x30200000 0x00 0x07e00000>;
+ device_type = "pci";
+ linux,pci-domain = <0>;
+ interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
+ bus-range = <0x00 0xff>;
+ clocks = <&infracfg CLK_INFRA_PCIE_PIPE_P0>,
+ <&infracfg CLK_INFRA_PCIE_GFMUX_TL_P0>,
+ <&infracfg CLK_INFRA_PCIE_PERI_26M_CK_P0>,
+ <&infracfg CLK_INFRA_133M_PCIE_CK_P0>,
+ <&topckgen CLK_TOP_PEXTP_P0_SEL>;
+ clock-names = "pl_250m", "tl_26m", "peri_26m",
+ "top_133m", "pextp_clk";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pcie0_pins>;
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 0x7>;
+ interrupt-map = <0 0 0 1 &pcie_intc0 0>,
+ <0 0 0 2 &pcie_intc0 1>,
+ <0 0 0 3 &pcie_intc0 2>,
+ <0 0 0 4 &pcie_intc0 3>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ status = "disabled";
+
+ pcie_intc0: interrupt-controller {
+ #address-cells = <0>;
+ #interrupt-cells = <1>;
+ interrupt-controller;
+ };
+ };
+
+ pcie1: pcie@11310000 {
+ compatible = "mediatek,mt7988-pcie",
+ "mediatek,mt7986-pcie",
+ "mediatek,mt8192-pcie";
+ reg = <0 0x11310000 0 0x2000>;
+ reg-names = "pcie-mac";
+ ranges = <0x81000000 0x00 0x38000000 0x00
+ 0x38000000 0x00 0x00200000>,
+ <0x82000000 0x00 0x38200000 0x00
+ 0x38200000 0x00 0x07e00000>;
+ device_type = "pci";
+ linux,pci-domain = <1>;
+ interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
+ bus-range = <0x00 0xff>;
+ clocks = <&infracfg CLK_INFRA_PCIE_PIPE_P1>,
+ <&infracfg CLK_INFRA_PCIE_GFMUX_TL_P1>,
+ <&infracfg CLK_INFRA_PCIE_PERI_26M_CK_P1>,
+ <&infracfg CLK_INFRA_133M_PCIE_CK_P1>,
+ <&topckgen CLK_TOP_PEXTP_P1_SEL>;
+ clock-names = "pl_250m", "tl_26m", "peri_26m",
+ "top_133m", "pextp_clk";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pcie1_pins>;
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 0x7>;
+ interrupt-map = <0 0 0 1 &pcie_intc1 0>,
+ <0 0 0 2 &pcie_intc1 1>,
+ <0 0 0 3 &pcie_intc1 2>,
+ <0 0 0 4 &pcie_intc1 3>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ status = "disabled";
+
+ pcie_intc1: interrupt-controller {
+ #address-cells = <0>;
+ #interrupt-cells = <1>;
+ interrupt-controller;
+ };
+ };
+
+ tphy: tphy@11c50000 {
+ compatible = "mediatek,mt7988",
+ "mediatek,generic-tphy-v2";
+ ranges;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ status = "disabled";
+
+ tphyu2port0: usb-phy@11c50000 {
+ reg = <0 0x11c50000 0 0x700>;
+ clocks = <&infracfg CLK_INFRA_USB_UTMI_CK_P1>;
+ clock-names = "ref";
+ #phy-cells = <1>;
+ };
+
+ tphyu3port0: usb-phy@11c50700 {
+ reg = <0 0x11c50700 0 0x900>;
+ clocks = <&infracfg CLK_INFRA_USB_PIPE_CK_P1>;
+ clock-names = "ref";
+ #phy-cells = <1>;
+ mediatek,usb3-pll-ssc-delta;
+ mediatek,usb3-pll-ssc-delta1;
+ };
+ };
+
+ topmisc: topmisc@11d10000 {
+ compatible = "mediatek,mt7988-topmisc", "syscon",
+ "mediatek,mt7988-power-controller";
+ reg = <0 0x11d10000 0 0x10000>;
+ #clock-cells = <1>;
+ #power-domain-cells = <1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ xsphy: xphy@11e10000 {
+ compatible = "mediatek,mt7988",
+ "mediatek,xsphy";
+ ranges;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ status = "disabled";
+
+ xphyu2port0: usb-phy@11e10000 {
+ reg = <0 0x11e10000 0 0x400>;
+ clocks = <&infracfg CLK_INFRA_USB_UTMI>;
+ clock-names = "ref";
+ #phy-cells = <1>;
+ };
+
+ xphyu3port0: usb-phy@11e13000 {
+ reg = <0 0x11e13400 0 0x500>;
+ clocks = <&infracfg CLK_INFRA_USB_PIPE>;
+ clock-names = "ref";
+ #phy-cells = <1>;
+ mediatek,syscon-type = <&topmisc 0x218 0>;
+ };
+ };
+
+ xfi_tphy0: phy@11f20000 {
+ compatible = "mediatek,mt7988-xfi-tphy";
+ reg = <0 0x11f20000 0 0x10000>;
+ resets = <&watchdog MT7988_TOPRGU_XFI_PEXTP0_GRST>;
+ clocks = <&xfi_pll CLK_XFIPLL_PLL_EN>, <&topckgen CLK_TOP_XFI_PHY_0_XTAL_SEL>;
+ clock-names = "xfipll", "topxtal";
+ mediatek,usxgmii-performance-errata;
+ #phy-cells = <0>;
+ };
+
+ xfi_tphy1: phy@11f30000 {
+ compatible = "mediatek,mt7988-xfi-tphy";
+ reg = <0 0x11f30000 0 0x10000>;
+ resets = <&watchdog MT7988_TOPRGU_XFI_PEXTP1_GRST>;
+ clocks = <&xfi_pll CLK_XFIPLL_PLL_EN>, <&topckgen CLK_TOP_XFI_PHY_1_XTAL_SEL>;
+ clock-names = "xfipll", "topxtal";
+ #phy-cells = <0>;
+ };
+
+ xfi_pll: clock-controller@11f40000 {
+ compatible = "mediatek,mt7988-xfi-pll";
+ reg = <0 0x11f40000 0 0x1000>;
+ resets = <&watchdog MT7988_TOPRGU_XFI_PLL_GRST>;
+ #clock-cells = <1>;
+ };
+
+ efuse: efuse@11f50000 {
+ compatible = "mediatek,efuse";
+ reg = <0 0x11f50000 0 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ lvts_calibration: calib@918 {
+ reg = <0x918 0x28>;
+ };
+
+ phy_calibration_p0: calib@940 {
+ reg = <0x940 0x10>;
+ };
+
+ phy_calibration_p1: calib@954 {
+ reg = <0x954 0x10>;
+ };
+
+ phy_calibration_p2: calib@968 {
+ reg = <0x968 0x10>;
+ };
+
+ phy_calibration_p3: calib@97c {
+ reg = <0x97c 0x10>;
+ };
+
+ cpufreq_calibration: calib@278 {
+ reg = <0x278 0x1>;
+ };
+ };
+
+ ethsys: syscon@15000000 {
+ compatible = "mediatek,mt7988-ethsys", "syscon";
+ reg = <0 0x15000000 0 0x1000>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ };
+
+ wed0: wed@15010000 {
+ compatible = "mediatek,mt7988-wed",
+ "syscon";
+ reg = <0 0x15010000 0 0x2000>;
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>;
+ memory-region = <&wo_emi0>, <&wo_data>;
+ memory-region-names = "wo-emi", "wo-data";
+ mediatek,wo-ccif = <&wo_ccif0>;
+ mediatek,wo-ilm = <&wo_ilm0>;
+ mediatek,wo-dlm = <&wo_dlm0>;
+ mediatek,wo-cpuboot = <&wo_cpuboot0>;
+ };
+
+ wed1: wed@15012000 {
+ compatible = "mediatek,mt7988-wed",
+ "syscon";
+ reg = <0 0x15012000 0 0x2000>;
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>;
+ memory-region = <&wo_emi1>, <&wo_data>;
+ memory-region-names = "wo-emi", "wo-data";
+ mediatek,wo-ccif = <&wo_ccif1>;
+ mediatek,wo-ilm = <&wo_ilm1>;
+ mediatek,wo-dlm = <&wo_dlm1>;
+ mediatek,wo-cpuboot = <&wo_cpuboot1>;
+ };
+
+ wed2: wed@15014000 {
+ compatible = "mediatek,mt7988-wed",
+ "syscon";
+ reg = <0 0x15014000 0 0x2000>;
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH>;
+ memory-region = <&wo_emi2>, <&wo_data>;
+ memory-region-names = "wo-emi", "wo-data";
+ mediatek,wo-ccif = <&wo_ccif2>;
+ mediatek,wo-ilm = <&wo_ilm2>;
+ mediatek,wo-dlm = <&wo_dlm2>;
+ mediatek,wo-cpuboot = <&wo_cpuboot2>;
+ };
+
+ switch: switch@15020000 {
+ compatible = "mediatek,mt7988-switch";
+ reg = <0 0x15020000 0 0x8000>;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>;
+ resets = <ðwarp MT7988_ETHWARP_RST_SWITCH>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ gsw_port0: port@0 {
+ reg = <0>;
+ phy-mode = "internal";
+ phy-handle = <&gsw_phy0>;
+ };
+
+ gsw_port1: port@1 {
+ reg = <1>;
+ phy-mode = "internal";
+ phy-handle = <&gsw_phy1>;
+ };
+
+ gsw_port2: port@2 {
+ reg = <2>;
+ phy-mode = "internal";
+ phy-handle = <&gsw_phy2>;
+ };
+
+ gsw_port3: port@3 {
+ reg = <3>;
+ phy-mode = "internal";
+ phy-handle = <&gsw_phy3>;
+ };
+
+ port@6 {
+ reg = <6>;
+ ethernet = <&gmac0>;
+ phy-mode = "internal";
+
+ fixed-link {
+ speed = <10000>;
+ full-duplex;
+ pause;
+ };
+ };
+ };
+
+ mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ mediatek,pio = <&pio>;
+
+ gsw_phy0: ethernet-phy@0 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <0>;
+ interrupts = <0>;
+ phy-mode = "internal";
+ nvmem-cells = <&phy_calibration_p0>;
+ nvmem-cell-names = "phy-cal-data";
+
+ leds {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ gsw_phy0_led0: gsw-phy0-led0@0 {
+ reg = <0>;
+ status = "disabled";
+ };
+
+ gsw_phy0_led1: gsw-phy0-led1@1 {
+ reg = <1>;
+ status = "disabled";
+ };
+ };
+ };
+
+ gsw_phy1: ethernet-phy@1 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <1>;
+ interrupts = <1>;
+ phy-mode = "internal";
+ nvmem-cells = <&phy_calibration_p1>;
+ nvmem-cell-names = "phy-cal-data";
+
+ leds {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ gsw_phy1_led0: gsw-phy1-led0@0 {
+ reg = <0>;
+ status = "disabled";
+ };
+
+ gsw_phy1_led1: gsw-phy1-led1@1 {
+ reg = <1>;
+ status = "disabled";
+ };
+ };
+ };
+
+ gsw_phy2: ethernet-phy@2 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <2>;
+ interrupts = <2>;
+ phy-mode = "internal";
+ nvmem-cells = <&phy_calibration_p2>;
+ nvmem-cell-names = "phy-cal-data";
+
+ leds {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ gsw_phy2_led0: gsw-phy2-led0@0 {
+ reg = <0>;
+ status = "disabled";
+ };
+
+ gsw_phy2_led1: gsw-phy2-led1@1 {
+ reg = <1>;
+ status = "disabled";
+ };
+ };
+ };
+
+ gsw_phy3: ethernet-phy@3 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <3>;
+ interrupts = <3>;
+ phy-mode = "internal";
+ nvmem-cells = <&phy_calibration_p3>;
+ nvmem-cell-names = "phy-cal-data";
+
+ leds {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ gsw_phy3_led0: gsw-phy3-led0@0 {
+ reg = <0>;
+ status = "disabled";
+ };
+
+ gsw_phy3_led1: gsw-phy3-led1@1 {
+ reg = <1>;
+ status = "disabled";
+ };
+ };
+ };
+ };
+ };
+
+ ethwarp: clock-controller@15031000 {
+ compatible = "mediatek,mt7988-ethwarp";
+ reg = <0 0x15031000 0 0x1000>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ };
+
+ eth: ethernet@15100000 {
+ compatible = "mediatek,mt7988-eth";
+ reg = <0 0x15100000 0 0x80000>,
+ <0 0x15400000 0 0x380000>;
+ interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <ðsys CLK_ETHDMA_XGP1_EN>,
+ <ðsys CLK_ETHDMA_XGP2_EN>,
+ <ðsys CLK_ETHDMA_XGP3_EN>,
+ <ðsys CLK_ETHDMA_FE_EN>,
+ <ðsys CLK_ETHDMA_GP2_EN>,
+ <ðsys CLK_ETHDMA_GP1_EN>,
+ <ðsys CLK_ETHDMA_GP3_EN>,
+ <ðsys CLK_ETHDMA_ESW_EN>,
+ <ðsys CLK_ETHDMA_CRYPT0_EN>,
+ <ðwarp CLK_ETHWARP_WOCPU2_EN>,
+ <ðwarp CLK_ETHWARP_WOCPU1_EN>,
+ <ðwarp CLK_ETHWARP_WOCPU0_EN>,
+ <&topckgen CLK_TOP_ETH_GMII_SEL>,
+ <&topckgen CLK_TOP_ETH_REFCK_50M_SEL>,
+ <&topckgen CLK_TOP_ETH_SYS_200M_SEL>,
+ <&topckgen CLK_TOP_ETH_SYS_SEL>,
+ <&topckgen CLK_TOP_ETH_XGMII_SEL>,
+ <&topckgen CLK_TOP_ETH_MII_SEL>,
+ <&topckgen CLK_TOP_NETSYS_SEL>,
+ <&topckgen CLK_TOP_NETSYS_500M_SEL>,
+ <&topckgen CLK_TOP_NETSYS_PAO_2X_SEL>,
+ <&topckgen CLK_TOP_NETSYS_SYNC_250M_SEL>,
+ <&topckgen CLK_TOP_NETSYS_PPEFB_250M_SEL>,
+ <&topckgen CLK_TOP_NETSYS_WARP_SEL>;
+ clock-names = "xgp1", "xgp2", "xgp3", "fe", "gp2", "gp1",
+ "gp3", "esw", "crypto",
+ "ethwarp_wocpu2", "ethwarp_wocpu1",
+ "ethwarp_wocpu0", "top_eth_gmii_sel",
+ "top_eth_refck_50m_sel", "top_eth_sys_200m_sel",
+ "top_eth_sys_sel", "top_eth_xgmii_sel",
+ "top_eth_mii_sel", "top_netsys_sel",
+ "top_netsys_500m_sel", "top_netsys_pao_2x_sel",
+ "top_netsys_sync_250m_sel",
+ "top_netsys_ppefb_250m_sel",
+ "top_netsys_warp_sel";
+ assigned-clocks = <&topckgen CLK_TOP_NETSYS_2X_SEL>,
+ <&topckgen CLK_TOP_NETSYS_GSW_SEL>,
+ <&topckgen CLK_TOP_USXGMII_SBUS_0_SEL>,
+ <&topckgen CLK_TOP_USXGMII_SBUS_1_SEL>,
+ <&topckgen CLK_TOP_SGM_0_SEL>,
+ <&topckgen CLK_TOP_SGM_1_SEL>;
+ assigned-clock-parents = <&apmixedsys CLK_APMIXED_NET2PLL>,
+ <&topckgen CLK_TOP_NET1PLL_D4>,
+ <&topckgen CLK_TOP_NET1PLL_D8_D4>,
+ <&topckgen CLK_TOP_NET1PLL_D8_D4>,
+ <&apmixedsys CLK_APMIXED_SGMPLL>,
+ <&apmixedsys CLK_APMIXED_SGMPLL>;
+ mediatek,ethsys = <ðsys>;
+ mediatek,infracfg = <&topmisc>;
+ mediatek,wed = <&wed0>, <&wed1>, <&wed2>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ gmac0: mac@0 {
+ compatible = "mediatek,eth-mac";
+ reg = <0>;
+ phy-mode = "internal";
+ status = "disabled";
+
+ fixed-link {
+ speed = <10000>;
+ full-duplex;
+ pause;
+ };
+ };
+
+ gmac1: mac@1 {
+ compatible = "mediatek,eth-mac";
+ reg = <1>;
+ status = "disabled";
+ pcs-handle = <&sgmiipcs1>, <&usxgmiisys1>;
+ phys = <&xfi_tphy1>;
+ };
+
+ gmac2: mac@2 {
+ compatible = "mediatek,eth-mac";
+ reg = <2>;
+ status = "disabled";
+ pcs-handle = <&sgmiipcs0>, <&usxgmiisys0>;
+ phys = <&xfi_tphy0>;
+ };
+
+ mdio_bus: mdio-bus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ /* internal 2.5G PHY */
+ int_2p5g_phy: ethernet-phy@15 {
+ compatible = "ethernet-phy-ieee802.3-c45";
+ reg = <15>;
+ phy-mode = "internal";
+
+ leds {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ i2p5gbe_led0: i2p5gbe-led0@0 {
+ reg = <0>;
+ function = LED_FUNCTION_LAN;
+ status = "disabled";
+ };
+
+ i2p5gbe_led1: i2p5gbe-led1@1 {
+ reg = <1>;
+ function = LED_FUNCTION_LAN;
+ status = "disabled";
+ };
+ };
+ };
+ };
+ };
+
+ wo_ccif0: syscon@151a5000 {
+ compatible = "mediatek,mt7988-wo-ccif", "syscon";
+ reg = <0 0x151a5000 0 0x1000>;
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ wo_ccif1: syscon@152a5000 {
+ compatible = "mediatek,mt7988-wo-ccif", "syscon";
+ reg = <0 0x152a5000 0 0x1000>;
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ wo_ccif2: syscon@153a5000 {
+ compatible = "mediatek,mt7988-wo-ccif", "syscon";
+ reg = <0 0x153a5000 0 0x1000>;
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ wo_ilm0: syscon@151e0000 {
+ compatible = "mediatek,mt7988-wo-ilm", "syscon";
+ reg = <0 0x151e0000 0 0x8000>;
+ };
+
+ wo_ilm1: syscon@152e0000 {
+ compatible = "mediatek,mt7988-wo-ilm", "syscon";
+ reg = <0 0x152e0000 0 0x8000>;
+ };
+
+ wo_ilm2: syscon@153e0000 {
+ compatible = "mediatek,mt7988-wo-ilm", "syscon";
+ reg = <0 0x153e0000 0 0x8000>;
+ };
+
+ wo_dlm0: syscon@151e8000 {
+ compatible = "mediatek,mt7988-wo-dlm", "syscon";
+ reg = <0 0x151e8000 0 0x2000>;
+ };
+
+ wo_dlm1: syscon@152e8000 {
+ compatible = "mediatek,mt7988-wo-dlm", "syscon";
+ reg = <0 0x152e8000 0 0x2000>;
+ };
+
+ wo_dlm2: syscon@153e8000 {
+ compatible = "mediatek,mt7988-wo-dlm", "syscon";
+ reg = <0 0x153e8000 0 0x2000>;
+ };
+
+ wo_cpuboot0: syscon@15194000 {
+ compatible = "mediatek,mt7988-wo-cpuboot", "syscon";
+ reg = <0 0x15194000 0 0x1000>;
+ };
+
+ wo_cpuboot1: syscon@15294000 {
+ compatible = "mediatek,mt7988-wo-cpuboot", "syscon";
+ reg = <0 0x15294000 0 0x1000>;
+ };
+
+ wo_cpuboot2: syscon@15394000 {
+ compatible = "mediatek,mt7988-wo-cpuboot", "syscon";
+ reg = <0 0x15394000 0 0x1000>;
+ };
+
+ crypto: crypto@15600000 {
+ compatible = "inside-secure,safexcel-eip197b";
+ reg = <0 0x15600000 0 0x180000>;
+ interrupts = <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "ring0", "ring1", "ring2", "ring3";
+ status = "okay";
+ };
+ };
+
+ thermal-zones {
+ cpu_thermal: cpu-thermal {
+ polling-delay-passive = <1000>;
+ polling-delay = <1000>;
+ thermal-sensors = <&lvts 0>;
+
+ trips {
+ cpu_trip_crit: crit {
+ temperature = <125000>;
+ hysteresis = <2000>;
+ type = "critical";
+ };
+ };
+ };
+ };
+
+ timer {
+ compatible = "arm,armv8-timer";
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
+ };
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * MFD driver for Airoha AN8855 Switch
+ */
+
+#include <linux/mfd/airoha-an8855-mfd.h>
+#include <linux/mfd/core.h>
+#include <linux/mdio.h>
+#include <linux/module.h>
+#include <linux/phy.h>
+#include <linux/regmap.h>
+
+static const struct mfd_cell an8855_mfd_devs[] = {
+ {
+ .name = "an8855-efuse",
+ .of_compatible = "airoha,an8855-efuse",
+ }, {
+ .name = "an8855-switch",
+ .of_compatible = "airoha,an8855-switch",
+ }, {
+ .name = "an8855-mdio",
+ .of_compatible = "airoha,an8855-mdio",
+ }
+};
+
+int an8855_mii_set_page(struct an8855_mfd_priv *priv, u8 phy_id,
+ u8 page) __must_hold(&priv->bus->mdio_lock)
+{
+ struct mii_bus *bus = priv->bus;
+ int ret;
+
+ ret = __mdiobus_write(bus, phy_id, AN8855_PHY_SELECT_PAGE, page);
+ if (ret < 0)
+ dev_err_ratelimited(&bus->dev,
+ "failed to set an8855 mii page\n");
+
+ /* Cache current page if next mii read/write is for switch */
+ priv->current_page = page;
+ return ret < 0 ? ret : 0;
+}
+EXPORT_SYMBOL_GPL(an8855_mii_set_page);
+
+static int an8855_mii_read32(struct mii_bus *bus, u8 phy_id, u32 reg,
+ u32 *val) __must_hold(&bus->mdio_lock)
+{
+ int lo, hi, ret;
+
+ ret = __mdiobus_write(bus, phy_id, AN8855_PBUS_MODE,
+ AN8855_PBUS_MODE_ADDR_FIXED);
+ if (ret < 0)
+ goto err;
+
+ ret = __mdiobus_write(bus, phy_id, AN8855_PBUS_RD_ADDR_HIGH,
+ upper_16_bits(reg));
+ if (ret < 0)
+ goto err;
+ ret = __mdiobus_write(bus, phy_id, AN8855_PBUS_RD_ADDR_LOW,
+ lower_16_bits(reg));
+ if (ret < 0)
+ goto err;
+
+ hi = __mdiobus_read(bus, phy_id, AN8855_PBUS_RD_DATA_HIGH);
+ if (hi < 0) {
+ ret = hi;
+ goto err;
+ }
+ lo = __mdiobus_read(bus, phy_id, AN8855_PBUS_RD_DATA_LOW);
+ if (lo < 0) {
+ ret = lo;
+ goto err;
+ }
+
+ *val = ((u16)hi << 16) | ((u16)lo & 0xffff);
+
+ return 0;
+err:
+ dev_err_ratelimited(&bus->dev,
+ "failed to read an8855 register\n");
+ return ret;
+}
+
+static int an8855_regmap_read(void *ctx, uint32_t reg, uint32_t *val)
+{
+ struct an8855_mfd_priv *priv = ctx;
+ struct mii_bus *bus = priv->bus;
+ u16 addr = priv->switch_addr;
+ int ret;
+
+ mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED);
+ ret = an8855_mii_set_page(priv, addr, AN8855_PHY_PAGE_EXTENDED_4);
+ if (ret < 0)
+ goto exit;
+
+ ret = an8855_mii_read32(bus, addr, reg, val);
+
+exit:
+ mutex_unlock(&bus->mdio_lock);
+
+ return ret < 0 ? ret : 0;
+}
+
+static int an8855_mii_write32(struct mii_bus *bus, u8 phy_id, u32 reg,
+ u32 val) __must_hold(&bus->mdio_lock)
+{
+ int ret;
+
+ ret = __mdiobus_write(bus, phy_id, AN8855_PBUS_MODE,
+ AN8855_PBUS_MODE_ADDR_FIXED);
+ if (ret < 0)
+ goto err;
+
+ ret = __mdiobus_write(bus, phy_id, AN8855_PBUS_WR_ADDR_HIGH,
+ upper_16_bits(reg));
+ if (ret < 0)
+ goto err;
+ ret = __mdiobus_write(bus, phy_id, AN8855_PBUS_WR_ADDR_LOW,
+ lower_16_bits(reg));
+ if (ret < 0)
+ goto err;
+
+ ret = __mdiobus_write(bus, phy_id, AN8855_PBUS_WR_DATA_HIGH,
+ upper_16_bits(val));
+ if (ret < 0)
+ goto err;
+ ret = __mdiobus_write(bus, phy_id, AN8855_PBUS_WR_DATA_LOW,
+ lower_16_bits(val));
+ if (ret < 0)
+ goto err;
+
+ return 0;
+err:
+ dev_err_ratelimited(&bus->dev,
+ "failed to write an8855 register\n");
+ return ret;
+}
+
+static int
+an8855_regmap_write(void *ctx, uint32_t reg, uint32_t val)
+{
+ struct an8855_mfd_priv *priv = ctx;
+ struct mii_bus *bus = priv->bus;
+ u16 addr = priv->switch_addr;
+ int ret;
+
+ mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED);
+ ret = an8855_mii_set_page(priv, addr, AN8855_PHY_PAGE_EXTENDED_4);
+ if (ret < 0)
+ goto exit;
+
+ ret = an8855_mii_write32(bus, addr, reg, val);
+
+exit:
+ mutex_unlock(&bus->mdio_lock);
+
+ return ret < 0 ? ret : 0;
+}
+
+static int an8855_regmap_update_bits(void *ctx, uint32_t reg, uint32_t mask,
+ uint32_t write_val)
+{
+ struct an8855_mfd_priv *priv = ctx;
+ struct mii_bus *bus = priv->bus;
+ u16 addr = priv->switch_addr;
+ u32 val;
+ int ret;
+
+ mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED);
+ ret = an8855_mii_set_page(priv, addr, AN8855_PHY_PAGE_EXTENDED_4);
+ if (ret < 0)
+ goto exit;
+
+ ret = an8855_mii_read32(bus, addr, reg, &val);
+ if (ret < 0)
+ goto exit;
+
+ val &= ~mask;
+ val |= write_val;
+ ret = an8855_mii_write32(bus, addr, reg, val);
+
+exit:
+ mutex_unlock(&bus->mdio_lock);
+
+ return ret < 0 ? ret : 0;
+}
+
+static const struct regmap_range an8855_readable_ranges[] = {
+ regmap_reg_range(0x10000000, 0x10000fff), /* SCU */
+ regmap_reg_range(0x10001000, 0x10001fff), /* RBUS */
+ regmap_reg_range(0x10002000, 0x10002fff), /* MCU */
+ regmap_reg_range(0x10005000, 0x10005fff), /* SYS SCU */
+ regmap_reg_range(0x10007000, 0x10007fff), /* I2C Slave */
+ regmap_reg_range(0x10008000, 0x10008fff), /* I2C Master */
+ regmap_reg_range(0x10009000, 0x10009fff), /* PDMA */
+ regmap_reg_range(0x1000a100, 0x1000a2ff), /* General Purpose Timer */
+ regmap_reg_range(0x1000a200, 0x1000a2ff), /* GPU timer */
+ regmap_reg_range(0x1000a300, 0x1000a3ff), /* GPIO */
+ regmap_reg_range(0x1000a400, 0x1000a5ff), /* EFUSE */
+ regmap_reg_range(0x1000c000, 0x1000cfff), /* GDMP CSR */
+ regmap_reg_range(0x10010000, 0x1001ffff), /* GDMP SRAM */
+ regmap_reg_range(0x10200000, 0x10203fff), /* Switch - ARL Global */
+ regmap_reg_range(0x10204000, 0x10207fff), /* Switch - BMU */
+ regmap_reg_range(0x10208000, 0x1020bfff), /* Switch - ARL Port */
+ regmap_reg_range(0x1020c000, 0x1020cfff), /* Switch - SCH */
+ regmap_reg_range(0x10210000, 0x10213fff), /* Switch - MAC */
+ regmap_reg_range(0x10214000, 0x10217fff), /* Switch - MIB */
+ regmap_reg_range(0x10218000, 0x1021bfff), /* Switch - Port Control */
+ regmap_reg_range(0x1021c000, 0x1021ffff), /* Switch - TOP */
+ regmap_reg_range(0x10220000, 0x1022ffff), /* SerDes */
+ regmap_reg_range(0x10286000, 0x10286fff), /* RG Batcher */
+ regmap_reg_range(0x1028c000, 0x1028ffff), /* ETHER_SYS */
+ regmap_reg_range(0x30000000, 0x37ffffff), /* I2C EEPROM */
+ regmap_reg_range(0x38000000, 0x3fffffff), /* BOOT_ROM */
+ regmap_reg_range(0xa0000000, 0xbfffffff), /* GPHY */
+};
+
+static const struct regmap_access_table an8855_readable_table = {
+ .yes_ranges = an8855_readable_ranges,
+ .n_yes_ranges = ARRAY_SIZE(an8855_readable_ranges),
+};
+
+static const struct regmap_config an8855_regmap_config = {
+ .reg_bits = 32,
+ .val_bits = 32,
+ .reg_stride = 4,
+ .max_register = 0xbfffffff,
+ .reg_read = an8855_regmap_read,
+ .reg_write = an8855_regmap_write,
+ .reg_update_bits = an8855_regmap_update_bits,
+ .disable_locking = true,
+ .rd_table = &an8855_readable_table,
+};
+
+static int an8855_mfd_probe(struct mdio_device *mdiodev)
+{
+ struct an8855_mfd_priv *priv;
+ struct regmap *regmap;
+
+ priv = devm_kzalloc(&mdiodev->dev, sizeof(*priv), GFP_KERNEL);
+ if (!priv)
+ return -ENOMEM;
+
+ priv->bus = mdiodev->bus;
+ priv->dev = &mdiodev->dev;
+ priv->switch_addr = mdiodev->addr;
+ /* no DMA for mdiobus, mute warning for DMA mask not set */
+ priv->dev->dma_mask = &priv->dev->coherent_dma_mask;
+
+ regmap = devm_regmap_init(priv->dev, NULL, priv,
+ &an8855_regmap_config);
+ if (IS_ERR(regmap))
+ dev_err_probe(priv->dev, PTR_ERR(priv->dev),
+ "regmap initialization failed\n");
+
+ dev_set_drvdata(&mdiodev->dev, priv);
+
+ return devm_mfd_add_devices(priv->dev, PLATFORM_DEVID_AUTO, an8855_mfd_devs,
+ ARRAY_SIZE(an8855_mfd_devs), NULL, 0,
+ NULL);
+}
+
+static const struct of_device_id an8855_mfd_of_match[] = {
+ { .compatible = "airoha,an8855-mfd" },
+ { /* sentinel */ }
+};
+MODULE_DEVICE_TABLE(of, an8855_mfd_of_match);
+
+static struct mdio_driver an8855_mfd_driver = {
+ .probe = an8855_mfd_probe,
+ .mdiodrv.driver = {
+ .name = "an8855",
+ .of_match_table = an8855_mfd_of_match,
+ },
+};
+mdio_module_driver(an8855_mfd_driver);
+
+MODULE_AUTHOR("Christian Marangi <ansuelsmth@gmail.com>");
+MODULE_DESCRIPTION("Driver for Airoha AN8855 MFD");
+MODULE_LICENSE("GPL");
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Airoha AN8855 DSA Switch driver
+ * Copyright (C) 2023 Min Yao <min.yao@airoha.com>
+ * Copyright (C) 2024 Christian Marangi <ansuelsmth@gmail.com>
+ */
+#include <linux/bitfield.h>
+#include <linux/ethtool.h>
+#include <linux/etherdevice.h>
+#include <linux/gpio/consumer.h>
+#include <linux/if_bridge.h>
+#include <linux/iopoll.h>
+#include <linux/netdevice.h>
+#include <linux/of_net.h>
+#include <linux/of_platform.h>
+#include <linux/phylink.h>
+#include <linux/platform_device.h>
+#include <linux/regmap.h>
+#include <net/dsa.h>
+
+#include "an8855.h"
+
+static const struct an8855_mib_desc an8855_mib[] = {
+ MIB_DESC(1, AN8855_PORT_MIB_TX_DROP, "TxDrop"),
+ MIB_DESC(1, AN8855_PORT_MIB_TX_CRC_ERR, "TxCrcErr"),
+ MIB_DESC(1, AN8855_PORT_MIB_TX_COLLISION, "TxCollision"),
+ MIB_DESC(1, AN8855_PORT_MIB_TX_OVERSIZE_DROP, "TxOversizeDrop"),
+ MIB_DESC(2, AN8855_PORT_MIB_TX_BAD_PKT_BYTES, "TxBadPktBytes"),
+ MIB_DESC(1, AN8855_PORT_MIB_RX_DROP, "RxDrop"),
+ MIB_DESC(1, AN8855_PORT_MIB_RX_FILTERING, "RxFiltering"),
+ MIB_DESC(1, AN8855_PORT_MIB_RX_CRC_ERR, "RxCrcErr"),
+ MIB_DESC(1, AN8855_PORT_MIB_RX_CTRL_DROP, "RxCtrlDrop"),
+ MIB_DESC(1, AN8855_PORT_MIB_RX_INGRESS_DROP, "RxIngressDrop"),
+ MIB_DESC(1, AN8855_PORT_MIB_RX_ARL_DROP, "RxArlDrop"),
+ MIB_DESC(1, AN8855_PORT_MIB_FLOW_CONTROL_DROP, "FlowControlDrop"),
+ MIB_DESC(1, AN8855_PORT_MIB_WRED_DROP, "WredDrop"),
+ MIB_DESC(1, AN8855_PORT_MIB_MIRROR_DROP, "MirrorDrop"),
+ MIB_DESC(2, AN8855_PORT_MIB_RX_BAD_PKT_BYTES, "RxBadPktBytes"),
+ MIB_DESC(1, AN8855_PORT_MIB_RXS_FLOW_SAMPLING_PKT_DROP, "RxsFlowSamplingPktDrop"),
+ MIB_DESC(1, AN8855_PORT_MIB_RXS_FLOW_TOTAL_PKT_DROP, "RxsFlowTotalPktDrop"),
+ MIB_DESC(1, AN8855_PORT_MIB_PORT_CONTROL_DROP, "PortControlDrop"),
+};
+
+static int
+an8855_mib_init(struct an8855_priv *priv)
+{
+ int ret;
+
+ ret = regmap_write(priv->regmap, AN8855_MIB_CCR,
+ AN8855_CCR_MIB_ENABLE);
+ if (ret)
+ return ret;
+
+ return regmap_write(priv->regmap, AN8855_MIB_CCR,
+ AN8855_CCR_MIB_ACTIVATE);
+}
+
+static void an8855_fdb_write(struct an8855_priv *priv, u16 vid,
+ u8 port_mask, const u8 *mac,
+ bool add) __must_hold(&priv->reg_mutex)
+{
+ u32 mac_reg[2] = { };
+ u32 reg;
+
+ mac_reg[0] |= FIELD_PREP(AN8855_ATA1_MAC0, mac[0]);
+ mac_reg[0] |= FIELD_PREP(AN8855_ATA1_MAC1, mac[1]);
+ mac_reg[0] |= FIELD_PREP(AN8855_ATA1_MAC2, mac[2]);
+ mac_reg[0] |= FIELD_PREP(AN8855_ATA1_MAC3, mac[3]);
+ mac_reg[1] |= FIELD_PREP(AN8855_ATA2_MAC4, mac[4]);
+ mac_reg[1] |= FIELD_PREP(AN8855_ATA2_MAC5, mac[5]);
+
+ regmap_bulk_write(priv->regmap, AN8855_ATA1, mac_reg,
+ ARRAY_SIZE(mac_reg));
+
+ reg = AN8855_ATWD_IVL;
+ if (add)
+ reg |= AN8855_ATWD_VLD;
+ reg |= FIELD_PREP(AN8855_ATWD_VID, vid);
+ reg |= FIELD_PREP(AN8855_ATWD_FID, AN8855_FID_BRIDGED);
+ regmap_write(priv->regmap, AN8855_ATWD, reg);
+ regmap_write(priv->regmap, AN8855_ATWD2,
+ FIELD_PREP(AN8855_ATWD2_PORT, port_mask));
+}
+
+static void an8855_fdb_read(struct an8855_priv *priv, struct an8855_fdb *fdb)
+{
+ u32 reg[4];
+
+ regmap_bulk_read(priv->regmap, AN8855_ATRD0, reg,
+ ARRAY_SIZE(reg));
+
+ fdb->live = FIELD_GET(AN8855_ATRD0_LIVE, reg[0]);
+ fdb->type = FIELD_GET(AN8855_ATRD0_TYPE, reg[0]);
+ fdb->ivl = FIELD_GET(AN8855_ATRD0_IVL, reg[0]);
+ fdb->vid = FIELD_GET(AN8855_ATRD0_VID, reg[0]);
+ fdb->fid = FIELD_GET(AN8855_ATRD0_FID, reg[0]);
+ fdb->aging = FIELD_GET(AN8855_ATRD1_AGING, reg[1]);
+ fdb->port_mask = FIELD_GET(AN8855_ATRD3_PORTMASK, reg[3]);
+ fdb->mac[0] = FIELD_GET(AN8855_ATRD2_MAC0, reg[2]);
+ fdb->mac[1] = FIELD_GET(AN8855_ATRD2_MAC1, reg[2]);
+ fdb->mac[2] = FIELD_GET(AN8855_ATRD2_MAC2, reg[2]);
+ fdb->mac[3] = FIELD_GET(AN8855_ATRD2_MAC3, reg[2]);
+ fdb->mac[4] = FIELD_GET(AN8855_ATRD1_MAC4, reg[1]);
+ fdb->mac[5] = FIELD_GET(AN8855_ATRD1_MAC5, reg[1]);
+ fdb->noarp = !!FIELD_GET(AN8855_ATRD0_ARP, reg[0]);
+}
+
+static int an8855_fdb_cmd(struct an8855_priv *priv, u32 cmd,
+ u32 *rsp) __must_hold(&priv->reg_mutex)
+{
+ u32 val;
+ int ret;
+
+ /* Set the command operating upon the MAC address entries */
+ val = AN8855_ATC_BUSY | cmd;
+ ret = regmap_write(priv->regmap, AN8855_ATC, val);
+ if (ret)
+ return ret;
+
+ ret = regmap_read_poll_timeout(priv->regmap, AN8855_ATC, val,
+ !(val & AN8855_ATC_BUSY), 20, 200000);
+ if (ret)
+ return ret;
+
+ if (rsp)
+ *rsp = val;
+
+ return 0;
+}
+
+static void
+an8855_port_stp_state_set(struct dsa_switch *ds, int port, u8 state)
+{
+ struct dsa_port *dp = dsa_to_port(ds, port);
+ struct an8855_priv *priv = ds->priv;
+ bool learning = false;
+ u32 stp_state;
+
+ switch (state) {
+ case BR_STATE_DISABLED:
+ stp_state = AN8855_STP_DISABLED;
+ break;
+ case BR_STATE_BLOCKING:
+ stp_state = AN8855_STP_BLOCKING;
+ break;
+ case BR_STATE_LISTENING:
+ stp_state = AN8855_STP_LISTENING;
+ break;
+ case BR_STATE_LEARNING:
+ stp_state = AN8855_STP_LEARNING;
+ learning = dp->learning;
+ break;
+ case BR_STATE_FORWARDING:
+ learning = dp->learning;
+ fallthrough;
+ default:
+ stp_state = AN8855_STP_FORWARDING;
+ break;
+ }
+
+ regmap_update_bits(priv->regmap, AN8855_SSP_P(port),
+ AN8855_FID_PST_MASK(AN8855_FID_BRIDGED),
+ AN8855_FID_PST_VAL(AN8855_FID_BRIDGED, stp_state));
+
+ regmap_update_bits(priv->regmap, AN8855_PSC_P(port), AN8855_SA_DIS,
+ learning ? 0 : AN8855_SA_DIS);
+}
+
+static void an8855_port_fast_age(struct dsa_switch *ds, int port)
+{
+ struct an8855_priv *priv = ds->priv;
+ int ret;
+
+ /* Set to clean Dynamic entry */
+ ret = regmap_write(priv->regmap, AN8855_ATA2, AN8855_ATA2_TYPE);
+ if (ret)
+ return;
+
+ /* Set Port */
+ ret = regmap_write(priv->regmap, AN8855_ATWD2,
+ FIELD_PREP(AN8855_ATWD2_PORT, BIT(port)));
+ if (ret)
+ return;
+
+ /* Flush Dynamic entry at port */
+ an8855_fdb_cmd(priv, AN8855_ATC_MAT(AND8855_FDB_MAT_MAC_TYPE_PORT) |
+ AN8855_FDB_FLUSH, NULL);
+}
+
+static int an8855_update_port_member(struct dsa_switch *ds, int port,
+ const struct net_device *bridge_dev,
+ bool join)
+{
+ struct an8855_priv *priv = ds->priv;
+ bool isolated, other_isolated;
+ struct dsa_port *dp;
+ u32 port_mask = 0;
+ int ret;
+
+ isolated = !!(priv->port_isolated_map & BIT(port));
+
+ dsa_switch_for_each_user_port(dp, ds) {
+ if (dp->index == port)
+ continue;
+
+ if (!dsa_port_offloads_bridge_dev(dp, bridge_dev))
+ continue;
+
+ other_isolated = !!(priv->port_isolated_map & BIT(dp->index));
+ port_mask |= BIT(dp->index);
+ /* Add/remove this port to the portvlan mask of the other
+ * ports in the bridge
+ */
+ if (join && !(isolated && other_isolated))
+ ret = regmap_set_bits(priv->regmap,
+ AN8855_PORTMATRIX_P(dp->index),
+ FIELD_PREP(AN8855_USER_PORTMATRIX,
+ BIT(port)));
+ else
+ ret = regmap_clear_bits(priv->regmap,
+ AN8855_PORTMATRIX_P(dp->index),
+ FIELD_PREP(AN8855_USER_PORTMATRIX,
+ BIT(port)));
+ if (ret)
+ return ret;
+ }
+
+ /* Add/remove all other ports to this port's portvlan mask */
+ return regmap_update_bits(priv->regmap, AN8855_PORTMATRIX_P(port),
+ AN8855_USER_PORTMATRIX,
+ join ? port_mask : ~port_mask);
+}
+
+static int an8855_port_pre_bridge_flags(struct dsa_switch *ds, int port,
+ struct switchdev_brport_flags flags,
+ struct netlink_ext_ack *extack)
+{
+ if (flags.mask & ~(BR_LEARNING | BR_FLOOD | BR_MCAST_FLOOD |
+ BR_BCAST_FLOOD | BR_ISOLATED))
+ return -EINVAL;
+
+ return 0;
+}
+
+static int an8855_port_bridge_flags(struct dsa_switch *ds, int port,
+ struct switchdev_brport_flags flags,
+ struct netlink_ext_ack *extack)
+{
+ struct an8855_priv *priv = ds->priv;
+ int ret;
+
+ if (flags.mask & BR_LEARNING) {
+ ret = regmap_update_bits(priv->regmap, AN8855_PSC_P(port), AN8855_SA_DIS,
+ flags.val & BR_LEARNING ? 0 : AN8855_SA_DIS);
+ if (ret)
+ return ret;
+ }
+
+ if (flags.mask & BR_FLOOD) {
+ ret = regmap_update_bits(priv->regmap, AN8855_UNUF, BIT(port),
+ flags.val & BR_FLOOD ? BIT(port) : 0);
+ if (ret)
+ return ret;
+ }
+
+ if (flags.mask & BR_MCAST_FLOOD) {
+ ret = regmap_update_bits(priv->regmap, AN8855_UNMF, BIT(port),
+ flags.val & BR_MCAST_FLOOD ? BIT(port) : 0);
+ if (ret)
+ return ret;
+
+ ret = regmap_update_bits(priv->regmap, AN8855_UNIPMF, BIT(port),
+ flags.val & BR_MCAST_FLOOD ? BIT(port) : 0);
+ if (ret)
+ return ret;
+ }
+
+ if (flags.mask & BR_BCAST_FLOOD) {
+ ret = regmap_update_bits(priv->regmap, AN8855_BCF, BIT(port),
+ flags.val & BR_BCAST_FLOOD ? BIT(port) : 0);
+ if (ret)
+ return ret;
+ }
+
+ if (flags.mask & BR_ISOLATED) {
+ struct dsa_port *dp = dsa_to_port(ds, port);
+ struct net_device *bridge_dev = dsa_port_bridge_dev_get(dp);
+
+ if (flags.val & BR_ISOLATED)
+ priv->port_isolated_map |= BIT(port);
+ else
+ priv->port_isolated_map &= ~BIT(port);
+
+ ret = an8855_update_port_member(ds, port, bridge_dev, true);
+ if (ret)
+ return ret;
+ }
+
+ return 0;
+}
+
+static int an8855_set_ageing_time(struct dsa_switch *ds, unsigned int msecs)
+{
+ struct an8855_priv *priv = ds->priv;
+ u32 age_count, age_unit, val;
+
+ /* Convert msec in AN8855_L2_AGING_MS_CONSTANT counter */
+ val = msecs / AN8855_L2_AGING_MS_CONSTANT;
+ /* Derive the count unit */
+ age_unit = val / FIELD_MAX(AN8855_AGE_UNIT);
+ /* Get the count in unit, age_unit is always incremented by 1 internally */
+ age_count = val / (age_unit + 1);
+
+ return regmap_update_bits(priv->regmap, AN8855_AAC,
+ AN8855_AGE_CNT | AN8855_AGE_UNIT,
+ FIELD_PREP(AN8855_AGE_CNT, age_count) |
+ FIELD_PREP(AN8855_AGE_UNIT, age_unit));
+}
+
+static int an8855_port_bridge_join(struct dsa_switch *ds, int port,
+ struct dsa_bridge bridge,
+ bool *tx_fwd_offload,
+ struct netlink_ext_ack *extack)
+{
+ struct an8855_priv *priv = ds->priv;
+ int ret;
+
+ ret = an8855_update_port_member(ds, port, bridge.dev, true);
+ if (ret)
+ return ret;
+
+ /* Set to fallback mode for independent VLAN learning if in a bridge */
+ return regmap_update_bits(priv->regmap, AN8855_PCR_P(port),
+ AN8855_PORT_VLAN,
+ FIELD_PREP(AN8855_PORT_VLAN,
+ AN8855_PORT_FALLBACK_MODE));
+}
+
+static void an8855_port_bridge_leave(struct dsa_switch *ds, int port,
+ struct dsa_bridge bridge)
+{
+ struct an8855_priv *priv = ds->priv;
+
+ an8855_update_port_member(ds, port, bridge.dev, false);
+
+ /* When a port is removed from the bridge, the port would be set up
+ * back to the default as is at initial boot which is a VLAN-unaware
+ * port.
+ */
+ regmap_update_bits(priv->regmap, AN8855_PCR_P(port),
+ AN8855_PORT_VLAN,
+ FIELD_PREP(AN8855_PORT_VLAN,
+ AN8855_PORT_MATRIX_MODE));
+}
+
+static int an8855_port_fdb_add(struct dsa_switch *ds, int port,
+ const unsigned char *addr, u16 vid,
+ struct dsa_db db)
+{
+ struct an8855_priv *priv = ds->priv;
+ u8 port_mask = BIT(port);
+ int ret;
+
+ /* Set the vid to the port vlan id if no vid is set */
+ if (!vid)
+ vid = AN8855_PORT_VID_DEFAULT;
+
+ mutex_lock(&priv->reg_mutex);
+ an8855_fdb_write(priv, vid, port_mask, addr, true);
+ ret = an8855_fdb_cmd(priv, AN8855_FDB_WRITE, NULL);
+ mutex_unlock(&priv->reg_mutex);
+
+ return ret;
+}
+
+static int an8855_port_fdb_del(struct dsa_switch *ds, int port,
+ const unsigned char *addr, u16 vid,
+ struct dsa_db db)
+{
+ struct an8855_priv *priv = ds->priv;
+ u8 port_mask = BIT(port);
+ int ret;
+
+ /* Set the vid to the port vlan id if no vid is set */
+ if (!vid)
+ vid = AN8855_PORT_VID_DEFAULT;
+
+ mutex_lock(&priv->reg_mutex);
+ an8855_fdb_write(priv, vid, port_mask, addr, false);
+ ret = an8855_fdb_cmd(priv, AN8855_FDB_WRITE, NULL);
+ mutex_unlock(&priv->reg_mutex);
+
+ return ret;
+}
+
+static int an8855_port_fdb_dump(struct dsa_switch *ds, int port,
+ dsa_fdb_dump_cb_t *cb, void *data)
+{
+ struct an8855_priv *priv = ds->priv;
+ int banks, count = 0;
+ u32 rsp;
+ int ret;
+ int i;
+
+ mutex_lock(&priv->reg_mutex);
+
+ /* Load search port */
+ ret = regmap_write(priv->regmap, AN8855_ATWD2,
+ FIELD_PREP(AN8855_ATWD2_PORT, BIT(port)));
+ if (ret)
+ goto exit;
+ ret = an8855_fdb_cmd(priv, AN8855_ATC_MAT(AND8855_FDB_MAT_MAC_PORT) |
+ AN8855_FDB_START, &rsp);
+ if (ret < 0)
+ goto exit;
+
+ do {
+ /* From response get the number of banks to read, exit if 0 */
+ banks = FIELD_GET(AN8855_ATC_HIT, rsp);
+ if (!banks)
+ break;
+
+ /* Each banks have 4 entry */
+ for (i = 0; i < 4; i++) {
+ struct an8855_fdb _fdb = { };
+
+ count++;
+
+ /* Check if bank is present */
+ if (!(banks & BIT(i)))
+ continue;
+
+ /* Select bank entry index */
+ ret = regmap_write(priv->regmap, AN8855_ATRDS,
+ FIELD_PREP(AN8855_ATRD_SEL, i));
+ if (ret)
+ break;
+ /* wait 1ms for the bank entry to be filled */
+ usleep_range(1000, 1500);
+ an8855_fdb_read(priv, &_fdb);
+
+ if (!_fdb.live)
+ continue;
+ ret = cb(_fdb.mac, _fdb.vid, _fdb.noarp, data);
+ if (ret < 0)
+ break;
+ }
+
+ /* Stop if reached max FDB number */
+ if (count >= AN8855_NUM_FDB_RECORDS)
+ break;
+
+ /* Read next bank */
+ ret = an8855_fdb_cmd(priv, AN8855_ATC_MAT(AND8855_FDB_MAT_MAC_PORT) |
+ AN8855_FDB_NEXT, &rsp);
+ if (ret < 0)
+ break;
+ } while (true);
+
+exit:
+ mutex_unlock(&priv->reg_mutex);
+ return ret;
+}
+
+static int an8855_vlan_cmd(struct an8855_priv *priv, enum an8855_vlan_cmd cmd,
+ u16 vid) __must_hold(&priv->reg_mutex)
+{
+ u32 val;
+ int ret;
+
+ val = AN8855_VTCR_BUSY | FIELD_PREP(AN8855_VTCR_FUNC, cmd) |
+ FIELD_PREP(AN8855_VTCR_VID, vid);
+ ret = regmap_write(priv->regmap, AN8855_VTCR, val);
+ if (ret)
+ return ret;
+
+ return regmap_read_poll_timeout(priv->regmap, AN8855_VTCR, val,
+ !(val & AN8855_VTCR_BUSY), 20, 200000);
+}
+
+static int an8855_vlan_add(struct an8855_priv *priv, u8 port, u16 vid,
+ bool untagged) __must_hold(&priv->reg_mutex)
+{
+ u32 port_mask;
+ u32 val;
+ int ret;
+
+ /* Fetch entry */
+ ret = an8855_vlan_cmd(priv, AN8855_VTCR_RD_VID, vid);
+ if (ret)
+ return ret;
+
+ ret = regmap_read(priv->regmap, AN8855_VARD0, &val);
+ if (ret)
+ return ret;
+ port_mask = FIELD_GET(AN8855_VA0_PORT, val) | BIT(port);
+
+ /* Validate the entry with independent learning, create egress tag per
+ * VLAN and joining the port as one of the port members.
+ */
+ val = (val & AN8855_VA0_ETAG) | AN8855_VA0_IVL_MAC |
+ AN8855_VA0_VTAG_EN | AN8855_VA0_VLAN_VALID |
+ FIELD_PREP(AN8855_VA0_PORT, port_mask) |
+ FIELD_PREP(AN8855_VA0_FID, AN8855_FID_BRIDGED);
+ ret = regmap_write(priv->regmap, AN8855_VAWD0, val);
+ if (ret)
+ return ret;
+ ret = regmap_write(priv->regmap, AN8855_VAWD1, 0);
+ if (ret)
+ return ret;
+
+ /* CPU port is always taken as a tagged port for serving more than one
+ * VLANs across and also being applied with egress type stack mode for
+ * that VLAN tags would be appended after hardware special tag used as
+ * DSA tag.
+ */
+ if (port == AN8855_CPU_PORT)
+ val = AN8855_VLAN_EGRESS_STACK;
+ /* Decide whether adding tag or not for those outgoing packets from the
+ * port inside the VLAN.
+ */
+ else
+ val = untagged ? AN8855_VLAN_EGRESS_UNTAG : AN8855_VLAN_EGRESS_TAG;
+ ret = regmap_update_bits(priv->regmap, AN8855_VAWD0,
+ AN8855_VA0_ETAG_PORT_MASK(port),
+ AN8855_VA0_ETAG_PORT_VAL(port, val));
+ if (ret)
+ return ret;
+
+ /* Flush result to hardware */
+ return an8855_vlan_cmd(priv, AN8855_VTCR_WR_VID, vid);
+}
+
+static int an8855_vlan_del(struct an8855_priv *priv, u8 port,
+ u16 vid) __must_hold(&priv->reg_mutex)
+{
+ u32 port_mask;
+ u32 val;
+ int ret;
+
+ /* Fetch entry */
+ ret = an8855_vlan_cmd(priv, AN8855_VTCR_RD_VID, vid);
+ if (ret)
+ return ret;
+
+ ret = regmap_read(priv->regmap, AN8855_VARD0, &val);
+ if (ret)
+ return ret;
+ port_mask = FIELD_GET(AN8855_VA0_PORT, val) & ~BIT(port);
+
+ if (!(val & AN8855_VA0_VLAN_VALID)) {
+ dev_err(priv->dev, "Cannot be deleted due to invalid entry\n");
+ return -EINVAL;
+ }
+
+ if (port_mask) {
+ val = (val & AN8855_VA0_ETAG) | AN8855_VA0_IVL_MAC |
+ AN8855_VA0_VTAG_EN | AN8855_VA0_VLAN_VALID |
+ FIELD_PREP(AN8855_VA0_PORT, port_mask);
+ ret = regmap_write(priv->regmap, AN8855_VAWD0, val);
+ if (ret)
+ return ret;
+ } else {
+ ret = regmap_write(priv->regmap, AN8855_VAWD0, 0);
+ if (ret)
+ return ret;
+ }
+ ret = regmap_write(priv->regmap, AN8855_VAWD1, 0);
+ if (ret)
+ return ret;
+
+ /* Flush result to hardware */
+ return an8855_vlan_cmd(priv, AN8855_VTCR_WR_VID, vid);
+}
+
+static int an8855_port_set_vlan_mode(struct an8855_priv *priv, int port,
+ enum an8855_port_mode port_mode,
+ enum an8855_vlan_port_eg_tag eg_tag,
+ enum an8855_vlan_port_attr vlan_attr,
+ enum an8855_vlan_port_acc_frm acc_frm)
+{
+ int ret;
+
+ ret = regmap_update_bits(priv->regmap, AN8855_PCR_P(port),
+ AN8855_PORT_VLAN,
+ FIELD_PREP(AN8855_PORT_VLAN, port_mode));
+ if (ret)
+ return ret;
+
+ return regmap_update_bits(priv->regmap, AN8855_PVC_P(port),
+ AN8855_PVC_EG_TAG | AN8855_VLAN_ATTR | AN8855_ACC_FRM,
+ FIELD_PREP(AN8855_PVC_EG_TAG, eg_tag) |
+ FIELD_PREP(AN8855_VLAN_ATTR, vlan_attr) |
+ FIELD_PREP(AN8855_ACC_FRM, acc_frm));
+}
+
+static int an8855_port_set_pid(struct an8855_priv *priv, int port,
+ u16 pid)
+{
+ int ret;
+
+ ret = regmap_update_bits(priv->regmap, AN8855_PPBV1_P(port),
+ AN8855_PPBV_G0_PORT_VID,
+ FIELD_PREP(AN8855_PPBV_G0_PORT_VID, pid));
+ if (ret)
+ return ret;
+
+ return regmap_update_bits(priv->regmap, AN8855_PVID_P(port),
+ AN8855_G0_PORT_VID,
+ FIELD_PREP(AN8855_G0_PORT_VID, pid));
+}
+
+static int an8855_port_vlan_filtering(struct dsa_switch *ds, int port,
+ bool vlan_filtering,
+ struct netlink_ext_ack *extack)
+{
+ struct an8855_priv *priv = ds->priv;
+ u32 val;
+ int ret;
+
+ /* The port is being kept as VLAN-unaware port when bridge is
+ * set up with vlan_filtering not being set, Otherwise, the
+ * port and the corresponding CPU port is required the setup
+ * for becoming a VLAN-aware port.
+ */
+ if (vlan_filtering) {
+ u32 acc_frm;
+ /* CPU port is set to fallback mode to let untagged
+ * frames pass through.
+ */
+ ret = an8855_port_set_vlan_mode(priv, AN8855_CPU_PORT,
+ AN8855_PORT_FALLBACK_MODE,
+ AN8855_VLAN_EG_CONSISTENT,
+ AN8855_VLAN_USER,
+ AN8855_VLAN_ACC_ALL);
+ if (ret)
+ return ret;
+
+ ret = regmap_read(priv->regmap, AN8855_PVID_P(port), &val);
+ if (ret)
+ return ret;
+
+ /* Only accept tagged frames if PVID is not set */
+ if (FIELD_GET(AN8855_G0_PORT_VID, val) != AN8855_PORT_VID_DEFAULT)
+ acc_frm = AN8855_VLAN_ACC_TAGGED;
+ else
+ acc_frm = AN8855_VLAN_ACC_ALL;
+
+ /* Trapped into security mode allows packet forwarding through VLAN
+ * table lookup.
+ * Set the port as a user port which is to be able to recognize VID
+ * from incoming packets before fetching entry within the VLAN table.
+ */
+ ret = an8855_port_set_vlan_mode(priv, port,
+ AN8855_PORT_SECURITY_MODE,
+ AN8855_VLAN_EG_DISABLED,
+ AN8855_VLAN_USER,
+ acc_frm);
+ if (ret)
+ return ret;
+ } else {
+ bool disable_cpu_vlan = true;
+ struct dsa_port *dp;
+ u32 port_mode;
+
+ /* This is called after .port_bridge_leave when leaving a VLAN-aware
+ * bridge. Don't set standalone ports to fallback mode.
+ */
+ if (dsa_port_bridge_dev_get(dsa_to_port(ds, port)))
+ port_mode = AN8855_PORT_FALLBACK_MODE;
+ else
+ port_mode = AN8855_PORT_MATRIX_MODE;
+
+ /* When a port is removed from the bridge, the port would be set up
+ * back to the default as is at initial boot which is a VLAN-unaware
+ * port.
+ */
+ ret = an8855_port_set_vlan_mode(priv, port, port_mode,
+ AN8855_VLAN_EG_CONSISTENT,
+ AN8855_VLAN_TRANSPARENT,
+ AN8855_VLAN_ACC_ALL);
+ if (ret)
+ return ret;
+
+ /* Restore default PVID */
+ ret = an8855_port_set_pid(priv, port, AN8855_PORT_VID_DEFAULT);
+ if (ret)
+ return ret;
+
+ dsa_switch_for_each_user_port(dp, ds) {
+ if (dsa_port_is_vlan_filtering(dp)) {
+ disable_cpu_vlan = false;
+ break;
+ }
+ }
+
+ if (disable_cpu_vlan) {
+ ret = an8855_port_set_vlan_mode(priv, AN8855_CPU_PORT,
+ AN8855_PORT_MATRIX_MODE,
+ AN8855_VLAN_EG_CONSISTENT,
+ AN8855_VLAN_USER,
+ AN8855_VLAN_ACC_ALL);
+ if (ret)
+ return ret;
+ }
+ }
+
+ return 0;
+}
+
+static int an8855_port_vlan_add(struct dsa_switch *ds, int port,
+ const struct switchdev_obj_port_vlan *vlan,
+ struct netlink_ext_ack *extack)
+{
+ bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED;
+ bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID;
+ struct an8855_priv *priv = ds->priv;
+ u32 val;
+ int ret;
+
+ mutex_lock(&priv->reg_mutex);
+ ret = an8855_vlan_add(priv, port, vlan->vid, untagged);
+ mutex_unlock(&priv->reg_mutex);
+ if (ret)
+ return ret;
+
+ if (pvid) {
+ /* Accept all frames if PVID is set */
+ regmap_update_bits(priv->regmap, AN8855_PVC_P(port), AN8855_ACC_FRM,
+ FIELD_PREP(AN8855_ACC_FRM, AN8855_VLAN_ACC_ALL));
+
+ /* Only configure PVID if VLAN filtering is enabled */
+ if (dsa_port_is_vlan_filtering(dsa_to_port(ds, port))) {
+ ret = an8855_port_set_pid(priv, port, vlan->vid);
+ if (ret)
+ return ret;
+ }
+ } else if (vlan->vid) {
+ ret = regmap_read(priv->regmap, AN8855_PVID_P(port), &val);
+ if (ret)
+ return ret;
+
+ if (FIELD_GET(AN8855_G0_PORT_VID, val) != vlan->vid)
+ return 0;
+
+ /* This VLAN is overwritten without PVID, so unset it */
+ if (dsa_port_is_vlan_filtering(dsa_to_port(ds, port))) {
+ ret = regmap_update_bits(priv->regmap, AN8855_PVC_P(port),
+ AN8855_ACC_FRM,
+ FIELD_PREP(AN8855_ACC_FRM,
+ AN8855_VLAN_ACC_TAGGED));
+ if (ret)
+ return ret;
+ }
+
+ ret = an8855_port_set_pid(priv, port, AN8855_PORT_VID_DEFAULT);
+ if (ret)
+ return ret;
+ }
+
+ return 0;
+}
+
+static int an8855_port_vlan_del(struct dsa_switch *ds, int port,
+ const struct switchdev_obj_port_vlan *vlan)
+{
+ struct an8855_priv *priv = ds->priv;
+ u32 val;
+ int ret;
+
+ mutex_lock(&priv->reg_mutex);
+ ret = an8855_vlan_del(priv, port, vlan->vid);
+ mutex_unlock(&priv->reg_mutex);
+ if (ret)
+ return ret;
+
+ ret = regmap_read(priv->regmap, AN8855_PVID_P(port), &val);
+ if (ret)
+ return ret;
+
+ /* PVID is being restored to the default whenever the PVID port
+ * is being removed from the VLAN.
+ */
+ if (FIELD_GET(AN8855_G0_PORT_VID, val) == vlan->vid) {
+ /* Only accept tagged frames if the port is VLAN-aware */
+ if (dsa_port_is_vlan_filtering(dsa_to_port(ds, port))) {
+ ret = regmap_update_bits(priv->regmap, AN8855_PVC_P(port),
+ AN8855_ACC_FRM,
+ FIELD_PREP(AN8855_ACC_FRM,
+ AN8855_VLAN_ACC_TAGGED));
+ if (ret)
+ return ret;
+ }
+
+ ret = an8855_port_set_pid(priv, port, AN8855_PORT_VID_DEFAULT);
+ if (ret)
+ return ret;
+ }
+
+ return 0;
+}
+
+static int
+an8855_port_mdb_add(struct dsa_switch *ds, int port,
+ const struct switchdev_obj_port_mdb *mdb,
+ struct dsa_db db)
+{
+ struct an8855_priv *priv = ds->priv;
+ const u8 *addr = mdb->addr;
+ u16 vid = mdb->vid;
+ u8 port_mask = 0;
+ u32 val;
+ int ret;
+
+ /* Set the vid to the port vlan id if no vid is set */
+ if (!vid)
+ vid = AN8855_PORT_VID_DEFAULT;
+
+ mutex_lock(&priv->reg_mutex);
+
+ an8855_fdb_write(priv, vid, 0, addr, false);
+ if (!an8855_fdb_cmd(priv, AN8855_FDB_READ, NULL)) {
+ ret = regmap_read(priv->regmap, AN8855_ATRD3, &val);
+ if (ret)
+ goto exit;
+
+ port_mask = FIELD_GET(AN8855_ATRD3_PORTMASK, val);
+ }
+
+ port_mask |= BIT(port);
+ an8855_fdb_write(priv, vid, port_mask, addr, true);
+ ret = an8855_fdb_cmd(priv, AN8855_FDB_WRITE, NULL);
+
+exit:
+ mutex_unlock(&priv->reg_mutex);
+
+ return ret;
+}
+
+static int
+an8855_port_mdb_del(struct dsa_switch *ds, int port,
+ const struct switchdev_obj_port_mdb *mdb,
+ struct dsa_db db)
+{
+ struct an8855_priv *priv = ds->priv;
+ const u8 *addr = mdb->addr;
+ u16 vid = mdb->vid;
+ u8 port_mask = 0;
+ u32 val;
+ int ret;
+
+ /* Set the vid to the port vlan id if no vid is set */
+ if (!vid)
+ vid = AN8855_PORT_VID_DEFAULT;
+
+ mutex_lock(&priv->reg_mutex);
+
+ an8855_fdb_write(priv, vid, 0, addr, 0);
+ if (!an8855_fdb_cmd(priv, AN8855_FDB_READ, NULL)) {
+ ret = regmap_read(priv->regmap, AN8855_ATRD3, &val);
+ if (ret)
+ goto exit;
+
+ port_mask = FIELD_GET(AN8855_ATRD3_PORTMASK, val);
+ }
+
+ port_mask &= ~BIT(port);
+ an8855_fdb_write(priv, vid, port_mask, addr, port_mask ? true : false);
+ ret = an8855_fdb_cmd(priv, AN8855_FDB_WRITE, NULL);
+
+exit:
+ mutex_unlock(&priv->reg_mutex);
+
+ return ret;
+}
+
+static int
+an8855_port_change_mtu(struct dsa_switch *ds, int port, int new_mtu)
+{
+ struct an8855_priv *priv = ds->priv;
+ int length;
+ u32 val;
+
+ /* When a new MTU is set, DSA always set the CPU port's MTU to the
+ * largest MTU of the slave ports. Because the switch only has a global
+ * RX length register, only allowing CPU port here is enough.
+ */
+ if (!dsa_is_cpu_port(ds, port))
+ return 0;
+
+ /* RX length also includes Ethernet header, MTK tag, and FCS length */
+ length = new_mtu + ETH_HLEN + MTK_TAG_LEN + ETH_FCS_LEN;
+ if (length <= 1522)
+ val = AN8855_MAX_RX_PKT_1518_1522;
+ else if (length <= 1536)
+ val = AN8855_MAX_RX_PKT_1536;
+ else if (length <= 1552)
+ val = AN8855_MAX_RX_PKT_1552;
+ else if (length <= 3072)
+ val = AN8855_MAX_RX_JUMBO_3K;
+ else if (length <= 4096)
+ val = AN8855_MAX_RX_JUMBO_4K;
+ else if (length <= 5120)
+ val = AN8855_MAX_RX_JUMBO_5K;
+ else if (length <= 6144)
+ val = AN8855_MAX_RX_JUMBO_6K;
+ else if (length <= 7168)
+ val = AN8855_MAX_RX_JUMBO_7K;
+ else if (length <= 8192)
+ val = AN8855_MAX_RX_JUMBO_8K;
+ else if (length <= 9216)
+ val = AN8855_MAX_RX_JUMBO_9K;
+ else if (length <= 12288)
+ val = AN8855_MAX_RX_JUMBO_12K;
+ else if (length <= 15360)
+ val = AN8855_MAX_RX_JUMBO_15K;
+ else
+ val = AN8855_MAX_RX_JUMBO_16K;
+
+ /* Enable JUMBO packet */
+ if (length > 1552)
+ val |= AN8855_MAX_RX_PKT_JUMBO;
+
+ return regmap_update_bits(priv->regmap, AN8855_GMACCR,
+ AN8855_MAX_RX_JUMBO | AN8855_MAX_RX_PKT_LEN,
+ val);
+}
+
+static int
+an8855_port_max_mtu(struct dsa_switch *ds, int port)
+{
+ return AN8855_MAX_MTU;
+}
+
+static void
+an8855_get_strings(struct dsa_switch *ds, int port, u32 stringset,
+ uint8_t *data)
+{
+ int i;
+
+ if (stringset != ETH_SS_STATS)
+ return;
+
+ for (i = 0; i < ARRAY_SIZE(an8855_mib); i++)
+ ethtool_puts(&data, an8855_mib[i].name);
+}
+
+static void
+an8855_read_port_stats(struct an8855_priv *priv, int port, u32 offset, u8 size,
+ uint64_t *data)
+{
+ u32 val, reg = AN8855_PORT_MIB_COUNTER(port) + offset;
+
+ regmap_read(priv->regmap, reg, &val);
+ *data = val;
+
+ if (size == 2) {
+ regmap_read(priv->regmap, reg + 4, &val);
+ *data |= (u64)val << 32;
+ }
+}
+
+static void
+an8855_get_ethtool_stats(struct dsa_switch *ds, int port, uint64_t *data)
+{
+ struct an8855_priv *priv = ds->priv;
+ const struct an8855_mib_desc *mib;
+ int i;
+
+ for (i = 0; i < ARRAY_SIZE(an8855_mib); i++) {
+ mib = &an8855_mib[i];
+
+ an8855_read_port_stats(priv, port, mib->offset, mib->size,
+ data + i);
+ }
+}
+
+static int
+an8855_get_sset_count(struct dsa_switch *ds, int port, int sset)
+{
+ if (sset != ETH_SS_STATS)
+ return 0;
+
+ return ARRAY_SIZE(an8855_mib);
+}
+
+static void
+an8855_get_eth_mac_stats(struct dsa_switch *ds, int port,
+ struct ethtool_eth_mac_stats *mac_stats)
+{
+ struct an8855_priv *priv = ds->priv;
+
+ /* MIB counter doesn't provide a FramesTransmittedOK but instead
+ * provide stats for Unicast, Broadcast and Multicast frames separately.
+ * To simulate a global frame counter, read Unicast and addition Multicast
+ * and Broadcast later
+ */
+ an8855_read_port_stats(priv, port, AN8855_PORT_MIB_TX_UNICAST, 1,
+ &mac_stats->FramesTransmittedOK);
+
+ an8855_read_port_stats(priv, port, AN8855_PORT_MIB_TX_SINGLE_COLLISION, 1,
+ &mac_stats->SingleCollisionFrames);
+
+ an8855_read_port_stats(priv, port, AN8855_PORT_MIB_TX_MULTIPLE_COLLISION, 1,
+ &mac_stats->MultipleCollisionFrames);
+
+ an8855_read_port_stats(priv, port, AN8855_PORT_MIB_RX_UNICAST, 1,
+ &mac_stats->FramesReceivedOK);
+
+ an8855_read_port_stats(priv, port, AN8855_PORT_MIB_TX_BYTES, 2,
+ &mac_stats->OctetsTransmittedOK);
+
+ an8855_read_port_stats(priv, port, AN8855_PORT_MIB_RX_ALIGN_ERR, 1,
+ &mac_stats->AlignmentErrors);
+
+ an8855_read_port_stats(priv, port, AN8855_PORT_MIB_TX_DEFERRED, 1,
+ &mac_stats->FramesWithDeferredXmissions);
+
+ an8855_read_port_stats(priv, port, AN8855_PORT_MIB_TX_LATE_COLLISION, 1,
+ &mac_stats->LateCollisions);
+
+ an8855_read_port_stats(priv, port, AN8855_PORT_MIB_TX_EXCESSIVE_COLLISION, 1,
+ &mac_stats->FramesAbortedDueToXSColls);
+
+ an8855_read_port_stats(priv, port, AN8855_PORT_MIB_RX_BYTES, 2,
+ &mac_stats->OctetsReceivedOK);
+
+ an8855_read_port_stats(priv, port, AN8855_PORT_MIB_TX_MULTICAST, 1,
+ &mac_stats->MulticastFramesXmittedOK);
+ mac_stats->FramesTransmittedOK += mac_stats->MulticastFramesXmittedOK;
+ an8855_read_port_stats(priv, port, AN8855_PORT_MIB_TX_BROADCAST, 1,
+ &mac_stats->BroadcastFramesXmittedOK);
+ mac_stats->FramesTransmittedOK += mac_stats->BroadcastFramesXmittedOK;
+
+ an8855_read_port_stats(priv, port, AN8855_PORT_MIB_RX_MULTICAST, 1,
+ &mac_stats->MulticastFramesReceivedOK);
+ mac_stats->FramesReceivedOK += mac_stats->MulticastFramesReceivedOK;
+ an8855_read_port_stats(priv, port, AN8855_PORT_MIB_RX_BROADCAST, 1,
+ &mac_stats->BroadcastFramesReceivedOK);
+ mac_stats->FramesReceivedOK += mac_stats->BroadcastFramesReceivedOK;
+}
+
+static const struct ethtool_rmon_hist_range an8855_rmon_ranges[] = {
+ { 0, 64 },
+ { 65, 127 },
+ { 128, 255 },
+ { 256, 511 },
+ { 512, 1023 },
+ { 1024, 1518 },
+ { 1519, AN8855_MAX_MTU },
+ {}
+};
+
+static void an8855_get_rmon_stats(struct dsa_switch *ds, int port,
+ struct ethtool_rmon_stats *rmon_stats,
+ const struct ethtool_rmon_hist_range **ranges)
+{
+ struct an8855_priv *priv = ds->priv;
+
+ an8855_read_port_stats(priv, port, AN8855_PORT_MIB_RX_UNDER_SIZE_ERR, 1,
+ &rmon_stats->undersize_pkts);
+ an8855_read_port_stats(priv, port, AN8855_PORT_MIB_RX_OVER_SZ_ERR, 1,
+ &rmon_stats->oversize_pkts);
+ an8855_read_port_stats(priv, port, AN8855_PORT_MIB_RX_FRAG_ERR, 1,
+ &rmon_stats->fragments);
+ an8855_read_port_stats(priv, port, AN8855_PORT_MIB_RX_JABBER_ERR, 1,
+ &rmon_stats->jabbers);
+
+ an8855_read_port_stats(priv, port, AN8855_PORT_MIB_RX_PKT_SZ_64, 1,
+ &rmon_stats->hist[0]);
+ an8855_read_port_stats(priv, port, AN8855_PORT_MIB_RX_PKT_SZ_65_TO_127, 1,
+ &rmon_stats->hist[1]);
+ an8855_read_port_stats(priv, port, AN8855_PORT_MIB_RX_PKT_SZ_128_TO_255, 1,
+ &rmon_stats->hist[2]);
+ an8855_read_port_stats(priv, port, AN8855_PORT_MIB_RX_PKT_SZ_256_TO_511, 1,
+ &rmon_stats->hist[3]);
+ an8855_read_port_stats(priv, port, AN8855_PORT_MIB_RX_PKT_SZ_512_TO_1023, 1,
+ &rmon_stats->hist[4]);
+ an8855_read_port_stats(priv, port, AN8855_PORT_MIB_RX_PKT_SZ_1024_TO_1518, 1,
+ &rmon_stats->hist[5]);
+ an8855_read_port_stats(priv, port, AN8855_PORT_MIB_RX_PKT_SZ_1519_TO_MAX, 1,
+ &rmon_stats->hist[6]);
+
+ an8855_read_port_stats(priv, port, AN8855_PORT_MIB_TX_PKT_SZ_64, 1,
+ &rmon_stats->hist_tx[0]);
+ an8855_read_port_stats(priv, port, AN8855_PORT_MIB_TX_PKT_SZ_65_TO_127, 1,
+ &rmon_stats->hist_tx[1]);
+ an8855_read_port_stats(priv, port, AN8855_PORT_MIB_TX_PKT_SZ_128_TO_255, 1,
+ &rmon_stats->hist_tx[2]);
+ an8855_read_port_stats(priv, port, AN8855_PORT_MIB_TX_PKT_SZ_256_TO_511, 1,
+ &rmon_stats->hist_tx[3]);
+ an8855_read_port_stats(priv, port, AN8855_PORT_MIB_TX_PKT_SZ_512_TO_1023, 1,
+ &rmon_stats->hist_tx[4]);
+ an8855_read_port_stats(priv, port, AN8855_PORT_MIB_TX_PKT_SZ_1024_TO_1518, 1,
+ &rmon_stats->hist_tx[5]);
+ an8855_read_port_stats(priv, port, AN8855_PORT_MIB_TX_PKT_SZ_1519_TO_MAX, 1,
+ &rmon_stats->hist_tx[6]);
+
+ *ranges = an8855_rmon_ranges;
+}
+
+static void an8855_get_eth_ctrl_stats(struct dsa_switch *ds, int port,
+ struct ethtool_eth_ctrl_stats *ctrl_stats)
+{
+ struct an8855_priv *priv = ds->priv;
+
+ an8855_read_port_stats(priv, port, AN8855_PORT_MIB_TX_PAUSE, 1,
+ &ctrl_stats->MACControlFramesTransmitted);
+
+ an8855_read_port_stats(priv, port, AN8855_PORT_MIB_RX_PAUSE, 1,
+ &ctrl_stats->MACControlFramesReceived);
+}
+
+static int an8855_port_mirror_add(struct dsa_switch *ds, int port,
+ struct dsa_mall_mirror_tc_entry *mirror,
+ bool ingress,
+ struct netlink_ext_ack *extack)
+{
+ struct an8855_priv *priv = ds->priv;
+ int monitor_port;
+ u32 val;
+ int ret;
+
+ /* Check for existent entry */
+ if ((ingress ? priv->mirror_rx : priv->mirror_tx) & BIT(port))
+ return -EEXIST;
+
+ ret = regmap_read(priv->regmap, AN8855_MIR, &val);
+ if (ret)
+ return ret;
+
+ /* AN8855 supports 4 monitor port, but only use first group */
+ monitor_port = FIELD_GET(AN8855_MIRROR_PORT, val);
+ if (val & AN8855_MIRROR_EN && monitor_port != mirror->to_local_port)
+ return -EEXIST;
+
+ val = AN8855_MIRROR_EN;
+ val |= FIELD_PREP(AN8855_MIRROR_PORT, mirror->to_local_port);
+ ret = regmap_update_bits(priv->regmap, AN8855_MIR,
+ AN8855_MIRROR_EN | AN8855_MIRROR_PORT,
+ val);
+ if (ret)
+ return ret;
+
+ ret = regmap_set_bits(priv->regmap, AN8855_PCR_P(port),
+ ingress ? AN8855_PORT_RX_MIR : AN8855_PORT_TX_MIR);
+ if (ret)
+ return ret;
+
+ if (ingress)
+ priv->mirror_rx |= BIT(port);
+ else
+ priv->mirror_tx |= BIT(port);
+
+ return 0;
+}
+
+static void an8855_port_mirror_del(struct dsa_switch *ds, int port,
+ struct dsa_mall_mirror_tc_entry *mirror)
+{
+ struct an8855_priv *priv = ds->priv;
+
+ if (mirror->ingress)
+ priv->mirror_rx &= ~BIT(port);
+ else
+ priv->mirror_tx &= ~BIT(port);
+
+ regmap_clear_bits(priv->regmap, AN8855_PCR_P(port),
+ mirror->ingress ? AN8855_PORT_RX_MIR :
+ AN8855_PORT_TX_MIR);
+
+ if (!priv->mirror_rx && !priv->mirror_tx)
+ regmap_clear_bits(priv->regmap, AN8855_MIR, AN8855_MIRROR_EN);
+}
+
+static int an8855_port_set_status(struct an8855_priv *priv, int port,
+ bool enable)
+{
+ if (enable)
+ return regmap_set_bits(priv->regmap, AN8855_PMCR_P(port),
+ AN8855_PMCR_TX_EN | AN8855_PMCR_RX_EN);
+ else
+ return regmap_clear_bits(priv->regmap, AN8855_PMCR_P(port),
+ AN8855_PMCR_TX_EN | AN8855_PMCR_RX_EN);
+}
+
+static int an8855_port_enable(struct dsa_switch *ds, int port,
+ struct phy_device *phy)
+{
+ return an8855_port_set_status(ds->priv, port, true);
+}
+
+static void an8855_port_disable(struct dsa_switch *ds, int port)
+{
+ an8855_port_set_status(ds->priv, port, false);
+}
+
+static u32 en8855_get_phy_flags(struct dsa_switch *ds, int port)
+{
+ struct an8855_priv *priv = ds->priv;
+
+ /* PHY doesn't need calibration */
+ if (!priv->phy_require_calib)
+ return 0;
+
+ /* Use AN8855_PHY_FLAGS_EN_CALIBRATION to signal
+ * calibration needed.
+ */
+ return AN8855_PHY_FLAGS_EN_CALIBRATION;
+}
+
+static enum dsa_tag_protocol
+an8855_get_tag_protocol(struct dsa_switch *ds, int port,
+ enum dsa_tag_protocol mp)
+{
+ return DSA_TAG_PROTO_MTK;
+}
+
+/* Similar to MT7530 also trap link local frame and special frame to CPU */
+static int an8855_trap_special_frames(struct an8855_priv *priv)
+{
+ int ret;
+
+ /* Trap BPDUs to the CPU port(s) and egress them
+ * VLAN-untagged.
+ */
+ ret = regmap_update_bits(priv->regmap, AN8855_BPC,
+ AN8855_BPDU_BPDU_FR | AN8855_BPDU_EG_TAG |
+ AN8855_BPDU_PORT_FW,
+ AN8855_BPDU_BPDU_FR |
+ FIELD_PREP(AN8855_BPDU_EG_TAG, AN8855_VLAN_EG_UNTAGGED) |
+ FIELD_PREP(AN8855_BPDU_PORT_FW, AN8855_BPDU_CPU_ONLY));
+ if (ret)
+ return ret;
+
+ /* Trap 802.1X PAE frames to the CPU port(s) and egress them
+ * VLAN-untagged.
+ */
+ ret = regmap_update_bits(priv->regmap, AN8855_PAC,
+ AN8855_PAE_BPDU_FR | AN8855_PAE_EG_TAG |
+ AN8855_PAE_PORT_FW,
+ AN8855_PAE_BPDU_FR |
+ FIELD_PREP(AN8855_PAE_EG_TAG, AN8855_VLAN_EG_UNTAGGED) |
+ FIELD_PREP(AN8855_PAE_PORT_FW, AN8855_BPDU_CPU_ONLY));
+ if (ret)
+ return ret;
+
+ /* Trap frames with :01 MAC DAs to the CPU port(s) and egress
+ * them VLAN-untagged.
+ */
+ ret = regmap_update_bits(priv->regmap, AN8855_RGAC1,
+ AN8855_R01_BPDU_FR | AN8855_R01_EG_TAG |
+ AN8855_R01_PORT_FW,
+ AN8855_R01_BPDU_FR |
+ FIELD_PREP(AN8855_R01_EG_TAG, AN8855_VLAN_EG_UNTAGGED) |
+ FIELD_PREP(AN8855_R01_PORT_FW, AN8855_BPDU_CPU_ONLY));
+ if (ret)
+ return ret;
+
+ /* Trap frames with :02 MAC DAs to the CPU port(s) and egress
+ * them VLAN-untagged.
+ */
+ ret = regmap_update_bits(priv->regmap, AN8855_RGAC1,
+ AN8855_R02_BPDU_FR | AN8855_R02_EG_TAG |
+ AN8855_R02_PORT_FW,
+ AN8855_R02_BPDU_FR |
+ FIELD_PREP(AN8855_R02_EG_TAG, AN8855_VLAN_EG_UNTAGGED) |
+ FIELD_PREP(AN8855_R02_PORT_FW, AN8855_BPDU_CPU_ONLY));
+ if (ret)
+ return ret;
+
+ /* Trap frames with :03 MAC DAs to the CPU port(s) and egress
+ * them VLAN-untagged.
+ */
+ ret = regmap_update_bits(priv->regmap, AN8855_RGAC1,
+ AN8855_R03_BPDU_FR | AN8855_R03_EG_TAG |
+ AN8855_R03_PORT_FW,
+ AN8855_R03_BPDU_FR |
+ FIELD_PREP(AN8855_R03_EG_TAG, AN8855_VLAN_EG_UNTAGGED) |
+ FIELD_PREP(AN8855_R03_PORT_FW, AN8855_BPDU_CPU_ONLY));
+ if (ret)
+ return ret;
+
+ /* Trap frames with :0E MAC DAs to the CPU port(s) and egress
+ * them VLAN-untagged.
+ */
+ return regmap_update_bits(priv->regmap, AN8855_RGAC1,
+ AN8855_R0E_BPDU_FR | AN8855_R0E_EG_TAG |
+ AN8855_R0E_PORT_FW,
+ AN8855_R0E_BPDU_FR |
+ FIELD_PREP(AN8855_R0E_EG_TAG, AN8855_VLAN_EG_UNTAGGED) |
+ FIELD_PREP(AN8855_R0E_PORT_FW, AN8855_BPDU_CPU_ONLY));
+}
+
+static int
+an8855_setup_pvid_vlan(struct an8855_priv *priv)
+{
+ u32 val;
+ int ret;
+
+ /* Validate the entry with independent learning, keep the original
+ * ingress tag attribute.
+ */
+ val = AN8855_VA0_IVL_MAC | AN8855_VA0_EG_CON |
+ FIELD_PREP(AN8855_VA0_FID, AN8855_FID_BRIDGED) |
+ AN8855_VA0_PORT | AN8855_VA0_VLAN_VALID;
+ ret = regmap_write(priv->regmap, AN8855_VAWD0, val);
+ if (ret)
+ return ret;
+
+ return an8855_vlan_cmd(priv, AN8855_VTCR_WR_VID,
+ AN8855_PORT_VID_DEFAULT);
+}
+
+static int an8855_setup(struct dsa_switch *ds)
+{
+ struct an8855_priv *priv = ds->priv;
+ struct dsa_port *dp;
+ int ret;
+
+ /* Enable and reset MIB counters */
+ ret = an8855_mib_init(priv);
+ if (ret)
+ return ret;
+
+ dsa_switch_for_each_user_port(dp, ds) {
+ /* Disable MAC by default on all user ports */
+ ret = an8855_port_set_status(priv, dp->index, false);
+ if (ret)
+ return ret;
+
+ /* Individual user ports get connected to CPU port only */
+ ret = regmap_write(priv->regmap, AN8855_PORTMATRIX_P(dp->index),
+ FIELD_PREP(AN8855_PORTMATRIX, BIT(AN8855_CPU_PORT)));
+ if (ret)
+ return ret;
+
+ /* Disable Broadcast Forward on user ports */
+ ret = regmap_clear_bits(priv->regmap, AN8855_BCF, BIT(dp->index));
+ if (ret)
+ return ret;
+
+ /* Disable Unknown Unicast Forward on user ports */
+ ret = regmap_clear_bits(priv->regmap, AN8855_UNUF, BIT(dp->index));
+ if (ret)
+ return ret;
+
+ /* Disable Unknown Multicast Forward on user ports */
+ ret = regmap_clear_bits(priv->regmap, AN8855_UNMF, BIT(dp->index));
+ if (ret)
+ return ret;
+
+ ret = regmap_clear_bits(priv->regmap, AN8855_UNIPMF, BIT(dp->index));
+ if (ret)
+ return ret;
+
+ /* Set default PVID to on all user ports */
+ ret = an8855_port_set_pid(priv, dp->index, AN8855_PORT_VID_DEFAULT);
+ if (ret)
+ return ret;
+ }
+
+ /* Enable Airoha header mode on the cpu port */
+ ret = regmap_write(priv->regmap, AN8855_PVC_P(AN8855_CPU_PORT),
+ AN8855_PORT_SPEC_REPLACE_MODE | AN8855_PORT_SPEC_TAG);
+ if (ret)
+ return ret;
+
+ /* Unknown multicast frame forwarding to the cpu port */
+ ret = regmap_write(priv->regmap, AN8855_UNMF, BIT(AN8855_CPU_PORT));
+ if (ret)
+ return ret;
+
+ /* Set CPU port number */
+ ret = regmap_update_bits(priv->regmap, AN8855_MFC,
+ AN8855_CPU_EN | AN8855_CPU_PORT_IDX,
+ AN8855_CPU_EN |
+ FIELD_PREP(AN8855_CPU_PORT_IDX, AN8855_CPU_PORT));
+ if (ret)
+ return ret;
+
+ /* CPU port gets connected to all user ports of
+ * the switch.
+ */
+ ret = regmap_write(priv->regmap, AN8855_PORTMATRIX_P(AN8855_CPU_PORT),
+ FIELD_PREP(AN8855_PORTMATRIX, dsa_user_ports(ds)));
+ if (ret)
+ return ret;
+
+ /* CPU port is set to fallback mode to let untagged
+ * frames pass through.
+ */
+ ret = regmap_update_bits(priv->regmap, AN8855_PCR_P(AN8855_CPU_PORT),
+ AN8855_PORT_VLAN,
+ FIELD_PREP(AN8855_PORT_VLAN, AN8855_PORT_FALLBACK_MODE));
+ if (ret)
+ return ret;
+
+ /* Enable Broadcast Forward on CPU port */
+ ret = regmap_set_bits(priv->regmap, AN8855_BCF, BIT(AN8855_CPU_PORT));
+ if (ret)
+ return ret;
+
+ /* Enable Unknown Unicast Forward on CPU port */
+ ret = regmap_set_bits(priv->regmap, AN8855_UNUF, BIT(AN8855_CPU_PORT));
+ if (ret)
+ return ret;
+
+ /* Enable Unknown Multicast Forward on CPU port */
+ ret = regmap_set_bits(priv->regmap, AN8855_UNMF, BIT(AN8855_CPU_PORT));
+ if (ret)
+ return ret;
+
+ ret = regmap_set_bits(priv->regmap, AN8855_UNIPMF, BIT(AN8855_CPU_PORT));
+ if (ret)
+ return ret;
+
+ /* Setup Trap special frame to CPU rules */
+ ret = an8855_trap_special_frames(priv);
+ if (ret)
+ return ret;
+
+ dsa_switch_for_each_port(dp, ds) {
+ /* Disable Learning on all ports.
+ * Learning on CPU is disabled for fdb isolation and handled by
+ * assisted_learning_on_cpu_port.
+ */
+ ret = regmap_set_bits(priv->regmap, AN8855_PSC_P(dp->index),
+ AN8855_SA_DIS);
+ if (ret)
+ return ret;
+
+ /* Enable consistent egress tag (for VLAN unware VLAN-passtrough) */
+ ret = regmap_update_bits(priv->regmap, AN8855_PVC_P(dp->index),
+ AN8855_PVC_EG_TAG,
+ FIELD_PREP(AN8855_PVC_EG_TAG, AN8855_VLAN_EG_CONSISTENT));
+ if (ret)
+ return ret;
+ }
+
+ /* Setup VLAN for Default PVID */
+ ret = an8855_setup_pvid_vlan(priv);
+ if (ret)
+ return ret;
+
+ ret = regmap_clear_bits(priv->regmap, AN8855_CKGCR,
+ AN8855_CKG_LNKDN_GLB_STOP | AN8855_CKG_LNKDN_PORT_STOP);
+ if (ret)
+ return ret;
+
+ /* Release global PHY power down */
+ ret = regmap_write(priv->regmap, AN8855_RG_GPHY_AFE_PWD, 0x0);
+ if (ret)
+ return ret;
+
+ ds->configure_vlan_while_not_filtering = true;
+
+ /* Flush the FDB table */
+ ret = an8855_fdb_cmd(priv, AN8855_FDB_FLUSH, NULL);
+ if (ret < 0)
+ return ret;
+
+ /* Set min a max ageing value supported */
+ ds->ageing_time_min = AN8855_L2_AGING_MS_CONSTANT;
+ ds->ageing_time_max = FIELD_MAX(AN8855_AGE_CNT) *
+ FIELD_MAX(AN8855_AGE_UNIT) *
+ AN8855_L2_AGING_MS_CONSTANT;
+
+ /* Enable assisted learning for fdb isolation */
+ ds->assisted_learning_on_cpu_port = true;
+
+ return 0;
+}
+
+static struct phylink_pcs *an8855_phylink_mac_select_pcs(struct phylink_config *config,
+ phy_interface_t interface)
+{
+ struct dsa_port *dp = dsa_phylink_to_port(config);
+ struct an8855_priv *priv = dp->ds->priv;
+
+ switch (interface) {
+ case PHY_INTERFACE_MODE_SGMII:
+ case PHY_INTERFACE_MODE_2500BASEX:
+ return &priv->pcs;
+ default:
+ return NULL;
+ }
+}
+
+static void an8855_phylink_mac_config(struct phylink_config *config,
+ unsigned int mode,
+ const struct phylink_link_state *state)
+{
+ struct dsa_port *dp = dsa_phylink_to_port(config);
+ struct dsa_switch *ds = dp->ds;
+ struct an8855_priv *priv;
+ int port = dp->index;
+
+ priv = ds->priv;
+
+ /* Nothing to configure for internal ports */
+ if (port != 5)
+ return;
+
+ regmap_update_bits(priv->regmap, AN8855_PMCR_P(port),
+ AN8855_PMCR_IFG_XMIT | AN8855_PMCR_MAC_MODE |
+ AN8855_PMCR_BACKOFF_EN | AN8855_PMCR_BACKPR_EN,
+ FIELD_PREP(AN8855_PMCR_IFG_XMIT, 0x1) |
+ AN8855_PMCR_MAC_MODE | AN8855_PMCR_BACKOFF_EN |
+ AN8855_PMCR_BACKPR_EN);
+}
+
+static void an8855_phylink_get_caps(struct dsa_switch *ds, int port,
+ struct phylink_config *config)
+{
+ switch (port) {
+ case 0:
+ case 1:
+ case 2:
+ case 3:
+ case 4:
+ __set_bit(PHY_INTERFACE_MODE_GMII,
+ config->supported_interfaces);
+ __set_bit(PHY_INTERFACE_MODE_INTERNAL,
+ config->supported_interfaces);
+ break;
+ case 5:
+ phy_interface_set_rgmii(config->supported_interfaces);
+ __set_bit(PHY_INTERFACE_MODE_SGMII,
+ config->supported_interfaces);
+ __set_bit(PHY_INTERFACE_MODE_2500BASEX,
+ config->supported_interfaces);
+ break;
+ }
+
+ config->mac_capabilities = MAC_ASYM_PAUSE | MAC_SYM_PAUSE |
+ MAC_10 | MAC_100 | MAC_1000FD | MAC_2500FD;
+}
+
+static void an8855_phylink_mac_link_down(struct phylink_config *config,
+ unsigned int mode,
+ phy_interface_t interface)
+{
+ struct dsa_port *dp = dsa_phylink_to_port(config);
+ struct an8855_priv *priv = dp->ds->priv;
+
+ /* With autoneg just disable TX/RX else also force link down */
+ if (phylink_autoneg_inband(mode)) {
+ regmap_clear_bits(priv->regmap, AN8855_PMCR_P(dp->index),
+ AN8855_PMCR_TX_EN | AN8855_PMCR_RX_EN);
+ } else {
+ regmap_update_bits(priv->regmap, AN8855_PMCR_P(dp->index),
+ AN8855_PMCR_TX_EN | AN8855_PMCR_RX_EN |
+ AN8855_PMCR_FORCE_MODE | AN8855_PMCR_FORCE_LNK,
+ AN8855_PMCR_FORCE_MODE);
+ }
+}
+
+static void an8855_phylink_mac_link_up(struct phylink_config *config,
+ struct phy_device *phydev, unsigned int mode,
+ phy_interface_t interface, int speed,
+ int duplex, bool tx_pause, bool rx_pause)
+{
+ struct dsa_port *dp = dsa_phylink_to_port(config);
+ struct an8855_priv *priv = dp->ds->priv;
+ int port = dp->index;
+ u32 reg;
+
+ reg = regmap_read(priv->regmap, AN8855_PMCR_P(port), ®);
+ if (phylink_autoneg_inband(mode)) {
+ reg &= ~AN8855_PMCR_FORCE_MODE;
+ } else {
+ reg |= AN8855_PMCR_FORCE_MODE | AN8855_PMCR_FORCE_LNK;
+
+ reg &= ~AN8855_PMCR_FORCE_SPEED;
+ switch (speed) {
+ case SPEED_10:
+ reg |= AN8855_PMCR_FORCE_SPEED_10;
+ break;
+ case SPEED_100:
+ reg |= AN8855_PMCR_FORCE_SPEED_100;
+ break;
+ case SPEED_1000:
+ reg |= AN8855_PMCR_FORCE_SPEED_1000;
+ break;
+ case SPEED_2500:
+ reg |= AN8855_PMCR_FORCE_SPEED_2500;
+ break;
+ case SPEED_5000:
+ dev_err(priv->dev, "Missing support for 5G speed. Aborting...\n");
+ return;
+ }
+
+ reg &= ~AN8855_PMCR_FORCE_FDX;
+ if (duplex == DUPLEX_FULL)
+ reg |= AN8855_PMCR_FORCE_FDX;
+
+ reg &= ~AN8855_PMCR_RX_FC_EN;
+ if (rx_pause || dsa_port_is_cpu(dp))
+ reg |= AN8855_PMCR_RX_FC_EN;
+
+ reg &= ~AN8855_PMCR_TX_FC_EN;
+ if (rx_pause || dsa_port_is_cpu(dp))
+ reg |= AN8855_PMCR_TX_FC_EN;
+
+ /* Disable any EEE options */
+ reg &= ~(AN8855_PMCR_FORCE_EEE5G | AN8855_PMCR_FORCE_EEE2P5G |
+ AN8855_PMCR_FORCE_EEE1G | AN8855_PMCR_FORCE_EEE100);
+ }
+
+ reg |= AN8855_PMCR_TX_EN | AN8855_PMCR_RX_EN;
+
+ regmap_write(priv->regmap, AN8855_PMCR_P(port), reg);
+}
+
+static unsigned int an8855_pcs_inband_caps(struct phylink_pcs *pcs,
+ phy_interface_t interface)
+{
+ /* SGMII can be configured to use inband with AN result */
+ if (interface == PHY_INTERFACE_MODE_SGMII)
+ return LINK_INBAND_DISABLE | LINK_INBAND_ENABLE;
+
+ /* inband is not supported in 2500-baseX and must be disabled */
+ return LINK_INBAND_DISABLE;
+}
+
+static void an8855_pcs_get_state(struct phylink_pcs *pcs,
+ struct phylink_link_state *state)
+{
+ struct an8855_priv *priv = container_of(pcs, struct an8855_priv, pcs);
+ u32 val;
+ int ret;
+
+ ret = regmap_read(priv->regmap, AN8855_PMSR_P(AN8855_CPU_PORT), &val);
+ if (ret < 0) {
+ state->link = false;
+ return;
+ }
+
+ state->link = !!(val & AN8855_PMSR_LNK);
+ state->an_complete = state->link;
+ state->duplex = (val & AN8855_PMSR_DPX) ? DUPLEX_FULL :
+ DUPLEX_HALF;
+
+ switch (val & AN8855_PMSR_SPEED) {
+ case AN8855_PMSR_SPEED_10:
+ state->speed = SPEED_10;
+ break;
+ case AN8855_PMSR_SPEED_100:
+ state->speed = SPEED_100;
+ break;
+ case AN8855_PMSR_SPEED_1000:
+ state->speed = SPEED_1000;
+ break;
+ case AN8855_PMSR_SPEED_2500:
+ state->speed = SPEED_2500;
+ break;
+ case AN8855_PMSR_SPEED_5000:
+ dev_err(priv->dev, "Missing support for 5G speed. Setting Unknown.\n");
+ fallthrough;
+ default:
+ state->speed = SPEED_UNKNOWN;
+ break;
+ }
+
+ if (val & AN8855_PMSR_RX_FC)
+ state->pause |= MLO_PAUSE_RX;
+ if (val & AN8855_PMSR_TX_FC)
+ state->pause |= MLO_PAUSE_TX;
+}
+
+static int an8855_pcs_config(struct phylink_pcs *pcs, unsigned int neg_mode,
+ phy_interface_t interface,
+ const unsigned long *advertising,
+ bool permit_pause_to_mac)
+{
+ struct an8855_priv *priv = container_of(pcs, struct an8855_priv, pcs);
+ u32 val;
+ int ret;
+
+ /* !!! WELCOME TO HELL !!! */
+
+ /* TX FIR - improve TX EYE */
+ ret = regmap_update_bits(priv->regmap, AN8855_INTF_CTRL_10,
+ AN8855_RG_DA_QP_TX_FIR_C2_SEL |
+ AN8855_RG_DA_QP_TX_FIR_C2_FORCE |
+ AN8855_RG_DA_QP_TX_FIR_C1_SEL |
+ AN8855_RG_DA_QP_TX_FIR_C1_FORCE,
+ AN8855_RG_DA_QP_TX_FIR_C2_SEL |
+ FIELD_PREP(AN8855_RG_DA_QP_TX_FIR_C2_FORCE, 0x4) |
+ AN8855_RG_DA_QP_TX_FIR_C1_SEL |
+ FIELD_PREP(AN8855_RG_DA_QP_TX_FIR_C1_FORCE, 0x0));
+ if (ret)
+ return ret;
+
+ if (interface == PHY_INTERFACE_MODE_2500BASEX)
+ val = 0x0;
+ else
+ val = 0xd;
+ ret = regmap_update_bits(priv->regmap, AN8855_INTF_CTRL_11,
+ AN8855_RG_DA_QP_TX_FIR_C0B_SEL |
+ AN8855_RG_DA_QP_TX_FIR_C0B_FORCE,
+ AN8855_RG_DA_QP_TX_FIR_C0B_SEL |
+ FIELD_PREP(AN8855_RG_DA_QP_TX_FIR_C0B_FORCE, val));
+ if (ret)
+ return ret;
+
+ /* RX CDR - improve RX Jitter Tolerance */
+ if (interface == PHY_INTERFACE_MODE_2500BASEX)
+ val = 0x5;
+ else
+ val = 0x6;
+ ret = regmap_update_bits(priv->regmap, AN8855_RG_QP_CDR_LPF_BOT_LIM,
+ AN8855_RG_QP_CDR_LPF_KP_GAIN |
+ AN8855_RG_QP_CDR_LPF_KI_GAIN,
+ FIELD_PREP(AN8855_RG_QP_CDR_LPF_KP_GAIN, val) |
+ FIELD_PREP(AN8855_RG_QP_CDR_LPF_KI_GAIN, val));
+ if (ret)
+ return ret;
+
+ /* PLL */
+ if (interface == PHY_INTERFACE_MODE_2500BASEX)
+ val = 0x1;
+ else
+ val = 0x0;
+ ret = regmap_update_bits(priv->regmap, AN8855_QP_DIG_MODE_CTRL_1,
+ AN8855_RG_TPHY_SPEED,
+ FIELD_PREP(AN8855_RG_TPHY_SPEED, val));
+ if (ret)
+ return ret;
+
+ /* PLL - LPF */
+ ret = regmap_update_bits(priv->regmap, AN8855_PLL_CTRL_2,
+ AN8855_RG_DA_QP_PLL_RICO_SEL_INTF |
+ AN8855_RG_DA_QP_PLL_FBKSEL_INTF |
+ AN8855_RG_DA_QP_PLL_BR_INTF |
+ AN8855_RG_DA_QP_PLL_BPD_INTF |
+ AN8855_RG_DA_QP_PLL_BPA_INTF |
+ AN8855_RG_DA_QP_PLL_BC_INTF,
+ AN8855_RG_DA_QP_PLL_RICO_SEL_INTF |
+ FIELD_PREP(AN8855_RG_DA_QP_PLL_FBKSEL_INTF, 0x0) |
+ FIELD_PREP(AN8855_RG_DA_QP_PLL_BR_INTF, 0x3) |
+ FIELD_PREP(AN8855_RG_DA_QP_PLL_BPD_INTF, 0x0) |
+ FIELD_PREP(AN8855_RG_DA_QP_PLL_BPA_INTF, 0x5) |
+ FIELD_PREP(AN8855_RG_DA_QP_PLL_BC_INTF, 0x1));
+ if (ret)
+ return ret;
+
+ /* PLL - ICO */
+ ret = regmap_set_bits(priv->regmap, AN8855_PLL_CTRL_4,
+ AN8855_RG_DA_QP_PLL_ICOLP_EN_INTF);
+ if (ret)
+ return ret;
+ ret = regmap_clear_bits(priv->regmap, AN8855_PLL_CTRL_2,
+ AN8855_RG_DA_QP_PLL_ICOIQ_EN_INTF);
+ if (ret)
+ return ret;
+
+ /* PLL - CHP */
+ if (interface == PHY_INTERFACE_MODE_2500BASEX)
+ val = 0x6;
+ else
+ val = 0x4;
+ ret = regmap_update_bits(priv->regmap, AN8855_PLL_CTRL_2,
+ AN8855_RG_DA_QP_PLL_IR_INTF,
+ FIELD_PREP(AN8855_RG_DA_QP_PLL_IR_INTF, val));
+ if (ret)
+ return ret;
+
+ /* PLL - PFD */
+ ret = regmap_update_bits(priv->regmap, AN8855_PLL_CTRL_2,
+ AN8855_RG_DA_QP_PLL_PFD_OFFSET_EN_INTRF |
+ AN8855_RG_DA_QP_PLL_PFD_OFFSET_INTF |
+ AN8855_RG_DA_QP_PLL_KBAND_PREDIV_INTF,
+ FIELD_PREP(AN8855_RG_DA_QP_PLL_PFD_OFFSET_INTF, 0x1) |
+ FIELD_PREP(AN8855_RG_DA_QP_PLL_KBAND_PREDIV_INTF, 0x1));
+ if (ret)
+ return ret;
+
+ /* PLL - POSTDIV */
+ ret = regmap_update_bits(priv->regmap, AN8855_PLL_CTRL_2,
+ AN8855_RG_DA_QP_PLL_POSTDIV_EN_INTF |
+ AN8855_RG_DA_QP_PLL_PHY_CK_EN_INTF |
+ AN8855_RG_DA_QP_PLL_PCK_SEL_INTF,
+ AN8855_RG_DA_QP_PLL_PCK_SEL_INTF);
+ if (ret)
+ return ret;
+
+ /* PLL - SDM */
+ ret = regmap_update_bits(priv->regmap, AN8855_PLL_CTRL_2,
+ AN8855_RG_DA_QP_PLL_SDM_HREN_INTF,
+ FIELD_PREP(AN8855_RG_DA_QP_PLL_SDM_HREN_INTF, 0x0));
+ if (ret)
+ return ret;
+ ret = regmap_clear_bits(priv->regmap, AN8855_PLL_CTRL_2,
+ AN8855_RG_DA_QP_PLL_SDM_IFM_INTF);
+ if (ret)
+ return ret;
+
+ ret = regmap_update_bits(priv->regmap, AN8855_SS_LCPLL_PWCTL_SETTING_2,
+ AN8855_RG_NCPO_ANA_MSB,
+ FIELD_PREP(AN8855_RG_NCPO_ANA_MSB, 0x1));
+ if (ret)
+ return ret;
+
+ if (interface == PHY_INTERFACE_MODE_2500BASEX)
+ val = 0x7a000000;
+ else
+ val = 0x48000000;
+ ret = regmap_write(priv->regmap, AN8855_SS_LCPLL_TDC_FLT_2,
+ FIELD_PREP(AN8855_RG_LCPLL_NCPO_VALUE, val));
+ if (ret)
+ return ret;
+ ret = regmap_write(priv->regmap, AN8855_SS_LCPLL_TDC_PCW_1,
+ FIELD_PREP(AN8855_RG_LCPLL_PON_HRDDS_PCW_NCPO_GPON, val));
+ if (ret)
+ return ret;
+
+ ret = regmap_clear_bits(priv->regmap, AN8855_SS_LCPLL_TDC_FLT_5,
+ AN8855_RG_LCPLL_NCPO_CHG);
+ if (ret)
+ return ret;
+ ret = regmap_clear_bits(priv->regmap, AN8855_PLL_CK_CTRL_0,
+ AN8855_RG_DA_QP_PLL_SDM_DI_EN_INTF);
+ if (ret)
+ return ret;
+
+ /* PLL - SS */
+ ret = regmap_update_bits(priv->regmap, AN8855_PLL_CTRL_3,
+ AN8855_RG_DA_QP_PLL_SSC_DELTA_INTF,
+ FIELD_PREP(AN8855_RG_DA_QP_PLL_SSC_DELTA_INTF, 0x0));
+ if (ret)
+ return ret;
+ ret = regmap_update_bits(priv->regmap, AN8855_PLL_CTRL_4,
+ AN8855_RG_DA_QP_PLL_SSC_DIR_DLY_INTF,
+ FIELD_PREP(AN8855_RG_DA_QP_PLL_SSC_DIR_DLY_INTF, 0x0));
+ if (ret)
+ return ret;
+ ret = regmap_update_bits(priv->regmap, AN8855_PLL_CTRL_3,
+ AN8855_RG_DA_QP_PLL_SSC_PERIOD_INTF,
+ FIELD_PREP(AN8855_RG_DA_QP_PLL_SSC_PERIOD_INTF, 0x0));
+ if (ret)
+ return ret;
+
+ /* PLL - TDC */
+ ret = regmap_clear_bits(priv->regmap, AN8855_PLL_CK_CTRL_0,
+ AN8855_RG_DA_QP_PLL_TDC_TXCK_SEL_INTF);
+ if (ret)
+ return ret;
+
+ ret = regmap_set_bits(priv->regmap, AN8855_RG_QP_PLL_SDM_ORD,
+ AN8855_RG_QP_PLL_SSC_TRI_EN);
+ if (ret)
+ return ret;
+ ret = regmap_set_bits(priv->regmap, AN8855_RG_QP_PLL_SDM_ORD,
+ AN8855_RG_QP_PLL_SSC_PHASE_INI);
+ if (ret)
+ return ret;
+
+ ret = regmap_update_bits(priv->regmap, AN8855_RG_QP_RX_DAC_EN,
+ AN8855_RG_QP_SIGDET_HF,
+ FIELD_PREP(AN8855_RG_QP_SIGDET_HF, 0x2));
+ if (ret)
+ return ret;
+
+ /* TCL Disable (only for Co-SIM) */
+ ret = regmap_clear_bits(priv->regmap, AN8855_PON_RXFEDIG_CTRL_0,
+ AN8855_RG_QP_EQ_RX500M_CK_SEL);
+ if (ret)
+ return ret;
+
+ /* TX Init */
+ if (interface == PHY_INTERFACE_MODE_2500BASEX)
+ val = 0x4;
+ else
+ val = 0x0;
+ ret = regmap_update_bits(priv->regmap, AN8855_RG_QP_TX_MODE,
+ AN8855_RG_QP_TX_RESERVE |
+ AN8855_RG_QP_TX_MODE_16B_EN,
+ FIELD_PREP(AN8855_RG_QP_TX_RESERVE, val));
+ if (ret)
+ return ret;
+
+ /* RX Control/Init */
+ ret = regmap_set_bits(priv->regmap, AN8855_RG_QP_RXAFE_RESERVE,
+ AN8855_RG_QP_CDR_PD_10B_EN);
+ if (ret)
+ return ret;
+
+ if (interface == PHY_INTERFACE_MODE_2500BASEX)
+ val = 0x1;
+ else
+ val = 0x2;
+ ret = regmap_update_bits(priv->regmap, AN8855_RG_QP_CDR_LPF_MJV_LIM,
+ AN8855_RG_QP_CDR_LPF_RATIO,
+ FIELD_PREP(AN8855_RG_QP_CDR_LPF_RATIO, val));
+ if (ret)
+ return ret;
+
+ ret = regmap_update_bits(priv->regmap, AN8855_RG_QP_CDR_LPF_SETVALUE,
+ AN8855_RG_QP_CDR_PR_BUF_IN_SR |
+ AN8855_RG_QP_CDR_PR_BETA_SEL,
+ FIELD_PREP(AN8855_RG_QP_CDR_PR_BUF_IN_SR, 0x6) |
+ FIELD_PREP(AN8855_RG_QP_CDR_PR_BETA_SEL, 0x1));
+ if (ret)
+ return ret;
+
+ if (interface == PHY_INTERFACE_MODE_2500BASEX)
+ val = 0xf;
+ else
+ val = 0xc;
+ ret = regmap_update_bits(priv->regmap, AN8855_RG_QP_CDR_PR_CKREF_DIV1,
+ AN8855_RG_QP_CDR_PR_DAC_BAND,
+ FIELD_PREP(AN8855_RG_QP_CDR_PR_DAC_BAND, val));
+ if (ret)
+ return ret;
+
+ ret = regmap_update_bits(priv->regmap, AN8855_RG_QP_CDR_PR_KBAND_DIV_PCIE,
+ AN8855_RG_QP_CDR_PR_KBAND_PCIE_MODE |
+ AN8855_RG_QP_CDR_PR_KBAND_DIV_PCIE_MASK,
+ FIELD_PREP(AN8855_RG_QP_CDR_PR_KBAND_DIV_PCIE_MASK, 0x19));
+ if (ret)
+ return ret;
+
+ ret = regmap_update_bits(priv->regmap, AN8855_RG_QP_CDR_FORCE_IBANDLPF_R_OFF,
+ AN8855_RG_QP_CDR_PHYCK_SEL |
+ AN8855_RG_QP_CDR_PHYCK_RSTB |
+ AN8855_RG_QP_CDR_PHYCK_DIV,
+ FIELD_PREP(AN8855_RG_QP_CDR_PHYCK_SEL, 0x2) |
+ FIELD_PREP(AN8855_RG_QP_CDR_PHYCK_DIV, 0x21));
+ if (ret)
+ return ret;
+
+ ret = regmap_clear_bits(priv->regmap, AN8855_RG_QP_CDR_PR_KBAND_DIV_PCIE,
+ AN8855_RG_QP_CDR_PR_XFICK_EN);
+ if (ret)
+ return ret;
+
+ ret = regmap_update_bits(priv->regmap, AN8855_RG_QP_CDR_PR_CKREF_DIV1,
+ AN8855_RG_QP_CDR_PR_KBAND_DIV,
+ FIELD_PREP(AN8855_RG_QP_CDR_PR_KBAND_DIV, 0x4));
+ if (ret)
+ return ret;
+
+ ret = regmap_update_bits(priv->regmap, AN8855_RX_CTRL_26,
+ AN8855_RG_QP_EQ_RETRAIN_ONLY_EN |
+ AN8855_RG_LINK_NE_EN |
+ AN8855_RG_LINK_ERRO_EN,
+ AN8855_RG_QP_EQ_RETRAIN_ONLY_EN |
+ AN8855_RG_LINK_ERRO_EN);
+ if (ret)
+ return ret;
+
+ ret = regmap_update_bits(priv->regmap, AN8855_RX_DLY_0,
+ AN8855_RG_QP_RX_SAOSC_EN_H_DLY |
+ AN8855_RG_QP_RX_PI_CAL_EN_H_DLY,
+ FIELD_PREP(AN8855_RG_QP_RX_SAOSC_EN_H_DLY, 0x3f) |
+ FIELD_PREP(AN8855_RG_QP_RX_PI_CAL_EN_H_DLY, 0x6f));
+ if (ret)
+ return ret;
+
+ ret = regmap_update_bits(priv->regmap, AN8855_RX_CTRL_42,
+ AN8855_RG_QP_EQ_EN_DLY,
+ FIELD_PREP(AN8855_RG_QP_EQ_EN_DLY, 0x150));
+ if (ret)
+ return ret;
+
+ ret = regmap_update_bits(priv->regmap, AN8855_RX_CTRL_2,
+ AN8855_RG_QP_RX_EQ_EN_H_DLY,
+ FIELD_PREP(AN8855_RG_QP_RX_EQ_EN_H_DLY, 0x150));
+ if (ret)
+ return ret;
+
+ ret = regmap_update_bits(priv->regmap, AN8855_PON_RXFEDIG_CTRL_9,
+ AN8855_RG_QP_EQ_LEQOSC_DLYCNT,
+ FIELD_PREP(AN8855_RG_QP_EQ_LEQOSC_DLYCNT, 0x1));
+ if (ret)
+ return ret;
+
+ ret = regmap_update_bits(priv->regmap, AN8855_RX_CTRL_8,
+ AN8855_RG_DA_QP_SAOSC_DONE_TIME |
+ AN8855_RG_DA_QP_LEQOS_EN_TIME,
+ FIELD_PREP(AN8855_RG_DA_QP_SAOSC_DONE_TIME, 0x200) |
+ FIELD_PREP(AN8855_RG_DA_QP_LEQOS_EN_TIME, 0xfff));
+ if (ret)
+ return ret;
+
+ /* Frequency meter */
+ if (interface == PHY_INTERFACE_MODE_2500BASEX)
+ val = 0x10;
+ else
+ val = 0x28;
+ ret = regmap_update_bits(priv->regmap, AN8855_RX_CTRL_5,
+ AN8855_RG_FREDET_CHK_CYCLE,
+ FIELD_PREP(AN8855_RG_FREDET_CHK_CYCLE, val));
+ if (ret)
+ return ret;
+
+ ret = regmap_update_bits(priv->regmap, AN8855_RX_CTRL_6,
+ AN8855_RG_FREDET_GOLDEN_CYCLE,
+ FIELD_PREP(AN8855_RG_FREDET_GOLDEN_CYCLE, 0x64));
+ if (ret)
+ return ret;
+
+ ret = regmap_update_bits(priv->regmap, AN8855_RX_CTRL_7,
+ AN8855_RG_FREDET_TOLERATE_CYCLE,
+ FIELD_PREP(AN8855_RG_FREDET_TOLERATE_CYCLE, 0x2710));
+ if (ret)
+ return ret;
+
+ ret = regmap_set_bits(priv->regmap, AN8855_PLL_CTRL_0,
+ AN8855_RG_PHYA_AUTO_INIT);
+ if (ret)
+ return ret;
+
+ /* PCS Init */
+ if (interface == PHY_INTERFACE_MODE_SGMII &&
+ neg_mode == PHYLINK_PCS_NEG_INBAND_DISABLED) {
+ ret = regmap_clear_bits(priv->regmap, AN8855_QP_DIG_MODE_CTRL_0,
+ AN8855_RG_SGMII_MODE | AN8855_RG_SGMII_AN_EN);
+ if (ret)
+ return ret;
+ }
+
+ ret = regmap_clear_bits(priv->regmap, AN8855_RG_HSGMII_PCS_CTROL_1,
+ AN8855_RG_TBI_10B_MODE);
+ if (ret)
+ return ret;
+
+ if (neg_mode == PHYLINK_PCS_NEG_INBAND_ENABLED) {
+ /* Set AN Ability - Interrupt */
+ ret = regmap_set_bits(priv->regmap, AN8855_SGMII_REG_AN_FORCE_CL37,
+ AN8855_RG_FORCE_AN_DONE);
+ if (ret)
+ return ret;
+
+ ret = regmap_update_bits(priv->regmap, AN8855_SGMII_REG_AN_13,
+ AN8855_SGMII_REMOTE_FAULT_DIS |
+ AN8855_SGMII_IF_MODE,
+ AN8855_SGMII_REMOTE_FAULT_DIS |
+ FIELD_PREP(AN8855_SGMII_IF_MODE, 0xb));
+ if (ret)
+ return ret;
+ }
+
+ /* Rate Adaption - GMII path config. */
+ if (interface == PHY_INTERFACE_MODE_2500BASEX) {
+ ret = regmap_clear_bits(priv->regmap, AN8855_RATE_ADP_P0_CTRL_0,
+ AN8855_RG_P0_DIS_MII_MODE);
+ if (ret)
+ return ret;
+ } else {
+ if (neg_mode == PHYLINK_PCS_NEG_INBAND_ENABLED) {
+ ret = regmap_set_bits(priv->regmap, AN8855_MII_RA_AN_ENABLE,
+ AN8855_RG_P0_RA_AN_EN);
+ if (ret)
+ return ret;
+ } else {
+ ret = regmap_update_bits(priv->regmap, AN8855_RG_AN_SGMII_MODE_FORCE,
+ AN8855_RG_FORCE_CUR_SGMII_MODE |
+ AN8855_RG_FORCE_CUR_SGMII_SEL,
+ AN8855_RG_FORCE_CUR_SGMII_SEL);
+ if (ret)
+ return ret;
+
+ ret = regmap_clear_bits(priv->regmap, AN8855_RATE_ADP_P0_CTRL_0,
+ AN8855_RG_P0_MII_RA_RX_EN |
+ AN8855_RG_P0_MII_RA_TX_EN |
+ AN8855_RG_P0_MII_RA_RX_MODE |
+ AN8855_RG_P0_MII_RA_TX_MODE);
+ if (ret)
+ return ret;
+ }
+
+ ret = regmap_set_bits(priv->regmap, AN8855_RATE_ADP_P0_CTRL_0,
+ AN8855_RG_P0_MII_MODE);
+ if (ret)
+ return ret;
+ }
+
+ ret = regmap_set_bits(priv->regmap, AN8855_RG_RATE_ADAPT_CTRL_0,
+ AN8855_RG_RATE_ADAPT_RX_BYPASS |
+ AN8855_RG_RATE_ADAPT_TX_BYPASS |
+ AN8855_RG_RATE_ADAPT_RX_EN |
+ AN8855_RG_RATE_ADAPT_TX_EN);
+ if (ret)
+ return ret;
+
+ /* Disable AN if not in autoneg */
+ ret = regmap_update_bits(priv->regmap, AN8855_SGMII_REG_AN0, BMCR_ANENABLE,
+ neg_mode == PHYLINK_PCS_NEG_INBAND_ENABLED ? BMCR_ANENABLE :
+ 0);
+ if (ret)
+ return ret;
+
+ if (interface == PHY_INTERFACE_MODE_SGMII) {
+ /* Follow SDK init flow with restarting AN after AN enable */
+ if (neg_mode == PHYLINK_PCS_NEG_INBAND_ENABLED) {
+ ret = regmap_set_bits(priv->regmap, AN8855_SGMII_REG_AN0,
+ BMCR_ANRESTART);
+ if (ret)
+ return ret;
+ } else {
+ ret = regmap_set_bits(priv->regmap, AN8855_PHY_RX_FORCE_CTRL_0,
+ AN8855_RG_FORCE_TXC_SEL);
+ if (ret)
+ return ret;
+ }
+ }
+
+ /* Force Speed with fixed-link or 2500base-x as doesn't support aneg */
+ if (interface == PHY_INTERFACE_MODE_2500BASEX ||
+ neg_mode != PHYLINK_PCS_NEG_INBAND_ENABLED) {
+ if (interface == PHY_INTERFACE_MODE_2500BASEX)
+ val = AN8855_RG_LINK_MODE_P0_SPEED_2500;
+ else
+ val = AN8855_RG_LINK_MODE_P0_SPEED_1000;
+ ret = regmap_update_bits(priv->regmap, AN8855_SGMII_STS_CTRL_0,
+ AN8855_RG_LINK_MODE_P0 |
+ AN8855_RG_FORCE_SPD_MODE_P0,
+ val | AN8855_RG_FORCE_SPD_MODE_P0);
+ if (ret)
+ return ret;
+ }
+
+ /* bypass flow control to MAC */
+ ret = regmap_write(priv->regmap, AN8855_MSG_RX_LIK_STS_0,
+ AN8855_RG_DPX_STS_P3 | AN8855_RG_DPX_STS_P2 |
+ AN8855_RG_DPX_STS_P1 | AN8855_RG_TXFC_STS_P0 |
+ AN8855_RG_RXFC_STS_P0 | AN8855_RG_DPX_STS_P0);
+ if (ret)
+ return ret;
+ ret = regmap_write(priv->regmap, AN8855_MSG_RX_LIK_STS_2,
+ AN8855_RG_RXFC_AN_BYPASS_P3 |
+ AN8855_RG_RXFC_AN_BYPASS_P2 |
+ AN8855_RG_RXFC_AN_BYPASS_P1 |
+ AN8855_RG_TXFC_AN_BYPASS_P3 |
+ AN8855_RG_TXFC_AN_BYPASS_P2 |
+ AN8855_RG_TXFC_AN_BYPASS_P1 |
+ AN8855_RG_DPX_AN_BYPASS_P3 |
+ AN8855_RG_DPX_AN_BYPASS_P2 |
+ AN8855_RG_DPX_AN_BYPASS_P1 |
+ AN8855_RG_DPX_AN_BYPASS_P0);
+ if (ret)
+ return ret;
+
+ return 0;
+}
+
+static void an8855_pcs_an_restart(struct phylink_pcs *pcs)
+{
+ return;
+}
+
+static const struct phylink_pcs_ops an8855_pcs_ops = {
+ .pcs_inband_caps = an8855_pcs_inband_caps,
+ .pcs_get_state = an8855_pcs_get_state,
+ .pcs_config = an8855_pcs_config,
+ .pcs_an_restart = an8855_pcs_an_restart,
+};
+
+static const struct phylink_mac_ops an8855_phylink_mac_ops = {
+ .mac_select_pcs = an8855_phylink_mac_select_pcs,
+ .mac_config = an8855_phylink_mac_config,
+ .mac_link_down = an8855_phylink_mac_link_down,
+ .mac_link_up = an8855_phylink_mac_link_up,
+};
+
+static const struct dsa_switch_ops an8855_switch_ops = {
+ .get_tag_protocol = an8855_get_tag_protocol,
+ .setup = an8855_setup,
+ .get_phy_flags = en8855_get_phy_flags,
+ .phylink_get_caps = an8855_phylink_get_caps,
+ .get_strings = an8855_get_strings,
+ .get_ethtool_stats = an8855_get_ethtool_stats,
+ .get_sset_count = an8855_get_sset_count,
+ .get_eth_mac_stats = an8855_get_eth_mac_stats,
+ .get_eth_ctrl_stats = an8855_get_eth_ctrl_stats,
+ .get_rmon_stats = an8855_get_rmon_stats,
+ .port_enable = an8855_port_enable,
+ .port_disable = an8855_port_disable,
+ .set_ageing_time = an8855_set_ageing_time,
+ .port_bridge_join = an8855_port_bridge_join,
+ .port_bridge_leave = an8855_port_bridge_leave,
+ .port_fast_age = an8855_port_fast_age,
+ .port_stp_state_set = an8855_port_stp_state_set,
+ .port_pre_bridge_flags = an8855_port_pre_bridge_flags,
+ .port_bridge_flags = an8855_port_bridge_flags,
+ .port_vlan_filtering = an8855_port_vlan_filtering,
+ .port_vlan_add = an8855_port_vlan_add,
+ .port_vlan_del = an8855_port_vlan_del,
+ .port_fdb_add = an8855_port_fdb_add,
+ .port_fdb_del = an8855_port_fdb_del,
+ .port_fdb_dump = an8855_port_fdb_dump,
+ .port_mdb_add = an8855_port_mdb_add,
+ .port_mdb_del = an8855_port_mdb_del,
+ .port_change_mtu = an8855_port_change_mtu,
+ .port_max_mtu = an8855_port_max_mtu,
+ .port_mirror_add = an8855_port_mirror_add,
+ .port_mirror_del = an8855_port_mirror_del,
+};
+
+static int an8855_read_switch_id(struct an8855_priv *priv)
+{
+ u32 id;
+ int ret;
+
+ ret = regmap_read(priv->regmap, AN8855_CREV, &id);
+ if (ret)
+ return ret;
+
+ if (id != AN8855_ID) {
+ dev_err(priv->dev,
+ "Switch id detected %x but expected %x\n",
+ id, AN8855_ID);
+ return -ENODEV;
+ }
+
+ return 0;
+}
+
+static int an8855_switch_probe(struct platform_device *pdev)
+{
+ struct an8855_priv *priv;
+ u32 val;
+ int ret;
+
+ priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
+ if (!priv)
+ return -ENOMEM;
+
+ priv->dev = &pdev->dev;
+ priv->phy_require_calib = of_property_read_bool(priv->dev->of_node,
+ "airoha,ext-surge");
+
+ priv->reset_gpio = devm_gpiod_get_optional(priv->dev, "reset",
+ GPIOD_OUT_LOW);
+ if (IS_ERR(priv->reset_gpio))
+ return PTR_ERR(priv->reset_gpio);
+
+ /* Get regmap from MFD */
+ priv->regmap = dev_get_regmap(priv->dev->parent, NULL);
+
+ if (priv->reset_gpio) {
+ usleep_range(100000, 150000);
+ gpiod_set_value_cansleep(priv->reset_gpio, 0);
+ usleep_range(100000, 150000);
+ gpiod_set_value_cansleep(priv->reset_gpio, 1);
+
+ /* Poll HWTRAP reg to wait for Switch to fully Init */
+ ret = regmap_read_poll_timeout(priv->regmap, AN8855_HWTRAP, val,
+ val, 20, 200000);
+ if (ret)
+ return ret;
+ }
+
+ ret = an8855_read_switch_id(priv);
+ if (ret)
+ return ret;
+
+ priv->ds = devm_kzalloc(priv->dev, sizeof(*priv->ds), GFP_KERNEL);
+ if (!priv->ds)
+ return -ENOMEM;
+
+ priv->ds->dev = priv->dev;
+ priv->ds->num_ports = AN8855_NUM_PORTS;
+ priv->ds->priv = priv;
+ priv->ds->ops = &an8855_switch_ops;
+ devm_mutex_init(priv->dev, &priv->reg_mutex);
+ priv->ds->phylink_mac_ops = &an8855_phylink_mac_ops;
+
+ priv->pcs.ops = &an8855_pcs_ops;
+ priv->pcs.neg_mode = true;
+ priv->pcs.poll = true;
+
+ dev_set_drvdata(priv->dev, priv);
+
+ return dsa_register_switch(priv->ds);
+}
+
+static void an8855_switch_remove(struct platform_device *pdev)
+{
+ struct an8855_priv *priv = dev_get_drvdata(&pdev->dev);
+
+ if (priv)
+ dsa_unregister_switch(priv->ds);
+}
+
+static const struct of_device_id an8855_switch_of_match[] = {
+ { .compatible = "airoha,an8855-switch" },
+ { /* sentinel */ }
+};
+MODULE_DEVICE_TABLE(of, an8855_switch_of_match);
+
+static struct platform_driver an8855_switch_driver = {
+ .probe = an8855_switch_probe,
+ .remove_new = an8855_switch_remove,
+ .driver = {
+ .name = "an8855-switch",
+ .of_match_table = an8855_switch_of_match,
+ },
+};
+module_platform_driver(an8855_switch_driver);
+
+MODULE_AUTHOR("Min Yao <min.yao@airoha.com>");
+MODULE_AUTHOR("Christian Marangi <ansuelsmth@gmail.com>");
+MODULE_DESCRIPTION("Driver for Airoha AN8855 Switch");
+MODULE_LICENSE("GPL");
--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (C) 2023 Min Yao <min.yao@airoha.com>
+ * Copyright (C) 2024 Christian Marangi <ansuelsmth@gmail.com>
+ */
+
+#ifndef __AN8855_H
+#define __AN8855_H
+
+#include <linux/bitfield.h>
+
+#define AN8855_NUM_PORTS 6
+#define AN8855_CPU_PORT 5
+#define AN8855_NUM_FDB_RECORDS 2048
+#define AN8855_GPHY_SMI_ADDR_DEFAULT 1
+#define AN8855_PORT_VID_DEFAULT 0
+
+#define MTK_TAG_LEN 4
+#define AN8855_MAX_MTU (15360 - ETH_HLEN - ETH_FCS_LEN - MTK_TAG_LEN)
+
+#define AN8855_L2_AGING_MS_CONSTANT 1024
+
+#define AN8855_PHY_FLAGS_EN_CALIBRATION BIT(0)
+
+/* AN8855_SCU 0x10000000 */
+#define AN8855_RG_GPIO_LED_MODE 0x10000054
+#define AN8855_RG_GPIO_LED_SEL(i) (0x10000000 + (0x0058 + ((i) * 4)))
+#define AN8855_RG_INTB_MODE 0x10000080
+#define AN8855_RG_RGMII_TXCK_C 0x100001d0
+
+#define AN8855_PKG_SEL 0x10000094
+#define AN8855_PAG_SEL_AN8855H 0x2
+
+/* Register for hw trap status */
+#define AN8855_HWTRAP 0x1000009c
+
+#define AN8855_RG_GPIO_L_INV 0x10000010
+#define AN8855_RG_GPIO_CTRL 0x1000a300
+#define AN8855_RG_GPIO_DATA 0x1000a304
+#define AN8855_RG_GPIO_OE 0x1000a314
+
+#define AN8855_CREV 0x10005000
+#define AN8855_ID 0x8855
+
+/* Register for system reset */
+#define AN8855_RST_CTRL 0x100050c0
+#define AN8855_SYS_CTRL_SYS_RST BIT(31)
+
+#define AN8855_INT_MASK 0x100050f0
+#define AN8855_INT_SYS BIT(15)
+
+#define AN8855_RG_CLK_CPU_ICG 0x10005034
+#define AN8855_MCU_ENABLE BIT(3)
+
+#define AN8855_RG_TIMER_CTL 0x1000a100
+#define AN8855_WDOG_ENABLE BIT(25)
+
+#define AN8855_RG_GDMP_RAM 0x10010000
+
+/* Registers to mac forward control for unknown frames */
+#define AN8855_MFC 0x10200010
+#define AN8855_CPU_EN BIT(15)
+#define AN8855_CPU_PORT_IDX GENMASK(12, 8)
+
+#define AN8855_PAC 0x10200024
+#define AN8855_TAG_PAE_MANG_FR BIT(30)
+#define AN8855_TAG_PAE_BPDU_FR BIT(28)
+#define AN8855_TAG_PAE_EG_TAG GENMASK(27, 25)
+#define AN8855_TAG_PAE_LKY_VLAN BIT(24)
+#define AN8855_TAG_PAE_PRI_HIGH BIT(23)
+#define AN8855_TAG_PAE_MIR GENMASK(20, 19)
+#define AN8855_TAG_PAE_PORT_FW GENMASK(18, 16)
+#define AN8855_PAE_MANG_FR BIT(14)
+#define AN8855_PAE_BPDU_FR BIT(12)
+#define AN8855_PAE_EG_TAG GENMASK(11, 9)
+#define AN8855_PAE_LKY_VLAN BIT(8)
+#define AN8855_PAE_PRI_HIGH BIT(7)
+#define AN8855_PAE_MIR GENMASK(4, 3)
+#define AN8855_PAE_PORT_FW GENMASK(2, 0)
+
+#define AN8855_RGAC1 0x10200028
+#define AN8855_R02_MANG_FR BIT(30)
+#define AN8855_R02_BPDU_FR BIT(28)
+#define AN8855_R02_EG_TAG GENMASK(27, 25)
+#define AN8855_R02_LKY_VLAN BIT(24)
+#define AN8855_R02_PRI_HIGH BIT(23)
+#define AN8855_R02_MIR GENMASK(20, 19)
+#define AN8855_R02_PORT_FW GENMASK(18, 16)
+#define AN8855_R01_MANG_FR BIT(14)
+#define AN8855_R01_BPDU_FR BIT(12)
+#define AN8855_R01_EG_TAG GENMASK(11, 9)
+#define AN8855_R01_LKY_VLAN BIT(8)
+#define AN8855_R01_PRI_HIGH BIT(7)
+#define AN8855_R01_MIR GENMASK(4, 3)
+#define AN8855_R01_PORT_FW GENMASK(2, 0)
+
+#define AN8855_RGAC2 0x1020002c
+#define AN8855_R0E_MANG_FR BIT(30)
+#define AN8855_R0E_BPDU_FR BIT(28)
+#define AN8855_R0E_EG_TAG GENMASK(27, 25)
+#define AN8855_R0E_LKY_VLAN BIT(24)
+#define AN8855_R0E_PRI_HIGH BIT(23)
+#define AN8855_R0E_MIR GENMASK(20, 19)
+#define AN8855_R0E_PORT_FW GENMASK(18, 16)
+#define AN8855_R03_MANG_FR BIT(14)
+#define AN8855_R03_BPDU_FR BIT(12)
+#define AN8855_R03_EG_TAG GENMASK(11, 9)
+#define AN8855_R03_LKY_VLAN BIT(8)
+#define AN8855_R03_PRI_HIGH BIT(7)
+#define AN8855_R03_MIR GENMASK(4, 3)
+#define AN8855_R03_PORT_FW GENMASK(2, 0)
+
+#define AN8855_AAC 0x102000a0
+#define AN8855_MAC_AUTO_FLUSH BIT(28)
+/* Control Address Table Age time.
+ * (AN8855_AGE_CNT + 1) * ( AN8855_AGE_UNIT + 1 ) * AN8855_L2_AGING_MS_CONSTANT
+ */
+#define AN8855_AGE_CNT GENMASK(20, 12)
+/* Value in seconds. Value is always incremented of 1 */
+#define AN8855_AGE_UNIT GENMASK(10, 0)
+
+/* Registers for ARL Unknown Unicast Forward control */
+#define AN8855_UNUF 0x102000b4
+
+/* Registers for ARL Unknown Multicast Forward control */
+#define AN8855_UNMF 0x102000b8
+
+/* Registers for ARL Broadcast forward control */
+#define AN8855_BCF 0x102000bc
+
+/* Registers for port address age disable */
+#define AN8855_AGDIS 0x102000c0
+
+/* Registers for mirror port control */
+#define AN8855_MIR 0x102000cc
+#define AN8855_MIRROR_EN BIT(7)
+#define AN8855_MIRROR_PORT GENMASK(4, 0)
+
+/* Registers for BPDU and PAE frame control*/
+#define AN8855_BPC 0x102000d0
+#define AN8855_BPDU_MANG_FR BIT(14)
+#define AN8855_BPDU_BPDU_FR BIT(12)
+#define AN8855_BPDU_EG_TAG GENMASK(11, 9)
+#define AN8855_BPDU_LKY_VLAN BIT(8)
+#define AN8855_BPDU_PRI_HIGH BIT(7)
+#define AN8855_BPDU_MIR GENMASK(4, 3)
+#define AN8855_BPDU_PORT_FW GENMASK(2, 0)
+
+/* Registers for IP Unknown Multicast Forward control */
+#define AN8855_UNIPMF 0x102000dc
+
+enum an8855_bpdu_port_fw {
+ AN8855_BPDU_FOLLOW_MFC = 0,
+ AN8855_BPDU_CPU_EXCLUDE = 4,
+ AN8855_BPDU_CPU_INCLUDE = 5,
+ AN8855_BPDU_CPU_ONLY = 6,
+ AN8855_BPDU_DROP = 7,
+};
+
+/* Register for address table control */
+#define AN8855_ATC 0x10200300
+#define AN8855_ATC_BUSY BIT(31)
+#define AN8855_ATC_HASH GENMASK(24, 16)
+#define AN8855_ATC_HIT GENMASK(15, 12)
+#define AN8855_ATC_MAT_MASK GENMASK(11, 7)
+#define AN8855_ATC_MAT(x) FIELD_PREP(AN8855_ATC_MAT_MASK, x)
+#define AN8855_ATC_SAT GENMASK(5, 4)
+#define AN8855_ATC_CMD GENMASK(2, 0)
+
+enum an8855_fdb_mat_cmds {
+ AND8855_FDB_MAT_ALL = 0,
+ AND8855_FDB_MAT_MAC, /* All MAC address */
+ AND8855_FDB_MAT_DYNAMIC_MAC, /* All Dynamic MAC address */
+ AND8855_FDB_MAT_STATIC_MAC, /* All Static Mac Address */
+ AND8855_FDB_MAT_DIP, /* All DIP/GA address */
+ AND8855_FDB_MAT_DIP_IPV4, /* All DIP/GA IPv4 address */
+ AND8855_FDB_MAT_DIP_IPV6, /* All DIP/GA IPv6 address */
+ AND8855_FDB_MAT_DIP_SIP, /* All DIP_SIP address */
+ AND8855_FDB_MAT_DIP_SIP_IPV4, /* All DIP_SIP IPv4 address */
+ AND8855_FDB_MAT_DIP_SIP_IPV6, /* All DIP_SIP IPv6 address */
+ AND8855_FDB_MAT_MAC_CVID, /* All MAC address with CVID */
+ AND8855_FDB_MAT_MAC_FID, /* All MAC address with Filter ID */
+ AND8855_FDB_MAT_MAC_PORT, /* All MAC address with port */
+ AND8855_FDB_MAT_DIP_SIP_DIP_IPV4, /* All DIP_SIP address with DIP_IPV4 */
+ AND8855_FDB_MAT_DIP_SIP_SIP_IPV4, /* All DIP_SIP address with SIP_IPV4 */
+ AND8855_FDB_MAT_DIP_SIP_DIP_IPV6, /* All DIP_SIP address with DIP_IPV6 */
+ AND8855_FDB_MAT_DIP_SIP_SIP_IPV6, /* All DIP_SIP address with SIP_IPV6 */
+ /* All MAC address with MAC type (dynamic or static) with CVID */
+ AND8855_FDB_MAT_MAC_TYPE_CVID,
+ /* All MAC address with MAC type (dynamic or static) with Filter ID */
+ AND8855_FDB_MAT_MAC_TYPE_FID,
+ /* All MAC address with MAC type (dynamic or static) with port */
+ AND8855_FDB_MAT_MAC_TYPE_PORT,
+};
+
+enum an8855_fdb_cmds {
+ AN8855_FDB_READ = 0,
+ AN8855_FDB_WRITE = 1,
+ AN8855_FDB_FLUSH = 2,
+ AN8855_FDB_START = 4,
+ AN8855_FDB_NEXT = 5,
+};
+
+/* Registers for address table access */
+#define AN8855_ATA1 0x10200304
+#define AN8855_ATA1_MAC0 GENMASK(31, 24)
+#define AN8855_ATA1_MAC1 GENMASK(23, 16)
+#define AN8855_ATA1_MAC2 GENMASK(15, 8)
+#define AN8855_ATA1_MAC3 GENMASK(7, 0)
+#define AN8855_ATA2 0x10200308
+#define AN8855_ATA2_MAC4 GENMASK(31, 24)
+#define AN8855_ATA2_MAC5 GENMASK(23, 16)
+#define AN8855_ATA2_UNAUTH BIT(10)
+#define AN8855_ATA2_TYPE BIT(9) /* 1: dynamic, 0: static */
+#define AN8855_ATA2_AGE GENMASK(8, 0)
+
+/* Register for address table write data */
+#define AN8855_ATWD 0x10200324
+#define AN8855_ATWD_FID GENMASK(31, 28)
+#define AN8855_ATWD_VID GENMASK(27, 16)
+#define AN8855_ATWD_IVL BIT(15)
+#define AN8855_ATWD_EG_TAG GENMASK(14, 12)
+#define AN8855_ATWD_SA_MIR GENMASK(9, 8)
+#define AN8855_ATWD_SA_FWD GENMASK(7, 5)
+#define AN8855_ATWD_UPRI GENMASK(4, 2)
+#define AN8855_ATWD_LEAKY BIT(1)
+#define AN8855_ATWD_VLD BIT(0) /* vid LOAD */
+#define AN8855_ATWD2 0x10200328
+#define AN8855_ATWD2_PORT GENMASK(7, 0)
+
+/* Registers for table search read address */
+#define AN8855_ATRDS 0x10200330
+#define AN8855_ATRD_SEL GENMASK(1, 0)
+#define AN8855_ATRD0 0x10200334
+#define AN8855_ATRD0_FID GENMASK(28, 25)
+#define AN8855_ATRD0_VID GENMASK(21, 10)
+#define AN8855_ATRD0_IVL BIT(9)
+#define AN8855_ATRD0_TYPE GENMASK(4, 3)
+#define AN8855_ATRD0_ARP GENMASK(2, 1)
+#define AN8855_ATRD0_LIVE BIT(0)
+#define AN8855_ATRD1 0x10200338
+#define AN8855_ATRD1_MAC4 GENMASK(31, 24)
+#define AN8855_ATRD1_MAC5 GENMASK(23, 16)
+#define AN8855_ATRD1_AGING GENMASK(11, 3)
+#define AN8855_ATRD2 0x1020033c
+#define AN8855_ATRD2_MAC0 GENMASK(31, 24)
+#define AN8855_ATRD2_MAC1 GENMASK(23, 16)
+#define AN8855_ATRD2_MAC2 GENMASK(15, 8)
+#define AN8855_ATRD2_MAC3 GENMASK(7, 0)
+#define AN8855_ATRD3 0x10200340
+#define AN8855_ATRD3_PORTMASK GENMASK(7, 0)
+
+enum an8855_fdb_type {
+ AN8855_MAC_TB_TY_MAC = 0,
+ AN8855_MAC_TB_TY_DIP = 1,
+ AN8855_MAC_TB_TY_DIP_SIP = 2,
+};
+
+/* Register for vlan table control */
+#define AN8855_VTCR 0x10200600
+#define AN8855_VTCR_BUSY BIT(31)
+#define AN8855_VTCR_FUNC GENMASK(15, 12)
+#define AN8855_VTCR_VID GENMASK(11, 0)
+
+enum an8855_vlan_cmd {
+ /* Read/Write the specified VID entry from VAWD register based
+ * on VID.
+ */
+ AN8855_VTCR_RD_VID = 0,
+ AN8855_VTCR_WR_VID = 1,
+};
+
+/* Register for setup vlan write data */
+#define AN8855_VAWD0 0x10200604
+/* VLAN Member Control */
+#define AN8855_VA0_PORT GENMASK(31, 26)
+/* Egress Tag Control */
+#define AN8855_VA0_ETAG GENMASK(23, 12)
+#define AN8855_VA0_ETAG_PORT GENMASK(13, 12)
+#define AN8855_VA0_ETAG_PORT_SHIFT(port) ((port) * 2)
+#define AN8855_VA0_ETAG_PORT_MASK(port) (AN8855_VA0_ETAG_PORT << \
+ AN8855_VA0_ETAG_PORT_SHIFT(port))
+#define AN8855_VA0_ETAG_PORT_VAL(port, val) (FIELD_PREP(AN8855_VA0_ETAG_PORT, (val)) << \
+ AN8855_VA0_ETAG_PORT_SHIFT(port))
+#define AN8855_VA0_EG_CON BIT(11)
+#define AN8855_VA0_VTAG_EN BIT(10) /* Per VLAN Egress Tag Control */
+#define AN8855_VA0_IVL_MAC BIT(5) /* Independent VLAN Learning */
+#define AN8855_VA0_FID GENMASK(4, 1)
+#define AN8855_VA0_VLAN_VALID BIT(0) /* VLAN Entry Valid */
+#define AN8855_VAWD1 0x10200608
+#define AN8855_VA1_PORT_STAG BIT(1)
+
+enum an8855_fid {
+ AN8855_FID_STANDALONE = 0,
+ AN8855_FID_BRIDGED = 1,
+};
+
+/* Same register field of VAWD0 */
+#define AN8855_VARD0 0x10200618
+
+enum an8855_vlan_egress_attr {
+ AN8855_VLAN_EGRESS_UNTAG = 0,
+ AN8855_VLAN_EGRESS_TAG = 2,
+ AN8855_VLAN_EGRESS_STACK = 3,
+};
+
+/* Register for port STP state control */
+#define AN8855_SSP_P(x) (0x10208000 + ((x) * 0x200))
+/* Up to 16 FID supported, each with the same mask */
+#define AN8855_FID_PST GENMASK(1, 0)
+#define AN8855_FID_PST_SHIFT(fid) (2 * (fid))
+#define AN8855_FID_PST_MASK(fid) (AN8855_FID_PST << \
+ AN8855_FID_PST_SHIFT(fid))
+#define AN8855_FID_PST_VAL(fid, val) (FIELD_PREP(AN8855_FID_PST, (val)) << \
+ AN8855_FID_PST_SHIFT(fid))
+
+enum an8855_stp_state {
+ AN8855_STP_DISABLED = 0,
+ AN8855_STP_BLOCKING = 1,
+ AN8855_STP_LISTENING = AN8855_STP_BLOCKING,
+ AN8855_STP_LEARNING = 2,
+ AN8855_STP_FORWARDING = 3
+};
+
+/* Register for port control */
+#define AN8855_PCR_P(x) (0x10208004 + ((x) * 0x200))
+#define AN8855_EG_TAG GENMASK(29, 28)
+#define AN8855_PORT_PRI GENMASK(26, 24)
+#define AN8855_PORT_TX_MIR BIT(20)
+#define AN8855_PORT_RX_MIR BIT(16)
+#define AN8855_PORT_VLAN GENMASK(1, 0)
+
+enum an8855_port_mode {
+ /* Port Matrix Mode: Frames are forwarded by the PCR_MATRIX members. */
+ AN8855_PORT_MATRIX_MODE = 0,
+
+ /* Fallback Mode: Forward received frames with ingress ports that do
+ * not belong to the VLAN member. Frames whose VID is not listed on
+ * the VLAN table are forwarded by the PCR_MATRIX members.
+ */
+ AN8855_PORT_FALLBACK_MODE = 1,
+
+ /* Check Mode: Forward received frames whose ingress do not
+ * belong to the VLAN member. Discard frames if VID ismiddes on the
+ * VLAN table.
+ */
+ AN8855_PORT_CHECK_MODE = 2,
+
+ /* Security Mode: Discard any frame due to ingress membership
+ * violation or VID missed on the VLAN table.
+ */
+ AN8855_PORT_SECURITY_MODE = 3,
+};
+
+/* Register for port security control */
+#define AN8855_PSC_P(x) (0x1020800c + ((x) * 0x200))
+#define AN8855_SA_DIS BIT(4)
+
+/* Register for port vlan control */
+#define AN8855_PVC_P(x) (0x10208010 + ((x) * 0x200))
+#define AN8855_PORT_SPEC_REPLACE_MODE BIT(11)
+#define AN8855_PVC_EG_TAG GENMASK(10, 8)
+#define AN8855_VLAN_ATTR GENMASK(7, 6)
+#define AN8855_PORT_SPEC_TAG BIT(5)
+#define AN8855_ACC_FRM GENMASK(1, 0)
+
+enum an8855_vlan_port_eg_tag {
+ AN8855_VLAN_EG_DISABLED = 0,
+ AN8855_VLAN_EG_CONSISTENT = 1,
+ AN8855_VLAN_EG_UNTAGGED = 4,
+ AN8855_VLAN_EG_SWAP = 5,
+ AN8855_VLAN_EG_TAGGED = 6,
+ AN8855_VLAN_EG_STACK = 7,
+};
+
+enum an8855_vlan_port_attr {
+ AN8855_VLAN_USER = 0,
+ AN8855_VLAN_STACK = 1,
+ AN8855_VLAN_TRANSPARENT = 3,
+};
+
+enum an8855_vlan_port_acc_frm {
+ AN8855_VLAN_ACC_ALL = 0,
+ AN8855_VLAN_ACC_TAGGED = 1,
+ AN8855_VLAN_ACC_UNTAGGED = 2,
+};
+
+#define AN8855_PPBV1_P(x) (0x10208014 + ((x) * 0x200))
+#define AN8855_PPBV_G0_PORT_VID GENMASK(11, 0)
+
+#define AN8855_PORTMATRIX_P(x) (0x10208044 + ((x) * 0x200))
+#define AN8855_PORTMATRIX GENMASK(5, 0)
+/* Port matrix without the CPU port that should never be removed */
+#define AN8855_USER_PORTMATRIX GENMASK(4, 0)
+
+/* Register for port PVID */
+#define AN8855_PVID_P(x) (0x10208048 + ((x) * 0x200))
+#define AN8855_G0_PORT_VID GENMASK(11, 0)
+
+/* Register for port MAC control register */
+#define AN8855_PMCR_P(x) (0x10210000 + ((x) * 0x200))
+#define AN8855_PMCR_FORCE_MODE BIT(31)
+#define AN8855_PMCR_FORCE_SPEED GENMASK(30, 28)
+#define AN8855_PMCR_FORCE_SPEED_5000 FIELD_PREP_CONST(AN8855_PMCR_FORCE_SPEED, 0x4)
+#define AN8855_PMCR_FORCE_SPEED_2500 FIELD_PREP_CONST(AN8855_PMCR_FORCE_SPEED, 0x3)
+#define AN8855_PMCR_FORCE_SPEED_1000 FIELD_PREP_CONST(AN8855_PMCR_FORCE_SPEED, 0x2)
+#define AN8855_PMCR_FORCE_SPEED_100 FIELD_PREP_CONST(AN8855_PMCR_FORCE_SPEED, 0x1)
+#define AN8855_PMCR_FORCE_SPEED_10 FIELD_PREP_CONST(AN8855_PMCR_FORCE_SPEED, 0x1)
+#define AN8855_PMCR_FORCE_FDX BIT(25)
+#define AN8855_PMCR_FORCE_LNK BIT(24)
+#define AN8855_PMCR_IFG_XMIT GENMASK(21, 20)
+#define AN8855_PMCR_EXT_PHY BIT(19)
+#define AN8855_PMCR_MAC_MODE BIT(18)
+#define AN8855_PMCR_TX_EN BIT(16)
+#define AN8855_PMCR_RX_EN BIT(15)
+#define AN8855_PMCR_BACKOFF_EN BIT(12)
+#define AN8855_PMCR_BACKPR_EN BIT(11)
+#define AN8855_PMCR_FORCE_EEE5G BIT(9)
+#define AN8855_PMCR_FORCE_EEE2P5G BIT(8)
+#define AN8855_PMCR_FORCE_EEE1G BIT(7)
+#define AN8855_PMCR_FORCE_EEE100 BIT(6)
+#define AN8855_PMCR_TX_FC_EN BIT(5)
+#define AN8855_PMCR_RX_FC_EN BIT(4)
+
+#define AN8855_PMSR_P(x) (0x10210010 + (x) * 0x200)
+#define AN8855_PMSR_SPEED GENMASK(30, 28)
+#define AN8855_PMSR_SPEED_5000 FIELD_PREP_CONST(AN8855_PMSR_SPEED, 0x4)
+#define AN8855_PMSR_SPEED_2500 FIELD_PREP_CONST(AN8855_PMSR_SPEED, 0x3)
+#define AN8855_PMSR_SPEED_1000 FIELD_PREP_CONST(AN8855_PMSR_SPEED, 0x2)
+#define AN8855_PMSR_SPEED_100 FIELD_PREP_CONST(AN8855_PMSR_SPEED, 0x1)
+#define AN8855_PMSR_SPEED_10 FIELD_PREP_CONST(AN8855_PMSR_SPEED, 0x0)
+#define AN8855_PMSR_DPX BIT(25)
+#define AN8855_PMSR_LNK BIT(24)
+#define AN8855_PMSR_EEE1G BIT(7)
+#define AN8855_PMSR_EEE100M BIT(6)
+#define AN8855_PMSR_RX_FC BIT(5)
+#define AN8855_PMSR_TX_FC BIT(4)
+
+#define AN8855_PMEEECR_P(x) (0x10210004 + (x) * 0x200)
+#define AN8855_LPI_MODE_EN BIT(31)
+#define AN8855_WAKEUP_TIME_2500 GENMASK(23, 16)
+#define AN8855_WAKEUP_TIME_1000 GENMASK(15, 8)
+#define AN8855_WAKEUP_TIME_100 GENMASK(7, 0)
+#define AN8855_PMEEECR2_P(x) (0x10210008 + (x) * 0x200)
+#define AN8855_WAKEUP_TIME_5000 GENMASK(7, 0)
+
+#define AN8855_GMACCR 0x10213e00
+#define AN8855_MAX_RX_JUMBO GENMASK(7, 4)
+/* 2K for 0x0, 0x1, 0x2 */
+#define AN8855_MAX_RX_JUMBO_2K FIELD_PREP_CONST(AN8855_MAX_RX_JUMBO, 0x0)
+#define AN8855_MAX_RX_JUMBO_3K FIELD_PREP_CONST(AN8855_MAX_RX_JUMBO, 0x3)
+#define AN8855_MAX_RX_JUMBO_4K FIELD_PREP_CONST(AN8855_MAX_RX_JUMBO, 0x4)
+#define AN8855_MAX_RX_JUMBO_5K FIELD_PREP_CONST(AN8855_MAX_RX_JUMBO, 0x5)
+#define AN8855_MAX_RX_JUMBO_6K FIELD_PREP_CONST(AN8855_MAX_RX_JUMBO, 0x6)
+#define AN8855_MAX_RX_JUMBO_7K FIELD_PREP_CONST(AN8855_MAX_RX_JUMBO, 0x7)
+#define AN8855_MAX_RX_JUMBO_8K FIELD_PREP_CONST(AN8855_MAX_RX_JUMBO, 0x8)
+#define AN8855_MAX_RX_JUMBO_9K FIELD_PREP_CONST(AN8855_MAX_RX_JUMBO, 0x9)
+#define AN8855_MAX_RX_JUMBO_12K FIELD_PREP_CONST(AN8855_MAX_RX_JUMBO, 0xa)
+#define AN8855_MAX_RX_JUMBO_15K FIELD_PREP_CONST(AN8855_MAX_RX_JUMBO, 0xb)
+#define AN8855_MAX_RX_JUMBO_16K FIELD_PREP_CONST(AN8855_MAX_RX_JUMBO, 0xc)
+#define AN8855_MAX_RX_PKT_LEN GENMASK(1, 0)
+#define AN8855_MAX_RX_PKT_1518_1522 FIELD_PREP_CONST(AN8855_MAX_RX_PKT_LEN, 0x0)
+#define AN8855_MAX_RX_PKT_1536 FIELD_PREP_CONST(AN8855_MAX_RX_PKT_LEN, 0x1)
+#define AN8855_MAX_RX_PKT_1552 FIELD_PREP_CONST(AN8855_MAX_RX_PKT_LEN, 0x2)
+#define AN8855_MAX_RX_PKT_JUMBO FIELD_PREP_CONST(AN8855_MAX_RX_PKT_LEN, 0x3)
+
+#define AN8855_CKGCR 0x10213e1c
+#define AN8855_LPI_TXIDLE_THD_MASK GENMASK(31, 14)
+#define AN8855_CKG_LNKDN_PORT_STOP BIT(1)
+#define AN8855_CKG_LNKDN_GLB_STOP BIT(0)
+
+/* Register for MIB */
+#define AN8855_PORT_MIB_COUNTER(x) (0x10214000 + (x) * 0x200)
+/* Each define is an offset of AN8855_PORT_MIB_COUNTER */
+#define AN8855_PORT_MIB_TX_DROP 0x00
+#define AN8855_PORT_MIB_TX_CRC_ERR 0x04
+#define AN8855_PORT_MIB_TX_UNICAST 0x08
+#define AN8855_PORT_MIB_TX_MULTICAST 0x0c
+#define AN8855_PORT_MIB_TX_BROADCAST 0x10
+#define AN8855_PORT_MIB_TX_COLLISION 0x14
+#define AN8855_PORT_MIB_TX_SINGLE_COLLISION 0x18
+#define AN8855_PORT_MIB_TX_MULTIPLE_COLLISION 0x1c
+#define AN8855_PORT_MIB_TX_DEFERRED 0x20
+#define AN8855_PORT_MIB_TX_LATE_COLLISION 0x24
+#define AN8855_PORT_MIB_TX_EXCESSIVE_COLLISION 0x28
+#define AN8855_PORT_MIB_TX_PAUSE 0x2c
+#define AN8855_PORT_MIB_TX_PKT_SZ_64 0x30
+#define AN8855_PORT_MIB_TX_PKT_SZ_65_TO_127 0x34
+#define AN8855_PORT_MIB_TX_PKT_SZ_128_TO_255 0x38
+#define AN8855_PORT_MIB_TX_PKT_SZ_256_TO_511 0x3
+#define AN8855_PORT_MIB_TX_PKT_SZ_512_TO_1023 0x40
+#define AN8855_PORT_MIB_TX_PKT_SZ_1024_TO_1518 0x44
+#define AN8855_PORT_MIB_TX_PKT_SZ_1519_TO_MAX 0x48
+#define AN8855_PORT_MIB_TX_BYTES 0x4c /* 64 bytes */
+#define AN8855_PORT_MIB_TX_OVERSIZE_DROP 0x54
+#define AN8855_PORT_MIB_TX_BAD_PKT_BYTES 0x58 /* 64 bytes */
+#define AN8855_PORT_MIB_RX_DROP 0x80
+#define AN8855_PORT_MIB_RX_FILTERING 0x84
+#define AN8855_PORT_MIB_RX_UNICAST 0x88
+#define AN8855_PORT_MIB_RX_MULTICAST 0x8c
+#define AN8855_PORT_MIB_RX_BROADCAST 0x90
+#define AN8855_PORT_MIB_RX_ALIGN_ERR 0x94
+#define AN8855_PORT_MIB_RX_CRC_ERR 0x98
+#define AN8855_PORT_MIB_RX_UNDER_SIZE_ERR 0x9c
+#define AN8855_PORT_MIB_RX_FRAG_ERR 0xa0
+#define AN8855_PORT_MIB_RX_OVER_SZ_ERR 0xa4
+#define AN8855_PORT_MIB_RX_JABBER_ERR 0xa8
+#define AN8855_PORT_MIB_RX_PAUSE 0xac
+#define AN8855_PORT_MIB_RX_PKT_SZ_64 0xb0
+#define AN8855_PORT_MIB_RX_PKT_SZ_65_TO_127 0xb4
+#define AN8855_PORT_MIB_RX_PKT_SZ_128_TO_255 0xb8
+#define AN8855_PORT_MIB_RX_PKT_SZ_256_TO_511 0xbc
+#define AN8855_PORT_MIB_RX_PKT_SZ_512_TO_1023 0xc0
+#define AN8855_PORT_MIB_RX_PKT_SZ_1024_TO_1518 0xc4
+#define AN8855_PORT_MIB_RX_PKT_SZ_1519_TO_MAX 0xc8
+#define AN8855_PORT_MIB_RX_BYTES 0xcc /* 64 bytes */
+#define AN8855_PORT_MIB_RX_CTRL_DROP 0xd4
+#define AN8855_PORT_MIB_RX_INGRESS_DROP 0xd8
+#define AN8855_PORT_MIB_RX_ARL_DROP 0xdc
+#define AN8855_PORT_MIB_FLOW_CONTROL_DROP 0xe0
+#define AN8855_PORT_MIB_WRED_DROP 0xe4
+#define AN8855_PORT_MIB_MIRROR_DROP 0xe8
+#define AN8855_PORT_MIB_RX_BAD_PKT_BYTES 0xec /* 64 bytes */
+#define AN8855_PORT_MIB_RXS_FLOW_SAMPLING_PKT_DROP 0xf4
+#define AN8855_PORT_MIB_RXS_FLOW_TOTAL_PKT_DROP 0xf8
+#define AN8855_PORT_MIB_PORT_CONTROL_DROP 0xfc
+#define AN8855_MIB_CCR 0x10213e30
+#define AN8855_CCR_MIB_ENABLE BIT(31)
+#define AN8855_CCR_RX_OCT_CNT_GOOD BIT(7)
+#define AN8855_CCR_RX_OCT_CNT_BAD BIT(6)
+#define AN8855_CCR_TX_OCT_CNT_GOOD BIT(5)
+#define AN8855_CCR_TX_OCT_CNT_BAD BIT(4)
+#define AN8855_CCR_RX_OCT_CNT_GOOD_2 BIT(3)
+#define AN8855_CCR_RX_OCT_CNT_BAD_2 BIT(2)
+#define AN8855_CCR_TX_OCT_CNT_GOOD_2 BIT(1)
+#define AN8855_CCR_TX_OCT_CNT_BAD_2 BIT(0)
+#define AN8855_CCR_MIB_ACTIVATE (AN8855_CCR_MIB_ENABLE | \
+ AN8855_CCR_RX_OCT_CNT_GOOD | \
+ AN8855_CCR_RX_OCT_CNT_BAD | \
+ AN8855_CCR_TX_OCT_CNT_GOOD | \
+ AN8855_CCR_TX_OCT_CNT_BAD | \
+ AN8855_CCR_RX_OCT_CNT_BAD_2 | \
+ AN8855_CCR_TX_OCT_CNT_BAD_2)
+#define AN8855_MIB_CLR 0x10213e34
+#define AN8855_MIB_PORT6_CLR BIT(6)
+#define AN8855_MIB_PORT5_CLR BIT(5)
+#define AN8855_MIB_PORT4_CLR BIT(4)
+#define AN8855_MIB_PORT3_CLR BIT(3)
+#define AN8855_MIB_PORT2_CLR BIT(2)
+#define AN8855_MIB_PORT1_CLR BIT(1)
+#define AN8855_MIB_PORT0_CLR BIT(0)
+
+/* HSGMII/SGMII Configuration register */
+/* AN8855_HSGMII_AN_CSR_BASE 0x10220000 */
+#define AN8855_SGMII_REG_AN0 0x10220000
+/* AN8855_SGMII_AN_ENABLE BMCR_ANENABLE */
+/* AN8855_SGMII_AN_RESTART BMCR_ANRESTART */
+#define AN8855_SGMII_REG_AN_13 0x10220034
+#define AN8855_SGMII_REMOTE_FAULT_DIS BIT(8)
+#define AN8855_SGMII_IF_MODE GENMASK(5, 0)
+#define AN8855_SGMII_REG_AN_FORCE_CL37 0x10220060
+#define AN8855_RG_FORCE_AN_DONE BIT(0)
+
+/* AN8855_HSGMII_CSR_PCS_BASE 0x10220000 */
+#define AN8855_RG_HSGMII_PCS_CTROL_1 0x10220a00
+#define AN8855_RG_TBI_10B_MODE BIT(30)
+#define AN8855_RG_AN_SGMII_MODE_FORCE 0x10220a24
+#define AN8855_RG_FORCE_CUR_SGMII_MODE GENMASK(5, 4)
+#define AN8855_RG_FORCE_CUR_SGMII_SEL BIT(0)
+
+/* AN8855_MULTI_SGMII_CSR_BASE 0x10224000 */
+#define AN8855_SGMII_STS_CTRL_0 0x10224018
+#define AN8855_RG_LINK_MODE_P0 GENMASK(5, 4)
+#define AN8855_RG_LINK_MODE_P0_SPEED_2500 FIELD_PREP_CONST(AN8855_RG_LINK_MODE_P0, 0x3)
+#define AN8855_RG_LINK_MODE_P0_SPEED_1000 FIELD_PREP_CONST(AN8855_RG_LINK_MODE_P0, 0x2)
+#define AN8855_RG_LINK_MODE_P0_SPEED_100 FIELD_PREP_CONST(AN8855_RG_LINK_MODE_P0, 0x1)
+#define AN8855_RG_LINK_MODE_P0_SPEED_10 FIELD_PREP_CONST(AN8855_RG_LINK_MODE_P0, 0x0)
+#define AN8855_RG_FORCE_SPD_MODE_P0 BIT(2)
+#define AN8855_MSG_RX_CTRL_0 0x10224100
+#define AN8855_MSG_RX_LIK_STS_0 0x10224514
+#define AN8855_RG_DPX_STS_P3 BIT(24)
+#define AN8855_RG_DPX_STS_P2 BIT(16)
+#define AN8855_RG_EEE1G_STS_P1 BIT(12)
+#define AN8855_RG_DPX_STS_P1 BIT(8)
+#define AN8855_RG_TXFC_STS_P0 BIT(2)
+#define AN8855_RG_RXFC_STS_P0 BIT(1)
+#define AN8855_RG_DPX_STS_P0 BIT(0)
+#define AN8855_MSG_RX_LIK_STS_2 0x1022451c
+#define AN8855_RG_RXFC_AN_BYPASS_P3 BIT(11)
+#define AN8855_RG_RXFC_AN_BYPASS_P2 BIT(10)
+#define AN8855_RG_RXFC_AN_BYPASS_P1 BIT(9)
+#define AN8855_RG_TXFC_AN_BYPASS_P3 BIT(7)
+#define AN8855_RG_TXFC_AN_BYPASS_P2 BIT(6)
+#define AN8855_RG_TXFC_AN_BYPASS_P1 BIT(5)
+#define AN8855_RG_DPX_AN_BYPASS_P3 BIT(3)
+#define AN8855_RG_DPX_AN_BYPASS_P2 BIT(2)
+#define AN8855_RG_DPX_AN_BYPASS_P1 BIT(1)
+#define AN8855_RG_DPX_AN_BYPASS_P0 BIT(0)
+#define AN8855_PHY_RX_FORCE_CTRL_0 0x10224520
+#define AN8855_RG_FORCE_TXC_SEL BIT(4)
+
+/* AN8855_XFI_CSR_PCS_BASE 0x10225000 */
+#define AN8855_RG_USXGMII_AN_CONTROL_0 0x10225bf8
+
+/* AN8855_MULTI_PHY_RA_CSR_BASE 0x10226000 */
+#define AN8855_RG_RATE_ADAPT_CTRL_0 0x10226000
+#define AN8855_RG_RATE_ADAPT_RX_BYPASS BIT(27)
+#define AN8855_RG_RATE_ADAPT_TX_BYPASS BIT(26)
+#define AN8855_RG_RATE_ADAPT_RX_EN BIT(4)
+#define AN8855_RG_RATE_ADAPT_TX_EN BIT(0)
+#define AN8855_RATE_ADP_P0_CTRL_0 0x10226100
+#define AN8855_RG_P0_DIS_MII_MODE BIT(31)
+#define AN8855_RG_P0_MII_MODE BIT(28)
+#define AN8855_RG_P0_MII_RA_RX_EN BIT(3)
+#define AN8855_RG_P0_MII_RA_TX_EN BIT(2)
+#define AN8855_RG_P0_MII_RA_RX_MODE BIT(1)
+#define AN8855_RG_P0_MII_RA_TX_MODE BIT(0)
+#define AN8855_MII_RA_AN_ENABLE 0x10226300
+#define AN8855_RG_P0_RA_AN_EN BIT(0)
+
+/* AN8855_QP_DIG_CSR_BASE 0x1022a000 */
+#define AN8855_QP_CK_RST_CTRL_4 0x1022a310
+#define AN8855_QP_DIG_MODE_CTRL_0 0x1022a324
+#define AN8855_RG_SGMII_MODE GENMASK(5, 4)
+#define AN8855_RG_SGMII_AN_EN BIT(0)
+#define AN8855_QP_DIG_MODE_CTRL_1 0x1022a330
+#define AN8855_RG_TPHY_SPEED GENMASK(3, 2)
+
+/* AN8855_SERDES_WRAPPER_BASE 0x1022c000 */
+#define AN8855_USGMII_CTRL_0 0x1022c000
+
+/* AN8855_QP_PMA_TOP_BASE 0x1022e000 */
+#define AN8855_PON_RXFEDIG_CTRL_0 0x1022e100
+#define AN8855_RG_QP_EQ_RX500M_CK_SEL BIT(12)
+#define AN8855_PON_RXFEDIG_CTRL_9 0x1022e124
+#define AN8855_RG_QP_EQ_LEQOSC_DLYCNT GENMASK(2, 0)
+
+#define AN8855_SS_LCPLL_PWCTL_SETTING_2 0x1022e208
+#define AN8855_RG_NCPO_ANA_MSB GENMASK(17, 16)
+#define AN8855_SS_LCPLL_TDC_FLT_2 0x1022e230
+#define AN8855_RG_LCPLL_NCPO_VALUE GENMASK(30, 0)
+#define AN8855_SS_LCPLL_TDC_FLT_5 0x1022e23c
+#define AN8855_RG_LCPLL_NCPO_CHG BIT(24)
+#define AN8855_SS_LCPLL_TDC_PCW_1 0x1022e248
+#define AN8855_RG_LCPLL_PON_HRDDS_PCW_NCPO_GPON GENMASK(30, 0)
+#define AN8855_INTF_CTRL_8 0x1022e320
+#define AN8855_INTF_CTRL_9 0x1022e324
+#define AN8855_INTF_CTRL_10 0x1022e328
+#define AN8855_RG_DA_QP_TX_FIR_C2_SEL BIT(29)
+#define AN8855_RG_DA_QP_TX_FIR_C2_FORCE GENMASK(28, 24)
+#define AN8855_RG_DA_QP_TX_FIR_C1_SEL BIT(21)
+#define AN8855_RG_DA_QP_TX_FIR_C1_FORCE GENMASK(20, 16)
+#define AN8855_INTF_CTRL_11 0x1022e32c
+#define AN8855_RG_DA_QP_TX_FIR_C0B_SEL BIT(6)
+#define AN8855_RG_DA_QP_TX_FIR_C0B_FORCE GENMASK(5, 0)
+#define AN8855_PLL_CTRL_0 0x1022e400
+#define AN8855_RG_PHYA_AUTO_INIT BIT(0)
+#define AN8855_PLL_CTRL_2 0x1022e408
+#define AN8855_RG_DA_QP_PLL_SDM_IFM_INTF BIT(30)
+#define AN8855_RG_DA_QP_PLL_RICO_SEL_INTF BIT(29)
+#define AN8855_RG_DA_QP_PLL_POSTDIV_EN_INTF BIT(28)
+#define AN8855_RG_DA_QP_PLL_PHY_CK_EN_INTF BIT(27)
+#define AN8855_RG_DA_QP_PLL_PFD_OFFSET_EN_INTRF BIT(26)
+#define AN8855_RG_DA_QP_PLL_PFD_OFFSET_INTF GENMASK(25, 24)
+#define AN8855_RG_DA_QP_PLL_PCK_SEL_INTF BIT(22)
+#define AN8855_RG_DA_QP_PLL_KBAND_PREDIV_INTF GENMASK(21, 20)
+#define AN8855_RG_DA_QP_PLL_IR_INTF GENMASK(19, 16)
+#define AN8855_RG_DA_QP_PLL_ICOIQ_EN_INTF BIT(14)
+#define AN8855_RG_DA_QP_PLL_FBKSEL_INTF GENMASK(13, 12)
+#define AN8855_RG_DA_QP_PLL_BR_INTF GENMASK(10, 8)
+#define AN8855_RG_DA_QP_PLL_BPD_INTF GENMASK(7, 6)
+#define AN8855_RG_DA_QP_PLL_BPA_INTF GENMASK(4, 2)
+#define AN8855_RG_DA_QP_PLL_BC_INTF GENMASK(1, 0)
+#define AN8855_PLL_CTRL_3 0x1022e40c
+#define AN8855_RG_DA_QP_PLL_SSC_PERIOD_INTF GENMASK(31, 16)
+#define AN8855_RG_DA_QP_PLL_SSC_DELTA_INTF GENMASK(15, 0)
+#define AN8855_PLL_CTRL_4 0x1022e410
+#define AN8855_RG_DA_QP_PLL_SDM_HREN_INTF GENMASK(4, 3)
+#define AN8855_RG_DA_QP_PLL_ICOLP_EN_INTF BIT(2)
+#define AN8855_RG_DA_QP_PLL_SSC_DIR_DLY_INTF GENMASK(1, 0)
+#define AN8855_PLL_CK_CTRL_0 0x1022e414
+#define AN8855_RG_DA_QP_PLL_TDC_TXCK_SEL_INTF BIT(9)
+#define AN8855_RG_DA_QP_PLL_SDM_DI_EN_INTF BIT(8)
+#define AN8855_RX_DLY_0 0x1022e614
+#define AN8855_RG_QP_RX_SAOSC_EN_H_DLY GENMASK(13, 8)
+#define AN8855_RG_QP_RX_PI_CAL_EN_H_DLY GENMASK(7, 0)
+#define AN8855_RX_CTRL_2 0x1022e630
+#define AN8855_RG_QP_RX_EQ_EN_H_DLY GENMASK(28, 16)
+#define AN8855_RX_CTRL_5 0x1022e63c
+#define AN8855_RG_FREDET_CHK_CYCLE GENMASK(29, 10)
+#define AN8855_RX_CTRL_6 0x1022e640
+#define AN8855_RG_FREDET_GOLDEN_CYCLE GENMASK(19, 0)
+#define AN8855_RX_CTRL_7 0x1022e644
+#define AN8855_RG_FREDET_TOLERATE_CYCLE GENMASK(19, 0)
+#define AN8855_RX_CTRL_8 0x1022e648
+#define AN8855_RG_DA_QP_SAOSC_DONE_TIME GENMASK(27, 16)
+#define AN8855_RG_DA_QP_LEQOS_EN_TIME GENMASK(14, 0)
+#define AN8855_RX_CTRL_26 0x1022e690
+#define AN8855_RG_QP_EQ_RETRAIN_ONLY_EN BIT(26)
+#define AN8855_RG_LINK_NE_EN BIT(24)
+#define AN8855_RG_LINK_ERRO_EN BIT(23)
+#define AN8855_RX_CTRL_42 0x1022e6d0
+#define AN8855_RG_QP_EQ_EN_DLY GENMASK(12, 0)
+
+/* AN8855_QP_ANA_CSR_BASE 0x1022f000 */
+#define AN8855_RG_QP_RX_DAC_EN 0x1022f000
+#define AN8855_RG_QP_SIGDET_HF GENMASK(17, 16)
+#define AN8855_RG_QP_RXAFE_RESERVE 0x1022f004
+#define AN8855_RG_QP_CDR_PD_10B_EN BIT(11)
+#define AN8855_RG_QP_CDR_LPF_BOT_LIM 0x1022f008
+#define AN8855_RG_QP_CDR_LPF_KP_GAIN GENMASK(26, 24)
+#define AN8855_RG_QP_CDR_LPF_KI_GAIN GENMASK(22, 20)
+#define AN8855_RG_QP_CDR_LPF_MJV_LIM 0x1022f00c
+#define AN8855_RG_QP_CDR_LPF_RATIO GENMASK(5, 4)
+#define AN8855_RG_QP_CDR_LPF_SETVALUE 0x1022f014
+#define AN8855_RG_QP_CDR_PR_BUF_IN_SR GENMASK(31, 29)
+#define AN8855_RG_QP_CDR_PR_BETA_SEL GENMASK(28, 25)
+#define AN8855_RG_QP_CDR_PR_CKREF_DIV1 0x1022f018
+#define AN8855_RG_QP_CDR_PR_KBAND_DIV GENMASK(26, 24)
+#define AN8855_RG_QP_CDR_PR_DAC_BAND GENMASK(12, 8)
+#define AN8855_RG_QP_CDR_PR_KBAND_DIV_PCIE 0x1022f01c
+#define AN8855_RG_QP_CDR_PR_XFICK_EN BIT(30)
+#define AN8855_RG_QP_CDR_PR_KBAND_PCIE_MODE BIT(6)
+#define AN8855_RG_QP_CDR_PR_KBAND_DIV_PCIE_MASK GENMASK(5, 0)
+#define AN8855_RG_QP_CDR_FORCE_IBANDLPF_R_OFF 0x1022f020
+#define AN8855_RG_QP_CDR_PHYCK_SEL GENMASK(17, 16)
+#define AN8855_RG_QP_CDR_PHYCK_RSTB BIT(13)
+#define AN8855_RG_QP_CDR_PHYCK_DIV GENMASK(12, 6)
+#define AN8855_RG_QP_TX_MODE 0x1022f028
+#define AN8855_RG_QP_TX_RESERVE GENMASK(31, 16)
+#define AN8855_RG_QP_TX_MODE_16B_EN BIT(0)
+#define AN8855_RG_QP_PLL_IPLL_DIG_PWR_SEL 0x1022f03c
+#define AN8855_RG_QP_PLL_SDM_ORD 0x1022f040
+#define AN8855_RG_QP_PLL_SSC_PHASE_INI BIT(4)
+#define AN8855_RG_QP_PLL_SSC_TRI_EN BIT(3)
+
+/* AN8855_ETHER_SYS_BASE 0x1028c800 */
+#define AN8855_RG_GPHY_AFE_PWD 0x1028c840
+#define AN8855_RG_GPHY_SMI_ADDR 0x1028c848
+
+#define MIB_DESC(_s, _o, _n) \
+ { \
+ .size = (_s), \
+ .offset = (_o), \
+ .name = (_n), \
+ }
+
+struct an8855_mib_desc {
+ unsigned int size;
+ unsigned int offset;
+ const char *name;
+};
+
+struct an8855_fdb {
+ u16 vid;
+ u8 port_mask;
+ u16 aging;
+ u8 mac[6];
+ bool noarp;
+ u8 live;
+ u8 type;
+ u8 fid;
+ u8 ivl;
+};
+
+struct an8855_priv {
+ struct device *dev;
+ struct dsa_switch *ds;
+ struct regmap *regmap;
+ struct gpio_desc *reset_gpio;
+ /* Protect ATU or VLAN table access */
+ struct mutex reg_mutex;
+
+ struct phylink_pcs pcs;
+
+ u8 mirror_rx;
+ u8 mirror_tx;
+ u8 port_isolated_map;
+
+ bool phy_require_calib;
+};
+
+#endif /* __AN8855_H */
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * MDIO passthrough driver for Airoha AN8855 Switch
+ */
+
+#include <linux/mfd/airoha-an8855-mfd.h>
+#include <linux/module.h>
+#include <linux/of_mdio.h>
+#include <linux/platform_device.h>
+
+static int an855_phy_restore_page(struct an8855_mfd_priv *priv,
+ int phy) __must_hold(&priv->bus->mdio_lock)
+{
+ /* Check PHY page only for addr shared with switch */
+ if (phy != priv->switch_addr)
+ return 0;
+
+ /* Don't restore page if it's not set to switch page */
+ if (priv->current_page != FIELD_GET(AN8855_PHY_PAGE,
+ AN8855_PHY_PAGE_EXTENDED_4))
+ return 0;
+
+ /* Restore page to 0, PHY might change page right after but that
+ * will be ignored as it won't be a switch page.
+ */
+ return an8855_mii_set_page(priv, phy, AN8855_PHY_PAGE_STANDARD);
+}
+
+static int an8855_phy_read(struct mii_bus *bus, int phy, int regnum)
+{
+ struct an8855_mfd_priv *priv = bus->priv;
+ struct mii_bus *real_bus = priv->bus;
+ int ret;
+
+ mutex_lock_nested(&real_bus->mdio_lock, MDIO_MUTEX_NESTED);
+
+ ret = an855_phy_restore_page(priv, phy);
+ if (ret)
+ goto exit;
+
+ ret = __mdiobus_read(real_bus, phy, regnum);
+exit:
+ mutex_unlock(&real_bus->mdio_lock);
+
+ return ret;
+}
+
+static int an8855_phy_write(struct mii_bus *bus, int phy, int regnum, u16 val)
+{
+ struct an8855_mfd_priv *priv = bus->priv;
+ struct mii_bus *real_bus = priv->bus;
+ int ret;
+
+ mutex_lock_nested(&real_bus->mdio_lock, MDIO_MUTEX_NESTED);
+
+ ret = an855_phy_restore_page(priv, phy);
+ if (ret)
+ goto exit;
+
+ ret = __mdiobus_write(real_bus, phy, regnum, val);
+exit:
+ mutex_unlock(&real_bus->mdio_lock);
+
+ return ret;
+}
+
+static int an8855_mdio_probe(struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+ struct an8855_mfd_priv *priv;
+ struct mii_bus *bus;
+ int ret;
+
+ /* Get priv of MFD */
+ priv = dev_get_drvdata(dev->parent);
+
+ bus = devm_mdiobus_alloc(dev);
+ if (!bus)
+ return -ENOMEM;
+
+ bus->priv = priv;
+ bus->name = KBUILD_MODNAME "-mii";
+ snprintf(bus->id, MII_BUS_ID_SIZE, KBUILD_MODNAME "-%d",
+ priv->switch_addr);
+ bus->parent = dev;
+ bus->read = an8855_phy_read;
+ bus->write = an8855_phy_write;
+
+ ret = devm_of_mdiobus_register(dev, bus, dev->of_node);
+ if (ret)
+ return dev_err_probe(dev, ret, "failed to register MDIO bus\n");
+
+ return ret;
+}
+
+static const struct of_device_id an8855_mdio_of_match[] = {
+ { .compatible = "airoha,an8855-mdio", },
+ { /* sentinel */ }
+};
+MODULE_DEVICE_TABLE(of, an8855_mdio_of_match);
+
+static struct platform_driver an8855_mdio_driver = {
+ .probe = an8855_mdio_probe,
+ .driver = {
+ .name = "an8855-mdio",
+ .of_match_table = an8855_mdio_of_match,
+ },
+};
+module_platform_driver(an8855_mdio_driver);
+
+MODULE_AUTHOR("Christian Marangi <ansuelsmth@gmail.com>");
+MODULE_DESCRIPTION("Driver for AN8855 MDIO passthrough");
+MODULE_LICENSE("GPL");
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2024 Christian Marangi <ansuelsmth@gmail.com>
+ */
+
+#include <linux/bitfield.h>
+#include <linux/module.h>
+#include <linux/nvmem-consumer.h>
+#include <linux/phy.h>
+
+#define AN8855_PHY_SELECT_PAGE 0x1f
+#define AN8855_PHY_PAGE GENMASK(2, 0)
+#define AN8855_PHY_PAGE_STANDARD FIELD_PREP_CONST(AN8855_PHY_PAGE, 0x0)
+#define AN8855_PHY_PAGE_EXTENDED_1 FIELD_PREP_CONST(AN8855_PHY_PAGE, 0x1)
+
+/* MII Registers Page 1 */
+#define AN8855_PHY_EXT_REG_14 0x14
+#define AN8855_PHY_EN_DOWN_SHIFT BIT(4)
+
+/* R50 Calibration regs in MDIO_MMD_VEND1 */
+#define AN8855_PHY_R500HM_RSEL_TX_AB 0x174
+#define AN8855_PHY_R50OHM_RSEL_TX_A_EN BIT(15)
+#define AN8855_PHY_R50OHM_RSEL_TX_A GENMASK(14, 8)
+#define AN8855_PHY_R50OHM_RSEL_TX_B_EN BIT(7)
+#define AN8855_PHY_R50OHM_RSEL_TX_B GENMASK(6, 0)
+#define AN8855_PHY_R500HM_RSEL_TX_CD 0x175
+#define AN8855_PHY_R50OHM_RSEL_TX_C_EN BIT(15)
+#define AN8855_PHY_R50OHM_RSEL_TX_C GENMASK(14, 8)
+#define AN8855_PHY_R50OHM_RSEL_TX_D_EN BIT(7)
+#define AN8855_PHY_R50OHM_RSEL_TX_D GENMASK(6, 0)
+
+#define AN8855_SWITCH_EFUSE_R50O GENMASK(30, 24)
+
+/* PHY TX PAIR DELAY SELECT Register */
+#define AN8855_PHY_TX_PAIR_DLY_SEL_GBE 0x013
+#define AN8855_PHY_CR_DA_TX_PAIR_DELKAY_SEL_A_GBE GENMASK(14, 12)
+#define AN8855_PHY_CR_DA_TX_PAIR_DELKAY_SEL_B_GBE GENMASK(10, 8)
+#define AN8855_PHY_CR_DA_TX_PAIR_DELKAY_SEL_C_GBE GENMASK(6, 4)
+#define AN8855_PHY_CR_DA_TX_PAIR_DELKAY_SEL_D_GBE GENMASK(2, 0)
+/* PHY ADC Register */
+#define AN8855_PHY_RXADC_CTRL 0x0d8
+#define AN8855_PHY_RG_AD_SAMNPLE_PHSEL_A BIT(12)
+#define AN8855_PHY_RG_AD_SAMNPLE_PHSEL_B BIT(8)
+#define AN8855_PHY_RG_AD_SAMNPLE_PHSEL_C BIT(4)
+#define AN8855_PHY_RG_AD_SAMNPLE_PHSEL_D BIT(0)
+#define AN8855_PHY_RXADC_REV_0 0x0d9
+#define AN8855_PHY_RG_AD_RESERVE0_A GENMASK(15, 8)
+#define AN8855_PHY_RG_AD_RESERVE0_B GENMASK(7, 0)
+#define AN8855_PHY_RXADC_REV_1 0x0da
+#define AN8855_PHY_RG_AD_RESERVE0_C GENMASK(15, 8)
+#define AN8855_PHY_RG_AD_RESERVE0_D GENMASK(7, 0)
+
+#define AN8855_PHY_ID 0xc0ff0410
+
+#define AN8855_PHY_FLAGS_EN_CALIBRATION BIT(0)
+
+struct air_an8855_priv {
+ u8 calibration_data[4];
+};
+
+static const u8 dsa_r50ohm_table[] = {
+ 127, 127, 127, 127, 127, 127, 127, 127, 127, 127,
+ 127, 127, 127, 127, 127, 127, 127, 126, 122, 117,
+ 112, 109, 104, 101, 97, 94, 90, 88, 84, 80,
+ 78, 74, 72, 68, 66, 64, 61, 58, 56, 53,
+ 51, 48, 47, 44, 42, 40, 38, 36, 34, 32,
+ 31, 28, 27, 24, 24, 22, 20, 18, 16, 16,
+ 14, 12, 11, 9
+};
+
+static int en8855_get_r50ohm_val(struct device *dev, const char *calib_name,
+ u8 *dest)
+{
+ u32 shift_sel, val;
+ int ret;
+ int i;
+
+ ret = nvmem_cell_read_u32(dev, calib_name, &val);
+ if (ret)
+ return ret;
+
+ shift_sel = FIELD_GET(AN8855_SWITCH_EFUSE_R50O, val);
+ for (i = 0; i < ARRAY_SIZE(dsa_r50ohm_table); i++)
+ if (dsa_r50ohm_table[i] == shift_sel)
+ break;
+
+ if (i < 8 || i >= ARRAY_SIZE(dsa_r50ohm_table))
+ *dest = dsa_r50ohm_table[25];
+ else
+ *dest = dsa_r50ohm_table[i - 8];
+
+ return 0;
+}
+
+static int an8855_probe(struct phy_device *phydev)
+{
+ struct device *dev = &phydev->mdio.dev;
+ struct device_node *node = dev->of_node;
+ struct air_an8855_priv *priv;
+
+ /* If we don't have a node, skip calib */
+ if (!node)
+ return 0;
+
+ priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
+ if (!priv)
+ return -ENOMEM;
+
+ phydev->priv = priv;
+
+ return 0;
+}
+
+static int an8855_get_downshift(struct phy_device *phydev, u8 *data)
+{
+ int val;
+
+ val = phy_read_paged(phydev, AN8855_PHY_PAGE_EXTENDED_1, AN8855_PHY_EXT_REG_14);
+ if (val < 0)
+ return val;
+
+ *data = val & AN8855_PHY_EN_DOWN_SHIFT ? DOWNSHIFT_DEV_DEFAULT_COUNT :
+ DOWNSHIFT_DEV_DISABLE;
+
+ return 0;
+}
+
+static int an8855_set_downshift(struct phy_device *phydev, u8 cnt)
+{
+ u16 ds = cnt != DOWNSHIFT_DEV_DISABLE ? AN8855_PHY_EN_DOWN_SHIFT : 0;
+
+ return phy_modify_paged(phydev, AN8855_PHY_PAGE_EXTENDED_1,
+ AN8855_PHY_EXT_REG_14, AN8855_PHY_EN_DOWN_SHIFT,
+ ds);
+}
+
+static int an8855_config_init(struct phy_device *phydev)
+{
+ struct air_an8855_priv *priv = phydev->priv;
+ struct device *dev = &phydev->mdio.dev;
+ int ret;
+
+ /* Enable HW auto downshift */
+ ret = an8855_set_downshift(phydev, DOWNSHIFT_DEV_DEFAULT_COUNT);
+ if (ret)
+ return ret;
+
+ /* Apply calibration values, if needed.
+ * AN8855_PHY_FLAGS_EN_CALIBRATION signal this.
+ */
+ if (priv && phydev->dev_flags & AN8855_PHY_FLAGS_EN_CALIBRATION) {
+ u8 *calibration_data = priv->calibration_data;
+
+ ret = en8855_get_r50ohm_val(dev, "tx_a", &calibration_data[0]);
+ if (ret)
+ return ret;
+
+ ret = en8855_get_r50ohm_val(dev, "tx_b", &calibration_data[1]);
+ if (ret)
+ return ret;
+
+ ret = en8855_get_r50ohm_val(dev, "tx_c", &calibration_data[2]);
+ if (ret)
+ return ret;
+
+ ret = en8855_get_r50ohm_val(dev, "tx_d", &calibration_data[3]);
+ if (ret)
+ return ret;
+
+ ret = phy_modify_mmd(phydev, MDIO_MMD_VEND1, AN8855_PHY_R500HM_RSEL_TX_AB,
+ AN8855_PHY_R50OHM_RSEL_TX_A | AN8855_PHY_R50OHM_RSEL_TX_B,
+ FIELD_PREP(AN8855_PHY_R50OHM_RSEL_TX_A, calibration_data[0]) |
+ FIELD_PREP(AN8855_PHY_R50OHM_RSEL_TX_B, calibration_data[1]));
+ if (ret)
+ return ret;
+ ret = phy_modify_mmd(phydev, MDIO_MMD_VEND1, AN8855_PHY_R500HM_RSEL_TX_CD,
+ AN8855_PHY_R50OHM_RSEL_TX_C | AN8855_PHY_R50OHM_RSEL_TX_D,
+ FIELD_PREP(AN8855_PHY_R50OHM_RSEL_TX_C, calibration_data[2]) |
+ FIELD_PREP(AN8855_PHY_R50OHM_RSEL_TX_D, calibration_data[3]));
+ if (ret)
+ return ret;
+ }
+
+ /* Apply values to reduce signal noise */
+ ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, AN8855_PHY_TX_PAIR_DLY_SEL_GBE,
+ FIELD_PREP(AN8855_PHY_CR_DA_TX_PAIR_DELKAY_SEL_A_GBE, 0x4) |
+ FIELD_PREP(AN8855_PHY_CR_DA_TX_PAIR_DELKAY_SEL_C_GBE, 0x4));
+ if (ret)
+ return ret;
+ ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, AN8855_PHY_RXADC_CTRL,
+ AN8855_PHY_RG_AD_SAMNPLE_PHSEL_A |
+ AN8855_PHY_RG_AD_SAMNPLE_PHSEL_C);
+ if (ret)
+ return ret;
+ ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, AN8855_PHY_RXADC_REV_0,
+ FIELD_PREP(AN8855_PHY_RG_AD_RESERVE0_A, 0x1));
+ if (ret)
+ return ret;
+ ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, AN8855_PHY_RXADC_REV_1,
+ FIELD_PREP(AN8855_PHY_RG_AD_RESERVE0_C, 0x1));
+ if (ret)
+ return ret;
+
+ return 0;
+}
+
+static int an8855_get_tunable(struct phy_device *phydev,
+ struct ethtool_tunable *tuna, void *data)
+{
+ switch (tuna->id) {
+ case ETHTOOL_PHY_DOWNSHIFT:
+ return an8855_get_downshift(phydev, data);
+ default:
+ return -EOPNOTSUPP;
+ }
+}
+
+static int an8855_set_tunable(struct phy_device *phydev,
+ struct ethtool_tunable *tuna, const void *data)
+{
+ switch (tuna->id) {
+ case ETHTOOL_PHY_DOWNSHIFT:
+ return an8855_set_downshift(phydev, *(const u8 *)data);
+ default:
+ return -EOPNOTSUPP;
+ }
+}
+
+static int an8855_read_page(struct phy_device *phydev)
+{
+ return __phy_read(phydev, AN8855_PHY_SELECT_PAGE);
+}
+
+static int an8855_write_page(struct phy_device *phydev, int page)
+{
+ return __phy_write(phydev, AN8855_PHY_SELECT_PAGE, page);
+}
+
+static struct phy_driver an8855_driver[] = {
+{
+ PHY_ID_MATCH_EXACT(AN8855_PHY_ID),
+ .name = "Airoha AN8855 internal PHY",
+ /* PHY_GBIT_FEATURES */
+ .flags = PHY_IS_INTERNAL,
+ .probe = an8855_probe,
+ .config_init = an8855_config_init,
+ .soft_reset = genphy_soft_reset,
+ .get_tunable = an8855_get_tunable,
+ .set_tunable = an8855_set_tunable,
+ .suspend = genphy_suspend,
+ .resume = genphy_resume,
+ .read_page = an8855_read_page,
+ .write_page = an8855_write_page,
+}, };
+
+module_phy_driver(an8855_driver);
+
+static struct mdio_device_id __maybe_unused an8855_tbl[] = {
+ { PHY_ID_MATCH_EXACT(AN8855_PHY_ID) },
+ { }
+};
+
+MODULE_DEVICE_TABLE(mdio, an8855_tbl);
+
+MODULE_DESCRIPTION("Airoha AN8855 PHY driver");
+MODULE_AUTHOR("Christian Marangi <ansuelsmth@gmail.com>");
+MODULE_LICENSE("GPL");
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Airoha AN8855 Switch EFUSE Driver
+ */
+
+#include <linux/mod_devicetable.h>
+#include <linux/module.h>
+#include <linux/nvmem-provider.h>
+#include <linux/platform_device.h>
+#include <linux/regmap.h>
+
+#define AN8855_EFUSE_CELL 50
+
+#define AN8855_EFUSE_DATA0 0x1000a500
+#define AN8855_EFUSE_R50O GENMASK(30, 24)
+
+static int an8855_efuse_read(void *context, unsigned int offset,
+ void *val, size_t bytes)
+{
+ struct regmap *regmap = context;
+
+ return regmap_bulk_read(regmap, AN8855_EFUSE_DATA0 + offset,
+ val, bytes / sizeof(u32));
+}
+
+static int an8855_efuse_probe(struct platform_device *pdev)
+{
+ struct nvmem_config an8855_nvmem_config = {
+ .name = "an8855-efuse",
+ .size = AN8855_EFUSE_CELL * sizeof(u32),
+ .stride = sizeof(u32),
+ .word_size = sizeof(u32),
+ .reg_read = an8855_efuse_read,
+ };
+ struct device *dev = &pdev->dev;
+ struct nvmem_device *nvmem;
+
+ /* Assign NVMEM priv to MFD regmap */
+ an8855_nvmem_config.priv = dev_get_regmap(dev->parent, NULL);
+ an8855_nvmem_config.dev = dev;
+ nvmem = devm_nvmem_register(dev, &an8855_nvmem_config);
+
+ return PTR_ERR_OR_ZERO(nvmem);
+}
+
+static const struct of_device_id an8855_efuse_of_match[] = {
+ { .compatible = "airoha,an8855-efuse", },
+ { /* sentinel */ }
+};
+MODULE_DEVICE_TABLE(of, an8855_efuse_of_match);
+
+static struct platform_driver an8855_efuse_driver = {
+ .probe = an8855_efuse_probe,
+ .driver = {
+ .name = "an8855-efuse",
+ .of_match_table = an8855_efuse_of_match,
+ },
+};
+module_platform_driver(an8855_efuse_driver);
+
+MODULE_AUTHOR("Christian Marangi <ansuelsmth@gmail.com>");
+MODULE_DESCRIPTION("Driver for AN8855 Switch EFUSE");
+MODULE_LICENSE("GPL");
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * The MT7988 driver based on Linux generic pinctrl binding.
+ *
+ * Copyright (C) 2020 MediaTek Inc.
+ * Author: Sam Shih <sam.shih@mediatek.com>
+ */
+
+#include "pinctrl-moore.h"
+
+enum MT7988_PINCTRL_REG_PAGE {
+ GPIO_BASE,
+ IOCFG_TR_BASE,
+ IOCFG_BR_BASE,
+ IOCFG_RB_BASE,
+ IOCFG_LB_BASE,
+ IOCFG_TL_BASE,
+};
+
+#define MT7988_PIN(_number, _name) MTK_PIN(_number, _name, 0, _number, DRV_GRP4)
+
+#define PIN_FIELD_BASE(_s_pin, _e_pin, _i_base, _s_addr, _x_addrs, _s_bit, \
+ _x_bits) \
+ PIN_FIELD_CALC(_s_pin, _e_pin, _i_base, _s_addr, _x_addrs, _s_bit, \
+ _x_bits, 32, 0)
+
+#define PINS_FIELD_BASE(_s_pin, _e_pin, _i_base, _s_addr, _x_addrs, _s_bit, \
+ _x_bits) \
+ PIN_FIELD_CALC(_s_pin, _e_pin, _i_base, _s_addr, _x_addrs, _s_bit, \
+ _x_bits, 32, 1)
+
+static const struct mtk_pin_field_calc mt7988_pin_mode_range[] = {
+ PIN_FIELD(0, 83, 0x300, 0x10, 0, 4),
+};
+
+static const struct mtk_pin_field_calc mt7988_pin_dir_range[] = {
+ PIN_FIELD(0, 83, 0x0, 0x10, 0, 1),
+};
+
+static const struct mtk_pin_field_calc mt7988_pin_di_range[] = {
+ PIN_FIELD(0, 83, 0x200, 0x10, 0, 1),
+};
+
+static const struct mtk_pin_field_calc mt7988_pin_do_range[] = {
+ PIN_FIELD(0, 83, 0x100, 0x10, 0, 1),
+};
+
+static const struct mtk_pin_field_calc mt7988_pin_ies_range[] = {
+ PIN_FIELD_BASE(0, 0, 5, 0x30, 0x10, 13, 1),
+ PIN_FIELD_BASE(1, 1, 5, 0x30, 0x10, 14, 1),
+ PIN_FIELD_BASE(2, 2, 5, 0x30, 0x10, 11, 1),
+ PIN_FIELD_BASE(3, 3, 5, 0x30, 0x10, 12, 1),
+ PIN_FIELD_BASE(4, 4, 5, 0x30, 0x10, 0, 1),
+ PIN_FIELD_BASE(5, 5, 5, 0x30, 0x10, 9, 1),
+ PIN_FIELD_BASE(6, 6, 5, 0x30, 0x10, 10, 1),
+
+ PIN_FIELD_BASE(7, 7, 4, 0x30, 0x10, 8, 1),
+ PIN_FIELD_BASE(8, 8, 4, 0x30, 0x10, 6, 1),
+ PIN_FIELD_BASE(9, 9, 4, 0x30, 0x10, 5, 1),
+ PIN_FIELD_BASE(10, 10, 4, 0x30, 0x10, 3, 1),
+
+ PIN_FIELD_BASE(11, 11, 1, 0x40, 0x10, 0, 1),
+ PIN_FIELD_BASE(12, 12, 1, 0x40, 0x10, 21, 1),
+ PIN_FIELD_BASE(13, 13, 1, 0x40, 0x10, 1, 1),
+ PIN_FIELD_BASE(14, 14, 1, 0x40, 0x10, 2, 1),
+
+ PIN_FIELD_BASE(15, 15, 5, 0x30, 0x10, 7, 1),
+ PIN_FIELD_BASE(16, 16, 5, 0x30, 0x10, 8, 1),
+ PIN_FIELD_BASE(17, 17, 5, 0x30, 0x10, 3, 1),
+ PIN_FIELD_BASE(18, 18, 5, 0x30, 0x10, 4, 1),
+
+ PIN_FIELD_BASE(19, 19, 4, 0x30, 0x10, 7, 1),
+ PIN_FIELD_BASE(20, 20, 4, 0x30, 0x10, 4, 1),
+
+ PIN_FIELD_BASE(21, 21, 3, 0x50, 0x10, 17, 1),
+ PIN_FIELD_BASE(22, 22, 3, 0x50, 0x10, 23, 1),
+ PIN_FIELD_BASE(23, 23, 3, 0x50, 0x10, 20, 1),
+ PIN_FIELD_BASE(24, 24, 3, 0x50, 0x10, 19, 1),
+ PIN_FIELD_BASE(25, 25, 3, 0x50, 0x10, 21, 1),
+ PIN_FIELD_BASE(26, 26, 3, 0x50, 0x10, 22, 1),
+ PIN_FIELD_BASE(27, 27, 3, 0x50, 0x10, 18, 1),
+ PIN_FIELD_BASE(28, 28, 3, 0x50, 0x10, 25, 1),
+ PIN_FIELD_BASE(29, 29, 3, 0x50, 0x10, 26, 1),
+ PIN_FIELD_BASE(30, 30, 3, 0x50, 0x10, 27, 1),
+ PIN_FIELD_BASE(31, 31, 3, 0x50, 0x10, 24, 1),
+ PIN_FIELD_BASE(32, 32, 3, 0x50, 0x10, 28, 1),
+ PIN_FIELD_BASE(33, 33, 3, 0x60, 0x10, 0, 1),
+ PIN_FIELD_BASE(34, 34, 3, 0x50, 0x10, 31, 1),
+ PIN_FIELD_BASE(35, 35, 3, 0x50, 0x10, 29, 1),
+ PIN_FIELD_BASE(36, 36, 3, 0x50, 0x10, 30, 1),
+ PIN_FIELD_BASE(37, 37, 3, 0x60, 0x10, 1, 1),
+ PIN_FIELD_BASE(38, 38, 3, 0x50, 0x10, 11, 1),
+ PIN_FIELD_BASE(39, 39, 3, 0x50, 0x10, 10, 1),
+ PIN_FIELD_BASE(40, 40, 3, 0x50, 0x10, 0, 1),
+ PIN_FIELD_BASE(41, 41, 3, 0x50, 0x10, 1, 1),
+ PIN_FIELD_BASE(42, 42, 3, 0x50, 0x10, 9, 1),
+ PIN_FIELD_BASE(43, 43, 3, 0x50, 0x10, 8, 1),
+ PIN_FIELD_BASE(44, 44, 3, 0x50, 0x10, 7, 1),
+ PIN_FIELD_BASE(45, 45, 3, 0x50, 0x10, 6, 1),
+ PIN_FIELD_BASE(46, 46, 3, 0x50, 0x10, 5, 1),
+ PIN_FIELD_BASE(47, 47, 3, 0x50, 0x10, 4, 1),
+ PIN_FIELD_BASE(48, 48, 3, 0x50, 0x10, 3, 1),
+ PIN_FIELD_BASE(49, 49, 3, 0x50, 0x10, 2, 1),
+ PIN_FIELD_BASE(50, 50, 3, 0x50, 0x10, 15, 1),
+ PIN_FIELD_BASE(51, 51, 3, 0x50, 0x10, 12, 1),
+ PIN_FIELD_BASE(52, 52, 3, 0x50, 0x10, 13, 1),
+ PIN_FIELD_BASE(53, 53, 3, 0x50, 0x10, 14, 1),
+ PIN_FIELD_BASE(54, 54, 3, 0x50, 0x10, 16, 1),
+
+ PIN_FIELD_BASE(55, 55, 1, 0x40, 0x10, 14, 1),
+ PIN_FIELD_BASE(56, 56, 1, 0x40, 0x10, 15, 1),
+ PIN_FIELD_BASE(57, 57, 1, 0x40, 0x10, 13, 1),
+ PIN_FIELD_BASE(58, 58, 1, 0x40, 0x10, 4, 1),
+ PIN_FIELD_BASE(59, 59, 1, 0x40, 0x10, 5, 1),
+ PIN_FIELD_BASE(60, 60, 1, 0x40, 0x10, 6, 1),
+ PIN_FIELD_BASE(61, 61, 1, 0x40, 0x10, 3, 1),
+ PIN_FIELD_BASE(62, 62, 1, 0x40, 0x10, 7, 1),
+ PIN_FIELD_BASE(63, 63, 1, 0x40, 0x10, 20, 1),
+ PIN_FIELD_BASE(64, 64, 1, 0x40, 0x10, 8, 1),
+ PIN_FIELD_BASE(65, 65, 1, 0x40, 0x10, 9, 1),
+ PIN_FIELD_BASE(66, 66, 1, 0x40, 0x10, 10, 1),
+ PIN_FIELD_BASE(67, 67, 1, 0x40, 0x10, 11, 1),
+ PIN_FIELD_BASE(68, 68, 1, 0x40, 0x10, 12, 1),
+
+ PIN_FIELD_BASE(69, 69, 5, 0x30, 0x10, 1, 1),
+ PIN_FIELD_BASE(70, 70, 5, 0x30, 0x10, 2, 1),
+ PIN_FIELD_BASE(71, 71, 5, 0x30, 0x10, 5, 1),
+ PIN_FIELD_BASE(72, 72, 5, 0x30, 0x10, 6, 1),
+
+ PIN_FIELD_BASE(73, 73, 4, 0x30, 0x10, 10, 1),
+ PIN_FIELD_BASE(74, 74, 4, 0x30, 0x10, 1, 1),
+ PIN_FIELD_BASE(75, 75, 4, 0x30, 0x10, 11, 1),
+ PIN_FIELD_BASE(76, 76, 4, 0x30, 0x10, 9, 1),
+ PIN_FIELD_BASE(77, 77, 4, 0x30, 0x10, 2, 1),
+ PIN_FIELD_BASE(78, 78, 4, 0x30, 0x10, 0, 1),
+ PIN_FIELD_BASE(79, 79, 4, 0x30, 0x10, 12, 1),
+
+ PIN_FIELD_BASE(80, 80, 1, 0x40, 0x10, 18, 1),
+ PIN_FIELD_BASE(81, 81, 1, 0x40, 0x10, 19, 1),
+ PIN_FIELD_BASE(82, 82, 1, 0x40, 0x10, 16, 1),
+ PIN_FIELD_BASE(83, 83, 1, 0x40, 0x10, 17, 1),
+};
+
+static const struct mtk_pin_field_calc mt7988_pin_smt_range[] = {
+ PIN_FIELD_BASE(0, 0, 5, 0xc0, 0x10, 13, 1),
+ PIN_FIELD_BASE(1, 1, 5, 0xc0, 0x10, 14, 1),
+ PIN_FIELD_BASE(2, 2, 5, 0xc0, 0x10, 11, 1),
+ PIN_FIELD_BASE(3, 3, 5, 0xc0, 0x10, 12, 1),
+ PIN_FIELD_BASE(4, 4, 5, 0xc0, 0x10, 0, 1),
+ PIN_FIELD_BASE(5, 5, 5, 0xc0, 0x10, 9, 1),
+ PIN_FIELD_BASE(6, 6, 5, 0xc0, 0x10, 10, 1),
+
+ PIN_FIELD_BASE(7, 7, 4, 0xb0, 0x10, 8, 1),
+ PIN_FIELD_BASE(8, 8, 4, 0xb0, 0x10, 6, 1),
+ PIN_FIELD_BASE(9, 9, 4, 0xb0, 0x10, 5, 1),
+ PIN_FIELD_BASE(10, 10, 4, 0xb0, 0x10, 3, 1),
+
+ PIN_FIELD_BASE(11, 11, 1, 0xe0, 0x10, 0, 1),
+ PIN_FIELD_BASE(12, 12, 1, 0xe0, 0x10, 21, 1),
+ PIN_FIELD_BASE(13, 13, 1, 0xe0, 0x10, 1, 1),
+ PIN_FIELD_BASE(14, 14, 1, 0xe0, 0x10, 2, 1),
+
+ PIN_FIELD_BASE(15, 15, 5, 0xc0, 0x10, 7, 1),
+ PIN_FIELD_BASE(16, 16, 5, 0xc0, 0x10, 8, 1),
+ PIN_FIELD_BASE(17, 17, 5, 0xc0, 0x10, 3, 1),
+ PIN_FIELD_BASE(18, 18, 5, 0xc0, 0x10, 4, 1),
+
+ PIN_FIELD_BASE(19, 19, 4, 0xb0, 0x10, 7, 1),
+ PIN_FIELD_BASE(20, 20, 4, 0xb0, 0x10, 4, 1),
+
+ PIN_FIELD_BASE(21, 21, 3, 0x140, 0x10, 17, 1),
+ PIN_FIELD_BASE(22, 22, 3, 0x140, 0x10, 23, 1),
+ PIN_FIELD_BASE(23, 23, 3, 0x140, 0x10, 20, 1),
+ PIN_FIELD_BASE(24, 24, 3, 0x140, 0x10, 19, 1),
+ PIN_FIELD_BASE(25, 25, 3, 0x140, 0x10, 21, 1),
+ PIN_FIELD_BASE(26, 26, 3, 0x140, 0x10, 22, 1),
+ PIN_FIELD_BASE(27, 27, 3, 0x140, 0x10, 18, 1),
+ PIN_FIELD_BASE(28, 28, 3, 0x140, 0x10, 25, 1),
+ PIN_FIELD_BASE(29, 29, 3, 0x140, 0x10, 26, 1),
+ PIN_FIELD_BASE(30, 30, 3, 0x140, 0x10, 27, 1),
+ PIN_FIELD_BASE(31, 31, 3, 0x140, 0x10, 24, 1),
+ PIN_FIELD_BASE(32, 32, 3, 0x140, 0x10, 28, 1),
+ PIN_FIELD_BASE(33, 33, 3, 0x150, 0x10, 0, 1),
+ PIN_FIELD_BASE(34, 34, 3, 0x140, 0x10, 31, 1),
+ PIN_FIELD_BASE(35, 35, 3, 0x140, 0x10, 29, 1),
+ PIN_FIELD_BASE(36, 36, 3, 0x140, 0x10, 30, 1),
+ PIN_FIELD_BASE(37, 37, 3, 0x150, 0x10, 1, 1),
+ PIN_FIELD_BASE(38, 38, 3, 0x140, 0x10, 11, 1),
+ PIN_FIELD_BASE(39, 39, 3, 0x140, 0x10, 10, 1),
+ PIN_FIELD_BASE(40, 40, 3, 0x140, 0x10, 0, 1),
+ PIN_FIELD_BASE(41, 41, 3, 0x140, 0x10, 1, 1),
+ PIN_FIELD_BASE(42, 42, 3, 0x140, 0x10, 9, 1),
+ PIN_FIELD_BASE(43, 43, 3, 0x140, 0x10, 8, 1),
+ PIN_FIELD_BASE(44, 44, 3, 0x140, 0x10, 7, 1),
+ PIN_FIELD_BASE(45, 45, 3, 0x140, 0x10, 6, 1),
+ PIN_FIELD_BASE(46, 46, 3, 0x140, 0x10, 5, 1),
+ PIN_FIELD_BASE(47, 47, 3, 0x140, 0x10, 4, 1),
+ PIN_FIELD_BASE(48, 48, 3, 0x140, 0x10, 3, 1),
+ PIN_FIELD_BASE(49, 49, 3, 0x140, 0x10, 2, 1),
+ PIN_FIELD_BASE(50, 50, 3, 0x140, 0x10, 15, 1),
+ PIN_FIELD_BASE(51, 51, 3, 0x140, 0x10, 12, 1),
+ PIN_FIELD_BASE(52, 52, 3, 0x140, 0x10, 13, 1),
+ PIN_FIELD_BASE(53, 53, 3, 0x140, 0x10, 14, 1),
+ PIN_FIELD_BASE(54, 54, 3, 0x140, 0x10, 16, 1),
+
+ PIN_FIELD_BASE(55, 55, 1, 0xe0, 0x10, 14, 1),
+ PIN_FIELD_BASE(56, 56, 1, 0xe0, 0x10, 15, 1),
+ PIN_FIELD_BASE(57, 57, 1, 0xe0, 0x10, 13, 1),
+ PIN_FIELD_BASE(58, 58, 1, 0xe0, 0x10, 4, 1),
+ PIN_FIELD_BASE(59, 59, 1, 0xe0, 0x10, 5, 1),
+ PIN_FIELD_BASE(60, 60, 1, 0xe0, 0x10, 6, 1),
+ PIN_FIELD_BASE(61, 61, 1, 0xe0, 0x10, 3, 1),
+ PIN_FIELD_BASE(62, 62, 1, 0xe0, 0x10, 7, 1),
+ PIN_FIELD_BASE(63, 63, 1, 0xe0, 0x10, 20, 1),
+ PIN_FIELD_BASE(64, 64, 1, 0xe0, 0x10, 8, 1),
+ PIN_FIELD_BASE(65, 65, 1, 0xe0, 0x10, 9, 1),
+ PIN_FIELD_BASE(66, 66, 1, 0xe0, 0x10, 10, 1),
+ PIN_FIELD_BASE(67, 67, 1, 0xe0, 0x10, 11, 1),
+ PIN_FIELD_BASE(68, 68, 1, 0xe0, 0x10, 12, 1),
+
+ PIN_FIELD_BASE(69, 69, 5, 0xc0, 0x10, 1, 1),
+ PIN_FIELD_BASE(70, 70, 5, 0xc0, 0x10, 2, 1),
+ PIN_FIELD_BASE(71, 71, 5, 0xc0, 0x10, 5, 1),
+ PIN_FIELD_BASE(72, 72, 5, 0xc0, 0x10, 6, 1),
+
+ PIN_FIELD_BASE(73, 73, 4, 0xb0, 0x10, 10, 1),
+ PIN_FIELD_BASE(74, 74, 4, 0xb0, 0x10, 1, 1),
+ PIN_FIELD_BASE(75, 75, 4, 0xb0, 0x10, 11, 1),
+ PIN_FIELD_BASE(76, 76, 4, 0xb0, 0x10, 9, 1),
+ PIN_FIELD_BASE(77, 77, 4, 0xb0, 0x10, 2, 1),
+ PIN_FIELD_BASE(78, 78, 4, 0xb0, 0x10, 0, 1),
+ PIN_FIELD_BASE(79, 79, 4, 0xb0, 0x10, 12, 1),
+
+ PIN_FIELD_BASE(80, 80, 1, 0xe0, 0x10, 18, 1),
+ PIN_FIELD_BASE(81, 81, 1, 0xe0, 0x10, 19, 1),
+ PIN_FIELD_BASE(82, 82, 1, 0xe0, 0x10, 16, 1),
+ PIN_FIELD_BASE(83, 83, 1, 0xe0, 0x10, 17, 1),
+};
+
+static const struct mtk_pin_field_calc mt7988_pin_pu_range[] = {
+ PIN_FIELD_BASE(7, 7, 4, 0x60, 0x10, 5, 1),
+ PIN_FIELD_BASE(8, 8, 4, 0x60, 0x10, 4, 1),
+ PIN_FIELD_BASE(9, 9, 4, 0x60, 0x10, 3, 1),
+ PIN_FIELD_BASE(10, 10, 4, 0x60, 0x10, 2, 1),
+
+ PIN_FIELD_BASE(13, 13, 1, 0x70, 0x10, 0, 1),
+ PIN_FIELD_BASE(14, 14, 1, 0x70, 0x10, 1, 1),
+ PIN_FIELD_BASE(63, 63, 1, 0x70, 0x10, 2, 1),
+
+ PIN_FIELD_BASE(75, 75, 4, 0x60, 0x10, 7, 1),
+ PIN_FIELD_BASE(76, 76, 4, 0x60, 0x10, 6, 1),
+ PIN_FIELD_BASE(77, 77, 4, 0x60, 0x10, 1, 1),
+ PIN_FIELD_BASE(78, 78, 4, 0x60, 0x10, 0, 1),
+ PIN_FIELD_BASE(79, 79, 4, 0x60, 0x10, 8, 1),
+};
+
+static const struct mtk_pin_field_calc mt7988_pin_pd_range[] = {
+ PIN_FIELD_BASE(7, 7, 4, 0x40, 0x10, 5, 1),
+ PIN_FIELD_BASE(8, 8, 4, 0x40, 0x10, 4, 1),
+ PIN_FIELD_BASE(9, 9, 4, 0x40, 0x10, 3, 1),
+ PIN_FIELD_BASE(10, 10, 4, 0x40, 0x10, 2, 1),
+
+ PIN_FIELD_BASE(13, 13, 1, 0x50, 0x10, 0, 1),
+ PIN_FIELD_BASE(14, 14, 1, 0x50, 0x10, 1, 1),
+
+ PIN_FIELD_BASE(15, 15, 5, 0x40, 0x10, 4, 1),
+ PIN_FIELD_BASE(16, 16, 5, 0x40, 0x10, 5, 1),
+ PIN_FIELD_BASE(17, 17, 5, 0x40, 0x10, 0, 1),
+ PIN_FIELD_BASE(18, 18, 5, 0x40, 0x10, 1, 1),
+
+ PIN_FIELD_BASE(63, 63, 1, 0x50, 0x10, 2, 1),
+ PIN_FIELD_BASE(71, 71, 5, 0x40, 0x10, 2, 1),
+ PIN_FIELD_BASE(72, 72, 5, 0x40, 0x10, 3, 1),
+
+ PIN_FIELD_BASE(75, 75, 4, 0x40, 0x10, 7, 1),
+ PIN_FIELD_BASE(76, 76, 4, 0x40, 0x10, 6, 1),
+ PIN_FIELD_BASE(77, 77, 4, 0x40, 0x10, 1, 1),
+ PIN_FIELD_BASE(78, 78, 4, 0x40, 0x10, 0, 1),
+ PIN_FIELD_BASE(79, 79, 4, 0x40, 0x10, 8, 1),
+};
+
+static const struct mtk_pin_field_calc mt7988_pin_drv_range[] = {
+ PIN_FIELD_BASE(0, 0, 5, 0x00, 0x10, 21, 3),
+ PIN_FIELD_BASE(1, 1, 5, 0x00, 0x10, 24, 3),
+ PIN_FIELD_BASE(2, 2, 5, 0x00, 0x10, 15, 3),
+ PIN_FIELD_BASE(3, 3, 5, 0x00, 0x10, 18, 3),
+ PIN_FIELD_BASE(4, 4, 5, 0x00, 0x10, 0, 3),
+ PIN_FIELD_BASE(5, 5, 5, 0x00, 0x10, 9, 3),
+ PIN_FIELD_BASE(6, 6, 5, 0x00, 0x10, 12, 3),
+
+ PIN_FIELD_BASE(7, 7, 4, 0x00, 0x10, 24, 3),
+ PIN_FIELD_BASE(8, 8, 4, 0x00, 0x10, 28, 3),
+ PIN_FIELD_BASE(9, 9, 4, 0x00, 0x10, 15, 3),
+ PIN_FIELD_BASE(10, 10, 4, 0x00, 0x10, 9, 3),
+
+ PIN_FIELD_BASE(11, 11, 1, 0x00, 0x10, 0, 3),
+ PIN_FIELD_BASE(12, 12, 1, 0x20, 0x10, 3, 3),
+ PIN_FIELD_BASE(13, 13, 1, 0x00, 0x10, 3, 3),
+ PIN_FIELD_BASE(14, 14, 1, 0x00, 0x10, 6, 3),
+
+ PIN_FIELD_BASE(19, 19, 4, 0x00, 0x10, 21, 3),
+ PIN_FIELD_BASE(20, 20, 4, 0x00, 0x10, 12, 3),
+
+ PIN_FIELD_BASE(21, 21, 3, 0x10, 0x10, 21, 3),
+ PIN_FIELD_BASE(22, 22, 3, 0x20, 0x10, 9, 3),
+ PIN_FIELD_BASE(23, 23, 3, 0x20, 0x10, 0, 3),
+ PIN_FIELD_BASE(24, 24, 3, 0x10, 0x10, 27, 3),
+ PIN_FIELD_BASE(25, 25, 3, 0x20, 0x10, 3, 3),
+ PIN_FIELD_BASE(26, 26, 3, 0x20, 0x10, 6, 3),
+ PIN_FIELD_BASE(27, 27, 3, 0x10, 0x10, 24, 3),
+ PIN_FIELD_BASE(28, 28, 3, 0x20, 0x10, 15, 3),
+ PIN_FIELD_BASE(29, 29, 3, 0x20, 0x10, 18, 3),
+ PIN_FIELD_BASE(30, 30, 3, 0x20, 0x10, 21, 3),
+ PIN_FIELD_BASE(31, 31, 3, 0x20, 0x10, 12, 3),
+ PIN_FIELD_BASE(32, 32, 3, 0x20, 0x10, 24, 3),
+ PIN_FIELD_BASE(33, 33, 3, 0x30, 0x10, 6, 3),
+ PIN_FIELD_BASE(34, 34, 3, 0x30, 0x10, 3, 3),
+ PIN_FIELD_BASE(35, 35, 3, 0x20, 0x10, 27, 3),
+ PIN_FIELD_BASE(36, 36, 3, 0x30, 0x10, 0, 3),
+ PIN_FIELD_BASE(37, 37, 3, 0x30, 0x10, 9, 3),
+ PIN_FIELD_BASE(38, 38, 3, 0x10, 0x10, 3, 3),
+ PIN_FIELD_BASE(39, 39, 3, 0x10, 0x10, 0, 3),
+ PIN_FIELD_BASE(40, 40, 3, 0x00, 0x10, 0, 3),
+ PIN_FIELD_BASE(41, 41, 3, 0x00, 0x10, 3, 3),
+ PIN_FIELD_BASE(42, 42, 3, 0x00, 0x10, 27, 3),
+ PIN_FIELD_BASE(43, 43, 3, 0x00, 0x10, 24, 3),
+ PIN_FIELD_BASE(44, 44, 3, 0x00, 0x10, 21, 3),
+ PIN_FIELD_BASE(45, 45, 3, 0x00, 0x10, 18, 3),
+ PIN_FIELD_BASE(46, 46, 3, 0x00, 0x10, 15, 3),
+ PIN_FIELD_BASE(47, 47, 3, 0x00, 0x10, 12, 3),
+ PIN_FIELD_BASE(48, 48, 3, 0x00, 0x10, 9, 3),
+ PIN_FIELD_BASE(49, 49, 3, 0x00, 0x10, 6, 3),
+ PIN_FIELD_BASE(50, 50, 3, 0x10, 0x10, 15, 3),
+ PIN_FIELD_BASE(51, 51, 3, 0x10, 0x10, 6, 3),
+ PIN_FIELD_BASE(52, 52, 3, 0x10, 0x10, 9, 3),
+ PIN_FIELD_BASE(53, 53, 3, 0x10, 0x10, 12, 3),
+ PIN_FIELD_BASE(54, 54, 3, 0x10, 0x10, 18, 3),
+
+ PIN_FIELD_BASE(55, 55, 1, 0x10, 0x10, 12, 3),
+ PIN_FIELD_BASE(56, 56, 1, 0x10, 0x10, 15, 3),
+ PIN_FIELD_BASE(57, 57, 1, 0x10, 0x10, 9, 3),
+ PIN_FIELD_BASE(58, 58, 1, 0x00, 0x10, 12, 3),
+ PIN_FIELD_BASE(59, 59, 1, 0x00, 0x10, 15, 3),
+ PIN_FIELD_BASE(60, 60, 1, 0x00, 0x10, 18, 3),
+ PIN_FIELD_BASE(61, 61, 1, 0x00, 0x10, 9, 3),
+ PIN_FIELD_BASE(62, 62, 1, 0x00, 0x10, 21, 3),
+ PIN_FIELD_BASE(63, 63, 1, 0x20, 0x10, 0, 3),
+ PIN_FIELD_BASE(64, 64, 1, 0x00, 0x10, 24, 3),
+ PIN_FIELD_BASE(65, 65, 1, 0x00, 0x10, 27, 3),
+ PIN_FIELD_BASE(66, 66, 1, 0x10, 0x10, 0, 3),
+ PIN_FIELD_BASE(67, 67, 1, 0x10, 0x10, 3, 3),
+ PIN_FIELD_BASE(68, 68, 1, 0x10, 0x10, 6, 3),
+
+ PIN_FIELD_BASE(69, 69, 5, 0x00, 0x10, 3, 3),
+ PIN_FIELD_BASE(70, 70, 5, 0x00, 0x10, 6, 3),
+
+ PIN_FIELD_BASE(73, 73, 4, 0x10, 0x10, 0, 3),
+ PIN_FIELD_BASE(74, 74, 4, 0x00, 0x10, 3, 3),
+ PIN_FIELD_BASE(75, 75, 4, 0x10, 0x10, 3, 3),
+ PIN_FIELD_BASE(76, 76, 4, 0x00, 0x10, 27, 3),
+ PIN_FIELD_BASE(77, 77, 4, 0x00, 0x10, 6, 3),
+ PIN_FIELD_BASE(78, 78, 4, 0x00, 0x10, 0, 3),
+ PIN_FIELD_BASE(79, 79, 4, 0x10, 0x10, 6, 3),
+
+ PIN_FIELD_BASE(80, 80, 1, 0x10, 0x10, 24, 3),
+ PIN_FIELD_BASE(81, 81, 1, 0x10, 0x10, 27, 3),
+ PIN_FIELD_BASE(82, 82, 1, 0x10, 0x10, 18, 3),
+ PIN_FIELD_BASE(83, 83, 1, 0x10, 0x10, 21, 3),
+};
+
+static const struct mtk_pin_field_calc mt7988_pin_pupd_range[] = {
+ PIN_FIELD_BASE(0, 0, 5, 0x50, 0x10, 7, 1),
+ PIN_FIELD_BASE(1, 1, 5, 0x50, 0x10, 8, 1),
+ PIN_FIELD_BASE(2, 2, 5, 0x50, 0x10, 5, 1),
+ PIN_FIELD_BASE(3, 3, 5, 0x50, 0x10, 6, 1),
+ PIN_FIELD_BASE(4, 4, 5, 0x50, 0x10, 0, 1),
+ PIN_FIELD_BASE(5, 5, 5, 0x50, 0x10, 3, 1),
+ PIN_FIELD_BASE(6, 6, 5, 0x50, 0x10, 4, 1),
+
+ PIN_FIELD_BASE(11, 11, 1, 0x60, 0x10, 0, 1),
+ PIN_FIELD_BASE(12, 12, 1, 0x60, 0x10, 18, 1),
+
+ PIN_FIELD_BASE(19, 19, 4, 0x50, 0x10, 2, 1),
+ PIN_FIELD_BASE(20, 20, 4, 0x50, 0x10, 1, 1),
+
+ PIN_FIELD_BASE(21, 21, 3, 0x70, 0x10, 17, 1),
+ PIN_FIELD_BASE(22, 22, 3, 0x70, 0x10, 23, 1),
+ PIN_FIELD_BASE(23, 23, 3, 0x70, 0x10, 20, 1),
+ PIN_FIELD_BASE(24, 24, 3, 0x70, 0x10, 19, 1),
+ PIN_FIELD_BASE(25, 25, 3, 0x70, 0x10, 21, 1),
+ PIN_FIELD_BASE(26, 26, 3, 0x70, 0x10, 22, 1),
+ PIN_FIELD_BASE(27, 27, 3, 0x70, 0x10, 18, 1),
+ PIN_FIELD_BASE(28, 28, 3, 0x70, 0x10, 25, 1),
+ PIN_FIELD_BASE(29, 29, 3, 0x70, 0x10, 26, 1),
+ PIN_FIELD_BASE(30, 30, 3, 0x70, 0x10, 27, 1),
+ PIN_FIELD_BASE(31, 31, 3, 0x70, 0x10, 24, 1),
+ PIN_FIELD_BASE(32, 32, 3, 0x70, 0x10, 28, 1),
+ PIN_FIELD_BASE(33, 33, 3, 0x80, 0x10, 0, 1),
+ PIN_FIELD_BASE(34, 34, 3, 0x70, 0x10, 31, 1),
+ PIN_FIELD_BASE(35, 35, 3, 0x70, 0x10, 29, 1),
+ PIN_FIELD_BASE(36, 36, 3, 0x70, 0x10, 30, 1),
+ PIN_FIELD_BASE(37, 37, 3, 0x80, 0x10, 1, 1),
+ PIN_FIELD_BASE(38, 38, 3, 0x70, 0x10, 11, 1),
+ PIN_FIELD_BASE(39, 39, 3, 0x70, 0x10, 10, 1),
+ PIN_FIELD_BASE(40, 40, 3, 0x70, 0x10, 0, 1),
+ PIN_FIELD_BASE(41, 41, 3, 0x70, 0x10, 1, 1),
+ PIN_FIELD_BASE(42, 42, 3, 0x70, 0x10, 9, 1),
+ PIN_FIELD_BASE(43, 43, 3, 0x70, 0x10, 8, 1),
+ PIN_FIELD_BASE(44, 44, 3, 0x70, 0x10, 7, 1),
+ PIN_FIELD_BASE(45, 45, 3, 0x70, 0x10, 6, 1),
+ PIN_FIELD_BASE(46, 46, 3, 0x70, 0x10, 5, 1),
+ PIN_FIELD_BASE(47, 47, 3, 0x70, 0x10, 4, 1),
+ PIN_FIELD_BASE(48, 48, 3, 0x70, 0x10, 3, 1),
+ PIN_FIELD_BASE(49, 49, 3, 0x70, 0x10, 2, 1),
+ PIN_FIELD_BASE(50, 50, 3, 0x70, 0x10, 15, 1),
+ PIN_FIELD_BASE(51, 51, 3, 0x70, 0x10, 12, 1),
+ PIN_FIELD_BASE(52, 52, 3, 0x70, 0x10, 13, 1),
+ PIN_FIELD_BASE(53, 53, 3, 0x70, 0x10, 14, 1),
+ PIN_FIELD_BASE(54, 54, 3, 0x70, 0x10, 16, 1),
+
+ PIN_FIELD_BASE(55, 55, 1, 0x60, 0x10, 12, 1),
+ PIN_FIELD_BASE(56, 56, 1, 0x60, 0x10, 13, 1),
+ PIN_FIELD_BASE(57, 57, 1, 0x60, 0x10, 11, 1),
+ PIN_FIELD_BASE(58, 58, 1, 0x60, 0x10, 2, 1),
+ PIN_FIELD_BASE(59, 59, 1, 0x60, 0x10, 3, 1),
+ PIN_FIELD_BASE(60, 60, 1, 0x60, 0x10, 4, 1),
+ PIN_FIELD_BASE(61, 61, 1, 0x60, 0x10, 1, 1),
+ PIN_FIELD_BASE(62, 62, 1, 0x60, 0x10, 5, 1),
+ PIN_FIELD_BASE(64, 64, 1, 0x60, 0x10, 6, 1),
+ PIN_FIELD_BASE(65, 65, 1, 0x60, 0x10, 7, 1),
+ PIN_FIELD_BASE(66, 66, 1, 0x60, 0x10, 8, 1),
+ PIN_FIELD_BASE(67, 67, 1, 0x60, 0x10, 9, 1),
+ PIN_FIELD_BASE(68, 68, 1, 0x60, 0x10, 10, 1),
+
+ PIN_FIELD_BASE(69, 69, 5, 0x50, 0x10, 1, 1),
+ PIN_FIELD_BASE(70, 70, 5, 0x50, 0x10, 2, 1),
+
+ PIN_FIELD_BASE(73, 73, 4, 0x50, 0x10, 3, 1),
+ PIN_FIELD_BASE(74, 74, 4, 0x50, 0x10, 0, 1),
+
+ PIN_FIELD_BASE(80, 80, 1, 0x60, 0x10, 16, 1),
+ PIN_FIELD_BASE(81, 81, 1, 0x60, 0x10, 17, 1),
+ PIN_FIELD_BASE(82, 82, 1, 0x60, 0x10, 14, 1),
+ PIN_FIELD_BASE(83, 83, 1, 0x60, 0x10, 15, 1),
+};
+
+static const struct mtk_pin_field_calc mt7988_pin_r0_range[] = {
+ PIN_FIELD_BASE(0, 0, 5, 0x60, 0x10, 7, 1),
+ PIN_FIELD_BASE(1, 1, 5, 0x60, 0x10, 8, 1),
+ PIN_FIELD_BASE(2, 2, 5, 0x60, 0x10, 5, 1),
+ PIN_FIELD_BASE(3, 3, 5, 0x60, 0x10, 6, 1),
+ PIN_FIELD_BASE(4, 4, 5, 0x60, 0x10, 0, 1),
+ PIN_FIELD_BASE(5, 5, 5, 0x60, 0x10, 3, 1),
+ PIN_FIELD_BASE(6, 6, 5, 0x60, 0x10, 4, 1),
+
+ PIN_FIELD_BASE(11, 11, 1, 0x80, 0x10, 0, 1),
+ PIN_FIELD_BASE(12, 12, 1, 0x80, 0x10, 18, 1),
+
+ PIN_FIELD_BASE(19, 19, 4, 0x70, 0x10, 2, 1),
+ PIN_FIELD_BASE(20, 20, 4, 0x70, 0x10, 1, 1),
+
+ PIN_FIELD_BASE(21, 21, 3, 0x90, 0x10, 17, 1),
+ PIN_FIELD_BASE(22, 22, 3, 0x90, 0x10, 23, 1),
+ PIN_FIELD_BASE(23, 23, 3, 0x90, 0x10, 20, 1),
+ PIN_FIELD_BASE(24, 24, 3, 0x90, 0x10, 19, 1),
+ PIN_FIELD_BASE(25, 25, 3, 0x90, 0x10, 21, 1),
+ PIN_FIELD_BASE(26, 26, 3, 0x90, 0x10, 22, 1),
+ PIN_FIELD_BASE(27, 27, 3, 0x90, 0x10, 18, 1),
+ PIN_FIELD_BASE(28, 28, 3, 0x90, 0x10, 25, 1),
+ PIN_FIELD_BASE(29, 29, 3, 0x90, 0x10, 26, 1),
+ PIN_FIELD_BASE(30, 30, 3, 0x90, 0x10, 27, 1),
+ PIN_FIELD_BASE(31, 31, 3, 0x90, 0x10, 24, 1),
+ PIN_FIELD_BASE(32, 32, 3, 0x90, 0x10, 28, 1),
+ PIN_FIELD_BASE(33, 33, 3, 0xa0, 0x10, 0, 1),
+ PIN_FIELD_BASE(34, 34, 3, 0x90, 0x10, 31, 1),
+ PIN_FIELD_BASE(35, 35, 3, 0x90, 0x10, 29, 1),
+ PIN_FIELD_BASE(36, 36, 3, 0x90, 0x10, 30, 1),
+ PIN_FIELD_BASE(37, 37, 3, 0xa0, 0x10, 1, 1),
+ PIN_FIELD_BASE(38, 38, 3, 0x90, 0x10, 11, 1),
+ PIN_FIELD_BASE(39, 39, 3, 0x90, 0x10, 10, 1),
+ PIN_FIELD_BASE(40, 40, 3, 0x90, 0x10, 0, 1),
+ PIN_FIELD_BASE(41, 41, 3, 0x90, 0x10, 1, 1),
+ PIN_FIELD_BASE(42, 42, 3, 0x90, 0x10, 9, 1),
+ PIN_FIELD_BASE(43, 43, 3, 0x90, 0x10, 8, 1),
+ PIN_FIELD_BASE(44, 44, 3, 0x90, 0x10, 7, 1),
+ PIN_FIELD_BASE(45, 45, 3, 0x90, 0x10, 6, 1),
+ PIN_FIELD_BASE(46, 46, 3, 0x90, 0x10, 5, 1),
+ PIN_FIELD_BASE(47, 47, 3, 0x90, 0x10, 4, 1),
+ PIN_FIELD_BASE(48, 48, 3, 0x90, 0x10, 3, 1),
+ PIN_FIELD_BASE(49, 49, 3, 0x90, 0x10, 2, 1),
+ PIN_FIELD_BASE(50, 50, 3, 0x90, 0x10, 15, 1),
+ PIN_FIELD_BASE(51, 51, 3, 0x90, 0x10, 12, 1),
+ PIN_FIELD_BASE(52, 52, 3, 0x90, 0x10, 13, 1),
+ PIN_FIELD_BASE(53, 53, 3, 0x90, 0x10, 14, 1),
+ PIN_FIELD_BASE(54, 54, 3, 0x90, 0x10, 16, 1),
+
+ PIN_FIELD_BASE(55, 55, 1, 0x80, 0x10, 12, 1),
+ PIN_FIELD_BASE(56, 56, 1, 0x80, 0x10, 13, 1),
+ PIN_FIELD_BASE(57, 57, 1, 0x80, 0x10, 11, 1),
+ PIN_FIELD_BASE(58, 58, 1, 0x80, 0x10, 2, 1),
+ PIN_FIELD_BASE(59, 59, 1, 0x80, 0x10, 3, 1),
+ PIN_FIELD_BASE(60, 60, 1, 0x80, 0x10, 4, 1),
+ PIN_FIELD_BASE(61, 61, 1, 0x80, 0x10, 1, 1),
+ PIN_FIELD_BASE(62, 62, 1, 0x80, 0x10, 5, 1),
+ PIN_FIELD_BASE(64, 64, 1, 0x80, 0x10, 6, 1),
+ PIN_FIELD_BASE(65, 65, 1, 0x80, 0x10, 7, 1),
+ PIN_FIELD_BASE(66, 66, 1, 0x80, 0x10, 8, 1),
+ PIN_FIELD_BASE(67, 67, 1, 0x80, 0x10, 9, 1),
+ PIN_FIELD_BASE(68, 68, 1, 0x80, 0x10, 10, 1),
+
+ PIN_FIELD_BASE(69, 69, 5, 0x60, 0x10, 1, 1),
+ PIN_FIELD_BASE(70, 70, 5, 0x60, 0x10, 2, 1),
+
+ PIN_FIELD_BASE(73, 73, 4, 0x70, 0x10, 3, 1),
+ PIN_FIELD_BASE(74, 74, 4, 0x70, 0x10, 0, 1),
+
+ PIN_FIELD_BASE(80, 80, 1, 0x80, 0x10, 16, 1),
+ PIN_FIELD_BASE(81, 81, 1, 0x80, 0x10, 17, 1),
+ PIN_FIELD_BASE(82, 82, 1, 0x80, 0x10, 14, 1),
+ PIN_FIELD_BASE(83, 83, 1, 0x80, 0x10, 15, 1),
+};
+
+static const struct mtk_pin_field_calc mt7988_pin_r1_range[] = {
+ PIN_FIELD_BASE(0, 0, 5, 0x70, 0x10, 7, 1),
+ PIN_FIELD_BASE(1, 1, 5, 0x70, 0x10, 8, 1),
+ PIN_FIELD_BASE(2, 2, 5, 0x70, 0x10, 5, 1),
+ PIN_FIELD_BASE(3, 3, 5, 0x70, 0x10, 6, 1),
+ PIN_FIELD_BASE(4, 4, 5, 0x70, 0x10, 0, 1),
+ PIN_FIELD_BASE(5, 5, 5, 0x70, 0x10, 3, 1),
+ PIN_FIELD_BASE(6, 6, 5, 0x70, 0x10, 4, 1),
+
+ PIN_FIELD_BASE(11, 11, 1, 0x90, 0x10, 0, 1),
+ PIN_FIELD_BASE(12, 12, 1, 0x90, 0x10, 18, 1),
+
+ PIN_FIELD_BASE(19, 19, 4, 0x80, 0x10, 2, 1),
+ PIN_FIELD_BASE(20, 20, 4, 0x80, 0x10, 1, 1),
+
+ PIN_FIELD_BASE(21, 21, 3, 0xb0, 0x10, 17, 1),
+ PIN_FIELD_BASE(22, 22, 3, 0xb0, 0x10, 23, 1),
+ PIN_FIELD_BASE(23, 23, 3, 0xb0, 0x10, 20, 1),
+ PIN_FIELD_BASE(24, 24, 3, 0xb0, 0x10, 19, 1),
+ PIN_FIELD_BASE(25, 25, 3, 0xb0, 0x10, 21, 1),
+ PIN_FIELD_BASE(26, 26, 3, 0xb0, 0x10, 22, 1),
+ PIN_FIELD_BASE(27, 27, 3, 0xb0, 0x10, 18, 1),
+ PIN_FIELD_BASE(28, 28, 3, 0xb0, 0x10, 25, 1),
+ PIN_FIELD_BASE(29, 29, 3, 0xb0, 0x10, 26, 1),
+ PIN_FIELD_BASE(30, 30, 3, 0xb0, 0x10, 27, 1),
+ PIN_FIELD_BASE(31, 31, 3, 0xb0, 0x10, 24, 1),
+ PIN_FIELD_BASE(32, 32, 3, 0xb0, 0x10, 28, 1),
+ PIN_FIELD_BASE(33, 33, 3, 0xc0, 0x10, 0, 1),
+ PIN_FIELD_BASE(34, 34, 3, 0xb0, 0x10, 31, 1),
+ PIN_FIELD_BASE(35, 35, 3, 0xb0, 0x10, 29, 1),
+ PIN_FIELD_BASE(36, 36, 3, 0xb0, 0x10, 30, 1),
+ PIN_FIELD_BASE(37, 37, 3, 0xc0, 0x10, 1, 1),
+ PIN_FIELD_BASE(38, 38, 3, 0xb0, 0x10, 11, 1),
+ PIN_FIELD_BASE(39, 39, 3, 0xb0, 0x10, 10, 1),
+ PIN_FIELD_BASE(40, 40, 3, 0xb0, 0x10, 0, 1),
+ PIN_FIELD_BASE(41, 41, 3, 0xb0, 0x10, 1, 1),
+ PIN_FIELD_BASE(42, 42, 3, 0xb0, 0x10, 9, 1),
+ PIN_FIELD_BASE(43, 43, 3, 0xb0, 0x10, 8, 1),
+ PIN_FIELD_BASE(44, 44, 3, 0xb0, 0x10, 7, 1),
+ PIN_FIELD_BASE(45, 45, 3, 0xb0, 0x10, 6, 1),
+ PIN_FIELD_BASE(46, 46, 3, 0xb0, 0x10, 5, 1),
+ PIN_FIELD_BASE(47, 47, 3, 0xb0, 0x10, 4, 1),
+ PIN_FIELD_BASE(48, 48, 3, 0xb0, 0x10, 3, 1),
+ PIN_FIELD_BASE(49, 49, 3, 0xb0, 0x10, 2, 1),
+ PIN_FIELD_BASE(50, 50, 3, 0xb0, 0x10, 15, 1),
+ PIN_FIELD_BASE(51, 51, 3, 0xb0, 0x10, 12, 1),
+ PIN_FIELD_BASE(52, 52, 3, 0xb0, 0x10, 13, 1),
+ PIN_FIELD_BASE(53, 53, 3, 0xb0, 0x10, 14, 1),
+ PIN_FIELD_BASE(54, 54, 3, 0xb0, 0x10, 16, 1),
+
+ PIN_FIELD_BASE(55, 55, 1, 0x90, 0x10, 12, 1),
+ PIN_FIELD_BASE(56, 56, 1, 0x90, 0x10, 13, 1),
+ PIN_FIELD_BASE(57, 57, 1, 0x90, 0x10, 11, 1),
+ PIN_FIELD_BASE(58, 58, 1, 0x90, 0x10, 2, 1),
+ PIN_FIELD_BASE(59, 59, 1, 0x90, 0x10, 3, 1),
+ PIN_FIELD_BASE(60, 60, 1, 0x90, 0x10, 4, 1),
+ PIN_FIELD_BASE(61, 61, 1, 0x90, 0x10, 1, 1),
+ PIN_FIELD_BASE(62, 62, 1, 0x90, 0x10, 5, 1),
+ PIN_FIELD_BASE(64, 64, 1, 0x90, 0x10, 6, 1),
+ PIN_FIELD_BASE(65, 65, 1, 0x90, 0x10, 7, 1),
+ PIN_FIELD_BASE(66, 66, 1, 0x90, 0x10, 8, 1),
+ PIN_FIELD_BASE(67, 67, 1, 0x90, 0x10, 9, 1),
+ PIN_FIELD_BASE(68, 68, 1, 0x90, 0x10, 10, 1),
+
+ PIN_FIELD_BASE(69, 69, 5, 0x70, 0x10, 1, 1),
+ PIN_FIELD_BASE(70, 70, 5, 0x70, 0x10, 2, 1),
+
+ PIN_FIELD_BASE(73, 73, 4, 0x80, 0x10, 3, 1),
+ PIN_FIELD_BASE(74, 74, 4, 0x80, 0x10, 0, 1),
+
+ PIN_FIELD_BASE(80, 80, 1, 0x90, 0x10, 16, 1),
+ PIN_FIELD_BASE(81, 81, 1, 0x90, 0x10, 17, 1),
+ PIN_FIELD_BASE(82, 82, 1, 0x90, 0x10, 14, 1),
+ PIN_FIELD_BASE(83, 83, 1, 0x90, 0x10, 15, 1),
+};
+
+static const unsigned int mt7988_pull_type[] = {
+ MTK_PULL_PUPD_R1R0_TYPE,/*0*/ MTK_PULL_PUPD_R1R0_TYPE,/*1*/
+ MTK_PULL_PUPD_R1R0_TYPE,/*2*/ MTK_PULL_PUPD_R1R0_TYPE,/*3*/
+ MTK_PULL_PUPD_R1R0_TYPE,/*4*/ MTK_PULL_PUPD_R1R0_TYPE,/*5*/
+ MTK_PULL_PUPD_R1R0_TYPE,/*6*/ MTK_PULL_PU_PD_TYPE, /*7*/
+ MTK_PULL_PU_PD_TYPE, /*8*/ MTK_PULL_PU_PD_TYPE, /*9*/
+ MTK_PULL_PU_PD_TYPE, /*10*/ MTK_PULL_PUPD_R1R0_TYPE,/*11*/
+ MTK_PULL_PUPD_R1R0_TYPE,/*12*/ MTK_PULL_PU_PD_TYPE, /*13*/
+ MTK_PULL_PU_PD_TYPE, /*14*/ MTK_PULL_PD_TYPE, /*15*/
+ MTK_PULL_PD_TYPE, /*16*/ MTK_PULL_PD_TYPE, /*17*/
+ MTK_PULL_PD_TYPE, /*18*/ MTK_PULL_PUPD_R1R0_TYPE,/*19*/
+ MTK_PULL_PUPD_R1R0_TYPE,/*20*/ MTK_PULL_PUPD_R1R0_TYPE,/*21*/
+ MTK_PULL_PUPD_R1R0_TYPE,/*22*/ MTK_PULL_PUPD_R1R0_TYPE,/*23*/
+ MTK_PULL_PUPD_R1R0_TYPE,/*24*/ MTK_PULL_PUPD_R1R0_TYPE,/*25*/
+ MTK_PULL_PUPD_R1R0_TYPE,/*26*/ MTK_PULL_PUPD_R1R0_TYPE,/*27*/
+ MTK_PULL_PUPD_R1R0_TYPE,/*28*/ MTK_PULL_PUPD_R1R0_TYPE,/*29*/
+ MTK_PULL_PUPD_R1R0_TYPE,/*30*/ MTK_PULL_PUPD_R1R0_TYPE,/*31*/
+ MTK_PULL_PUPD_R1R0_TYPE,/*32*/ MTK_PULL_PUPD_R1R0_TYPE,/*33*/
+ MTK_PULL_PUPD_R1R0_TYPE,/*34*/ MTK_PULL_PUPD_R1R0_TYPE,/*35*/
+ MTK_PULL_PUPD_R1R0_TYPE,/*36*/ MTK_PULL_PUPD_R1R0_TYPE,/*37*/
+ MTK_PULL_PUPD_R1R0_TYPE,/*38*/ MTK_PULL_PUPD_R1R0_TYPE,/*39*/
+ MTK_PULL_PUPD_R1R0_TYPE,/*40*/ MTK_PULL_PUPD_R1R0_TYPE,/*41*/
+ MTK_PULL_PUPD_R1R0_TYPE,/*42*/ MTK_PULL_PUPD_R1R0_TYPE,/*43*/
+ MTK_PULL_PUPD_R1R0_TYPE,/*44*/ MTK_PULL_PUPD_R1R0_TYPE,/*45*/
+ MTK_PULL_PUPD_R1R0_TYPE,/*46*/ MTK_PULL_PUPD_R1R0_TYPE,/*47*/
+ MTK_PULL_PUPD_R1R0_TYPE,/*48*/ MTK_PULL_PUPD_R1R0_TYPE,/*49*/
+ MTK_PULL_PUPD_R1R0_TYPE,/*50*/ MTK_PULL_PUPD_R1R0_TYPE,/*51*/
+ MTK_PULL_PUPD_R1R0_TYPE,/*52*/ MTK_PULL_PUPD_R1R0_TYPE,/*53*/
+ MTK_PULL_PUPD_R1R0_TYPE,/*54*/ MTK_PULL_PUPD_R1R0_TYPE,/*55*/
+ MTK_PULL_PUPD_R1R0_TYPE,/*56*/ MTK_PULL_PUPD_R1R0_TYPE,/*57*/
+ MTK_PULL_PUPD_R1R0_TYPE,/*58*/ MTK_PULL_PUPD_R1R0_TYPE,/*59*/
+ MTK_PULL_PUPD_R1R0_TYPE,/*60*/ MTK_PULL_PUPD_R1R0_TYPE,/*61*/
+ MTK_PULL_PUPD_R1R0_TYPE,/*62*/ MTK_PULL_PU_PD_TYPE, /*63*/
+ MTK_PULL_PUPD_R1R0_TYPE,/*64*/ MTK_PULL_PUPD_R1R0_TYPE,/*65*/
+ MTK_PULL_PUPD_R1R0_TYPE,/*66*/ MTK_PULL_PUPD_R1R0_TYPE,/*67*/
+ MTK_PULL_PUPD_R1R0_TYPE,/*68*/ MTK_PULL_PUPD_R1R0_TYPE,/*69*/
+ MTK_PULL_PUPD_R1R0_TYPE,/*70*/ MTK_PULL_PD_TYPE, /*71*/
+ MTK_PULL_PD_TYPE, /*72*/ MTK_PULL_PUPD_R1R0_TYPE,/*73*/
+ MTK_PULL_PUPD_R1R0_TYPE,/*74*/ MTK_PULL_PU_PD_TYPE, /*75*/
+ MTK_PULL_PU_PD_TYPE, /*76*/ MTK_PULL_PU_PD_TYPE, /*77*/
+ MTK_PULL_PU_PD_TYPE, /*78*/ MTK_PULL_PU_PD_TYPE, /*79*/
+ MTK_PULL_PUPD_R1R0_TYPE,/*80*/ MTK_PULL_PUPD_R1R0_TYPE,/*81*/
+ MTK_PULL_PUPD_R1R0_TYPE,/*82*/ MTK_PULL_PUPD_R1R0_TYPE,/*83*/
+};
+
+static const struct mtk_pin_reg_calc mt7988_reg_cals[] = {
+ [PINCTRL_PIN_REG_MODE] = MTK_RANGE(mt7988_pin_mode_range),
+ [PINCTRL_PIN_REG_DIR] = MTK_RANGE(mt7988_pin_dir_range),
+ [PINCTRL_PIN_REG_DI] = MTK_RANGE(mt7988_pin_di_range),
+ [PINCTRL_PIN_REG_DO] = MTK_RANGE(mt7988_pin_do_range),
+ [PINCTRL_PIN_REG_SMT] = MTK_RANGE(mt7988_pin_smt_range),
+ [PINCTRL_PIN_REG_IES] = MTK_RANGE(mt7988_pin_ies_range),
+ [PINCTRL_PIN_REG_PU] = MTK_RANGE(mt7988_pin_pu_range),
+ [PINCTRL_PIN_REG_PD] = MTK_RANGE(mt7988_pin_pd_range),
+ [PINCTRL_PIN_REG_DRV] = MTK_RANGE(mt7988_pin_drv_range),
+ [PINCTRL_PIN_REG_PUPD] = MTK_RANGE(mt7988_pin_pupd_range),
+ [PINCTRL_PIN_REG_R0] = MTK_RANGE(mt7988_pin_r0_range),
+ [PINCTRL_PIN_REG_R1] = MTK_RANGE(mt7988_pin_r1_range),
+};
+
+static const struct mtk_pin_desc mt7988_pins[] = {
+ MT7988_PIN(0, "UART2_RXD"),
+ MT7988_PIN(1, "UART2_TXD"),
+ MT7988_PIN(2, "UART2_CTS"),
+ MT7988_PIN(3, "UART2_RTS"),
+ MT7988_PIN(4, "GPIO_A"),
+ MT7988_PIN(5, "SMI_0_MDC"),
+ MT7988_PIN(6, "SMI_0_MDIO"),
+ MT7988_PIN(7, "PCIE30_2L_0_WAKE_N"),
+ MT7988_PIN(8, "PCIE30_2L_0_CLKREQ_N"),
+ MT7988_PIN(9, "PCIE30_1L_1_WAKE_N"),
+ MT7988_PIN(10, "PCIE30_1L_1_CLKREQ_N"),
+ MT7988_PIN(11, "GPIO_P"),
+ MT7988_PIN(12, "WATCHDOG"),
+ MT7988_PIN(13, "GPIO_RESET"),
+ MT7988_PIN(14, "GPIO_WPS"),
+ MT7988_PIN(15, "PMIC_I2C_SCL"),
+ MT7988_PIN(16, "PMIC_I2C_SDA"),
+ MT7988_PIN(17, "I2C_1_SCL"),
+ MT7988_PIN(18, "I2C_1_SDA"),
+ MT7988_PIN(19, "PCIE30_2L_0_PRESET_N"),
+ MT7988_PIN(20, "PCIE30_1L_1_PRESET_N"),
+ MT7988_PIN(21, "PWMD1"),
+ MT7988_PIN(22, "SPI0_WP"),
+ MT7988_PIN(23, "SPI0_HOLD"),
+ MT7988_PIN(24, "SPI0_CSB"),
+ MT7988_PIN(25, "SPI0_MISO"),
+ MT7988_PIN(26, "SPI0_MOSI"),
+ MT7988_PIN(27, "SPI0_CLK"),
+ MT7988_PIN(28, "SPI1_CSB"),
+ MT7988_PIN(29, "SPI1_MISO"),
+ MT7988_PIN(30, "SPI1_MOSI"),
+ MT7988_PIN(31, "SPI1_CLK"),
+ MT7988_PIN(32, "SPI2_CLK"),
+ MT7988_PIN(33, "SPI2_MOSI"),
+ MT7988_PIN(34, "SPI2_MISO"),
+ MT7988_PIN(35, "SPI2_CSB"),
+ MT7988_PIN(36, "SPI2_HOLD"),
+ MT7988_PIN(37, "SPI2_WP"),
+ MT7988_PIN(38, "EMMC_RSTB"),
+ MT7988_PIN(39, "EMMC_DSL"),
+ MT7988_PIN(40, "EMMC_CK"),
+ MT7988_PIN(41, "EMMC_CMD"),
+ MT7988_PIN(42, "EMMC_DATA_7"),
+ MT7988_PIN(43, "EMMC_DATA_6"),
+ MT7988_PIN(44, "EMMC_DATA_5"),
+ MT7988_PIN(45, "EMMC_DATA_4"),
+ MT7988_PIN(46, "EMMC_DATA_3"),
+ MT7988_PIN(47, "EMMC_DATA_2"),
+ MT7988_PIN(48, "EMMC_DATA_1"),
+ MT7988_PIN(49, "EMMC_DATA_0"),
+ MT7988_PIN(50, "PCM_FS_I2S_LRCK"),
+ MT7988_PIN(51, "PCM_CLK_I2S_BCLK"),
+ MT7988_PIN(52, "PCM_DRX_I2S_DIN"),
+ MT7988_PIN(53, "PCM_DTX_I2S_DOUT"),
+ MT7988_PIN(54, "PCM_MCK_I2S_MCLK"),
+ MT7988_PIN(55, "UART0_RXD"),
+ MT7988_PIN(56, "UART0_TXD"),
+ MT7988_PIN(57, "PWMD0"),
+ MT7988_PIN(58, "JTAG_JTDI"),
+ MT7988_PIN(59, "JTAG_JTDO"),
+ MT7988_PIN(60, "JTAG_JTMS"),
+ MT7988_PIN(61, "JTAG_JTCLK"),
+ MT7988_PIN(62, "JTAG_JTRST_N"),
+ MT7988_PIN(63, "USB_DRV_VBUS_P1"),
+ MT7988_PIN(64, "LED_A"),
+ MT7988_PIN(65, "LED_B"),
+ MT7988_PIN(66, "LED_C"),
+ MT7988_PIN(67, "LED_D"),
+ MT7988_PIN(68, "LED_E"),
+ MT7988_PIN(69, "GPIO_B"),
+ MT7988_PIN(70, "GPIO_C"),
+ MT7988_PIN(71, "I2C_2_SCL"),
+ MT7988_PIN(72, "I2C_2_SDA"),
+ MT7988_PIN(73, "PCIE30_2L_1_PRESET_N"),
+ MT7988_PIN(74, "PCIE30_1L_0_PRESET_N"),
+ MT7988_PIN(75, "PCIE30_2L_1_WAKE_N"),
+ MT7988_PIN(76, "PCIE30_2L_1_CLKREQ_N"),
+ MT7988_PIN(77, "PCIE30_1L_0_WAKE_N"),
+ MT7988_PIN(78, "PCIE30_1L_0_CLKREQ_N"),
+ MT7988_PIN(79, "USB_DRV_VBUS_P0"),
+ MT7988_PIN(80, "UART1_RXD"),
+ MT7988_PIN(81, "UART1_TXD"),
+ MT7988_PIN(82, "UART1_CTS"),
+ MT7988_PIN(83, "UART1_RTS"),
+};
+
+/* jtag */
+static int mt7988_tops_jtag0_0_pins[] = { 0, 1, 2, 3, 4 };
+static int mt7988_tops_jtag0_0_funcs[] = { 2, 2, 2, 2, 2 };
+
+static int mt7988_wo0_jtag_pins[] = { 50, 51, 52, 53, 54 };
+static int mt7988_wo0_jtag_funcs[] = { 3, 3, 3, 3, 3 };
+
+static int mt7988_wo1_jtag_pins[] = { 50, 51, 52, 53, 54 };
+static int mt7988_wo1_jtag_funcs[] = { 4, 4, 4, 4, 4 };
+
+static int mt7988_wo2_jtag_pins[] = { 50, 51, 52, 53, 54 };
+static int mt7988_wo2_jtag_funcs[] = { 5, 5, 5, 5, 5 };
+
+static int mt7988_jtag_pins[] = { 58, 59, 60, 61, 62 };
+static int mt7988_jtag_funcs[] = { 1, 1, 1, 1, 1 };
+
+static int mt7988_tops_jtag0_1_pins[] = { 58, 59, 60, 61, 62 };
+static int mt7988_tops_jtag0_1_funcs[] = { 4, 4, 4, 4, 4 };
+
+/* int_usxgmii */
+static int mt7988_int_usxgmii_pins[] = { 2, 3 };
+static int mt7988_int_usxgmii_funcs[] = { 3, 3 };
+
+/* pwm */
+static int mt7988_pwm0_pins[] = { 57 };
+static int mt7988_pwm0_funcs[] = { 1 };
+
+static int mt7988_pwm1_pins[] = { 21 };
+static int mt7988_pwm1_funcs[] = { 1 };
+
+static int mt7988_pwm2_pins[] = { 80 };
+static int mt7988_pwm2_funcs[] = { 2 };
+
+static int mt7988_pwm2_0_pins[] = { 58 };
+static int mt7988_pwm2_0_funcs[] = { 5 };
+
+static int mt7988_pwm3_pins[] = { 81 };
+static int mt7988_pwm3_funcs[] = { 2 };
+
+static int mt7988_pwm3_0_pins[] = { 59 };
+static int mt7988_pwm3_0_funcs[] = { 5 };
+
+static int mt7988_pwm4_pins[] = { 82 };
+static int mt7988_pwm4_funcs[] = { 2 };
+
+static int mt7988_pwm4_0_pins[] = { 60 };
+static int mt7988_pwm4_0_funcs[] = { 5 };
+
+static int mt7988_pwm5_pins[] = { 83 };
+static int mt7988_pwm5_funcs[] = { 2 };
+
+static int mt7988_pwm5_0_pins[] = { 61 };
+static int mt7988_pwm5_0_funcs[] = { 5 };
+
+static int mt7988_pwm6_pins[] = { 69 };
+static int mt7988_pwm6_funcs[] = { 3 };
+
+static int mt7988_pwm6_0_pins[] = { 62 };
+static int mt7988_pwm6_0_funcs[] = { 5 };
+
+static int mt7988_pwm7_pins[] = { 70 };
+static int mt7988_pwm7_funcs[] = { 3 };
+
+static int mt7988_pwm7_0_pins[] = { 4 };
+static int mt7988_pwm7_0_funcs[] = { 3 };
+
+/* dfd */
+static int mt7988_dfd_pins[] = { 0, 1, 2, 3, 4 };
+static int mt7988_dfd_funcs[] = { 4, 4, 4, 4, 4 };
+
+/* i2c */
+static int mt7988_xfi_phy0_i2c0_pins[] = { 0, 1 };
+static int mt7988_xfi_phy0_i2c0_funcs[] = { 5, 5 };
+
+static int mt7988_xfi_phy1_i2c0_pins[] = { 0, 1 };
+static int mt7988_xfi_phy1_i2c0_funcs[] = { 6, 6 };
+
+static int mt7988_xfi_phy_pll_i2c0_pins[] = { 3, 4 };
+static int mt7988_xfi_phy_pll_i2c0_funcs[] = { 5, 5 };
+
+static int mt7988_xfi_phy_pll_i2c1_pins[] = { 3, 4 };
+static int mt7988_xfi_phy_pll_i2c1_funcs[] = { 6, 6 };
+
+static int mt7988_i2c0_0_pins[] = { 5, 6 };
+static int mt7988_i2c0_0_funcs[] = { 2, 2 };
+
+static int mt7988_i2c1_sfp_pins[] = { 5, 6 };
+static int mt7988_i2c1_sfp_funcs[] = { 4, 4 };
+
+static int mt7988_xfi_pextp_phy0_i2c_pins[] = { 5, 6 };
+static int mt7988_xfi_pextp_phy0_i2c_funcs[] = { 5, 5 };
+
+static int mt7988_xfi_pextp_phy1_i2c_pins[] = { 5, 6 };
+static int mt7988_xfi_pextp_phy1_i2c_funcs[] = { 6, 6 };
+
+static int mt7988_i2c0_1_pins[] = { 15, 16 };
+static int mt7988_i2c0_1_funcs[] = { 1, 1 };
+
+static int mt7988_u30_phy_i2c0_pins[] = { 15, 16 };
+static int mt7988_u30_phy_i2c0_funcs[] = { 2, 2 };
+
+static int mt7988_u32_phy_i2c0_pins[] = { 15, 16 };
+static int mt7988_u32_phy_i2c0_funcs[] = { 3, 3 };
+
+static int mt7988_xfi_phy0_i2c1_pins[] = { 15, 16 };
+static int mt7988_xfi_phy0_i2c1_funcs[] = { 5, 5 };
+
+static int mt7988_xfi_phy1_i2c1_pins[] = { 15, 16 };
+static int mt7988_xfi_phy1_i2c1_funcs[] = { 6, 6 };
+
+static int mt7988_xfi_phy_pll_i2c2_pins[] = { 15, 16 };
+static int mt7988_xfi_phy_pll_i2c2_funcs[] = { 7, 7 };
+
+static int mt7988_i2c1_0_pins[] = { 17, 18 };
+static int mt7988_i2c1_0_funcs[] = { 1, 1 };
+
+static int mt7988_u30_phy_i2c1_pins[] = { 17, 18 };
+static int mt7988_u30_phy_i2c1_funcs[] = { 2, 2 };
+
+static int mt7988_u32_phy_i2c1_pins[] = { 17, 18 };
+static int mt7988_u32_phy_i2c1_funcs[] = { 3, 3 };
+
+static int mt7988_xfi_phy_pll_i2c3_pins[] = { 17, 18 };
+static int mt7988_xfi_phy_pll_i2c3_funcs[] = { 4, 4 };
+
+static int mt7988_sgmii0_i2c_pins[] = { 17, 18 };
+static int mt7988_sgmii0_i2c_funcs[] = { 5, 5 };
+
+static int mt7988_sgmii1_i2c_pins[] = { 17, 18 };
+static int mt7988_sgmii1_i2c_funcs[] = { 6, 6 };
+
+static int mt7988_i2c1_2_pins[] = { 69, 70 };
+static int mt7988_i2c1_2_funcs[] = { 2, 2 };
+
+static int mt7988_i2c2_0_pins[] = { 69, 70 };
+static int mt7988_i2c2_0_funcs[] = { 4, 4 };
+
+static int mt7988_i2c2_1_pins[] = { 71, 72 };
+static int mt7988_i2c2_1_funcs[] = { 1, 1 };
+
+/* eth */
+static int mt7988_mdc_mdio0_pins[] = { 5, 6 };
+static int mt7988_mdc_mdio0_funcs[] = { 1, 1 };
+
+static int mt7988_2p5g_ext_mdio_pins[] = { 28, 29 };
+static int mt7988_2p5g_ext_mdio_funcs[] = { 6, 6 };
+
+static int mt7988_gbe_ext_mdio_pins[] = { 30, 31 };
+static int mt7988_gbe_ext_mdio_funcs[] = { 6, 6 };
+
+static int mt7988_mdc_mdio1_pins[] = { 69, 70 };
+static int mt7988_mdc_mdio1_funcs[] = { 1, 1 };
+
+/* pcie */
+static int mt7988_pcie_wake_n0_0_pins[] = { 7 };
+static int mt7988_pcie_wake_n0_0_funcs[] = { 1 };
+
+static int mt7988_pcie_clk_req_n0_0_pins[] = { 8 };
+static int mt7988_pcie_clk_req_n0_0_funcs[] = { 1 };
+
+static int mt7988_pcie_wake_n3_0_pins[] = { 9 };
+static int mt7988_pcie_wake_n3_0_funcs[] = { 1 };
+
+static int mt7988_pcie_clk_req_n3_pins[] = { 10 };
+static int mt7988_pcie_clk_req_n3_funcs[] = { 1 };
+
+static int mt7988_pcie_clk_req_n0_1_pins[] = { 10 };
+static int mt7988_pcie_clk_req_n0_1_funcs[] = { 2 };
+
+static int mt7988_pcie_p0_phy_i2c_pins[] = { 7, 8 };
+static int mt7988_pcie_p0_phy_i2c_funcs[] = { 3, 3 };
+
+static int mt7988_pcie_p1_phy_i2c_pins[] = { 7, 8 };
+static int mt7988_pcie_p1_phy_i2c_funcs[] = { 4, 4 };
+
+static int mt7988_pcie_p3_phy_i2c_pins[] = { 9, 10 };
+static int mt7988_pcie_p3_phy_i2c_funcs[] = { 4, 4 };
+
+static int mt7988_pcie_p2_phy_i2c_pins[] = { 7, 8 };
+static int mt7988_pcie_p2_phy_i2c_funcs[] = { 5, 5 };
+
+static int mt7988_ckm_phy_i2c_pins[] = { 9, 10 };
+static int mt7988_ckm_phy_i2c_funcs[] = { 5, 5 };
+
+static int mt7988_pcie_wake_n0_1_pins[] = { 13 };
+static int mt7988_pcie_wake_n0_1_funcs[] = { 2 };
+
+static int mt7988_pcie_wake_n3_1_pins[] = { 14 };
+static int mt7988_pcie_wake_n3_1_funcs[] = { 2 };
+
+static int mt7988_pcie_2l_0_pereset_pins[] = { 19 };
+static int mt7988_pcie_2l_0_pereset_funcs[] = { 1 };
+
+static int mt7988_pcie_1l_1_pereset_pins[] = { 20 };
+static int mt7988_pcie_1l_1_pereset_funcs[] = { 1 };
+
+static int mt7988_pcie_clk_req_n2_1_pins[] = { 63 };
+static int mt7988_pcie_clk_req_n2_1_funcs[] = { 2 };
+
+static int mt7988_pcie_2l_1_pereset_pins[] = { 73 };
+static int mt7988_pcie_2l_1_pereset_funcs[] = { 1 };
+
+static int mt7988_pcie_1l_0_pereset_pins[] = { 74 };
+static int mt7988_pcie_1l_0_pereset_funcs[] = { 1 };
+
+static int mt7988_pcie_wake_n1_0_pins[] = { 75 };
+static int mt7988_pcie_wake_n1_0_funcs[] = { 1 };
+
+static int mt7988_pcie_clk_req_n1_pins[] = { 76 };
+static int mt7988_pcie_clk_req_n1_funcs[] = { 1 };
+
+static int mt7988_pcie_wake_n2_0_pins[] = { 77 };
+static int mt7988_pcie_wake_n2_0_funcs[] = { 1 };
+
+static int mt7988_pcie_clk_req_n2_0_pins[] = { 78 };
+static int mt7988_pcie_clk_req_n2_0_funcs[] = { 1 };
+
+static int mt7988_pcie_wake_n2_1_pins[] = { 79 };
+static int mt7988_pcie_wake_n2_1_funcs[] = { 2 };
+
+/* pmic */
+static int mt7988_pmic_pins[] = { 11 };
+static int mt7988_pmic_funcs[] = { 1 };
+
+/* watchdog */
+static int mt7988_watchdog_pins[] = { 12 };
+static int mt7988_watchdog_funcs[] = { 1 };
+
+/* spi */
+static int mt7988_spi0_wp_hold_pins[] = { 22, 23 };
+static int mt7988_spi0_wp_hold_funcs[] = { 1, 1 };
+
+static int mt7988_spi0_pins[] = { 24, 25, 26, 27 };
+static int mt7988_spi0_funcs[] = { 1, 1, 1, 1 };
+
+static int mt7988_spi1_pins[] = { 28, 29, 30, 31 };
+static int mt7988_spi1_funcs[] = { 1, 1, 1, 1 };
+
+static int mt7988_spi2_pins[] = { 32, 33, 34, 35 };
+static int mt7988_spi2_funcs[] = { 1, 1, 1, 1 };
+
+static int mt7988_spi2_wp_hold_pins[] = { 36, 37 };
+static int mt7988_spi2_wp_hold_funcs[] = { 1, 1 };
+
+/* flash */
+static int mt7988_snfi_pins[] = { 22, 23, 24, 25, 26, 27 };
+static int mt7988_snfi_funcs[] = { 2, 2, 2, 2, 2, 2 };
+
+static int mt7988_emmc_45_pins[] = {
+ 21, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37
+};
+static int mt7988_emmc_45_funcs[] = { 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5 };
+
+static int mt7988_sdcard_pins[] = { 32, 33, 34, 35, 36, 37 };
+static int mt7988_sdcard_funcs[] = { 5, 5, 5, 5, 5, 5 };
+
+static int mt7988_emmc_51_pins[] = { 38, 39, 40, 41, 42, 43,
+ 44, 45, 46, 47, 48, 49 };
+static int mt7988_emmc_51_funcs[] = { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 };
+
+/* uart */
+static int mt7988_uart2_pins[] = { 0, 1, 2, 3 };
+static int mt7988_uart2_funcs[] = { 1, 1, 1, 1 };
+
+static int mt7988_tops_uart0_0_pins[] = { 22, 23 };
+static int mt7988_tops_uart0_0_funcs[] = { 3, 3 };
+
+static int mt7988_uart2_0_pins[] = { 28, 29, 30, 31 };
+static int mt7988_uart2_0_funcs[] = { 2, 2, 2, 2 };
+
+static int mt7988_uart1_0_pins[] = { 32, 33, 34, 35 };
+static int mt7988_uart1_0_funcs[] = { 2, 2, 2, 2 };
+
+static int mt7988_uart2_1_pins[] = { 32, 33, 34, 35 };
+static int mt7988_uart2_1_funcs[] = { 3, 3, 3, 3 };
+
+static int mt7988_net_wo0_uart_txd_0_pins[] = { 28 };
+static int mt7988_net_wo0_uart_txd_0_funcs[] = { 3 };
+
+static int mt7988_net_wo1_uart_txd_0_pins[] = { 29 };
+static int mt7988_net_wo1_uart_txd_0_funcs[] = { 3 };
+
+static int mt7988_net_wo2_uart_txd_0_pins[] = { 30 };
+static int mt7988_net_wo2_uart_txd_0_funcs[] = { 3 };
+
+static int mt7988_tops_uart1_0_pins[] = { 28, 29 };
+static int mt7988_tops_uart1_0_funcs[] = { 4, 4 };
+
+static int mt7988_tops_uart0_1_pins[] = { 30, 31 };
+static int mt7988_tops_uart0_1_funcs[] = { 4, 4 };
+
+static int mt7988_tops_uart1_1_pins[] = { 36, 37 };
+static int mt7988_tops_uart1_1_funcs[] = { 3, 3 };
+
+static int mt7988_uart0_pins[] = { 55, 56 };
+static int mt7988_uart0_funcs[] = { 1, 1 };
+
+static int mt7988_tops_uart0_2_pins[] = { 55, 56 };
+static int mt7988_tops_uart0_2_funcs[] = { 2, 2 };
+
+static int mt7988_uart2_2_pins[] = { 50, 51, 52, 53 };
+static int mt7988_uart2_2_funcs[] = { 2, 2, 2, 2 };
+
+static int mt7988_uart1_1_pins[] = { 58, 59, 60, 61 };
+static int mt7988_uart1_1_funcs[] = { 2, 2, 2, 2 };
+
+static int mt7988_uart2_3_pins[] = { 58, 59, 60, 61 };
+static int mt7988_uart2_3_funcs[] = { 3, 3, 3, 3 };
+
+static int mt7988_uart1_2_pins[] = { 80, 81, 82, 83 };
+static int mt7988_uart1_2_funcs[] = { 1, 1, 1, 1 };
+
+static int mt7988_uart1_2_lite_pins[] = { 80, 81 };
+static int mt7988_uart1_2_lite_funcs[] = { 1, 1 };
+
+static int mt7988_tops_uart1_2_pins[] = { 80, 81 };
+static int mt7988_tops_uart1_2_funcs[] = { 4, 4, };
+
+static int mt7988_net_wo0_uart_txd_1_pins[] = { 80 };
+static int mt7988_net_wo0_uart_txd_1_funcs[] = { 3 };
+
+static int mt7988_net_wo1_uart_txd_1_pins[] = { 81 };
+static int mt7988_net_wo1_uart_txd_1_funcs[] = { 3 };
+
+static int mt7988_net_wo2_uart_txd_1_pins[] = { 82 };
+static int mt7988_net_wo2_uart_txd_1_funcs[] = { 3 };
+
+/* udi */
+static int mt7988_udi_pins[] = { 32, 33, 34, 35, 36 };
+static int mt7988_udi_funcs[] = { 4, 4, 4, 4, 4 };
+
+/* i2s */
+static int mt7988_i2s_pins[] = { 50, 51, 52, 53, 54 };
+static int mt7988_i2s_funcs[] = { 1, 1, 1, 1, 1 };
+
+/* pcm */
+static int mt7988_pcm_pins[] = { 50, 51, 52, 53 };
+static int mt7988_pcm_funcs[] = { 1, 1, 1, 1 };
+
+/* led */
+static int mt7988_gbe0_led1_pins[] = { 58 };
+static int mt7988_gbe0_led1_funcs[] = { 6 };
+static int mt7988_gbe1_led1_pins[] = { 59 };
+static int mt7988_gbe1_led1_funcs[] = { 6 };
+static int mt7988_gbe2_led1_pins[] = { 60 };
+static int mt7988_gbe2_led1_funcs[] = { 6 };
+static int mt7988_gbe3_led1_pins[] = { 61 };
+static int mt7988_gbe3_led1_funcs[] = { 6 };
+
+static int mt7988_2p5gbe_led1_pins[] = { 62 };
+static int mt7988_2p5gbe_led1_funcs[] = { 6 };
+
+static int mt7988_gbe0_led0_pins[] = { 64 };
+static int mt7988_gbe0_led0_funcs[] = { 1 };
+static int mt7988_gbe1_led0_pins[] = { 65 };
+static int mt7988_gbe1_led0_funcs[] = { 1 };
+static int mt7988_gbe2_led0_pins[] = { 66 };
+static int mt7988_gbe2_led0_funcs[] = { 1 };
+static int mt7988_gbe3_led0_pins[] = { 67 };
+static int mt7988_gbe3_led0_funcs[] = { 1 };
+
+static int mt7988_2p5gbe_led0_pins[] = { 68 };
+static int mt7988_2p5gbe_led0_funcs[] = { 1 };
+
+/* usb */
+static int mt7988_drv_vbus_p1_pins[] = { 63 };
+static int mt7988_drv_vbus_p1_funcs[] = { 1 };
+
+static int mt7988_drv_vbus_pins[] = { 79 };
+static int mt7988_drv_vbus_funcs[] = { 1 };
+
+static const struct group_desc mt7988_groups[] = {
+ /* @GPIO(0,1,2,3): uart2 */
+ PINCTRL_PIN_GROUP("uart2", mt7988_uart2),
+ /* @GPIO(0,1,2,3,4): tops_jtag0_0 */
+ PINCTRL_PIN_GROUP("tops_jtag0_0", mt7988_tops_jtag0_0),
+ /* @GPIO(2,3): int_usxgmii */
+ PINCTRL_PIN_GROUP("int_usxgmii", mt7988_int_usxgmii),
+ /* @GPIO(0,1,2,3,4): dfd */
+ PINCTRL_PIN_GROUP("dfd", mt7988_dfd),
+ /* @GPIO(0,1): xfi_phy0_i2c0 */
+ PINCTRL_PIN_GROUP("xfi_phy0_i2c0", mt7988_xfi_phy0_i2c0),
+ /* @GPIO(0,1): xfi_phy1_i2c0 */
+ PINCTRL_PIN_GROUP("xfi_phy1_i2c0", mt7988_xfi_phy1_i2c0),
+ /* @GPIO(3,4): xfi_phy_pll_i2c0 */
+ PINCTRL_PIN_GROUP("xfi_phy_pll_i2c0", mt7988_xfi_phy_pll_i2c0),
+ /* @GPIO(3,4): xfi_phy_pll_i2c1 */
+ PINCTRL_PIN_GROUP("xfi_phy_pll_i2c1", mt7988_xfi_phy_pll_i2c1),
+ /* @GPIO(4): pwm7 */
+ PINCTRL_PIN_GROUP("pwm7_0", mt7988_pwm7_0),
+ /* @GPIO(5,6) i2c0_0 */
+ PINCTRL_PIN_GROUP("i2c0_0", mt7988_i2c0_0),
+ /* @GPIO(5,6) i2c1_sfp */
+ PINCTRL_PIN_GROUP("i2c1_sfp", mt7988_i2c1_sfp),
+ /* @GPIO(5,6) xfi_pextp_phy0_i2c */
+ PINCTRL_PIN_GROUP("xfi_pextp_phy0_i2c", mt7988_xfi_pextp_phy0_i2c),
+ /* @GPIO(5,6) xfi_pextp_phy1_i2c */
+ PINCTRL_PIN_GROUP("xfi_pextp_phy1_i2c", mt7988_xfi_pextp_phy1_i2c),
+ /* @GPIO(5,6) mdc_mdio0 */
+ PINCTRL_PIN_GROUP("mdc_mdio0", mt7988_mdc_mdio0),
+ /* @GPIO(7): pcie_wake_n0_0 */
+ PINCTRL_PIN_GROUP("pcie_wake_n0_0", mt7988_pcie_wake_n0_0),
+ /* @GPIO(8): pcie_clk_req_n0_0 */
+ PINCTRL_PIN_GROUP("pcie_clk_req_n0_0", mt7988_pcie_clk_req_n0_0),
+ /* @GPIO(9): pcie_wake_n3_0 */
+ PINCTRL_PIN_GROUP("pcie_wake_n3_0", mt7988_pcie_wake_n3_0),
+ /* @GPIO(10): pcie_clk_req_n3 */
+ PINCTRL_PIN_GROUP("pcie_clk_req_n3", mt7988_pcie_clk_req_n3),
+ /* @GPIO(10): pcie_clk_req_n0_1 */
+ PINCTRL_PIN_GROUP("pcie_clk_req_n0_1", mt7988_pcie_clk_req_n0_1),
+ /* @GPIO(7,8) pcie_p0_phy_i2c */
+ PINCTRL_PIN_GROUP("pcie_p0_phy_i2c", mt7988_pcie_p0_phy_i2c),
+ /* @GPIO(7,8) pcie_p1_phy_i2c */
+ PINCTRL_PIN_GROUP("pcie_p1_phy_i2c", mt7988_pcie_p1_phy_i2c),
+ /* @GPIO(7,8) pcie_p2_phy_i2c */
+ PINCTRL_PIN_GROUP("pcie_p2_phy_i2c", mt7988_pcie_p2_phy_i2c),
+ /* @GPIO(9,10) pcie_p3_phy_i2c */
+ PINCTRL_PIN_GROUP("pcie_p3_phy_i2c", mt7988_pcie_p3_phy_i2c),
+ /* @GPIO(9,10) ckm_phy_i2c */
+ PINCTRL_PIN_GROUP("ckm_phy_i2c", mt7988_ckm_phy_i2c),
+ /* @GPIO(11): pmic */
+ PINCTRL_PIN_GROUP("pcie_pmic", mt7988_pmic),
+ /* @GPIO(12): watchdog */
+ PINCTRL_PIN_GROUP("watchdog", mt7988_watchdog),
+ /* @GPIO(13): pcie_wake_n0_1 */
+ PINCTRL_PIN_GROUP("pcie_wake_n0_1", mt7988_pcie_wake_n0_1),
+ /* @GPIO(14): pcie_wake_n3_1 */
+ PINCTRL_PIN_GROUP("pcie_wake_n3_1", mt7988_pcie_wake_n3_1),
+ /* @GPIO(15,16) i2c0_1 */
+ PINCTRL_PIN_GROUP("i2c0_1", mt7988_i2c0_1),
+ /* @GPIO(15,16) u30_phy_i2c0 */
+ PINCTRL_PIN_GROUP("u30_phy_i2c0", mt7988_u30_phy_i2c0),
+ /* @GPIO(15,16) u32_phy_i2c0 */
+ PINCTRL_PIN_GROUP("u32_phy_i2c0", mt7988_u32_phy_i2c0),
+ /* @GPIO(15,16) xfi_phy0_i2c1 */
+ PINCTRL_PIN_GROUP("xfi_phy0_i2c1", mt7988_xfi_phy0_i2c1),
+ /* @GPIO(15,16) xfi_phy1_i2c1 */
+ PINCTRL_PIN_GROUP("xfi_phy1_i2c1", mt7988_xfi_phy1_i2c1),
+ /* @GPIO(15,16) xfi_phy_pll_i2c2 */
+ PINCTRL_PIN_GROUP("xfi_phy_pll_i2c2", mt7988_xfi_phy_pll_i2c2),
+ /* @GPIO(17,18) i2c1_0 */
+ PINCTRL_PIN_GROUP("i2c1_0", mt7988_i2c1_0),
+ /* @GPIO(17,18) u30_phy_i2c1 */
+ PINCTRL_PIN_GROUP("u30_phy_i2c1", mt7988_u30_phy_i2c1),
+ /* @GPIO(17,18) u32_phy_i2c1 */
+ PINCTRL_PIN_GROUP("u32_phy_i2c1", mt7988_u32_phy_i2c1),
+ /* @GPIO(17,18) xfi_phy_pll_i2c3 */
+ PINCTRL_PIN_GROUP("xfi_phy_pll_i2c3", mt7988_xfi_phy_pll_i2c3),
+ /* @GPIO(17,18) sgmii0_i2c */
+ PINCTRL_PIN_GROUP("sgmii0_i2c", mt7988_sgmii0_i2c),
+ /* @GPIO(17,18) sgmii1_i2c */
+ PINCTRL_PIN_GROUP("sgmii1_i2c", mt7988_sgmii1_i2c),
+ /* @GPIO(19): pcie_2l_0_pereset */
+ PINCTRL_PIN_GROUP("pcie_2l_0_pereset", mt7988_pcie_2l_0_pereset),
+ /* @GPIO(20): pcie_1l_1_pereset */
+ PINCTRL_PIN_GROUP("pcie_1l_1_pereset", mt7988_pcie_1l_1_pereset),
+ /* @GPIO(21): pwm1 */
+ PINCTRL_PIN_GROUP("pwm1", mt7988_pwm1),
+ /* @GPIO(22,23) spi0_wp_hold */
+ PINCTRL_PIN_GROUP("spi0_wp_hold", mt7988_spi0_wp_hold),
+ /* @GPIO(24,25,26,27) spi0 */
+ PINCTRL_PIN_GROUP("spi0", mt7988_spi0),
+ /* @GPIO(28,29,30,31) spi1 */
+ PINCTRL_PIN_GROUP("spi1", mt7988_spi1),
+ /* @GPIO(32,33,34,35) spi2 */
+ PINCTRL_PIN_GROUP("spi2", mt7988_spi2),
+ /* @GPIO(36,37) spi2_wp_hold */
+ PINCTRL_PIN_GROUP("spi2_wp_hold", mt7988_spi2_wp_hold),
+ /* @GPIO(22,23,24,25,26,27) snfi */
+ PINCTRL_PIN_GROUP("snfi", mt7988_snfi),
+ /* @GPIO(22,23) tops_uart0_0 */
+ PINCTRL_PIN_GROUP("tops_uart0_0", mt7988_tops_uart0_0),
+ /* @GPIO(28,29,30,31) uart2_0 */
+ PINCTRL_PIN_GROUP("uart2_0", mt7988_uart2_0),
+ /* @GPIO(32,33,34,35) uart1_0 */
+ PINCTRL_PIN_GROUP("uart1_0", mt7988_uart1_0),
+ /* @GPIO(32,33,34,35) uart2_1 */
+ PINCTRL_PIN_GROUP("uart2_1", mt7988_uart2_1),
+ /* @GPIO(28) net_wo0_uart_txd_0 */
+ PINCTRL_PIN_GROUP("net_wo0_uart_txd_0", mt7988_net_wo0_uart_txd_0),
+ /* @GPIO(29) net_wo1_uart_txd_0 */
+ PINCTRL_PIN_GROUP("net_wo1_uart_txd_0", mt7988_net_wo1_uart_txd_0),
+ /* @GPIO(30) net_wo2_uart_txd_0 */
+ PINCTRL_PIN_GROUP("net_wo2_uart_txd_0", mt7988_net_wo2_uart_txd_0),
+ /* @GPIO(28,29) tops_uart1_0 */
+ PINCTRL_PIN_GROUP("tops_uart0_0", mt7988_tops_uart1_0),
+ /* @GPIO(30,31) tops_uart0_1 */
+ PINCTRL_PIN_GROUP("tops_uart0_1", mt7988_tops_uart0_1),
+ /* @GPIO(36,37) tops_uart1_1 */
+ PINCTRL_PIN_GROUP("tops_uart1_1", mt7988_tops_uart1_1),
+ /* @GPIO(32,33,34,35,36) udi */
+ PINCTRL_PIN_GROUP("udi", mt7988_udi),
+ /* @GPIO(21,28,29,30,31,32,33,34,35,36,37) emmc_45 */
+ PINCTRL_PIN_GROUP("emmc_45", mt7988_emmc_45),
+ /* @GPIO(32,33,34,35,36,37) sdcard */
+ PINCTRL_PIN_GROUP("sdcard", mt7988_sdcard),
+ /* @GPIO(38,39,40,41,42,43,44,45,46,47,48,49) emmc_51 */
+ PINCTRL_PIN_GROUP("emmc_51", mt7988_emmc_51),
+ /* @GPIO(28,29) 2p5g_ext_mdio */
+ PINCTRL_PIN_GROUP("2p5g_ext_mdio", mt7988_2p5g_ext_mdio),
+ /* @GPIO(30,31) gbe_ext_mdio */
+ PINCTRL_PIN_GROUP("gbe_ext_mdio", mt7988_gbe_ext_mdio),
+ /* @GPIO(50,51,52,53,54) i2s */
+ PINCTRL_PIN_GROUP("i2s", mt7988_i2s),
+ /* @GPIO(50,51,52,53) pcm */
+ PINCTRL_PIN_GROUP("pcm", mt7988_pcm),
+ /* @GPIO(55,56) uart0 */
+ PINCTRL_PIN_GROUP("uart0", mt7988_uart0),
+ /* @GPIO(55,56) tops_uart0_2 */
+ PINCTRL_PIN_GROUP("tops_uart0_2", mt7988_tops_uart0_2),
+ /* @GPIO(50,51,52,53) uart2_2 */
+ PINCTRL_PIN_GROUP("uart2_2", mt7988_uart2_2),
+ /* @GPIO(50,51,52,53,54) wo0_jtag */
+ PINCTRL_PIN_GROUP("wo0_jtag", mt7988_wo0_jtag),
+ /* @GPIO(50,51,52,53,54) wo1-wo1_jtag */
+ PINCTRL_PIN_GROUP("wo1_jtag", mt7988_wo1_jtag),
+ /* @GPIO(50,51,52,53,54) wo2_jtag */
+ PINCTRL_PIN_GROUP("wo2_jtag", mt7988_wo2_jtag),
+ /* @GPIO(57) pwm0 */
+ PINCTRL_PIN_GROUP("pwm0", mt7988_pwm0),
+ /* @GPIO(58) pwm2_0 */
+ PINCTRL_PIN_GROUP("pwm2_0", mt7988_pwm2_0),
+ /* @GPIO(59) pwm3_0 */
+ PINCTRL_PIN_GROUP("pwm3_0", mt7988_pwm3_0),
+ /* @GPIO(60) pwm4_0 */
+ PINCTRL_PIN_GROUP("pwm4_0", mt7988_pwm4_0),
+ /* @GPIO(61) pwm5_0 */
+ PINCTRL_PIN_GROUP("pwm5_0", mt7988_pwm5_0),
+ /* @GPIO(58,59,60,61,62) jtag */
+ PINCTRL_PIN_GROUP("jtag", mt7988_jtag),
+ /* @GPIO(58,59,60,61,62) tops_jtag0_1 */
+ PINCTRL_PIN_GROUP("tops_jtag0_1", mt7988_tops_jtag0_1),
+ /* @GPIO(58,59,60,61) uart2_3 */
+ PINCTRL_PIN_GROUP("uart2_3", mt7988_uart2_3),
+ /* @GPIO(58,59,60,61) uart1_1 */
+ PINCTRL_PIN_GROUP("uart1_1", mt7988_uart1_1),
+ /* @GPIO(58,59,60,61) gbe_led1 */
+ PINCTRL_PIN_GROUP("gbe0_led1", mt7988_gbe0_led1),
+ PINCTRL_PIN_GROUP("gbe1_led1", mt7988_gbe1_led1),
+ PINCTRL_PIN_GROUP("gbe2_led1", mt7988_gbe2_led1),
+ PINCTRL_PIN_GROUP("gbe3_led1", mt7988_gbe3_led1),
+ /* @GPIO(62) pwm6_0 */
+ PINCTRL_PIN_GROUP("pwm6_0", mt7988_pwm6_0),
+ /* @GPIO(62) 2p5gbe_led1 */
+ PINCTRL_PIN_GROUP("2p5gbe_led1", mt7988_2p5gbe_led1),
+ /* @GPIO(64,65,66,67) gbe_led0 */
+ PINCTRL_PIN_GROUP("gbe0_led0", mt7988_gbe0_led0),
+ PINCTRL_PIN_GROUP("gbe1_led0", mt7988_gbe1_led0),
+ PINCTRL_PIN_GROUP("gbe2_led0", mt7988_gbe2_led0),
+ PINCTRL_PIN_GROUP("gbe3_led0", mt7988_gbe3_led0),
+ /* @GPIO(68) 2p5gbe_led0 */
+ PINCTRL_PIN_GROUP("2p5gbe_led0", mt7988_2p5gbe_led0),
+ /* @GPIO(63) drv_vbus_p1 */
+ PINCTRL_PIN_GROUP("drv_vbus_p1", mt7988_drv_vbus_p1),
+ /* @GPIO(63) pcie_clk_req_n2_1 */
+ PINCTRL_PIN_GROUP("pcie_clk_req_n2_1", mt7988_pcie_clk_req_n2_1),
+ /* @GPIO(69, 70) mdc_mdio1 */
+ PINCTRL_PIN_GROUP("mdc_mdio1", mt7988_mdc_mdio1),
+ /* @GPIO(69, 70) i2c1_2 */
+ PINCTRL_PIN_GROUP("i2c1_2", mt7988_i2c1_2),
+ /* @GPIO(69) pwm6 */
+ PINCTRL_PIN_GROUP("pwm6", mt7988_pwm6),
+ /* @GPIO(70) pwm7 */
+ PINCTRL_PIN_GROUP("pwm7", mt7988_pwm7),
+ /* @GPIO(69,70) i2c2_0 */
+ PINCTRL_PIN_GROUP("i2c2_0", mt7988_i2c2_0),
+ /* @GPIO(71,72) i2c2_1 */
+ PINCTRL_PIN_GROUP("i2c2_1", mt7988_i2c2_1),
+ /* @GPIO(73) pcie_2l_1_pereset */
+ PINCTRL_PIN_GROUP("pcie_2l_1_pereset", mt7988_pcie_2l_1_pereset),
+ /* @GPIO(74) pcie_1l_0_pereset */
+ PINCTRL_PIN_GROUP("pcie_1l_0_pereset", mt7988_pcie_1l_0_pereset),
+ /* @GPIO(75) pcie_wake_n1_0 */
+ PINCTRL_PIN_GROUP("pcie_wake_n1_0", mt7988_pcie_wake_n1_0),
+ /* @GPIO(76) pcie_clk_req_n1 */
+ PINCTRL_PIN_GROUP("pcie_clk_req_n1", mt7988_pcie_clk_req_n1),
+ /* @GPIO(77) pcie_wake_n2_0 */
+ PINCTRL_PIN_GROUP("pcie_wake_n2_0", mt7988_pcie_wake_n2_0),
+ /* @GPIO(78) pcie_clk_req_n2_0 */
+ PINCTRL_PIN_GROUP("pcie_clk_req_n2_0", mt7988_pcie_clk_req_n2_0),
+ /* @GPIO(79) drv_vbus */
+ PINCTRL_PIN_GROUP("drv_vbus", mt7988_drv_vbus),
+ /* @GPIO(79) pcie_wake_n2_1 */
+ PINCTRL_PIN_GROUP("pcie_wake_n2_1", mt7988_pcie_wake_n2_1),
+ /* @GPIO(80,81,82,83) uart1_2 */
+ PINCTRL_PIN_GROUP("uart1_2", mt7988_uart1_2),
+ /* @GPIO(80,81) uart1_2_lite */
+ PINCTRL_PIN_GROUP("uart1_2_lite", mt7988_uart1_2_lite),
+ /* @GPIO(80) pwm2 */
+ PINCTRL_PIN_GROUP("pwm2", mt7988_pwm2),
+ /* @GPIO(81) pwm3 */
+ PINCTRL_PIN_GROUP("pwm3", mt7988_pwm3),
+ /* @GPIO(82) pwm4 */
+ PINCTRL_PIN_GROUP("pwm4", mt7988_pwm4),
+ /* @GPIO(83) pwm5 */
+ PINCTRL_PIN_GROUP("pwm5", mt7988_pwm5),
+ /* @GPIO(80) net_wo0_uart_txd_0 */
+ PINCTRL_PIN_GROUP("net_wo0_uart_txd_0", mt7988_net_wo0_uart_txd_0),
+ /* @GPIO(81) net_wo1_uart_txd_0 */
+ PINCTRL_PIN_GROUP("net_wo1_uart_txd_0", mt7988_net_wo1_uart_txd_0),
+ /* @GPIO(82) net_wo2_uart_txd_0 */
+ PINCTRL_PIN_GROUP("net_wo2_uart_txd_0", mt7988_net_wo2_uart_txd_0),
+ /* @GPIO(80,81) tops_uart1_2 */
+ PINCTRL_PIN_GROUP("tops_uart1_2", mt7988_tops_uart1_2),
+ /* @GPIO(80) net_wo0_uart_txd_1 */
+ PINCTRL_PIN_GROUP("net_wo0_uart_txd_1", mt7988_net_wo0_uart_txd_1),
+ /* @GPIO(81) net_wo1_uart_txd_1 */
+ PINCTRL_PIN_GROUP("net_wo1_uart_txd_1", mt7988_net_wo1_uart_txd_1),
+ /* @GPIO(82) net_wo2_uart_txd_1 */
+ PINCTRL_PIN_GROUP("net_wo2_uart_txd_1", mt7988_net_wo2_uart_txd_1),
+};
+
+/* Joint those groups owning the same capability in user point of view which
+ * allows that people tend to use through the device tree.
+ */
+static const char * const mt7988_jtag_groups[] = {
+ "tops_jtag0_0", "wo0_jtag", "wo1_jtag",
+ "wo2_jtag", "jtag", "tops_jtag0_1",
+};
+static const char * const mt7988_int_usxgmii_groups[] = {
+ "int_usxgmii",
+};
+static const char * const mt7988_pwm_groups[] = {
+ "pwm0", "pwm1", "pwm2", "pwm2_0", "pwm3", "pwm3_0", "pwm4", "pwm4_0",
+ "pwm5", "pwm5_0", "pwm6", "pwm6_0", "pwm7", "pwm7_0",
+};
+static const char * const mt7988_dfd_groups[] = {
+ "dfd",
+};
+static const char * const mt7988_i2c_groups[] = {
+ "xfi_phy0_i2c0",
+ "xfi_phy1_i2c0",
+ "xfi_phy_pll_i2c0",
+ "xfi_phy_pll_i2c1",
+ "i2c0_0",
+ "i2c1_sfp",
+ "xfi_pextp_phy0_i2c",
+ "xfi_pextp_phy1_i2c",
+ "i2c0_1",
+ "u30_phy_i2c0",
+ "u32_phy_i2c0",
+ "xfi_phy0_i2c1",
+ "xfi_phy1_i2c1",
+ "xfi_phy_pll_i2c2",
+ "i2c1_0",
+ "u30_phy_i2c1",
+ "u32_phy_i2c1",
+ "xfi_phy_pll_i2c3",
+ "sgmii0_i2c",
+ "sgmii1_i2c",
+ "i2c1_2",
+ "i2c2_0",
+ "i2c2_1",
+};
+static const char * const mt7988_ethernet_groups[] = {
+ "mdc_mdio0",
+ "2p5g_ext_mdio",
+ "gbe_ext_mdio",
+ "mdc_mdio1",
+};
+static const char * const mt7988_pcie_groups[] = {
+ "pcie_wake_n0_0", "pcie_clk_req_n0_0", "pcie_wake_n3_0",
+ "pcie_clk_req_n3", "pcie_p0_phy_i2c", "pcie_p1_phy_i2c",
+ "pcie_p3_phy_i2c", "pcie_p2_phy_i2c", "ckm_phy_i2c",
+ "pcie_wake_n0_1", "pcie_wake_n3_1", "pcie_2l_0_pereset",
+ "pcie_1l_1_pereset", "pcie_clk_req_n2_1", "pcie_2l_1_pereset",
+ "pcie_1l_0_pereset", "pcie_wake_n1_0", "pcie_clk_req_n1",
+ "pcie_wake_n2_0", "pcie_clk_req_n2_0", "pcie_wake_n2_1",
+ "pcie_clk_req_n0_1"
+};
+static const char * const mt7988_pmic_groups[] = {
+ "pmic",
+};
+static const char * const mt7988_wdt_groups[] = {
+ "watchdog",
+};
+static const char * const mt7988_spi_groups[] = {
+ "spi0", "spi0_wp_hold", "spi1", "spi2", "spi2_wp_hold",
+};
+static const char * const mt7988_flash_groups[] = { "emmc_45", "sdcard", "snfi",
+ "emmc_51" };
+static const char * const mt7988_uart_groups[] = {
+ "uart2",
+ "tops_uart0_0",
+ "uart2_0",
+ "uart1_0",
+ "uart2_1",
+ "net_wo0_uart_txd_0",
+ "net_wo1_uart_txd_0",
+ "net_wo2_uart_txd_0",
+ "tops_uart1_0",
+ "ops_uart0_1",
+ "ops_uart1_1",
+ "uart0",
+ "tops_uart0_2",
+ "uart1_1",
+ "uart2_3",
+ "uart1_2",
+ "uart1_2_lite",
+ "tops_uart1_2",
+ "net_wo0_uart_txd_1",
+ "net_wo1_uart_txd_1",
+ "net_wo2_uart_txd_1",
+};
+static const char * const mt7988_udi_groups[] = {
+ "udi",
+};
+static const char * const mt7988_audio_groups[] = {
+ "i2s", "pcm",
+};
+static const char * const mt7988_led_groups[] = {
+ "gbe0_led1", "gbe1_led1", "gbe2_led1", "gbe3_led1", "2p5gbe_led1",
+ "gbe0_led0", "gbe1_led0", "gbe2_led0", "gbe3_led0", "2p5gbe_led0",
+ "wf5g_led0", "wf5g_led1",
+};
+static const char * const mt7988_usb_groups[] = {
+ "drv_vbus",
+ "drv_vbus_p1",
+};
+
+static const struct function_desc mt7988_functions[] = {
+ { "audio", mt7988_audio_groups, ARRAY_SIZE(mt7988_audio_groups) },
+ { "jtag", mt7988_jtag_groups, ARRAY_SIZE(mt7988_jtag_groups) },
+ { "int_usxgmii", mt7988_int_usxgmii_groups,
+ ARRAY_SIZE(mt7988_int_usxgmii_groups) },
+ { "pwm", mt7988_pwm_groups, ARRAY_SIZE(mt7988_pwm_groups) },
+ { "dfd", mt7988_dfd_groups, ARRAY_SIZE(mt7988_dfd_groups) },
+ { "i2c", mt7988_i2c_groups, ARRAY_SIZE(mt7988_i2c_groups) },
+ { "eth", mt7988_ethernet_groups, ARRAY_SIZE(mt7988_ethernet_groups) },
+ { "pcie", mt7988_pcie_groups, ARRAY_SIZE(mt7988_pcie_groups) },
+ { "pmic", mt7988_pmic_groups, ARRAY_SIZE(mt7988_pmic_groups) },
+ { "watchdog", mt7988_wdt_groups, ARRAY_SIZE(mt7988_wdt_groups) },
+ { "spi", mt7988_spi_groups, ARRAY_SIZE(mt7988_spi_groups) },
+ { "flash", mt7988_flash_groups, ARRAY_SIZE(mt7988_flash_groups) },
+ { "uart", mt7988_uart_groups, ARRAY_SIZE(mt7988_uart_groups) },
+ { "udi", mt7988_udi_groups, ARRAY_SIZE(mt7988_udi_groups) },
+ { "usb", mt7988_usb_groups, ARRAY_SIZE(mt7988_usb_groups) },
+ { "led", mt7988_led_groups, ARRAY_SIZE(mt7988_led_groups) },
+};
+
+static const struct mtk_eint_hw mt7988_eint_hw = {
+ .port_mask = 7,
+ .ports = 7,
+ .ap_num = ARRAY_SIZE(mt7988_pins),
+ .db_cnt = 16,
+};
+
+static const char * const mt7988_pinctrl_register_base_names[] = {
+ "gpio_base", "iocfg_tr_base", "iocfg_br_base",
+ "iocfg_rb_base", "iocfg_lb_base", "iocfg_tl_base",
+};
+
+static struct mtk_pin_soc mt7988_data = {
+ .reg_cal = mt7988_reg_cals,
+ .pins = mt7988_pins,
+ .npins = ARRAY_SIZE(mt7988_pins),
+ .grps = mt7988_groups,
+ .ngrps = ARRAY_SIZE(mt7988_groups),
+ .funcs = mt7988_functions,
+ .nfuncs = ARRAY_SIZE(mt7988_functions),
+ .eint_hw = &mt7988_eint_hw,
+ .gpio_m = 0,
+ .ies_present = false,
+ .base_names = mt7988_pinctrl_register_base_names,
+ .nbase_names = ARRAY_SIZE(mt7988_pinctrl_register_base_names),
+ .bias_disable_set = mtk_pinconf_bias_disable_set,
+ .bias_disable_get = mtk_pinconf_bias_disable_get,
+ .bias_set = mtk_pinconf_bias_set,
+ .bias_get = mtk_pinconf_bias_get,
+ .pull_type = mt7988_pull_type,
+ .bias_set_combo = mtk_pinconf_bias_set_combo,
+ .bias_get_combo = mtk_pinconf_bias_get_combo,
+ .drive_set = mtk_pinconf_drive_set_rev1,
+ .drive_get = mtk_pinconf_drive_get_rev1,
+ .adv_pull_get = mtk_pinconf_adv_pull_get,
+ .adv_pull_set = mtk_pinconf_adv_pull_set,
+};
+
+static const struct of_device_id mt7988_pinctrl_of_match[] = {
+ {
+ .compatible = "mediatek,mt7988-pinctrl",
+ },
+ {}
+};
+
+static int mt7988_pinctrl_probe(struct platform_device *pdev)
+{
+ return mtk_moore_pinctrl_probe(pdev, &mt7988_data);
+}
+
+static struct platform_driver mt7988_pinctrl_driver = {
+ .driver = {
+ .name = "mt7988-pinctrl",
+ .of_match_table = mt7988_pinctrl_of_match,
+ },
+ .probe = mt7988_pinctrl_probe,
+};
+
+static int __init mt7988_pinctrl_init(void)
+{
+ return platform_driver_register(&mt7988_pinctrl_driver);
+}
+arch_initcall(mt7988_pinctrl_init);
--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * MFD driver for Airoha AN8855 Switch
+ */
+#ifndef _LINUX_INCLUDE_MFD_AIROHA_AN8855_MFD_H
+#define _LINUX_INCLUDE_MFD_AIROHA_AN8855_MFD_H
+
+#include <linux/bitfield.h>
+
+/* MII Registers */
+#define AN8855_PHY_SELECT_PAGE 0x1f
+#define AN8855_PHY_PAGE GENMASK(2, 0)
+#define AN8855_PHY_PAGE_STANDARD FIELD_PREP_CONST(AN8855_PHY_PAGE, 0x0)
+#define AN8855_PHY_PAGE_EXTENDED_1 FIELD_PREP_CONST(AN8855_PHY_PAGE, 0x1)
+#define AN8855_PHY_PAGE_EXTENDED_4 FIELD_PREP_CONST(AN8855_PHY_PAGE, 0x4)
+
+/* MII Registers Page 4 */
+#define AN8855_PBUS_MODE 0x10
+#define AN8855_PBUS_MODE_ADDR_FIXED 0x0
+#define AN8855_PBUS_MODE_ADDR_INCR BIT(15)
+#define AN8855_PBUS_WR_ADDR_HIGH 0x11
+#define AN8855_PBUS_WR_ADDR_LOW 0x12
+#define AN8855_PBUS_WR_DATA_HIGH 0x13
+#define AN8855_PBUS_WR_DATA_LOW 0x14
+#define AN8855_PBUS_RD_ADDR_HIGH 0x15
+#define AN8855_PBUS_RD_ADDR_LOW 0x16
+#define AN8855_PBUS_RD_DATA_HIGH 0x17
+#define AN8855_PBUS_RD_DATA_LOW 0x18
+
+struct an8855_mfd_priv {
+ struct device *dev;
+ struct mii_bus *bus;
+
+ unsigned int switch_addr;
+ u16 current_page;
+};
+
+int an8855_mii_set_page(struct an8855_mfd_priv *priv, u8 phy_id,
+ u8 page);
+
+#endif
--- /dev/null
+CONFIG_64BIT=y
+# CONFIG_AHCI_MTK is not set
+CONFIG_AIROHA_EN8801SC_PHY=y
+CONFIG_AIR_AN8855_PHY=y
+CONFIG_ARCH_BINFMT_ELF_EXTRA_PHDRS=y
+CONFIG_ARCH_CORRECT_STACKTRACE_ON_KRETPROBE=y
+CONFIG_ARCH_DEFAULT_KEXEC_IMAGE_VERIFY_SIG=y
+CONFIG_ARCH_DMA_ADDR_T_64BIT=y
+CONFIG_ARCH_FORCE_MAX_ORDER=10
+CONFIG_ARCH_KEEP_MEMBLOCK=y
+CONFIG_ARCH_MEDIATEK=y
+CONFIG_ARCH_MHP_MEMMAP_ON_MEMORY_ENABLE=y
+CONFIG_ARCH_MMAP_RND_BITS=18
+CONFIG_ARCH_MMAP_RND_BITS_MAX=24
+CONFIG_ARCH_MMAP_RND_BITS_MIN=18
+CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MIN=11
+CONFIG_ARCH_PROC_KCORE_TEXT=y
+CONFIG_ARCH_SPARSEMEM_ENABLE=y
+CONFIG_ARCH_STACKWALK=y
+CONFIG_ARCH_SUSPEND_POSSIBLE=y
+CONFIG_ARCH_WANTS_NO_INSTR=y
+CONFIG_ARCH_WANTS_THP_SWAP=y
+CONFIG_ARM64=y
+CONFIG_ARM64_4K_PAGES=y
+CONFIG_ARM64_ERRATUM_843419=y
+CONFIG_ARM64_LD_HAS_FIX_ERRATUM_843419=y
+CONFIG_ARM64_PAGE_SHIFT=12
+CONFIG_ARM64_PA_BITS=48
+CONFIG_ARM64_PA_BITS_48=y
+CONFIG_ARM64_TAGGED_ADDR_ABI=y
+CONFIG_ARM64_VA_BITS=39
+CONFIG_ARM64_VA_BITS_39=y
+CONFIG_ARM_AMBA=y
+CONFIG_ARM_ARCH_TIMER=y
+CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y
+CONFIG_ARM_GIC=y
+CONFIG_ARM_GIC_V2M=y
+CONFIG_ARM_GIC_V3=y
+CONFIG_ARM_GIC_V3_ITS=y
+CONFIG_ARM_GIC_V3_ITS_PCI=y
+CONFIG_ARM_MEDIATEK_CPUFREQ=y
+CONFIG_ARM_PMU=y
+CONFIG_ARM_PMUV3=y
+CONFIG_ARM_PSCI_FW=y
+CONFIG_ATA=y
+CONFIG_AUDIT_ARCH_COMPAT_GENERIC=y
+CONFIG_BLK_DEV_LOOP=y
+CONFIG_BLK_DEV_SD=y
+CONFIG_BLK_MQ_PCI=y
+CONFIG_BLK_PM=y
+CONFIG_BLOCK_NOTIFIERS=y
+CONFIG_BSD_PROCESS_ACCT=y
+CONFIG_BSD_PROCESS_ACCT_V3=y
+CONFIG_BUFFER_HEAD=y
+CONFIG_BUILTIN_RETURN_ADDRESS_STRIPS_PAC=y
+CONFIG_CC_HAVE_SHADOW_CALL_STACK=y
+CONFIG_CC_HAVE_STACKPROTECTOR_SYSREG=y
+CONFIG_CLKSRC_MMIO=y
+CONFIG_CLONE_BACKWARDS=y
+CONFIG_CMDLINE_OVERRIDE=y
+CONFIG_COMMON_CLK=y
+CONFIG_COMMON_CLK_MEDIATEK=y
+# CONFIG_COMMON_CLK_MT2712 is not set
+# CONFIG_COMMON_CLK_MT6779 is not set
+# CONFIG_COMMON_CLK_MT6795 is not set
+# CONFIG_COMMON_CLK_MT6797 is not set
+# CONFIG_COMMON_CLK_MT7622 is not set
+CONFIG_COMMON_CLK_MT7981=y
+CONFIG_COMMON_CLK_MT7981_ETHSYS=y
+CONFIG_COMMON_CLK_MT7986=y
+CONFIG_COMMON_CLK_MT7986_ETHSYS=y
+CONFIG_COMMON_CLK_MT7988=y
+# CONFIG_COMMON_CLK_MT8173 is not set
+# CONFIG_COMMON_CLK_MT8183 is not set
+# CONFIG_COMMON_CLK_MT8186 is not set
+# CONFIG_COMMON_CLK_MT8195 is not set
+# CONFIG_COMMON_CLK_MT8365 is not set
+# CONFIG_COMMON_CLK_MT8516 is not set
+CONFIG_COMPACT_UNEVICTABLE_DEFAULT=1
+# CONFIG_COMPAT_32BIT_TIME is not set
+CONFIG_CONFIGFS_FS=y
+CONFIG_CONSOLE_LOGLEVEL_DEFAULT=15
+CONFIG_CONTEXT_TRACKING=y
+CONFIG_CONTEXT_TRACKING_IDLE=y
+CONFIG_CPU_FREQ=y
+# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set
+CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE=y
+CONFIG_CPU_FREQ_GOV_ATTR_SET=y
+CONFIG_CPU_FREQ_GOV_COMMON=y
+CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y
+CONFIG_CPU_FREQ_GOV_ONDEMAND=y
+CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
+CONFIG_CPU_FREQ_GOV_POWERSAVE=y
+CONFIG_CPU_FREQ_GOV_SCHEDUTIL=y
+CONFIG_CPU_FREQ_GOV_USERSPACE=y
+CONFIG_CPU_FREQ_STAT=y
+CONFIG_CPU_LITTLE_ENDIAN=y
+CONFIG_CPU_MITIGATIONS=y
+CONFIG_CPU_RMAP=y
+CONFIG_CPU_THERMAL=y
+CONFIG_CRC16=y
+CONFIG_CRC_CCITT=y
+CONFIG_CRYPTO_AES_ARM64=y
+CONFIG_CRYPTO_AES_ARM64_CE=y
+CONFIG_CRYPTO_AES_ARM64_CE_BLK=y
+CONFIG_CRYPTO_AES_ARM64_CE_CCM=y
+CONFIG_CRYPTO_CMAC=y
+CONFIG_CRYPTO_CRC32=y
+CONFIG_CRYPTO_CRC32C=y
+CONFIG_CRYPTO_CRYPTD=y
+CONFIG_CRYPTO_DEFLATE=y
+CONFIG_CRYPTO_DRBG=y
+CONFIG_CRYPTO_DRBG_HMAC=y
+CONFIG_CRYPTO_DRBG_MENU=y
+CONFIG_CRYPTO_ECB=y
+CONFIG_CRYPTO_ECC=y
+CONFIG_CRYPTO_ECDH=y
+CONFIG_CRYPTO_GHASH_ARM64_CE=y
+CONFIG_CRYPTO_HASH_INFO=y
+CONFIG_CRYPTO_HMAC=y
+CONFIG_CRYPTO_JITTERENTROPY=y
+CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y
+CONFIG_CRYPTO_LIB_GF128MUL=y
+CONFIG_CRYPTO_LIB_SHA1=y
+CONFIG_CRYPTO_LIB_SHA256=y
+CONFIG_CRYPTO_LIB_UTILS=y
+CONFIG_CRYPTO_LZO=y
+CONFIG_CRYPTO_RNG=y
+CONFIG_CRYPTO_RNG2=y
+CONFIG_CRYPTO_RNG_DEFAULT=y
+CONFIG_CRYPTO_SHA256=y
+CONFIG_CRYPTO_SHA256_ARM64=y
+CONFIG_CRYPTO_SHA2_ARM64_CE=y
+CONFIG_CRYPTO_SHA3=y
+CONFIG_CRYPTO_SHA512=y
+CONFIG_CRYPTO_SM4=y
+CONFIG_CRYPTO_SM4_ARM64_CE_BLK=y
+CONFIG_CRYPTO_SM4_ARM64_CE_CCM=y
+CONFIG_CRYPTO_SM4_ARM64_CE_GCM=y
+CONFIG_CRYPTO_ZSTD=y
+CONFIG_DCACHE_WORD_ACCESS=y
+CONFIG_DEBUG_INFO=y
+CONFIG_DEBUG_MISC=y
+CONFIG_DIMLIB=y
+CONFIG_DMADEVICES=y
+CONFIG_DMATEST=y
+CONFIG_DMA_BOUNCE_UNALIGNED_KMALLOC=y
+CONFIG_DMA_DIRECT_REMAP=y
+CONFIG_DMA_ENGINE=y
+CONFIG_DMA_ENGINE_RAID=y
+CONFIG_DMA_OF=y
+CONFIG_DMA_VIRTUAL_CHANNELS=y
+CONFIG_DTC=y
+CONFIG_EDAC_SUPPORT=y
+CONFIG_EINT_MTK=y
+CONFIG_EXCLUSIVE_SYSTEM_RAM=y
+CONFIG_EXT4_FS=y
+CONFIG_F2FS_FS=y
+CONFIG_FIXED_PHY=y
+CONFIG_FIX_EARLYCON_MEM=y
+CONFIG_FRAME_POINTER=y
+CONFIG_FS_IOMAP=y
+CONFIG_FS_MBCACHE=y
+CONFIG_FUNCTION_ALIGNMENT=4
+CONFIG_FUNCTION_ALIGNMENT_4B=y
+CONFIG_FWNODE_MDIO=y
+CONFIG_FW_LOADER_PAGED_BUF=y
+CONFIG_FW_LOADER_SYSFS=y
+CONFIG_GCC_SUPPORTS_DYNAMIC_FTRACE_WITH_ARGS=y
+CONFIG_GENERIC_ALLOCATOR=y
+CONFIG_GENERIC_ARCH_TOPOLOGY=y
+CONFIG_GENERIC_BUG=y
+CONFIG_GENERIC_BUG_RELATIVE_POINTERS=y
+CONFIG_GENERIC_CLOCKEVENTS=y
+CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y
+CONFIG_GENERIC_CPU_AUTOPROBE=y
+CONFIG_GENERIC_CPU_VULNERABILITIES=y
+CONFIG_GENERIC_CSUM=y
+CONFIG_GENERIC_EARLY_IOREMAP=y
+CONFIG_GENERIC_GETTIMEOFDAY=y
+CONFIG_GENERIC_IDLE_POLL_SETUP=y
+CONFIG_GENERIC_IOREMAP=y
+CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y
+CONFIG_GENERIC_IRQ_SHOW=y
+CONFIG_GENERIC_IRQ_SHOW_LEVEL=y
+CONFIG_GENERIC_LIB_DEVMEM_IS_ALLOWED=y
+CONFIG_GENERIC_MSI_IRQ=y
+CONFIG_GENERIC_PCI_IOMAP=y
+CONFIG_GENERIC_PHY=y
+CONFIG_GENERIC_PINCONF=y
+CONFIG_GENERIC_PINCTRL_GROUPS=y
+CONFIG_GENERIC_PINMUX_FUNCTIONS=y
+CONFIG_GENERIC_SCHED_CLOCK=y
+CONFIG_GENERIC_SMP_IDLE_THREAD=y
+CONFIG_GENERIC_STRNCPY_FROM_USER=y
+CONFIG_GENERIC_STRNLEN_USER=y
+CONFIG_GENERIC_TIME_VSYSCALL=y
+CONFIG_GLOB=y
+CONFIG_GPIO_CDEV=y
+CONFIG_GPIO_WATCHDOG=y
+CONFIG_GPIO_WATCHDOG_ARCH_INITCALL=y
+CONFIG_GRO_CELLS=y
+CONFIG_HARDIRQS_SW_RESEND=y
+CONFIG_HAS_DMA=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT=y
+CONFIG_HAS_IOPORT_MAP=y
+CONFIG_HWMON=y
+CONFIG_HW_RANDOM=y
+CONFIG_HW_RANDOM_MTK=y
+CONFIG_I2C=y
+CONFIG_I2C_BOARDINFO=y
+CONFIG_I2C_CHARDEV=y
+CONFIG_I2C_MT65XX=y
+CONFIG_ICPLUS_PHY=y
+CONFIG_ILLEGAL_POINTER_VALUE=0xdead000000000000
+CONFIG_INITRAMFS_SOURCE=""
+CONFIG_IRQCHIP=y
+CONFIG_IRQ_DOMAIN=y
+CONFIG_IRQ_DOMAIN_HIERARCHY=y
+CONFIG_IRQ_FORCED_THREADING=y
+CONFIG_IRQ_TIME_ACCOUNTING=y
+CONFIG_IRQ_WORK=y
+CONFIG_JBD2=y
+CONFIG_JUMP_LABEL=y
+CONFIG_LEDS_PWM=y
+CONFIG_LEDS_SMARTRG_LED=y
+CONFIG_LEDS_TRIGGER_PATTERN=y
+CONFIG_LIBFDT=y
+CONFIG_LOCK_DEBUGGING_SUPPORT=y
+CONFIG_LOCK_SPIN_ON_OWNER=y
+CONFIG_LZO_COMPRESS=y
+CONFIG_LZO_DECOMPRESS=y
+CONFIG_MAGIC_SYSRQ=y
+CONFIG_MAXLINEAR_GPHY=y
+CONFIG_MDIO_AN8855=y
+CONFIG_MDIO_BUS=y
+CONFIG_MDIO_DEVICE=y
+CONFIG_MDIO_DEVRES=y
+CONFIG_MEDIATEK_2P5GE_PHY=y
+CONFIG_MEDIATEK_GE_PHY=y
+CONFIG_MEDIATEK_GE_SOC_PHY=y
+CONFIG_MEDIATEK_WATCHDOG=y
+CONFIG_MESSAGE_LOGLEVEL_DEFAULT=7
+CONFIG_MFD_AIROHA_AN8855=y
+CONFIG_MFD_CORE=y
+CONFIG_MFD_SYSCON=y
+CONFIG_MIGRATION=y
+CONFIG_MMC=y
+CONFIG_MMC_BLOCK=y
+CONFIG_MMC_CQHCI=y
+CONFIG_MMC_MTK=y
+CONFIG_MMU_LAZY_TLB_REFCOUNT=y
+CONFIG_MODULES_TREE_LOOKUP=y
+CONFIG_MODULES_USE_ELF_RELA=y
+CONFIG_MTD_NAND_CORE=y
+CONFIG_MTD_NAND_ECC=y
+CONFIG_MTD_NAND_ECC_MEDIATEK=y
+CONFIG_MTD_NAND_ECC_SW_HAMMING=y
+CONFIG_MTD_NAND_MTK=y
+CONFIG_MTD_NAND_MTK_BMT=y
+CONFIG_MTD_PARSER_TRX=y
+CONFIG_MTD_RAW_NAND=y
+CONFIG_MTD_SPI_NAND=y
+CONFIG_MTD_SPI_NOR=y
+CONFIG_MTD_SPLIT_FIRMWARE=y
+CONFIG_MTD_SPLIT_FIT_FW=y
+CONFIG_MTD_UBI=y
+CONFIG_MTD_UBI_BEB_LIMIT=20
+CONFIG_MTD_UBI_BLOCK=y
+CONFIG_MTD_UBI_FASTMAP=y
+CONFIG_MTD_UBI_NVMEM=y
+CONFIG_MTD_UBI_WL_THRESHOLD=4096
+CONFIG_MTD_VIRT_CONCAT=y
+# CONFIG_MTK_CMDQ is not set
+CONFIG_MTK_CPUX_TIMER=y
+# CONFIG_MTK_CQDMA is not set
+CONFIG_MTK_HSDMA=y
+CONFIG_MTK_INFRACFG=y
+CONFIG_MTK_LVTS_THERMAL=y
+CONFIG_MTK_LVTS_THERMAL_DEBUGFS=y
+CONFIG_MTK_NET_PHYLIB=y
+CONFIG_MTK_PMIC_WRAP=y
+CONFIG_MTK_REGULATOR_COUPLER=y
+CONFIG_MTK_SCPSYS=y
+CONFIG_MTK_SCPSYS_PM_DOMAINS=y
+CONFIG_MTK_SOC_THERMAL=y
+# CONFIG_MTK_SVS is not set
+CONFIG_MTK_THERMAL=y
+CONFIG_MTK_TIMER=y
+# CONFIG_MTK_UART_APDMA is not set
+CONFIG_MUTEX_SPIN_ON_OWNER=y
+CONFIG_NEED_DMA_MAP_STATE=y
+CONFIG_NEED_SG_DMA_LENGTH=y
+CONFIG_NET_DEVLINK=y
+CONFIG_NET_DSA=y
+CONFIG_NET_DSA_AN8855=y
+CONFIG_NET_DSA_MT7530=y
+CONFIG_NET_DSA_MT7530_MDIO=y
+CONFIG_NET_DSA_MT7530_MMIO=y
+CONFIG_NET_DSA_TAG_MTK=y
+CONFIG_NET_EGRESS=y
+CONFIG_NET_FLOW_LIMIT=y
+CONFIG_NET_INGRESS=y
+CONFIG_NET_MEDIATEK_SOC=y
+CONFIG_NET_MEDIATEK_SOC_WED=y
+CONFIG_NET_SELFTESTS=y
+CONFIG_NET_VENDOR_MEDIATEK=y
+CONFIG_NET_XGRESS=y
+CONFIG_NLS=y
+CONFIG_NO_HZ_COMMON=y
+CONFIG_NO_HZ_IDLE=y
+CONFIG_NR_CPUS=4
+CONFIG_NVMEM=y
+CONFIG_NVMEM_AN8855_EFUSE=y
+CONFIG_NVMEM_BLOCK=y
+CONFIG_NVMEM_LAYOUTS=y
+CONFIG_NVMEM_LAYOUT_ADTRAN=y
+CONFIG_NVMEM_MTK_EFUSE=y
+CONFIG_NVMEM_SYSFS=y
+CONFIG_OF=y
+CONFIG_OF_ADDRESS=y
+CONFIG_OF_DYNAMIC=y
+CONFIG_OF_EARLY_FLATTREE=y
+CONFIG_OF_FLATTREE=y
+CONFIG_OF_GPIO=y
+CONFIG_OF_IRQ=y
+CONFIG_OF_KOBJ=y
+CONFIG_OF_MDIO=y
+CONFIG_OF_OVERLAY=y
+CONFIG_OF_RESOLVE=y
+CONFIG_PADATA=y
+CONFIG_PAGE_POOL=y
+CONFIG_PAGE_POOL_STATS=y
+CONFIG_PAGE_SIZE_LESS_THAN_256KB=y
+CONFIG_PAGE_SIZE_LESS_THAN_64KB=y
+CONFIG_PARTITION_PERCPU=y
+CONFIG_PCI=y
+CONFIG_PCIEAER=y
+CONFIG_PCIEASPM=y
+# CONFIG_PCIEASPM_DEFAULT is not set
+CONFIG_PCIEASPM_PERFORMANCE=y
+# CONFIG_PCIEASPM_POWERSAVE is not set
+# CONFIG_PCIEASPM_POWER_SUPERSAVE is not set
+CONFIG_PCIEPORTBUS=y
+# CONFIG_PCIE_MEDIATEK is not set
+CONFIG_PCIE_MEDIATEK_GEN3=y
+CONFIG_PCIE_PME=y
+CONFIG_PCI_DEBUG=y
+CONFIG_PCI_DOMAINS=y
+CONFIG_PCI_DOMAINS_GENERIC=y
+CONFIG_PCI_MSI=y
+CONFIG_PCS_MTK_LYNXI=y
+CONFIG_PCS_MTK_USXGMII=y
+CONFIG_PERF_EVENTS=y
+CONFIG_PER_VMA_LOCK=y
+CONFIG_PGTABLE_LEVELS=3
+CONFIG_PHYLIB=y
+CONFIG_PHYLIB_LEDS=y
+CONFIG_PHYLINK=y
+CONFIG_PHYS_ADDR_T_64BIT=y
+# CONFIG_PHY_MTK_DP is not set
+# CONFIG_PHY_MTK_PCIE is not set
+CONFIG_PHY_MTK_TPHY=y
+# CONFIG_PHY_MTK_UFS is not set
+CONFIG_PHY_MTK_XFI_TPHY=y
+CONFIG_PHY_MTK_XSPHY=y
+CONFIG_PINCTRL=y
+# CONFIG_PINCTRL_MT2712 is not set
+# CONFIG_PINCTRL_MT6765 is not set
+# CONFIG_PINCTRL_MT6795 is not set
+# CONFIG_PINCTRL_MT6797 is not set
+# CONFIG_PINCTRL_MT7622 is not set
+CONFIG_PINCTRL_MT7981=y
+CONFIG_PINCTRL_MT7986=y
+CONFIG_PINCTRL_MT7988=y
+# CONFIG_PINCTRL_MT8173 is not set
+# CONFIG_PINCTRL_MT8183 is not set
+# CONFIG_PINCTRL_MT8186 is not set
+# CONFIG_PINCTRL_MT8188 is not set
+# CONFIG_PINCTRL_MT8516 is not set
+CONFIG_PINCTRL_MTK_MOORE=y
+CONFIG_PINCTRL_MTK_V2=y
+# CONFIG_PINCTRL_SINGLE is not set
+CONFIG_PM=y
+CONFIG_PM_CLK=y
+CONFIG_PM_GENERIC_DOMAINS=y
+CONFIG_PM_GENERIC_DOMAINS_OF=y
+CONFIG_PM_OPP=y
+CONFIG_POLYNOMIAL=y
+CONFIG_POSIX_CPU_TIMERS_TASK_WORK=y
+CONFIG_POWER_RESET=y
+CONFIG_POWER_RESET_SYSCON=y
+CONFIG_POWER_SUPPLY=y
+CONFIG_PREEMPT_NONE_BUILD=y
+CONFIG_PRINTK_TIME=y
+CONFIG_PSTORE=y
+CONFIG_PSTORE_COMPRESS=y
+CONFIG_PSTORE_CONSOLE=y
+CONFIG_PSTORE_PMSG=y
+CONFIG_PSTORE_RAM=y
+CONFIG_PTP_1588_CLOCK_OPTIONAL=y
+CONFIG_PWM=y
+CONFIG_PWM_MEDIATEK=y
+# CONFIG_PWM_MTK_DISP is not set
+CONFIG_PWM_SYSFS=y
+CONFIG_QUEUED_RWLOCKS=y
+CONFIG_QUEUED_SPINLOCKS=y
+CONFIG_RANDSTRUCT_NONE=y
+CONFIG_RAS=y
+CONFIG_RATIONAL=y
+# CONFIG_RAVE_SP_CORE is not set
+CONFIG_REALTEK_PHY=y
+CONFIG_REALTEK_PHY_HWMON=y
+CONFIG_REED_SOLOMON=y
+CONFIG_REED_SOLOMON_DEC8=y
+CONFIG_REED_SOLOMON_ENC8=y
+CONFIG_REGMAP=y
+CONFIG_REGMAP_I2C=y
+CONFIG_REGMAP_MMIO=y
+CONFIG_REGULATOR=y
+CONFIG_REGULATOR_FIXED_VOLTAGE=y
+CONFIG_REGULATOR_MT6380=y
+CONFIG_REGULATOR_RT5190A=y
+CONFIG_RESET_CONTROLLER=y
+CONFIG_RESET_TI_SYSCON=y
+CONFIG_RFS_ACCEL=y
+CONFIG_RODATA_FULL_DEFAULT_ENABLED=y
+CONFIG_RPS=y
+CONFIG_RTC_CLASS=y
+CONFIG_RTC_DRV_MT7622=y
+CONFIG_RTC_I2C_AND_SPI=y
+CONFIG_RTL8261N_PHY=y
+# CONFIG_RTL8367S_GSW is not set
+CONFIG_RWSEM_SPIN_ON_OWNER=y
+CONFIG_SCHED_MC=y
+CONFIG_SCSI=y
+CONFIG_SCSI_COMMON=y
+# CONFIG_SECTION_MISMATCH_WARN_ONLY is not set
+CONFIG_SERIAL_8250_FSL=y
+CONFIG_SERIAL_8250_MT6577=y
+CONFIG_SERIAL_8250_NR_UARTS=3
+CONFIG_SERIAL_8250_RUNTIME_UARTS=3
+CONFIG_SERIAL_DEV_BUS=y
+CONFIG_SERIAL_DEV_CTRL_TTYPORT=y
+CONFIG_SERIAL_MCTRL_GPIO=y
+CONFIG_SERIAL_OF_PLATFORM=y
+CONFIG_SGL_ALLOC=y
+CONFIG_SG_POOL=y
+CONFIG_SMP=y
+CONFIG_SOCK_RX_QUEUE_MAPPING=y
+CONFIG_SOFTIRQ_ON_OWN_STACK=y
+CONFIG_SPARSEMEM=y
+CONFIG_SPARSEMEM_EXTREME=y
+CONFIG_SPARSEMEM_VMEMMAP=y
+CONFIG_SPARSEMEM_VMEMMAP_ENABLE=y
+CONFIG_SPARSE_IRQ=y
+CONFIG_SPI=y
+CONFIG_SPI_DYNAMIC=y
+CONFIG_SPI_MASTER=y
+CONFIG_SPI_MEM=y
+CONFIG_SPI_MT65XX=y
+# CONFIG_SPI_MTK_NOR is not set
+CONFIG_SPI_MTK_SNFI=y
+CONFIG_SQUASHFS_DECOMP_MULTI_PERCPU=y
+CONFIG_SWIOTLB=y
+CONFIG_SWPHY=y
+CONFIG_SYSCTL_EXCEPTION_TRACE=y
+CONFIG_THERMAL=y
+CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y
+CONFIG_THERMAL_EMERGENCY_POWEROFF_DELAY_MS=0
+CONFIG_THERMAL_GOV_BANG_BANG=y
+CONFIG_THERMAL_GOV_FAIR_SHARE=y
+CONFIG_THERMAL_GOV_STEP_WISE=y
+CONFIG_THERMAL_GOV_USER_SPACE=y
+CONFIG_THERMAL_HWMON=y
+CONFIG_THERMAL_OF=y
+CONFIG_THERMAL_WRITABLE_TRIPS=y
+CONFIG_THREAD_INFO_IN_TASK=y
+CONFIG_TICK_CPU_ACCOUNTING=y
+CONFIG_TIMER_OF=y
+CONFIG_TIMER_PROBE=y
+CONFIG_TRACE_IRQFLAGS_NMI_SUPPORT=y
+CONFIG_TREE_RCU=y
+CONFIG_TREE_SRCU=y
+CONFIG_UBIFS_FS=y
+# CONFIG_UCLAMP_TASK is not set
+CONFIG_UIMAGE_FIT_BLK=y
+# CONFIG_UNMAP_KERNEL_AT_EL0 is not set
+CONFIG_USB_SUPPORT=y
+CONFIG_VMAP_STACK=y
+CONFIG_WATCHDOG_CORE=y
+CONFIG_WATCHDOG_PRETIMEOUT_DEFAULT_GOV_PANIC=y
+CONFIG_WATCHDOG_PRETIMEOUT_GOV=y
+# CONFIG_WATCHDOG_PRETIMEOUT_GOV_NOOP is not set
+CONFIG_WATCHDOG_PRETIMEOUT_GOV_PANIC=y
+CONFIG_WATCHDOG_PRETIMEOUT_GOV_SEL=m
+CONFIG_WATCHDOG_SYSFS=y
+CONFIG_XPS=y
+CONFIG_XXHASH=y
+CONFIG_ZLIB_DEFLATE=y
+CONFIG_ZLIB_INFLATE=y
+CONFIG_ZONE_DMA32=y
+CONFIG_ZSTD_COMMON=y
+CONFIG_ZSTD_COMPRESS=y
+CONFIG_ZSTD_DECOMPRESS=y
--- /dev/null
+CONFIG_64BIT=y
+# CONFIG_AHCI_MTK is not set
+# CONFIG_AIROHA_EN8801SC_PHY is not set
+# CONFIG_AIR_AN8855_PHY is not set
+CONFIG_AQUANTIA_PHY=y
+CONFIG_ARCH_BINFMT_ELF_EXTRA_PHDRS=y
+CONFIG_ARCH_CORRECT_STACKTRACE_ON_KRETPROBE=y
+CONFIG_ARCH_DEFAULT_KEXEC_IMAGE_VERIFY_SIG=y
+CONFIG_ARCH_DMA_ADDR_T_64BIT=y
+CONFIG_ARCH_FORCE_MAX_ORDER=10
+CONFIG_ARCH_KEEP_MEMBLOCK=y
+CONFIG_ARCH_MEDIATEK=y
+CONFIG_ARCH_MHP_MEMMAP_ON_MEMORY_ENABLE=y
+CONFIG_ARCH_MMAP_RND_BITS=18
+CONFIG_ARCH_MMAP_RND_BITS_MAX=24
+CONFIG_ARCH_MMAP_RND_BITS_MIN=18
+CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MIN=11
+CONFIG_ARCH_PROC_KCORE_TEXT=y
+CONFIG_ARCH_SPARSEMEM_ENABLE=y
+CONFIG_ARCH_STACKWALK=y
+CONFIG_ARCH_SUSPEND_POSSIBLE=y
+CONFIG_ARCH_WANTS_NO_INSTR=y
+CONFIG_ARCH_WANTS_THP_SWAP=y
+CONFIG_ARM64=y
+CONFIG_ARM64_4K_PAGES=y
+CONFIG_ARM64_ERRATUM_843419=y
+CONFIG_ARM64_LD_HAS_FIX_ERRATUM_843419=y
+CONFIG_ARM64_PAGE_SHIFT=12
+CONFIG_ARM64_PA_BITS=48
+CONFIG_ARM64_PA_BITS_48=y
+CONFIG_ARM64_TAGGED_ADDR_ABI=y
+CONFIG_ARM64_VA_BITS=39
+CONFIG_ARM64_VA_BITS_39=y
+CONFIG_ARM_AMBA=y
+CONFIG_ARM_ARCH_TIMER=y
+CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y
+CONFIG_ARM_GIC=y
+CONFIG_ARM_GIC_V2M=y
+CONFIG_ARM_GIC_V3=y
+CONFIG_ARM_GIC_V3_ITS=y
+CONFIG_ARM_GIC_V3_ITS_PCI=y
+CONFIG_ARM_MEDIATEK_CPUFREQ=y
+CONFIG_ARM_PMU=y
+CONFIG_ARM_PMUV3=y
+CONFIG_ARM_PSCI_FW=y
+CONFIG_ATA=y
+CONFIG_AUDIT_ARCH_COMPAT_GENERIC=y
+CONFIG_BLK_DEV_LOOP=y
+CONFIG_BLK_DEV_SD=y
+CONFIG_BLK_MQ_PCI=y
+CONFIG_BLK_PM=y
+CONFIG_BLOCK_NOTIFIERS=y
+CONFIG_BSD_PROCESS_ACCT=y
+CONFIG_BSD_PROCESS_ACCT_V3=y
+CONFIG_BUFFER_HEAD=y
+CONFIG_BUILTIN_RETURN_ADDRESS_STRIPS_PAC=y
+CONFIG_CC_HAVE_SHADOW_CALL_STACK=y
+CONFIG_CC_HAVE_STACKPROTECTOR_SYSREG=y
+CONFIG_CLKSRC_MMIO=y
+CONFIG_CLONE_BACKWARDS=y
+# CONFIG_CMDLINE_OVERRIDE is not set
+CONFIG_COMMON_CLK=y
+CONFIG_COMMON_CLK_MEDIATEK=y
+CONFIG_COMMON_CLK_MT2712=y
+# CONFIG_COMMON_CLK_MT2712_BDPSYS is not set
+# CONFIG_COMMON_CLK_MT2712_IMGSYS is not set
+# CONFIG_COMMON_CLK_MT2712_JPGDECSYS is not set
+# CONFIG_COMMON_CLK_MT2712_MFGCFG is not set
+# CONFIG_COMMON_CLK_MT2712_MMSYS is not set
+# CONFIG_COMMON_CLK_MT2712_VDECSYS is not set
+# CONFIG_COMMON_CLK_MT2712_VENCSYS is not set
+# CONFIG_COMMON_CLK_MT6779 is not set
+# CONFIG_COMMON_CLK_MT6795 is not set
+# CONFIG_COMMON_CLK_MT6797 is not set
+CONFIG_COMMON_CLK_MT7622=y
+CONFIG_COMMON_CLK_MT7622_AUDSYS=y
+CONFIG_COMMON_CLK_MT7622_ETHSYS=y
+CONFIG_COMMON_CLK_MT7622_HIFSYS=y
+# CONFIG_COMMON_CLK_MT7981 is not set
+# CONFIG_COMMON_CLK_MT7986 is not set
+# CONFIG_COMMON_CLK_MT7988 is not set
+# CONFIG_COMMON_CLK_MT8173 is not set
+# CONFIG_COMMON_CLK_MT8183 is not set
+# CONFIG_COMMON_CLK_MT8186 is not set
+# CONFIG_COMMON_CLK_MT8195 is not set
+# CONFIG_COMMON_CLK_MT8365 is not set
+# CONFIG_COMMON_CLK_MT8516 is not set
+CONFIG_COMPACT_UNEVICTABLE_DEFAULT=1
+CONFIG_COMPAT_32BIT_TIME=y
+CONFIG_CONFIGFS_FS=y
+CONFIG_CONSOLE_LOGLEVEL_DEFAULT=15
+CONFIG_CONTEXT_TRACKING=y
+CONFIG_CONTEXT_TRACKING_IDLE=y
+CONFIG_CPU_FREQ=y
+CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y
+# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set
+CONFIG_CPU_FREQ_GOV_ATTR_SET=y
+CONFIG_CPU_FREQ_GOV_COMMON=y
+CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y
+CONFIG_CPU_FREQ_GOV_ONDEMAND=y
+CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
+CONFIG_CPU_FREQ_GOV_POWERSAVE=y
+CONFIG_CPU_FREQ_GOV_SCHEDUTIL=y
+CONFIG_CPU_FREQ_GOV_USERSPACE=y
+CONFIG_CPU_FREQ_STAT=y
+CONFIG_CPU_LITTLE_ENDIAN=y
+CONFIG_CPU_MITIGATIONS=y
+CONFIG_CPU_RMAP=y
+CONFIG_CPU_THERMAL=y
+CONFIG_CRC16=y
+CONFIG_CRC_CCITT=y
+CONFIG_CRYPTO_AES_ARM64=y
+CONFIG_CRYPTO_AES_ARM64_CE=y
+CONFIG_CRYPTO_AES_ARM64_CE_BLK=y
+CONFIG_CRYPTO_AES_ARM64_CE_CCM=y
+CONFIG_CRYPTO_CMAC=y
+CONFIG_CRYPTO_CRC32=y
+CONFIG_CRYPTO_CRC32C=y
+CONFIG_CRYPTO_CRYPTD=y
+CONFIG_CRYPTO_DEFLATE=y
+CONFIG_CRYPTO_DRBG=y
+CONFIG_CRYPTO_DRBG_HMAC=y
+CONFIG_CRYPTO_DRBG_MENU=y
+CONFIG_CRYPTO_ECB=y
+CONFIG_CRYPTO_ECC=y
+CONFIG_CRYPTO_ECDH=y
+CONFIG_CRYPTO_GHASH_ARM64_CE=y
+CONFIG_CRYPTO_HASH_INFO=y
+CONFIG_CRYPTO_HMAC=y
+CONFIG_CRYPTO_JITTERENTROPY=y
+CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y
+CONFIG_CRYPTO_LIB_GF128MUL=y
+CONFIG_CRYPTO_LIB_SHA1=y
+CONFIG_CRYPTO_LIB_SHA256=y
+CONFIG_CRYPTO_LIB_UTILS=y
+CONFIG_CRYPTO_LZO=y
+CONFIG_CRYPTO_RNG=y
+CONFIG_CRYPTO_RNG2=y
+CONFIG_CRYPTO_RNG_DEFAULT=y
+CONFIG_CRYPTO_SHA256=y
+CONFIG_CRYPTO_SHA256_ARM64=y
+CONFIG_CRYPTO_SHA2_ARM64_CE=y
+CONFIG_CRYPTO_SHA3=y
+CONFIG_CRYPTO_SHA512=y
+CONFIG_CRYPTO_SM4=y
+CONFIG_CRYPTO_SM4_ARM64_CE_BLK=y
+CONFIG_CRYPTO_SM4_ARM64_CE_CCM=y
+CONFIG_CRYPTO_SM4_ARM64_CE_GCM=y
+CONFIG_CRYPTO_ZSTD=y
+CONFIG_DCACHE_WORD_ACCESS=y
+CONFIG_DEBUG_INFO=y
+CONFIG_DEBUG_MISC=y
+CONFIG_DIMLIB=y
+CONFIG_DMADEVICES=y
+CONFIG_DMA_BOUNCE_UNALIGNED_KMALLOC=y
+CONFIG_DMA_DIRECT_REMAP=y
+CONFIG_DMA_ENGINE=y
+CONFIG_DMA_OF=y
+CONFIG_DMA_VIRTUAL_CHANNELS=y
+CONFIG_DTC=y
+CONFIG_EDAC_SUPPORT=y
+CONFIG_EINT_MTK=y
+CONFIG_EXCLUSIVE_SYSTEM_RAM=y
+CONFIG_EXT4_FS=y
+CONFIG_F2FS_FS=y
+CONFIG_FIXED_PHY=y
+CONFIG_FIX_EARLYCON_MEM=y
+CONFIG_FRAME_POINTER=y
+CONFIG_FS_IOMAP=y
+CONFIG_FS_MBCACHE=y
+CONFIG_FUNCTION_ALIGNMENT=4
+CONFIG_FUNCTION_ALIGNMENT_4B=y
+CONFIG_FWNODE_MDIO=y
+CONFIG_FW_LOADER_PAGED_BUF=y
+CONFIG_FW_LOADER_SYSFS=y
+CONFIG_GCC_SUPPORTS_DYNAMIC_FTRACE_WITH_ARGS=y
+CONFIG_GENERIC_ALLOCATOR=y
+CONFIG_GENERIC_ARCH_TOPOLOGY=y
+CONFIG_GENERIC_BUG=y
+CONFIG_GENERIC_BUG_RELATIVE_POINTERS=y
+CONFIG_GENERIC_CLOCKEVENTS=y
+CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y
+CONFIG_GENERIC_CPU_AUTOPROBE=y
+CONFIG_GENERIC_CPU_VULNERABILITIES=y
+CONFIG_GENERIC_CSUM=y
+CONFIG_GENERIC_EARLY_IOREMAP=y
+CONFIG_GENERIC_GETTIMEOFDAY=y
+CONFIG_GENERIC_IDLE_POLL_SETUP=y
+CONFIG_GENERIC_IOREMAP=y
+CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y
+CONFIG_GENERIC_IRQ_SHOW=y
+CONFIG_GENERIC_IRQ_SHOW_LEVEL=y
+CONFIG_GENERIC_LIB_DEVMEM_IS_ALLOWED=y
+CONFIG_GENERIC_MSI_IRQ=y
+CONFIG_GENERIC_PCI_IOMAP=y
+CONFIG_GENERIC_PHY=y
+CONFIG_GENERIC_PINCONF=y
+CONFIG_GENERIC_PINCTRL_GROUPS=y
+CONFIG_GENERIC_PINMUX_FUNCTIONS=y
+CONFIG_GENERIC_SCHED_CLOCK=y
+CONFIG_GENERIC_SMP_IDLE_THREAD=y
+CONFIG_GENERIC_STRNCPY_FROM_USER=y
+CONFIG_GENERIC_STRNLEN_USER=y
+CONFIG_GENERIC_TIME_VSYSCALL=y
+CONFIG_GLOB=y
+CONFIG_GPIO_CDEV=y
+CONFIG_GRO_CELLS=y
+CONFIG_HARDIRQS_SW_RESEND=y
+CONFIG_HAS_DMA=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT=y
+CONFIG_HAS_IOPORT_MAP=y
+CONFIG_HWMON=y
+CONFIG_HW_RANDOM=y
+CONFIG_HW_RANDOM_MTK=y
+CONFIG_I2C=y
+CONFIG_I2C_BOARDINFO=y
+CONFIG_I2C_CHARDEV=y
+CONFIG_I2C_MT65XX=y
+CONFIG_ICPLUS_PHY=y
+CONFIG_ILLEGAL_POINTER_VALUE=0xdead000000000000
+CONFIG_INITRAMFS_SOURCE=""
+CONFIG_INTEL_XWAY_PHY=y
+CONFIG_IRQCHIP=y
+CONFIG_IRQ_DOMAIN=y
+CONFIG_IRQ_DOMAIN_HIERARCHY=y
+CONFIG_IRQ_FORCED_THREADING=y
+CONFIG_IRQ_TIME_ACCOUNTING=y
+CONFIG_IRQ_WORK=y
+CONFIG_JBD2=y
+CONFIG_JUMP_LABEL=y
+CONFIG_LEDS_SMARTRG_LED=y
+CONFIG_LIBFDT=y
+CONFIG_LOCK_DEBUGGING_SUPPORT=y
+CONFIG_LOCK_SPIN_ON_OWNER=y
+CONFIG_LZO_COMPRESS=y
+CONFIG_LZO_DECOMPRESS=y
+CONFIG_MAGIC_SYSRQ=y
+CONFIG_MAXLINEAR_GPHY=y
+CONFIG_MDIO_BUS=y
+CONFIG_MDIO_DEVICE=y
+CONFIG_MDIO_DEVRES=y
+# CONFIG_MEDIATEK_2P5GE_PHY is not set
+CONFIG_MEDIATEK_GE_PHY=y
+# CONFIG_MEDIATEK_GE_SOC_PHY is not set
+CONFIG_MEDIATEK_WATCHDOG=y
+CONFIG_MESSAGE_LOGLEVEL_DEFAULT=7
+# CONFIG_MFD_AIROHA_AN8855 is not set
+CONFIG_MFD_SYSCON=y
+CONFIG_MIGRATION=y
+# CONFIG_MITIGATE_SPECTRE_BRANCH_HISTORY is not set
+CONFIG_MMC=y
+CONFIG_MMC_BLOCK=y
+CONFIG_MMC_CQHCI=y
+CONFIG_MMC_MTK=y
+CONFIG_MMU_LAZY_TLB_REFCOUNT=y
+CONFIG_MODULES_TREE_LOOKUP=y
+CONFIG_MODULES_USE_ELF_RELA=y
+CONFIG_MTD_NAND_CORE=y
+CONFIG_MTD_NAND_ECC=y
+CONFIG_MTD_NAND_ECC_MEDIATEK=y
+CONFIG_MTD_NAND_ECC_SW_HAMMING=y
+CONFIG_MTD_NAND_MTK=y
+CONFIG_MTD_NAND_MTK_BMT=y
+CONFIG_MTD_PARSER_TRX=y
+CONFIG_MTD_RAW_NAND=y
+CONFIG_MTD_SPI_NAND=y
+CONFIG_MTD_SPI_NOR=y
+CONFIG_MTD_SPI_NOR_USE_VARIABLE_ERASE=y
+CONFIG_MTD_SPLIT_FIRMWARE=y
+CONFIG_MTD_SPLIT_FIT_FW=y
+CONFIG_MTD_UBI=y
+CONFIG_MTD_UBI_BEB_LIMIT=20
+CONFIG_MTD_UBI_BLOCK=y
+CONFIG_MTD_UBI_FASTMAP=y
+CONFIG_MTD_UBI_NVMEM=y
+CONFIG_MTD_UBI_WL_THRESHOLD=4096
+# CONFIG_MTK_CMDQ is not set
+CONFIG_MTK_CPUX_TIMER=y
+# CONFIG_MTK_CQDMA is not set
+CONFIG_MTK_HSDMA=y
+CONFIG_MTK_INFRACFG=y
+# CONFIG_MTK_LVTS_THERMAL is not set
+CONFIG_MTK_NET_PHYLIB=y
+CONFIG_MTK_PMIC_WRAP=y
+CONFIG_MTK_REGULATOR_COUPLER=y
+CONFIG_MTK_SCPSYS=y
+CONFIG_MTK_SCPSYS_PM_DOMAINS=y
+CONFIG_MTK_SOC_THERMAL=y
+# CONFIG_MTK_SVS is not set
+CONFIG_MTK_THERMAL=y
+CONFIG_MTK_TIMER=y
+# CONFIG_MTK_UART_APDMA is not set
+CONFIG_MUTEX_SPIN_ON_OWNER=y
+CONFIG_NEED_DMA_MAP_STATE=y
+CONFIG_NEED_SG_DMA_LENGTH=y
+CONFIG_NET_DEVLINK=y
+CONFIG_NET_DSA=y
+CONFIG_NET_DSA_MT7530=y
+CONFIG_NET_DSA_MT7530_MDIO=y
+# CONFIG_NET_DSA_MT7530_MMIO is not set
+CONFIG_NET_DSA_TAG_MTK=y
+CONFIG_NET_EGRESS=y
+CONFIG_NET_FLOW_LIMIT=y
+CONFIG_NET_INGRESS=y
+CONFIG_NET_MEDIATEK_SOC=y
+CONFIG_NET_MEDIATEK_SOC_WED=y
+CONFIG_NET_SELFTESTS=y
+CONFIG_NET_VENDOR_MEDIATEK=y
+CONFIG_NET_XGRESS=y
+CONFIG_NLS=y
+CONFIG_NO_HZ_COMMON=y
+CONFIG_NO_HZ_IDLE=y
+CONFIG_NR_CPUS=2
+CONFIG_NVMEM=y
+CONFIG_NVMEM_BLOCK=y
+CONFIG_NVMEM_LAYOUTS=y
+CONFIG_NVMEM_LAYOUT_ADTRAN=y
+CONFIG_NVMEM_MTK_EFUSE=y
+CONFIG_NVMEM_SYSFS=y
+CONFIG_OF=y
+CONFIG_OF_ADDRESS=y
+CONFIG_OF_DYNAMIC=y
+CONFIG_OF_EARLY_FLATTREE=y
+CONFIG_OF_FLATTREE=y
+CONFIG_OF_GPIO=y
+CONFIG_OF_IRQ=y
+CONFIG_OF_KOBJ=y
+CONFIG_OF_MDIO=y
+CONFIG_OF_OVERLAY=y
+CONFIG_OF_RESOLVE=y
+CONFIG_PADATA=y
+CONFIG_PAGE_POOL=y
+CONFIG_PAGE_POOL_STATS=y
+CONFIG_PAGE_SIZE_LESS_THAN_256KB=y
+CONFIG_PAGE_SIZE_LESS_THAN_64KB=y
+CONFIG_PARTITION_PERCPU=y
+CONFIG_PCI=y
+CONFIG_PCIEAER=y
+CONFIG_PCIEASPM=y
+# CONFIG_PCIEASPM_DEFAULT is not set
+CONFIG_PCIEASPM_PERFORMANCE=y
+# CONFIG_PCIEASPM_POWERSAVE is not set
+# CONFIG_PCIEASPM_POWER_SUPERSAVE is not set
+CONFIG_PCIEPORTBUS=y
+CONFIG_PCIE_MEDIATEK=y
+CONFIG_PCIE_PME=y
+CONFIG_PCI_DEBUG=y
+CONFIG_PCI_DOMAINS=y
+CONFIG_PCI_DOMAINS_GENERIC=y
+CONFIG_PCI_MSI=y
+CONFIG_PCS_MTK_LYNXI=y
+CONFIG_PERF_EVENTS=y
+CONFIG_PER_VMA_LOCK=y
+CONFIG_PGTABLE_LEVELS=3
+CONFIG_PHYLIB=y
+CONFIG_PHYLIB_LEDS=y
+CONFIG_PHYLINK=y
+CONFIG_PHYS_ADDR_T_64BIT=y
+# CONFIG_PHY_MTK_DP is not set
+# CONFIG_PHY_MTK_PCIE is not set
+CONFIG_PHY_MTK_TPHY=y
+# CONFIG_PHY_MTK_UFS is not set
+# CONFIG_PHY_MTK_XSPHY is not set
+CONFIG_PINCTRL=y
+# CONFIG_PINCTRL_MT2712 is not set
+# CONFIG_PINCTRL_MT6765 is not set
+# CONFIG_PINCTRL_MT6795 is not set
+# CONFIG_PINCTRL_MT6797 is not set
+CONFIG_PINCTRL_MT7622=y
+# CONFIG_PINCTRL_MT7981 is not set
+# CONFIG_PINCTRL_MT7986 is not set
+# CONFIG_PINCTRL_MT7988 is not set
+# CONFIG_PINCTRL_MT8173 is not set
+# CONFIG_PINCTRL_MT8183 is not set
+# CONFIG_PINCTRL_MT8186 is not set
+# CONFIG_PINCTRL_MT8188 is not set
+# CONFIG_PINCTRL_MT8516 is not set
+CONFIG_PINCTRL_MTK_MOORE=y
+CONFIG_PINCTRL_MTK_V2=y
+CONFIG_PM=y
+CONFIG_PM_CLK=y
+CONFIG_PM_GENERIC_DOMAINS=y
+CONFIG_PM_GENERIC_DOMAINS_OF=y
+CONFIG_PM_OPP=y
+CONFIG_POLYNOMIAL=y
+CONFIG_POSIX_CPU_TIMERS_TASK_WORK=y
+CONFIG_POWER_RESET=y
+CONFIG_POWER_RESET_SYSCON=y
+CONFIG_POWER_SUPPLY=y
+CONFIG_PREEMPT_NONE_BUILD=y
+CONFIG_PRINTK_TIME=y
+CONFIG_PSTORE=y
+CONFIG_PSTORE_COMPRESS=y
+CONFIG_PSTORE_CONSOLE=y
+CONFIG_PSTORE_PMSG=y
+CONFIG_PSTORE_RAM=y
+CONFIG_PTP_1588_CLOCK_OPTIONAL=y
+CONFIG_PWM=y
+CONFIG_PWM_MEDIATEK=y
+# CONFIG_PWM_MTK_DISP is not set
+CONFIG_PWM_SYSFS=y
+CONFIG_QUEUED_RWLOCKS=y
+CONFIG_QUEUED_SPINLOCKS=y
+CONFIG_RANDSTRUCT_NONE=y
+CONFIG_RAS=y
+CONFIG_RATIONAL=y
+# CONFIG_RAVE_SP_CORE is not set
+CONFIG_REALTEK_PHY=y
+CONFIG_REALTEK_PHY_HWMON=y
+CONFIG_REED_SOLOMON=y
+CONFIG_REED_SOLOMON_DEC8=y
+CONFIG_REED_SOLOMON_ENC8=y
+CONFIG_REGMAP=y
+CONFIG_REGMAP_MMIO=y
+CONFIG_REGULATOR=y
+CONFIG_REGULATOR_FIXED_VOLTAGE=y
+CONFIG_REGULATOR_MT6380=y
+CONFIG_RESET_CONTROLLER=y
+CONFIG_RFS_ACCEL=y
+CONFIG_RODATA_FULL_DEFAULT_ENABLED=y
+CONFIG_RPS=y
+CONFIG_RTC_CLASS=y
+CONFIG_RTC_DRV_MT7622=y
+CONFIG_RTC_I2C_AND_SPI=y
+CONFIG_RTL8367S_GSW=y
+CONFIG_RWSEM_SPIN_ON_OWNER=y
+CONFIG_SCHED_MC=y
+CONFIG_SCSI=y
+CONFIG_SCSI_COMMON=y
+# CONFIG_SECTION_MISMATCH_WARN_ONLY is not set
+CONFIG_SERIAL_8250_FSL=y
+CONFIG_SERIAL_8250_MT6577=y
+CONFIG_SERIAL_8250_NR_UARTS=3
+CONFIG_SERIAL_8250_RUNTIME_UARTS=3
+CONFIG_SERIAL_DEV_BUS=y
+CONFIG_SERIAL_DEV_CTRL_TTYPORT=y
+CONFIG_SERIAL_MCTRL_GPIO=y
+CONFIG_SERIAL_OF_PLATFORM=y
+CONFIG_SGL_ALLOC=y
+CONFIG_SG_POOL=y
+CONFIG_SMP=y
+CONFIG_SOCK_RX_QUEUE_MAPPING=y
+CONFIG_SOFTIRQ_ON_OWN_STACK=y
+CONFIG_SPARSEMEM=y
+CONFIG_SPARSEMEM_EXTREME=y
+CONFIG_SPARSEMEM_VMEMMAP=y
+CONFIG_SPARSEMEM_VMEMMAP_ENABLE=y
+CONFIG_SPARSE_IRQ=y
+CONFIG_SPI=y
+CONFIG_SPI_DYNAMIC=y
+CONFIG_SPI_MASTER=y
+CONFIG_SPI_MEM=y
+CONFIG_SPI_MT65XX=y
+CONFIG_SPI_MTK_NOR=y
+CONFIG_SPI_MTK_SNFI=y
+CONFIG_SQUASHFS_DECOMP_MULTI_PERCPU=y
+CONFIG_SWCONFIG=y
+CONFIG_SWIOTLB=y
+CONFIG_SWPHY=y
+CONFIG_SYSCTL_EXCEPTION_TRACE=y
+CONFIG_THERMAL=y
+CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y
+CONFIG_THERMAL_EMERGENCY_POWEROFF_DELAY_MS=0
+CONFIG_THERMAL_EMULATION=y
+CONFIG_THERMAL_GOV_BANG_BANG=y
+CONFIG_THERMAL_GOV_FAIR_SHARE=y
+CONFIG_THERMAL_GOV_STEP_WISE=y
+CONFIG_THERMAL_GOV_USER_SPACE=y
+CONFIG_THERMAL_HWMON=y
+CONFIG_THERMAL_OF=y
+CONFIG_THERMAL_WRITABLE_TRIPS=y
+CONFIG_THREAD_INFO_IN_TASK=y
+CONFIG_TICK_CPU_ACCOUNTING=y
+CONFIG_TIMER_OF=y
+CONFIG_TIMER_PROBE=y
+CONFIG_TRACE_IRQFLAGS_NMI_SUPPORT=y
+CONFIG_TREE_RCU=y
+CONFIG_TREE_SRCU=y
+CONFIG_UBIFS_FS=y
+# CONFIG_UCLAMP_TASK is not set
+CONFIG_UIMAGE_FIT_BLK=y
+# CONFIG_UNMAP_KERNEL_AT_EL0 is not set
+CONFIG_USB_SUPPORT=y
+CONFIG_VMAP_STACK=y
+CONFIG_WATCHDOG_CORE=y
+CONFIG_WATCHDOG_PRETIMEOUT_DEFAULT_GOV_PANIC=y
+CONFIG_WATCHDOG_PRETIMEOUT_GOV=y
+# CONFIG_WATCHDOG_PRETIMEOUT_GOV_NOOP is not set
+CONFIG_WATCHDOG_PRETIMEOUT_GOV_PANIC=y
+CONFIG_WATCHDOG_PRETIMEOUT_GOV_SEL=m
+CONFIG_WATCHDOG_SYSFS=y
+CONFIG_XPS=y
+CONFIG_XXHASH=y
+CONFIG_ZLIB_DEFLATE=y
+CONFIG_ZLIB_INFLATE=y
+CONFIG_ZONE_DMA32=y
+CONFIG_ZSTD_COMMON=y
+CONFIG_ZSTD_COMPRESS=y
+CONFIG_ZSTD_DECOMPRESS=y
--- /dev/null
+# CONFIG_AIO is not set
+# CONFIG_AIROHA_EN8801SC_PHY is not set
+# CONFIG_AIR_AN8855_PHY is not set
+CONFIG_ALIGNMENT_TRAP=y
+CONFIG_ARCH_32BIT_OFF_T=y
+CONFIG_ARCH_HIBERNATION_POSSIBLE=y
+CONFIG_ARCH_KEEP_MEMBLOCK=y
+CONFIG_ARCH_MEDIATEK=y
+CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y
+CONFIG_ARCH_MULTIPLATFORM=y
+CONFIG_ARCH_MULTI_V6_V7=y
+CONFIG_ARCH_MULTI_V7=y
+CONFIG_ARCH_OPTIONAL_KERNEL_RWX=y
+CONFIG_ARCH_OPTIONAL_KERNEL_RWX_DEFAULT=y
+CONFIG_ARCH_SELECT_MEMORY_MODEL=y
+CONFIG_ARCH_SPARSEMEM_ENABLE=y
+CONFIG_ARCH_STACKWALK=y
+CONFIG_ARCH_SUSPEND_POSSIBLE=y
+CONFIG_ARM=y
+CONFIG_ARM_APPENDED_DTB=y
+CONFIG_ARM_ARCH_TIMER=y
+CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y
+# CONFIG_ARM_ATAG_DTB_COMPAT is not set
+CONFIG_ARM_CPU_SUSPEND=y
+# CONFIG_ARM_CPU_TOPOLOGY is not set
+CONFIG_ARM_DMA_IOMMU_ALIGNMENT=8
+CONFIG_ARM_DMA_USE_IOMMU=y
+CONFIG_ARM_GIC=y
+CONFIG_ARM_HAS_GROUP_RELOCS=y
+CONFIG_ARM_L1_CACHE_SHIFT=6
+CONFIG_ARM_L1_CACHE_SHIFT_6=y
+# CONFIG_ARM_MEDIATEK_CCI_DEVFREQ is not set
+CONFIG_ARM_MEDIATEK_CPUFREQ=y
+CONFIG_ARM_PATCH_IDIV=y
+CONFIG_ARM_PATCH_PHYS_VIRT=y
+# CONFIG_ARM_SMMU is not set
+CONFIG_ARM_THUMB=y
+CONFIG_ARM_THUMBEE=y
+CONFIG_ARM_UNWIND=y
+CONFIG_ARM_VIRT_EXT=y
+CONFIG_ASYNC_TX_ENABLE_CHANNEL_SWITCH=y
+CONFIG_ATAGS=y
+CONFIG_AUTO_ZRELADDR=y
+CONFIG_BACKLIGHT_CLASS_DEVICE=y
+CONFIG_BACKLIGHT_GPIO=y
+CONFIG_BACKLIGHT_LED=y
+CONFIG_BACKLIGHT_PWM=y
+CONFIG_BINFMT_FLAT_ARGVP_ENVP_ON_STACK=y
+CONFIG_BLK_DEV_LOOP=y
+CONFIG_BLK_MQ_PCI=y
+CONFIG_BLK_PM=y
+CONFIG_BOUNCE=y
+CONFIG_BUFFER_HEAD=y
+# CONFIG_CACHE_L2X0 is not set
+CONFIG_CC_HAVE_STACKPROTECTOR_TLS=y
+CONFIG_CLKSRC_MMIO=y
+CONFIG_CLONE_BACKWARDS=y
+CONFIG_CMDLINE="earlyprintk console=ttyS0,115200 rootfstype=squashfs,jffs2"
+CONFIG_CMDLINE_FROM_BOOTLOADER=y
+# CONFIG_CMDLINE_OVERRIDE is not set
+CONFIG_CMDLINE_PARTITION=y
+CONFIG_COMMON_CLK=y
+CONFIG_COMMON_CLK_MEDIATEK=y
+CONFIG_COMMON_CLK_MT2701=y
+CONFIG_COMMON_CLK_MT2701_AUDSYS=y
+CONFIG_COMMON_CLK_MT2701_BDPSYS=y
+CONFIG_COMMON_CLK_MT2701_ETHSYS=y
+CONFIG_COMMON_CLK_MT2701_G3DSYS=y
+CONFIG_COMMON_CLK_MT2701_HIFSYS=y
+CONFIG_COMMON_CLK_MT2701_IMGSYS=y
+CONFIG_COMMON_CLK_MT2701_MMSYS=y
+CONFIG_COMMON_CLK_MT2701_VDECSYS=y
+# CONFIG_COMMON_CLK_MT6795 is not set
+# CONFIG_COMMON_CLK_MT7622 is not set
+# CONFIG_COMMON_CLK_MT7629 is not set
+# CONFIG_COMMON_CLK_MT7981 is not set
+# CONFIG_COMMON_CLK_MT7986 is not set
+# CONFIG_COMMON_CLK_MT7988 is not set
+# CONFIG_COMMON_CLK_MT8135 is not set
+# CONFIG_COMMON_CLK_MT8365 is not set
+# CONFIG_COMMON_CLK_MT8516 is not set
+CONFIG_COMPACT_UNEVICTABLE_DEFAULT=1
+CONFIG_COMPAT_32BIT_TIME=y
+CONFIG_CONFIGFS_FS=y
+CONFIG_CONSOLE_TRANSLATIONS=y
+CONFIG_CONTEXT_TRACKING=y
+CONFIG_CONTEXT_TRACKING_IDLE=y
+CONFIG_COREDUMP=y
+CONFIG_CPU_32v6K=y
+CONFIG_CPU_32v7=y
+CONFIG_CPU_ABRT_EV7=y
+CONFIG_CPU_CACHE_V7=y
+CONFIG_CPU_CACHE_VIPT=y
+CONFIG_CPU_COPY_V6=y
+CONFIG_CPU_CP15=y
+CONFIG_CPU_CP15_MMU=y
+CONFIG_CPU_FREQ=y
+CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE=y
+CONFIG_CPU_FREQ_GOV_ATTR_SET=y
+CONFIG_CPU_FREQ_GOV_COMMON=y
+CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y
+CONFIG_CPU_FREQ_GOV_ONDEMAND=y
+CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
+CONFIG_CPU_FREQ_GOV_POWERSAVE=y
+# CONFIG_CPU_FREQ_GOV_USERSPACE is not set
+CONFIG_CPU_FREQ_STAT=y
+CONFIG_CPU_HAS_ASID=y
+CONFIG_CPU_LITTLE_ENDIAN=y
+CONFIG_CPU_MITIGATIONS=y
+CONFIG_CPU_PABRT_V7=y
+CONFIG_CPU_PM=y
+CONFIG_CPU_RMAP=y
+CONFIG_CPU_SPECTRE=y
+CONFIG_CPU_THUMB_CAPABLE=y
+CONFIG_CPU_TLB_V7=y
+CONFIG_CPU_V7=y
+CONFIG_CRC16=y
+CONFIG_CROSS_MEMORY_ATTACH=y
+CONFIG_CRYPTO_CRC32=y
+CONFIG_CRYPTO_CRC32C=y
+CONFIG_CRYPTO_DEFLATE=y
+CONFIG_CRYPTO_DRBG=y
+CONFIG_CRYPTO_DRBG_HMAC=y
+CONFIG_CRYPTO_DRBG_MENU=y
+CONFIG_CRYPTO_GENIV=y
+CONFIG_CRYPTO_HASH_INFO=y
+CONFIG_CRYPTO_HMAC=y
+CONFIG_CRYPTO_HW=y
+CONFIG_CRYPTO_JITTERENTROPY=y
+CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y
+CONFIG_CRYPTO_LIB_GF128MUL=y
+CONFIG_CRYPTO_LIB_SHA1=y
+CONFIG_CRYPTO_LIB_SHA256=y
+CONFIG_CRYPTO_LIB_UTILS=y
+CONFIG_CRYPTO_LZO=y
+CONFIG_CRYPTO_RNG=y
+CONFIG_CRYPTO_RNG2=y
+CONFIG_CRYPTO_RNG_DEFAULT=y
+CONFIG_CRYPTO_SEQIV=y
+CONFIG_CRYPTO_SHA1=y
+CONFIG_CRYPTO_SHA256=y
+CONFIG_CRYPTO_SHA3=y
+CONFIG_CRYPTO_SHA512=y
+CONFIG_CRYPTO_ZSTD=y
+CONFIG_CURRENT_POINTER_IN_TPIDRURO=y
+CONFIG_DCACHE_WORD_ACCESS=y
+CONFIG_DEBUG_ALIGN_RODATA=y
+CONFIG_DEBUG_BUGVERBOSE=y
+CONFIG_DEBUG_GPIO=y
+CONFIG_DEBUG_INFO=y
+CONFIG_DEBUG_LL=y
+CONFIG_DEBUG_LL_INCLUDE="debug/8250.S"
+CONFIG_DEBUG_MISC=y
+CONFIG_DEBUG_MT6589_UART0=y
+# CONFIG_DEBUG_MT8127_UART0 is not set
+# CONFIG_DEBUG_MT8135_UART3 is not set
+CONFIG_DEBUG_PREEMPT=y
+CONFIG_DEBUG_UART_8250=y
+CONFIG_DEBUG_UART_8250_SHIFT=2
+CONFIG_DEBUG_UART_PHYS=0x11004000
+CONFIG_DEBUG_UART_VIRT=0xf1004000
+# CONFIG_DEVFREQ_GOV_PASSIVE is not set
+# CONFIG_DEVFREQ_GOV_PERFORMANCE is not set
+# CONFIG_DEVFREQ_GOV_POWERSAVE is not set
+CONFIG_DEVFREQ_GOV_SIMPLE_ONDEMAND=y
+# CONFIG_DEVFREQ_GOV_USERSPACE is not set
+# CONFIG_DEVFREQ_THERMAL is not set
+CONFIG_DIMLIB=y
+CONFIG_DMADEVICES=y
+CONFIG_DMA_ENGINE=y
+CONFIG_DMA_OF=y
+CONFIG_DMA_OPS=y
+CONFIG_DMA_SHARED_BUFFER=y
+CONFIG_DMA_VIRTUAL_CHANNELS=y
+CONFIG_DRM=y
+CONFIG_DRM_BRIDGE=y
+CONFIG_DRM_DISPLAY_CONNECTOR=y
+CONFIG_DRM_FBDEV_EMULATION=y
+CONFIG_DRM_FBDEV_OVERALLOC=100
+CONFIG_DRM_GEM_SHMEM_HELPER=y
+CONFIG_DRM_KMS_HELPER=y
+CONFIG_DRM_LIMA=y
+CONFIG_DRM_LVDS_CODEC=y
+CONFIG_DRM_MEDIATEK=y
+# CONFIG_DRM_MEDIATEK_DP is not set
+CONFIG_DRM_MEDIATEK_HDMI=y
+CONFIG_DRM_MIPI_DSI=y
+CONFIG_DRM_PANEL=y
+CONFIG_DRM_PANEL_BRIDGE=y
+CONFIG_DRM_PANEL_ORIENTATION_QUIRKS=y
+CONFIG_DRM_PANEL_RASPBERRYPI_TOUCHSCREEN=y
+CONFIG_DRM_SCHED=y
+CONFIG_DRM_SIMPLE_BRIDGE=y
+CONFIG_DTC=y
+CONFIG_DUMMY_CONSOLE=y
+CONFIG_EARLY_PRINTK=y
+CONFIG_EDAC_ATOMIC_SCRUB=y
+CONFIG_EDAC_SUPPORT=y
+CONFIG_EINT_MTK=y
+CONFIG_ELF_CORE=y
+CONFIG_EXCLUSIVE_SYSTEM_RAM=y
+CONFIG_EXT4_FS=y
+CONFIG_EXTCON=y
+CONFIG_F2FS_FS=y
+CONFIG_FB=y
+CONFIG_FB_CORE=y
+CONFIG_FB_DEFERRED_IO=y
+CONFIG_FB_DEVICE=y
+CONFIG_FB_IOMEM_FOPS=y
+CONFIG_FB_SYSMEM_HELPERS=y
+CONFIG_FB_SYSMEM_HELPERS_DEFERRED=y
+CONFIG_FB_SYS_COPYAREA=y
+CONFIG_FB_SYS_FILLRECT=y
+CONFIG_FB_SYS_FOPS=y
+CONFIG_FB_SYS_IMAGEBLIT=y
+CONFIG_FIXED_PHY=y
+CONFIG_FIX_EARLYCON_MEM=y
+CONFIG_FONT_8x16=y
+CONFIG_FONT_8x8=y
+CONFIG_FONT_SUPPORT=y
+CONFIG_FRAMEBUFFER_CONSOLE=y
+CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y
+CONFIG_FRAMEBUFFER_CONSOLE_ROTATION=y
+CONFIG_FREEZER=y
+CONFIG_FS_IOMAP=y
+CONFIG_FS_MBCACHE=y
+CONFIG_FUNCTION_ALIGNMENT=0
+CONFIG_FWNODE_MDIO=y
+CONFIG_FW_CACHE=y
+CONFIG_FW_LOADER_PAGED_BUF=y
+CONFIG_FW_LOADER_SYSFS=y
+CONFIG_GENERIC_ALLOCATOR=y
+CONFIG_GENERIC_BUG=y
+CONFIG_GENERIC_CLOCKEVENTS=y
+CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y
+CONFIG_GENERIC_CPU_AUTOPROBE=y
+CONFIG_GENERIC_CPU_VULNERABILITIES=y
+CONFIG_GENERIC_EARLY_IOREMAP=y
+CONFIG_GENERIC_GETTIMEOFDAY=y
+CONFIG_GENERIC_IDLE_POLL_SETUP=y
+CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y
+CONFIG_GENERIC_IRQ_MIGRATION=y
+CONFIG_GENERIC_IRQ_MULTI_HANDLER=y
+CONFIG_GENERIC_IRQ_SHOW=y
+CONFIG_GENERIC_IRQ_SHOW_LEVEL=y
+CONFIG_GENERIC_LIB_DEVMEM_IS_ALLOWED=y
+CONFIG_GENERIC_MSI_IRQ=y
+CONFIG_GENERIC_PCI_IOMAP=y
+CONFIG_GENERIC_PHY=y
+CONFIG_GENERIC_PINCONF=y
+CONFIG_GENERIC_PINCTRL_GROUPS=y
+CONFIG_GENERIC_PINMUX_FUNCTIONS=y
+CONFIG_GENERIC_SCHED_CLOCK=y
+CONFIG_GENERIC_SMP_IDLE_THREAD=y
+CONFIG_GENERIC_STRNCPY_FROM_USER=y
+CONFIG_GENERIC_STRNLEN_USER=y
+CONFIG_GENERIC_TIME_VSYSCALL=y
+CONFIG_GENERIC_VDSO_32=y
+CONFIG_GPIO_CDEV=y
+CONFIG_GRO_CELLS=y
+# CONFIG_HARDEN_BRANCH_HISTORY is not set
+# CONFIG_HARDEN_BRANCH_PREDICTOR is not set
+CONFIG_HARDIRQS_SW_RESEND=y
+CONFIG_HAS_DMA=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT=y
+CONFIG_HAS_IOPORT_MAP=y
+CONFIG_HAVE_SMP=y
+CONFIG_HDMI=y
+CONFIG_HID=y
+CONFIG_HID_SUPPORT=y
+CONFIG_HIGHMEM=y
+CONFIG_HIGHPTE=y
+CONFIG_HOTPLUG_CORE_SYNC=y
+CONFIG_HOTPLUG_CORE_SYNC_DEAD=y
+CONFIG_HOTPLUG_CPU=y
+CONFIG_HWMON=y
+CONFIG_HW_CONSOLE=y
+CONFIG_HW_RANDOM=y
+CONFIG_HW_RANDOM_MTK=y
+CONFIG_HZ_FIXED=0
+CONFIG_I2C=y
+CONFIG_I2C_ALGOBIT=y
+CONFIG_I2C_BOARDINFO=y
+CONFIG_I2C_CHARDEV=y
+CONFIG_I2C_MT65XX=y
+CONFIG_ICPLUS_PHY=y
+CONFIG_IIO=y
+CONFIG_INITRAMFS_SOURCE=""
+CONFIG_INPUT=y
+CONFIG_INPUT_EVDEV=y
+CONFIG_INPUT_KEYBOARD=y
+CONFIG_INPUT_TOUCHSCREEN=y
+# CONFIG_IOMMUFD is not set
+CONFIG_IOMMU_API=y
+# CONFIG_IOMMU_DEBUGFS is not set
+# CONFIG_IOMMU_DEFAULT_DMA_LAZY is not set
+CONFIG_IOMMU_DEFAULT_DMA_STRICT=y
+# CONFIG_IOMMU_DEFAULT_PASSTHROUGH is not set
+CONFIG_IOMMU_IO_PGTABLE=y
+CONFIG_IOMMU_IO_PGTABLE_ARMV7S=y
+# CONFIG_IOMMU_IO_PGTABLE_ARMV7S_SELFTEST is not set
+# CONFIG_IOMMU_IO_PGTABLE_LPAE is not set
+CONFIG_IOMMU_SUPPORT=y
+CONFIG_IRQCHIP=y
+CONFIG_IRQSTACKS=y
+CONFIG_IRQ_DOMAIN=y
+CONFIG_IRQ_DOMAIN_HIERARCHY=y
+CONFIG_IRQ_FORCED_THREADING=y
+CONFIG_IRQ_WORK=y
+CONFIG_JBD2=y
+CONFIG_KALLSYMS=y
+CONFIG_KCMP=y
+CONFIG_KEYBOARD_MTK_PMIC=y
+CONFIG_KMAP_LOCAL=y
+CONFIG_KMAP_LOCAL_NON_LINEAR_PTE_ARRAY=y
+CONFIG_LCD_CLASS_DEVICE=y
+CONFIG_LCD_PLATFORM=y
+CONFIG_LEDS_MT6323=y
+# CONFIG_LEDS_QCOM_LPG is not set
+# CONFIG_LEDS_SMARTRG_LED is not set
+CONFIG_LIBFDT=y
+CONFIG_LOCK_DEBUGGING_SUPPORT=y
+CONFIG_LOCK_SPIN_ON_OWNER=y
+CONFIG_LOGO=y
+CONFIG_LOGO_LINUX_CLUT224=y
+# CONFIG_LOGO_LINUX_MONO is not set
+# CONFIG_LOGO_LINUX_VGA16 is not set
+CONFIG_LZO_COMPRESS=y
+CONFIG_LZO_DECOMPRESS=y
+# CONFIG_MACH_MT2701 is not set
+# CONFIG_MACH_MT6589 is not set
+# CONFIG_MACH_MT6592 is not set
+CONFIG_MACH_MT7623=y
+# CONFIG_MACH_MT7629 is not set
+# CONFIG_MACH_MT8127 is not set
+# CONFIG_MACH_MT8135 is not set
+CONFIG_MAGIC_SYSRQ=y
+CONFIG_MAILBOX=y
+# CONFIG_MAILBOX_TEST is not set
+CONFIG_MDIO_BITBANG=y
+CONFIG_MDIO_BUS=y
+CONFIG_MDIO_DEVICE=y
+CONFIG_MDIO_DEVRES=y
+CONFIG_MDIO_GPIO=y
+CONFIG_MEDIATEK_GE_PHY=y
+CONFIG_MEDIATEK_MT6577_AUXADC=y
+CONFIG_MEDIATEK_WATCHDOG=y
+CONFIG_MEMORY=y
+# CONFIG_MFD_AIROHA_AN8855 is not set
+CONFIG_MFD_CORE=y
+# CONFIG_MFD_HI6421_SPMI is not set
+CONFIG_MFD_MT6397=y
+CONFIG_MFD_SYSCON=y
+CONFIG_MIGHT_HAVE_CACHE_L2X0=y
+CONFIG_MIGRATION=y
+CONFIG_MMC=y
+CONFIG_MMC_BLOCK=y
+CONFIG_MMC_CQHCI=y
+CONFIG_MMC_MTK=y
+CONFIG_MMC_SDHCI=y
+# CONFIG_MMC_SDHCI_PCI is not set
+CONFIG_MMC_SDHCI_PLTFM=y
+CONFIG_MMU_LAZY_TLB_REFCOUNT=y
+CONFIG_MODULES_USE_ELF_REL=y
+CONFIG_MTD_CMDLINE_PARTS=y
+# CONFIG_MTD_NAND_ECC_MEDIATEK is not set
+CONFIG_MTD_SPI_NOR=y
+CONFIG_MTD_SPLIT_FIRMWARE=y
+CONFIG_MTD_SPLIT_UIMAGE_FW=y
+CONFIG_MTD_UBI=y
+CONFIG_MTD_UBI_BEB_LIMIT=20
+CONFIG_MTD_UBI_BLOCK=y
+CONFIG_MTD_UBI_WL_THRESHOLD=4096
+# CONFIG_MTK_ADSP_MBOX is not set
+CONFIG_MTK_CMDQ=y
+CONFIG_MTK_CMDQ_MBOX=y
+CONFIG_MTK_CPUX_TIMER=y
+CONFIG_MTK_CQDMA=y
+# CONFIG_MTK_HSDMA is not set
+CONFIG_MTK_INFRACFG=y
+CONFIG_MTK_IOMMU=y
+CONFIG_MTK_IOMMU_V1=y
+# CONFIG_MTK_LVTS_THERMAL is not set
+CONFIG_MTK_MMSYS=y
+CONFIG_MTK_NET_PHYLIB=y
+CONFIG_MTK_PMIC_WRAP=y
+CONFIG_MTK_REGULATOR_COUPLER=y
+CONFIG_MTK_SCPSYS=y
+CONFIG_MTK_SCPSYS_PM_DOMAINS=y
+CONFIG_MTK_SMI=y
+CONFIG_MTK_SOC_THERMAL=y
+# CONFIG_MTK_SVS is not set
+CONFIG_MTK_THERMAL=y
+CONFIG_MTK_TIMER=y
+# CONFIG_MTK_UART_APDMA is not set
+# CONFIG_MUSB_PIO_ONLY is not set
+CONFIG_MUTEX_SPIN_ON_OWNER=y
+CONFIG_NEED_DMA_MAP_STATE=y
+CONFIG_NEED_SG_DMA_LENGTH=y
+CONFIG_NEED_SRCU_NMI_SAFE=y
+CONFIG_NEON=y
+CONFIG_NET_DEVLINK=y
+CONFIG_NET_DSA=y
+CONFIG_NET_DSA_MT7530=y
+CONFIG_NET_DSA_MT7530_MDIO=y
+# CONFIG_NET_DSA_MT7530_MMIO is not set
+CONFIG_NET_DSA_TAG_MTK=y
+CONFIG_NET_EGRESS=y
+CONFIG_NET_FLOW_LIMIT=y
+CONFIG_NET_INGRESS=y
+CONFIG_NET_MEDIATEK_SOC=y
+CONFIG_NET_MEDIATEK_SOC_WED=y
+CONFIG_NET_SELFTESTS=y
+CONFIG_NET_VENDOR_MEDIATEK=y
+# CONFIG_NET_VENDOR_WIZNET is not set
+CONFIG_NET_XGRESS=y
+CONFIG_NLS=y
+CONFIG_NOP_USB_XCEIV=y
+CONFIG_NO_HZ=y
+CONFIG_NO_HZ_COMMON=y
+CONFIG_NO_HZ_IDLE=y
+CONFIG_NR_CPUS=4
+CONFIG_NVMEM=y
+CONFIG_NVMEM_LAYOUTS=y
+# CONFIG_NVMEM_LAYOUT_ADTRAN is not set
+CONFIG_NVMEM_MTK_EFUSE=y
+# CONFIG_NVMEM_SPMI_SDAM is not set
+CONFIG_NVMEM_SYSFS=y
+CONFIG_OF=y
+CONFIG_OF_ADDRESS=y
+CONFIG_OF_DYNAMIC=y
+CONFIG_OF_EARLY_FLATTREE=y
+CONFIG_OF_FLATTREE=y
+CONFIG_OF_GPIO=y
+CONFIG_OF_IOMMU=y
+CONFIG_OF_IRQ=y
+CONFIG_OF_KOBJ=y
+CONFIG_OF_MDIO=y
+CONFIG_OF_OVERLAY=y
+CONFIG_OF_RESOLVE=y
+CONFIG_OLD_SIGACTION=y
+CONFIG_OLD_SIGSUSPEND3=y
+CONFIG_PADATA=y
+CONFIG_PAGE_OFFSET=0xC0000000
+CONFIG_PAGE_POOL=y
+CONFIG_PAGE_POOL_STATS=y
+CONFIG_PAGE_SIZE_LESS_THAN_256KB=y
+CONFIG_PAGE_SIZE_LESS_THAN_64KB=y
+CONFIG_PCI=y
+CONFIG_PCIEAER=y
+CONFIG_PCIEPORTBUS=y
+CONFIG_PCIE_MEDIATEK=y
+CONFIG_PCIE_PME=y
+CONFIG_PCI_DOMAINS=y
+CONFIG_PCI_DOMAINS_GENERIC=y
+CONFIG_PCI_MSI=y
+CONFIG_PCS_MTK_LYNXI=y
+CONFIG_PERF_USE_VMALLOC=y
+CONFIG_PGTABLE_LEVELS=2
+CONFIG_PHYLIB=y
+CONFIG_PHYLIB_LEDS=y
+CONFIG_PHYLINK=y
+# CONFIG_PHY_MTK_DP is not set
+CONFIG_PHY_MTK_HDMI=y
+CONFIG_PHY_MTK_MIPI_DSI=y
+# CONFIG_PHY_MTK_PCIE is not set
+CONFIG_PHY_MTK_TPHY=y
+# CONFIG_PHY_MTK_UFS is not set
+# CONFIG_PHY_MTK_XSPHY is not set
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_MT2701=y
+# CONFIG_PINCTRL_MT6397 is not set
+CONFIG_PINCTRL_MT7623=y
+CONFIG_PINCTRL_MTK=y
+CONFIG_PINCTRL_MTK_MOORE=y
+CONFIG_PINCTRL_MTK_V2=y
+CONFIG_PM=y
+CONFIG_PM_CLK=y
+CONFIG_PM_DEVFREQ=y
+# CONFIG_PM_DEVFREQ_EVENT is not set
+CONFIG_PM_GENERIC_DOMAINS=y
+CONFIG_PM_GENERIC_DOMAINS_OF=y
+CONFIG_PM_GENERIC_DOMAINS_SLEEP=y
+CONFIG_PM_OPP=y
+CONFIG_PM_SLEEP=y
+CONFIG_PM_SLEEP_SMP=y
+CONFIG_POWER_RESET=y
+# CONFIG_POWER_RESET_MT6323 is not set
+CONFIG_POWER_SUPPLY=y
+CONFIG_POWER_SUPPLY_HWMON=y
+CONFIG_PREEMPT=y
+CONFIG_PREEMPTION=y
+CONFIG_PREEMPT_BUILD=y
+CONFIG_PREEMPT_COUNT=y
+# CONFIG_PREEMPT_NONE is not set
+CONFIG_PREEMPT_RCU=y
+CONFIG_PRINTK_TIME=y
+CONFIG_PTP_1588_CLOCK_OPTIONAL=y
+CONFIG_PWM=y
+CONFIG_PWM_MEDIATEK=y
+# CONFIG_PWM_MTK_DISP is not set
+CONFIG_PWM_SYSFS=y
+CONFIG_RANDSTRUCT_NONE=y
+CONFIG_RAS=y
+CONFIG_RATIONAL=y
+CONFIG_REGMAP=y
+CONFIG_REGMAP_I2C=y
+CONFIG_REGMAP_MMIO=y
+CONFIG_REGULATOR=y
+CONFIG_REGULATOR_FIXED_VOLTAGE=y
+CONFIG_REGULATOR_GPIO=y
+CONFIG_REGULATOR_MT6323=y
+# CONFIG_REGULATOR_MT6331 is not set
+# CONFIG_REGULATOR_MT6332 is not set
+# CONFIG_REGULATOR_MT6357 is not set
+# CONFIG_REGULATOR_MT6358 is not set
+# CONFIG_REGULATOR_MT6380 is not set
+# CONFIG_REGULATOR_MT6397 is not set
+# CONFIG_REGULATOR_QCOM_LABIBB is not set
+# CONFIG_REGULATOR_QCOM_SPMI is not set
+# CONFIG_REGULATOR_QCOM_USB_VBUS is not set
+CONFIG_RESET_CONTROLLER=y
+CONFIG_RFS_ACCEL=y
+CONFIG_RPS=y
+CONFIG_RTC_CLASS=y
+# CONFIG_RTC_DRV_MT6397 is not set
+# CONFIG_RTC_DRV_MT7622 is not set
+CONFIG_RTC_I2C_AND_SPI=y
+CONFIG_RTC_MC146818_LIB=y
+# CONFIG_RTL8367S_GSW is not set
+CONFIG_RWSEM_SPIN_ON_OWNER=y
+# CONFIG_SERIAL_8250_DMA is not set
+CONFIG_SERIAL_8250_FSL=y
+CONFIG_SERIAL_8250_MT6577=y
+CONFIG_SERIAL_8250_NR_UARTS=4
+CONFIG_SERIAL_8250_RUNTIME_UARTS=4
+CONFIG_SERIAL_MCTRL_GPIO=y
+CONFIG_SGL_ALLOC=y
+CONFIG_SMP=y
+# CONFIG_SMP_ON_UP is not set
+CONFIG_SOCK_RX_QUEUE_MAPPING=y
+CONFIG_SOFTIRQ_ON_OWN_STACK=y
+CONFIG_SPARSE_IRQ=y
+CONFIG_SPI=y
+CONFIG_SPI_BITBANG=y
+CONFIG_SPI_DYNAMIC=y
+CONFIG_SPI_MASTER=y
+CONFIG_SPI_MEM=y
+CONFIG_SPI_MT65XX=y
+# CONFIG_SPI_MTK_NOR is not set
+CONFIG_SPMI=y
+# CONFIG_SPMI_HISI3670 is not set
+# CONFIG_SPMI_MTK_PMIF is not set
+CONFIG_SQUASHFS_DECOMP_MULTI_PERCPU=y
+# CONFIG_STRIP_ASM_SYMS is not set
+CONFIG_SUSPEND=y
+CONFIG_SUSPEND_FREEZER=y
+CONFIG_SWPHY=y
+CONFIG_SWP_EMULATE=y
+CONFIG_SYNC_FILE=y
+CONFIG_SYS_SUPPORTS_APM_EMULATION=y
+CONFIG_THERMAL=y
+CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y
+CONFIG_THERMAL_EMERGENCY_POWEROFF_DELAY_MS=0
+CONFIG_THERMAL_GOV_STEP_WISE=y
+CONFIG_THERMAL_OF=y
+CONFIG_THREAD_INFO_IN_TASK=y
+CONFIG_TICK_CPU_ACCOUNTING=y
+CONFIG_TIMER_OF=y
+CONFIG_TIMER_PROBE=y
+CONFIG_TOUCHSCREEN_EDT_FT5X06=y
+CONFIG_TREE_RCU=y
+CONFIG_TREE_SRCU=y
+CONFIG_UBIFS_FS=y
+CONFIG_UEVENT_HELPER_PATH=""
+CONFIG_UIMAGE_FIT_BLK=y
+CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h"
+CONFIG_UNINLINE_SPIN_UNLOCK=y
+CONFIG_UNWINDER_ARM=y
+CONFIG_USB=y
+CONFIG_USB_COMMON=y
+CONFIG_USB_F_ACM=y
+CONFIG_USB_F_ECM=y
+CONFIG_USB_F_MASS_STORAGE=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GPIO_VBUS=y
+CONFIG_USB_G_MULTI=y
+CONFIG_USB_G_MULTI_CDC=y
+# CONFIG_USB_G_MULTI_RNDIS is not set
+CONFIG_USB_HID=y
+CONFIG_USB_HIDDEV=y
+CONFIG_USB_INVENTRA_DMA=y
+CONFIG_USB_LIBCOMPOSITE=y
+CONFIG_USB_MUSB_DUAL_ROLE=y
+CONFIG_USB_MUSB_HDRC=y
+CONFIG_USB_MUSB_MEDIATEK=y
+CONFIG_USB_OTG=y
+CONFIG_USB_PHY=y
+CONFIG_USB_ROLE_SWITCH=y
+CONFIG_USB_SUPPORT=y
+CONFIG_USB_U_ETHER=y
+CONFIG_USB_U_SERIAL=y
+CONFIG_USE_OF=y
+CONFIG_VFP=y
+CONFIG_VFPv3=y
+CONFIG_VIDEOMODE_HELPERS=y
+CONFIG_VIDEO_CMDLINE=y
+CONFIG_VIDEO_NOMODESET=y
+CONFIG_VM_EVENT_COUNTERS=y
+CONFIG_VT=y
+CONFIG_VT_CONSOLE=y
+CONFIG_VT_CONSOLE_SLEEP=y
+CONFIG_VT_HW_CONSOLE_BINDING=y
+CONFIG_WATCHDOG_CORE=y
+CONFIG_XPS=y
+CONFIG_XXHASH=y
+CONFIG_XZ_DEC_ARM=y
+CONFIG_XZ_DEC_BCJ=y
+CONFIG_ZBOOT_ROM_BSS=0
+CONFIG_ZBOOT_ROM_TEXT=0
+CONFIG_ZLIB_DEFLATE=y
+CONFIG_ZLIB_INFLATE=y
+CONFIG_ZSTD_COMMON=y
+CONFIG_ZSTD_COMPRESS=y
+CONFIG_ZSTD_DECOMPRESS=y
--- /dev/null
+# CONFIG_AIROHA_EN8801SC_PHY is not set
+# CONFIG_AIR_AN8855_PHY is not set
+CONFIG_ALIGNMENT_TRAP=y
+CONFIG_ARCH_32BIT_OFF_T=y
+CONFIG_ARCH_HIBERNATION_POSSIBLE=y
+CONFIG_ARCH_KEEP_MEMBLOCK=y
+CONFIG_ARCH_MEDIATEK=y
+CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y
+CONFIG_ARCH_MULTIPLATFORM=y
+CONFIG_ARCH_MULTI_V6_V7=y
+CONFIG_ARCH_MULTI_V7=y
+CONFIG_ARCH_OPTIONAL_KERNEL_RWX=y
+CONFIG_ARCH_OPTIONAL_KERNEL_RWX_DEFAULT=y
+CONFIG_ARCH_SELECT_MEMORY_MODEL=y
+CONFIG_ARCH_SPARSEMEM_ENABLE=y
+CONFIG_ARCH_STACKWALK=y
+CONFIG_ARCH_SUSPEND_POSSIBLE=y
+CONFIG_ARM=y
+CONFIG_ARM_ARCH_TIMER=y
+CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y
+CONFIG_ARM_GIC=y
+CONFIG_ARM_HAS_GROUP_RELOCS=y
+CONFIG_ARM_HEAVY_MB=y
+CONFIG_ARM_L1_CACHE_SHIFT=6
+CONFIG_ARM_L1_CACHE_SHIFT_6=y
+CONFIG_ARM_PATCH_IDIV=y
+CONFIG_ARM_PATCH_PHYS_VIRT=y
+CONFIG_ARM_THUMB=y
+CONFIG_ARM_UNWIND=y
+CONFIG_ARM_VIRT_EXT=y
+CONFIG_ATAGS=y
+CONFIG_AUTO_ZRELADDR=y
+CONFIG_BINFMT_FLAT_ARGVP_ENVP_ON_STACK=y
+CONFIG_BLK_DEV_SD=y
+CONFIG_BLK_MQ_PCI=y
+CONFIG_BLK_PM=y
+CONFIG_BSD_PROCESS_ACCT=y
+CONFIG_BSD_PROCESS_ACCT_V3=y
+CONFIG_CACHE_L2X0=y
+CONFIG_CC_HAVE_STACKPROTECTOR_TLS=y
+# CONFIG_CC_OPTIMIZE_FOR_PERFORMANCE is not set
+CONFIG_CC_OPTIMIZE_FOR_SIZE=y
+CONFIG_CHR_DEV_SCH=y
+CONFIG_CLKSRC_MMIO=y
+CONFIG_CLONE_BACKWARDS=y
+CONFIG_CMDLINE="rootfstype=squashfs,jffs2"
+CONFIG_CMDLINE_FROM_BOOTLOADER=y
+CONFIG_CMDLINE_OVERRIDE=y
+CONFIG_COMMON_CLK=y
+CONFIG_COMMON_CLK_MEDIATEK=y
+# CONFIG_COMMON_CLK_MT2701 is not set
+# CONFIG_COMMON_CLK_MT6795 is not set
+# CONFIG_COMMON_CLK_MT7622 is not set
+CONFIG_COMMON_CLK_MT7629=y
+CONFIG_COMMON_CLK_MT7629_ETHSYS=y
+CONFIG_COMMON_CLK_MT7629_HIFSYS=y
+# CONFIG_COMMON_CLK_MT7981 is not set
+# CONFIG_COMMON_CLK_MT7986 is not set
+# CONFIG_COMMON_CLK_MT7988 is not set
+# CONFIG_COMMON_CLK_MT8135 is not set
+# CONFIG_COMMON_CLK_MT8365 is not set
+# CONFIG_COMMON_CLK_MT8516 is not set
+CONFIG_COMPACT_UNEVICTABLE_DEFAULT=1
+CONFIG_COMPAT_32BIT_TIME=y
+CONFIG_CONTEXT_TRACKING=y
+CONFIG_CONTEXT_TRACKING_IDLE=y
+CONFIG_CPU_32v6K=y
+CONFIG_CPU_32v7=y
+CONFIG_CPU_ABRT_EV7=y
+CONFIG_CPU_CACHE_V7=y
+CONFIG_CPU_CACHE_VIPT=y
+CONFIG_CPU_COPY_V6=y
+CONFIG_CPU_CP15=y
+CONFIG_CPU_CP15_MMU=y
+CONFIG_CPU_HAS_ASID=y
+CONFIG_CPU_IDLE=y
+CONFIG_CPU_IDLE_GOV_MENU=y
+CONFIG_CPU_LITTLE_ENDIAN=y
+CONFIG_CPU_MITIGATIONS=y
+CONFIG_CPU_PABRT_V7=y
+CONFIG_CPU_PM=y
+CONFIG_CPU_RMAP=y
+CONFIG_CPU_SPECTRE=y
+CONFIG_CPU_THUMB_CAPABLE=y
+CONFIG_CPU_TLB_V7=y
+CONFIG_CPU_V7=y
+CONFIG_CRC16=y
+CONFIG_CRYPTO_DEFLATE=y
+CONFIG_CRYPTO_HASH_INFO=y
+CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y
+CONFIG_CRYPTO_LIB_GF128MUL=y
+CONFIG_CRYPTO_LIB_SHA1=y
+CONFIG_CRYPTO_LIB_UTILS=y
+CONFIG_CRYPTO_LZO=y
+CONFIG_CRYPTO_ZSTD=y
+CONFIG_CURRENT_POINTER_IN_TPIDRURO=y
+CONFIG_DCACHE_WORD_ACCESS=y
+CONFIG_DEBUG_INFO=y
+CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S"
+CONFIG_DEBUG_MISC=y
+CONFIG_DEFAULT_HOSTNAME="(mt7629)"
+CONFIG_DIMLIB=y
+CONFIG_DMA_OPS=y
+CONFIG_DTC=y
+CONFIG_EDAC_ATOMIC_SCRUB=y
+CONFIG_EDAC_SUPPORT=y
+CONFIG_EINT_MTK=y
+CONFIG_EXCLUSIVE_SYSTEM_RAM=y
+CONFIG_FIXED_PHY=y
+CONFIG_FIX_EARLYCON_MEM=y
+CONFIG_FS_IOMAP=y
+CONFIG_FUNCTION_ALIGNMENT=0
+CONFIG_FWNODE_MDIO=y
+CONFIG_FW_LOADER_PAGED_BUF=y
+CONFIG_FW_LOADER_SYSFS=y
+CONFIG_GENERIC_ALLOCATOR=y
+CONFIG_GENERIC_ARCH_TOPOLOGY=y
+CONFIG_GENERIC_BUG=y
+CONFIG_GENERIC_CLOCKEVENTS=y
+CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y
+CONFIG_GENERIC_CPU_AUTOPROBE=y
+CONFIG_GENERIC_CPU_VULNERABILITIES=y
+CONFIG_GENERIC_EARLY_IOREMAP=y
+CONFIG_GENERIC_GETTIMEOFDAY=y
+CONFIG_GENERIC_IDLE_POLL_SETUP=y
+CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y
+CONFIG_GENERIC_IRQ_MIGRATION=y
+CONFIG_GENERIC_IRQ_MULTI_HANDLER=y
+CONFIG_GENERIC_IRQ_SHOW=y
+CONFIG_GENERIC_IRQ_SHOW_LEVEL=y
+CONFIG_GENERIC_LIB_DEVMEM_IS_ALLOWED=y
+CONFIG_GENERIC_MSI_IRQ=y
+CONFIG_GENERIC_PCI_IOMAP=y
+CONFIG_GENERIC_PHY=y
+CONFIG_GENERIC_PINCONF=y
+CONFIG_GENERIC_PINCTRL_GROUPS=y
+CONFIG_GENERIC_PINMUX_FUNCTIONS=y
+CONFIG_GENERIC_SCHED_CLOCK=y
+CONFIG_GENERIC_SMP_IDLE_THREAD=y
+CONFIG_GENERIC_STRNCPY_FROM_USER=y
+CONFIG_GENERIC_STRNLEN_USER=y
+CONFIG_GENERIC_TIME_VSYSCALL=y
+CONFIG_GENERIC_VDSO_32=y
+CONFIG_GPIO_CDEV=y
+CONFIG_GRO_CELLS=y
+# CONFIG_HARDEN_BRANCH_HISTORY is not set
+# CONFIG_HARDEN_BRANCH_PREDICTOR is not set
+CONFIG_HARDIRQS_SW_RESEND=y
+CONFIG_HAS_DMA=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT=y
+CONFIG_HAS_IOPORT_MAP=y
+CONFIG_HAVE_SMP=y
+CONFIG_HOTPLUG_CORE_SYNC=y
+CONFIG_HOTPLUG_CORE_SYNC_DEAD=y
+CONFIG_HOTPLUG_CPU=y
+CONFIG_HW_RANDOM=y
+CONFIG_HW_RANDOM_MTK=y
+CONFIG_HZ_FIXED=0
+CONFIG_INITRAMFS_SOURCE=""
+CONFIG_IRQCHIP=y
+CONFIG_IRQSTACKS=y
+CONFIG_IRQ_DOMAIN=y
+CONFIG_IRQ_DOMAIN_HIERARCHY=y
+CONFIG_IRQ_FORCED_THREADING=y
+CONFIG_IRQ_TIME_ACCOUNTING=y
+CONFIG_IRQ_WORK=y
+# CONFIG_LEDS_BRIGHTNESS_HW_CHANGED is not set
+# CONFIG_LEDS_SMARTRG_LED is not set
+CONFIG_LIBFDT=y
+CONFIG_LOCK_DEBUGGING_SUPPORT=y
+CONFIG_LOCK_SPIN_ON_OWNER=y
+CONFIG_LZO_COMPRESS=y
+CONFIG_LZO_DECOMPRESS=y
+# CONFIG_MACH_MT2701 is not set
+# CONFIG_MACH_MT6589 is not set
+# CONFIG_MACH_MT6592 is not set
+# CONFIG_MACH_MT7623 is not set
+CONFIG_MACH_MT7629=y
+# CONFIG_MACH_MT8127 is not set
+# CONFIG_MACH_MT8135 is not set
+CONFIG_MDIO_BUS=y
+CONFIG_MDIO_DEVICE=y
+CONFIG_MDIO_DEVRES=y
+CONFIG_MEDIATEK_GE_PHY=y
+CONFIG_MEDIATEK_WATCHDOG=y
+# CONFIG_MFD_AIROHA_AN8855 is not set
+CONFIG_MFD_SYSCON=y
+CONFIG_MIGHT_HAVE_CACHE_L2X0=y
+CONFIG_MIGRATION=y
+CONFIG_MMU_LAZY_TLB_REFCOUNT=y
+CONFIG_MODULES_USE_ELF_REL=y
+CONFIG_MTD_NAND_CORE=y
+CONFIG_MTD_NAND_ECC=y
+CONFIG_MTD_NAND_ECC_MEDIATEK=y
+CONFIG_MTD_NAND_ECC_SW_HAMMING=y
+CONFIG_MTD_NAND_MTK_BMT=y
+CONFIG_MTD_RAW_NAND=y
+CONFIG_MTD_SPI_NAND=y
+CONFIG_MTD_SPI_NOR=y
+CONFIG_MTD_SPLIT_FIRMWARE=y
+CONFIG_MTD_SPLIT_FIT_FW=y
+CONFIG_MTD_UBI=y
+CONFIG_MTD_UBI_BEB_LIMIT=20
+CONFIG_MTD_UBI_BLOCK=y
+CONFIG_MTD_UBI_WL_THRESHOLD=4096
+# CONFIG_MTK_CMDQ is not set
+CONFIG_MTK_CPUX_TIMER=y
+CONFIG_MTK_INFRACFG=y
+CONFIG_MTK_NET_PHYLIB=y
+# CONFIG_MTK_PMIC_WRAP is not set
+CONFIG_MTK_SCPSYS=y
+CONFIG_MTK_SCPSYS_PM_DOMAINS=y
+CONFIG_MTK_TIMER=y
+CONFIG_MUTEX_SPIN_ON_OWNER=y
+CONFIG_NEED_DMA_MAP_STATE=y
+CONFIG_NEED_SRCU_NMI_SAFE=y
+CONFIG_NETFILTER=y
+CONFIG_NETFILTER_BPF_LINK=y
+CONFIG_NET_DEVLINK=y
+CONFIG_NET_DSA=y
+CONFIG_NET_DSA_MT7530=y
+CONFIG_NET_DSA_MT7530_MDIO=y
+# CONFIG_NET_DSA_MT7530_MMIO is not set
+CONFIG_NET_DSA_TAG_MTK=y
+CONFIG_NET_EGRESS=y
+CONFIG_NET_FLOW_LIMIT=y
+CONFIG_NET_INGRESS=y
+CONFIG_NET_MEDIATEK_SOC=y
+CONFIG_NET_MEDIATEK_SOC_WED=y
+CONFIG_NET_SELFTESTS=y
+CONFIG_NET_VENDOR_MEDIATEK=y
+CONFIG_NET_XGRESS=y
+CONFIG_NLS=y
+CONFIG_NO_HZ_COMMON=y
+CONFIG_NO_HZ_IDLE=y
+CONFIG_NR_CPUS=2
+CONFIG_NVMEM=y
+CONFIG_NVMEM_LAYOUTS=y
+# CONFIG_NVMEM_LAYOUT_ADTRAN is not set
+# CONFIG_NVMEM_MTK_EFUSE is not set
+CONFIG_NVMEM_SYSFS=y
+CONFIG_OF=y
+CONFIG_OF_ADDRESS=y
+CONFIG_OF_EARLY_FLATTREE=y
+CONFIG_OF_FLATTREE=y
+CONFIG_OF_GPIO=y
+CONFIG_OF_IRQ=y
+CONFIG_OF_KOBJ=y
+CONFIG_OF_MDIO=y
+CONFIG_OLD_SIGACTION=y
+CONFIG_OLD_SIGSUSPEND3=y
+CONFIG_OUTER_CACHE=y
+CONFIG_OUTER_CACHE_SYNC=y
+CONFIG_PADATA=y
+CONFIG_PAGE_OFFSET=0xC0000000
+CONFIG_PAGE_POOL=y
+CONFIG_PAGE_POOL_STATS=y
+CONFIG_PAGE_SIZE_LESS_THAN_256KB=y
+CONFIG_PAGE_SIZE_LESS_THAN_64KB=y
+CONFIG_PCI=y
+CONFIG_PCIEAER=y
+CONFIG_PCIEPORTBUS=y
+CONFIG_PCIE_MEDIATEK=y
+CONFIG_PCIE_PME=y
+CONFIG_PCI_DOMAINS=y
+CONFIG_PCI_DOMAINS_GENERIC=y
+CONFIG_PCI_MSI=y
+CONFIG_PCS_MTK_LYNXI=y
+CONFIG_PERF_USE_VMALLOC=y
+CONFIG_PGTABLE_LEVELS=2
+CONFIG_PHYLIB=y
+CONFIG_PHYLIB_LEDS=y
+CONFIG_PHYLINK=y
+# CONFIG_PHY_MTK_DP is not set
+# CONFIG_PHY_MTK_PCIE is not set
+CONFIG_PHY_MTK_TPHY=y
+# CONFIG_PHY_MTK_UFS is not set
+# CONFIG_PHY_MTK_XSPHY is not set
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_MT7629=y
+CONFIG_PINCTRL_MTK_MOORE=y
+CONFIG_PINCTRL_MTK_V2=y
+CONFIG_PM=y
+CONFIG_PM_CLK=y
+CONFIG_PM_GENERIC_DOMAINS=y
+CONFIG_PM_GENERIC_DOMAINS_OF=y
+CONFIG_PREEMPT_NONE_BUILD=y
+CONFIG_PTP_1588_CLOCK_OPTIONAL=y
+CONFIG_PWM=y
+CONFIG_PWM_MEDIATEK=y
+# CONFIG_PWM_MTK_DISP is not set
+CONFIG_PWM_SYSFS=y
+CONFIG_RANDSTRUCT_NONE=y
+CONFIG_RAS=y
+CONFIG_RATIONAL=y
+CONFIG_REGMAP=y
+CONFIG_REGMAP_MMIO=y
+CONFIG_RESET_CONTROLLER=y
+CONFIG_RFS_ACCEL=y
+CONFIG_RPS=y
+# CONFIG_RTL8367S_GSW is not set
+CONFIG_RWSEM_SPIN_ON_OWNER=y
+CONFIG_SCSI=y
+CONFIG_SCSI_COMMON=y
+CONFIG_SERIAL_8250_FSL=y
+CONFIG_SERIAL_8250_MT6577=y
+CONFIG_SERIAL_8250_NR_UARTS=3
+CONFIG_SERIAL_8250_RUNTIME_UARTS=3
+CONFIG_SERIAL_MCTRL_GPIO=y
+CONFIG_SERIAL_OF_PLATFORM=y
+CONFIG_SGL_ALLOC=y
+CONFIG_SG_POOL=y
+CONFIG_SMP=y
+CONFIG_SMP_ON_UP=y
+CONFIG_SOCK_RX_QUEUE_MAPPING=y
+CONFIG_SOFTIRQ_ON_OWN_STACK=y
+CONFIG_SPARSE_IRQ=y
+CONFIG_SPI=y
+CONFIG_SPI_MASTER=y
+CONFIG_SPI_MEM=y
+CONFIG_SPI_MT65XX=y
+CONFIG_SPI_MTK_NOR=y
+CONFIG_SPI_MTK_SNFI=y
+CONFIG_SQUASHFS_DECOMP_MULTI_PERCPU=y
+CONFIG_STACKTRACE=y
+# CONFIG_SWAP is not set
+CONFIG_SWCONFIG=y
+CONFIG_SWPHY=y
+CONFIG_SWP_EMULATE=y
+CONFIG_SYS_SUPPORTS_APM_EMULATION=y
+CONFIG_THREAD_INFO_IN_TASK=y
+CONFIG_TICK_CPU_ACCOUNTING=y
+CONFIG_TIMER_OF=y
+CONFIG_TIMER_PROBE=y
+CONFIG_TREE_RCU=y
+CONFIG_TREE_SRCU=y
+CONFIG_UBIFS_FS=y
+CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h"
+CONFIG_UNWINDER_ARM=y
+CONFIG_USB=y
+CONFIG_USB_COMMON=y
+CONFIG_USB_SUPPORT=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_MTK=y
+# CONFIG_USB_XHCI_PLATFORM is not set
+CONFIG_USE_OF=y
+# CONFIG_VFP is not set
+CONFIG_WATCHDOG_CORE=y
+# CONFIG_WQ_POWER_EFFICIENT_DEFAULT is not set
+CONFIG_XPS=y
+CONFIG_XXHASH=y
+CONFIG_XZ_DEC_ARM=y
+CONFIG_XZ_DEC_BCJ=y
+CONFIG_ZBOOT_ROM_BSS=0
+CONFIG_ZBOOT_ROM_TEXT=0
+CONFIG_ZLIB_DEFLATE=y
+CONFIG_ZLIB_INFLATE=y
+CONFIG_ZSTD_COMMON=y
+CONFIG_ZSTD_COMPRESS=y
+CONFIG_ZSTD_DECOMPRESS=y
--- /dev/null
+--- a/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts
++++ b/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts
+@@ -1,7 +1,6 @@
+ /*
+- * Copyright (c) 2017 MediaTek Inc.
+- * Author: Ming Huang <ming.huang@mediatek.com>
+- * Sean Wang <sean.wang@mediatek.com>
++ * Copyright (c) 2018 MediaTek Inc.
++ * Author: Ryder Lee <ryder.lee@mediatek.com>
+ *
+ * SPDX-License-Identifier: (GPL-2.0 OR MIT)
+ */
+@@ -24,7 +23,7 @@
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+- bootargs = "earlycon=uart8250,mmio32,0x11002000 swiotlb=512";
++ bootargs = "earlycon=uart8250,mmio32,0x11002000 console=ttyS0,115200n1 swiotlb=512";
+ };
+
+ cpus {
+@@ -45,18 +44,18 @@
+ key-factory {
+ label = "factory";
+ linux,code = <BTN_0>;
+- gpios = <&pio 0 0>;
++ gpios = <&pio 0 GPIO_ACTIVE_LOW>;
+ };
+
+ key-wps {
+ label = "wps";
+ linux,code = <KEY_WPS_BUTTON>;
+- gpios = <&pio 102 0>;
++ gpios = <&pio 102 GPIO_ACTIVE_LOW>;
+ };
+ };
+
+ memory@40000000 {
+- reg = <0 0x40000000 0 0x20000000>;
++ reg = <0 0x40000000 0 0x40000000>;
+ device_type = "memory";
+ };
+
+@@ -133,22 +132,22 @@
+
+ port@0 {
+ reg = <0>;
+- label = "lan0";
++ label = "lan1";
+ };
+
+ port@1 {
+ reg = <1>;
+- label = "lan1";
++ label = "lan2";
+ };
+
+ port@2 {
+ reg = <2>;
+- label = "lan2";
++ label = "lan3";
+ };
+
+ port@3 {
+ reg = <3>;
+- label = "lan3";
++ label = "lan4";
+ };
+
+ port@4 {
+@@ -240,7 +239,22 @@
+ status = "okay";
+ };
+
++&pcie1 {
++ pinctrl-names = "default";
++ pinctrl-0 = <&pcie1_pins>;
++ status = "okay";
++};
++
+ &pio {
++ /* Attention: GPIO 90 is used to switch between PCIe@1,0 and
++ * SATA functions. i.e. output-high: PCIe, output-low: SATA
++ */
++ asm_sel {
++ gpio-hog;
++ gpios = <90 GPIO_ACTIVE_HIGH>;
++ output-high;
++ };
++
+ /* eMMC is shared pin with parallel NAND */
+ emmc_pins_default: emmc-pins-default {
+ mux {
+@@ -517,11 +531,11 @@
+ };
+
+ &sata {
+- status = "okay";
++ status = "disabled";
+ };
+
+ &sata_phy {
+- status = "okay";
++ status = "disabled";
+ };
+
+ &spi0 {
--- /dev/null
+--- a/arch/arm/boot/dts/mediatek/mt7629-rfb.dts
++++ b/arch/arm/boot/dts/mediatek/mt7629-rfb.dts
+@@ -18,6 +18,7 @@
+
+ chosen {
+ stdout-path = "serial0:115200n8";
++ bootargs = "earlycon=uart8250,mmio32,0x11002000 console=ttyS0,115200n8";
+ };
+
+ gpio-keys {
+@@ -70,6 +71,10 @@
+ compatible = "mediatek,eth-mac";
+ reg = <0>;
+ phy-mode = "2500base-x";
++
++ nvmem-cells = <&macaddr_factory_2a>;
++ nvmem-cell-names = "mac-address";
++
+ fixed-link {
+ speed = <2500>;
+ full-duplex;
+@@ -82,6 +87,9 @@
+ reg = <1>;
+ phy-mode = "gmii";
+ phy-handle = <&phy0>;
++
++ nvmem-cells = <&macaddr_factory_24>;
++ nvmem-cell-names = "mac-address";
+ };
+
+ mdio: mdio-bus {
+@@ -133,8 +141,9 @@
+ };
+
+ partition@b0000 {
+- label = "kernel";
++ label = "firmware";
+ reg = <0xb0000 0xb50000>;
++ compatible = "denx,fit";
+ };
+ };
+ };
+@@ -273,3 +282,19 @@
+ pinctrl-0 = <&watchdog_pins>;
+ status = "okay";
+ };
++
++&factory {
++ nvmem-layout {
++ compatible = "fixed-layout";
++ #address-cells = <1>;
++ #size-cells = <1>;
++
++ macaddr_factory_24: macaddr@24 {
++ reg = <0x24 0x6>;
++ };
++
++ macaddr_factory_2a: macaddr@2a {
++ reg = <0x2a 0x6>;
++ };
++ };
++};
--- /dev/null
+From d6a596012150960f0f3a214d31bbac4b607dbd1e Mon Sep 17 00:00:00 2001
+From: Chuanhong Guo <gch981213@gmail.com>
+Date: Fri, 29 Apr 2022 10:40:56 +0800
+Subject: [PATCH] arm: mediatek: select arch timer for mt7623
+
+Signed-off-by: Chuanhong Guo <gch981213@gmail.com>
+---
+ arch/arm/mach-mediatek/Kconfig | 1 +
+ 1 file changed, 1 insertion(+)
+
+--- a/arch/arm/mach-mediatek/Kconfig
++++ b/arch/arm/mach-mediatek/Kconfig
+@@ -26,6 +26,7 @@ config MACH_MT6592
+ config MACH_MT7623
+ bool "MediaTek MT7623 SoCs support"
+ default ARCH_MEDIATEK
++ select HAVE_ARM_ARCH_TIMER
+
+ config MACH_MT7629
+ bool "MediaTek MT7629 SoCs support"
--- /dev/null
+--- a/arch/arm64/boot/dts/mediatek/mt7622.dtsi
++++ b/arch/arm64/boot/dts/mediatek/mt7622.dtsi
+@@ -575,6 +575,7 @@
+ compatible = "mediatek,mt7622-nor",
+ "mediatek,mt8173-nor";
+ reg = <0 0x11014000 0 0xe0>;
++ interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_LOW>;
+ clocks = <&pericfg CLK_PERI_FLASH_PD>,
+ <&topckgen CLK_TOP_FLASH_SEL>;
+ clock-names = "spi", "sf";
--- /dev/null
+--- a/arch/arm64/boot/dts/mediatek/mt7622.dtsi
++++ b/arch/arm64/boot/dts/mediatek/mt7622.dtsi
+@@ -135,6 +135,13 @@
+ #size-cells = <2>;
+ ranges;
+
++ /* 64 KiB reserved for ramoops/pstore */
++ ramoops@42ff0000 {
++ compatible = "ramoops";
++ reg = <0 0x42ff0000 0 0x10000>;
++ record-size = <0x1000>;
++ };
++
+ /* 192 KiB reserved for ARM Trusted Firmware (BL31) */
+ secmon_reserved: secmon@43000000 {
+ reg = <0 0x43000000 0 0x30000>;
--- /dev/null
+--- a/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts
++++ b/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts
+@@ -109,10 +109,6 @@
+ status = "disabled";
+ };
+
+-&btif {
+- status = "okay";
+-};
+-
+ &cir {
+ pinctrl-names = "default";
+ pinctrl-0 = <&irrx_pins>;
+--- a/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts
++++ b/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts
+@@ -90,10 +90,6 @@
+ status = "disabled";
+ };
+
+-&btif {
+- status = "okay";
+-};
+-
+ &cir {
+ pinctrl-names = "default";
+ pinctrl-0 = <&irrx_pins>;
--- /dev/null
+--- a/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts
++++ b/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts
+@@ -145,9 +145,9 @@
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+- switch@0 {
++ switch@1f {
+ compatible = "mediatek,mt7531";
+- reg = <0>;
++ reg = <31>;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ interrupt-parent = <&pio>;
+--- a/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts
++++ b/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts
+@@ -117,9 +117,9 @@
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+- switch@0 {
++ switch@1f {
+ compatible = "mediatek,mt7531";
+- reg = <0>;
++ reg = <31>;
+ reset-gpios = <&pio 54 0>;
+
+ ports {
--- /dev/null
+--- a/arch/arm/boot/dts/mediatek/mt7623n-bananapi-bpi-r2.dts
++++ b/arch/arm/boot/dts/mediatek/mt7623n-bananapi-bpi-r2.dts
+@@ -19,6 +19,7 @@
+
+ chosen {
+ stdout-path = "serial2:115200n8";
++ bootargs = "console=ttyS2,115200n8 console=tty1";
+ };
+
+ connector {
--- /dev/null
+--- a/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts
++++ b/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts
+@@ -24,7 +24,7 @@
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+- bootargs = "earlycon=uart8250,mmio32,0x11002000 swiotlb=512";
++ bootargs = "earlycon=uart8250,mmio32,0x11002000 console=ttyS0,115200n1 swiotlb=512";
+ };
+
+ cpus {
--- /dev/null
+--- a/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts
++++ b/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts
+@@ -20,6 +20,7 @@
+
+ aliases {
+ serial0 = &uart0;
++ ethernet0 = &gmac0;
+ };
+
+ chosen {
+@@ -165,22 +166,22 @@
+
+ port@1 {
+ reg = <1>;
+- label = "lan0";
++ label = "lan1";
+ };
+
+ port@2 {
+ reg = <2>;
+- label = "lan1";
++ label = "lan2";
+ };
+
+ port@3 {
+ reg = <3>;
+- label = "lan2";
++ label = "lan3";
+ };
+
+ port@4 {
+ reg = <4>;
+- label = "lan3";
++ label = "lan4";
+ };
+
+ port@6 {
--- /dev/null
+--- a/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts
++++ b/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts
+@@ -21,6 +21,12 @@
+ aliases {
+ serial0 = &uart0;
+ ethernet0 = &gmac0;
++ led-boot = &led_system_green;
++ led-failsafe = &led_system_blue;
++ led-running = &led_system_green;
++ led-upgrade = &led_system_blue;
++ mmc0 = &mmc0;
++ mmc1 = &mmc1;
+ };
+
+ chosen {
+@@ -44,8 +50,8 @@
+ compatible = "gpio-keys";
+
+ factory-key {
+- label = "factory";
+- linux,code = <BTN_0>;
++ label = "reset";
++ linux,code = <KEY_RESTART>;
+ gpios = <&pio 0 GPIO_ACTIVE_HIGH>;
+ };
+
+@@ -59,17 +65,17 @@
+ leds {
+ compatible = "gpio-leds";
+
+- led-0 {
++ led_system_green: led-0 {
+ label = "bpi-r64:pio:green";
+ color = <LED_COLOR_ID_GREEN>;
+ gpios = <&pio 89 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ };
+
+- led-1 {
+- label = "bpi-r64:pio:red";
+- color = <LED_COLOR_ID_RED>;
+- gpios = <&pio 88 GPIO_ACTIVE_HIGH>;
++ led_system_blue: led-1 {
++ label = "bpi-r64:pio:blue";
++ color = <LED_COLOR_ID_BLUE>;
++ gpios = <&pio 85 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ };
+ };
--- /dev/null
+--- a/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts
++++ b/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts
+@@ -588,6 +588,10 @@
+ status = "okay";
+ };
+
++&rtc {
++ status = "disabled";
++};
++
+ &sata {
+ status = "disabled";
+ };
--- /dev/null
+From 4c4baed29b168e9bf39545a945a9523ea280cb44 Mon Sep 17 00:00:00 2001
+From: Daniel Golle <daniel@makrotopia.org>
+Date: Sat, 1 Feb 2025 04:24:17 +0000
+Subject: [PATCH 1/2] Revert "arm64: dts: mediatek: fix t-phy unit name"
+
+This reverts commit 963c3b0c47ec29b4c49c9f45965cd066f419d17f.
+---
+ arch/arm64/boot/dts/mediatek/mt7622.dtsi | 2 +-
+ arch/arm64/boot/dts/mediatek/mt7986a.dtsi | 2 +-
+ 2 files changed, 2 insertions(+), 2 deletions(-)
+
+--- a/arch/arm64/boot/dts/mediatek/mt7622.dtsi
++++ b/arch/arm64/boot/dts/mediatek/mt7622.dtsi
+@@ -908,7 +908,7 @@
+ status = "disabled";
+ };
+
+- sata_phy: t-phy {
++ sata_phy: t-phy@1a243000 {
+ compatible = "mediatek,mt7622-tphy",
+ "mediatek,generic-tphy-v1";
+ #address-cells = <2>;
+--- a/arch/arm64/boot/dts/mediatek/mt7986a.dtsi
++++ b/arch/arm64/boot/dts/mediatek/mt7986a.dtsi
+@@ -428,7 +428,7 @@
+ };
+ };
+
+- pcie_phy: t-phy {
++ pcie_phy: t-phy@11c00000 {
+ compatible = "mediatek,mt7986-tphy",
+ "mediatek,generic-tphy-v2";
+ ranges;
--- /dev/null
+From 98bc223d174c7f544e8f6c4f0caa8fa144f2f4dc Mon Sep 17 00:00:00 2001
+From: Christian Marangi <ansuelsmth@gmail.com>
+Date: Fri, 28 Jun 2024 12:55:40 +0200
+Subject: [PATCH 2/2] arm64: dts: mediatek: mt7622: readd syscon to pciesys
+ node
+
+Sata node reference the pciesys with the property mediatek,phy-node
+and that is used as a syscon to access the pciesys regs.
+
+Readd the syscon compatible to pciesys node to restore correct
+functionality of the SATA interface.
+
+Fixes: 3ba5a6159434 ("arm64: dts: mediatek: mt7622: fix clock controllers")
+Reported-by: Frank Wunderlich <frank-w@public-files.de>
+Co-developed-by: Frank Wunderlich <frank-w@public-files.de>
+Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
+Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
+Cc: stable@vger.kernel.org
+---
+ arch/arm64/boot/dts/mediatek/mt7622.dtsi | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+--- a/arch/arm64/boot/dts/mediatek/mt7622.dtsi
++++ b/arch/arm64/boot/dts/mediatek/mt7622.dtsi
+@@ -798,7 +798,7 @@
+ };
+
+ pciesys: clock-controller@1a100800 {
+- compatible = "mediatek,mt7622-pciesys";
++ compatible = "mediatek,mt7622-pciesys", "syscon";
+ reg = <0 0x1a100800 0 0x1000>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
--- /dev/null
+--- a/drivers/mtd/nand/spi/core.c
++++ b/drivers/mtd/nand/spi/core.c
+@@ -724,7 +724,7 @@ static int spinand_mtd_write(struct mtd_
+ static bool spinand_isbad(struct nand_device *nand, const struct nand_pos *pos)
+ {
+ struct spinand_device *spinand = nand_to_spinand(nand);
+- u8 marker[2] = { };
++ u8 marker[1] = { };
+ struct nand_page_io_req req = {
+ .pos = *pos,
+ .ooblen = sizeof(marker),
+@@ -735,7 +735,7 @@ static bool spinand_isbad(struct nand_de
+
+ spinand_select_target(spinand, pos->target);
+ spinand_read_page(spinand, &req);
+- if (marker[0] != 0xff || marker[1] != 0xff)
++ if (marker[0] != 0xff)
+ return true;
+
+ return false;
--- /dev/null
+From c813fbe806257c574240770ef716fbee19f7dbfa Mon Sep 17 00:00:00 2001
+From: Xiangsheng Hou <xiangsheng.hou@mediatek.com>
+Date: Thu, 6 Jun 2019 16:29:04 +0800
+Subject: [PATCH] spi: spi-mem: Mediatek: Add SPI Nand support for MT7629
+
+Signed-off-by: Xiangsheng Hou <xiangsheng.hou@mediatek.com>
+---
+ arch/arm/boot/dts/mediatek/mt7629-rfb.dts | 45 ++++++++++++++++++++++++++++++++
+ arch/arm/boot/dts/mediatek/mt7629.dtsi | 22 ++++++++++++++++
+ 3 files changed, 79 insertions(+)
+
+--- a/arch/arm/boot/dts/mediatek/mt7629.dtsi
++++ b/arch/arm/boot/dts/mediatek/mt7629.dtsi
+@@ -271,6 +271,27 @@
+ status = "disabled";
+ };
+
++ snfi: spi@1100d000 {
++ compatible = "mediatek,mt7629-snand";
++ reg = <0x1100d000 0x1000>;
++ interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_LOW>;
++ clocks = <&pericfg CLK_PERI_NFI_PD>, <&pericfg CLK_PERI_SNFI_PD>;
++ clock-names = "nfi_clk", "pad_clk";
++ nand-ecc-engine = <&bch>;
++ #address-cells = <1>;
++ #size-cells = <0>;
++ status = "disabled";
++ };
++
++ bch: ecc@1100e000 {
++ compatible = "mediatek,mt7622-ecc";
++ reg = <0x1100e000 0x1000>;
++ interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_LOW>;
++ clocks = <&pericfg CLK_PERI_NFIECC_PD>;
++ clock-names = "nfiecc_clk";
++ status = "disabled";
++ };
++
+ spi: spi@1100a000 {
+ compatible = "mediatek,mt7629-spi",
+ "mediatek,mt7622-spi";
+--- a/arch/arm/boot/dts/mediatek/mt7629-rfb.dts
++++ b/arch/arm/boot/dts/mediatek/mt7629-rfb.dts
+@@ -255,6 +255,50 @@
+ };
+ };
+
++&bch {
++ status = "okay";
++};
++
++&snfi {
++ pinctrl-names = "default";
++ pinctrl-0 = <&serial_nand_pins>;
++ status = "okay";
++ flash@0 {
++ compatible = "spi-nand";
++ reg = <0>;
++ spi-tx-bus-width = <4>;
++ spi-rx-bus-width = <4>;
++ nand-ecc-engine = <&snfi>;
++
++ partitions {
++ compatible = "fixed-partitions";
++ #address-cells = <1>;
++ #size-cells = <1>;
++
++ partition@0 {
++ label = "Bootloader";
++ reg = <0x00000 0x0100000>;
++ read-only;
++ };
++
++ partition@100000 {
++ label = "Config";
++ reg = <0x100000 0x0040000>;
++ };
++
++ partition@140000 {
++ label = "factory";
++ reg = <0x140000 0x0080000>;
++ };
++
++ partition@1c0000 {
++ label = "firmware";
++ reg = <0x1c0000 0x1000000>;
++ };
++ };
++ };
++};
++
+ &spi {
+ pinctrl-names = "default";
+ pinctrl-0 = <&spi_pins>;
--- /dev/null
+--- a/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts
++++ b/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts
+@@ -534,6 +534,65 @@
+ status = "disabled";
+ };
+
++&bch {
++ status = "okay";
++};
++
++&snfi {
++ pinctrl-names = "default";
++ pinctrl-0 = <&serial_nand_pins>;
++ status = "okay";
++ flash@0 {
++ compatible = "spi-nand";
++ reg = <0>;
++ spi-tx-bus-width = <4>;
++ spi-rx-bus-width = <4>;
++ nand-ecc-engine = <&snfi>;
++
++ partitions {
++ compatible = "fixed-partitions";
++ #address-cells = <1>;
++ #size-cells = <1>;
++
++ partition@0 {
++ label = "Preloader";
++ reg = <0x00000 0x0080000>;
++ read-only;
++ };
++
++ partition@80000 {
++ label = "ATF";
++ reg = <0x80000 0x0040000>;
++ };
++
++ partition@c0000 {
++ label = "Bootloader";
++ reg = <0xc0000 0x0080000>;
++ };
++
++ partition@140000 {
++ label = "Config";
++ reg = <0x140000 0x0080000>;
++ };
++
++ partition@1c0000 {
++ label = "Factory";
++ reg = <0x1c0000 0x0100000>;
++ };
++
++ partition@200000 {
++ label = "firmware";
++ reg = <0x2c0000 0x2000000>;
++ };
++
++ partition@2200000 {
++ label = "User_data";
++ reg = <0x22c0000 0x4000000>;
++ };
++ };
++ };
++};
++
+ &spi0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&spic0_pins>;
--- /dev/null
+--- a/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts
++++ b/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts
+@@ -575,7 +575,7 @@
+ reg = <0x140000 0x0080000>;
+ };
+
+- partition@1c0000 {
++ factory: partition@1c0000 {
+ label = "Factory";
+ reg = <0x1c0000 0x0100000>;
+ };
+@@ -636,5 +636,6 @@
+ &wmac {
+ pinctrl-names = "default";
+ pinctrl-0 = <&wmac_pins>;
++ mediatek,mtd-eeprom = <&factory 0x0000>;
+ status = "okay";
+ };
--- /dev/null
+--- a/arch/arm/boot/dts/mediatek/mt7623.dtsi
++++ b/arch/arm/boot/dts/mediatek/mt7623.dtsi
+@@ -995,17 +995,15 @@
+ };
+
+ crypto: crypto@1b240000 {
+- compatible = "mediatek,eip97-crypto";
++ compatible = "inside-secure,safexcel-eip97";
+ reg = <0 0x1b240000 0 0x20000>;
+ interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_SPI 83 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_SPI 84 IRQ_TYPE_LEVEL_LOW>,
+- <GIC_SPI 91 IRQ_TYPE_LEVEL_LOW>,
+- <GIC_SPI 97 IRQ_TYPE_LEVEL_LOW>;
++ <GIC_SPI 91 IRQ_TYPE_LEVEL_LOW>;
++ interrupt-names = "ring0", "ring1", "ring2", "ring3";
+ clocks = <ðsys CLK_ETHSYS_CRYPTO>;
+- clock-names = "cryp";
+- power-domains = <&scpsys MT2701_POWER_DOMAIN_ETH>;
+- status = "disabled";
++ status = "okay";
+ };
+
+ bdpsys: syscon@1c000000 {
--- /dev/null
+--- a/arch/arm/boot/dts/mediatek/mt7623n-bananapi-bpi-r2.dts
++++ b/arch/arm/boot/dts/mediatek/mt7623n-bananapi-bpi-r2.dts
+@@ -19,7 +19,7 @@
+
+ chosen {
+ stdout-path = "serial2:115200n8";
+- bootargs = "console=ttyS2,115200n8 console=tty1";
++ bootargs = "earlycon=uart8250,mmio32,0x11004000 console=ttyS2,115200n8 console=tty1";
+ };
+
+ connector {
--- /dev/null
+--- a/arch/arm/boot/dts/mediatek/mt7623n-bananapi-bpi-r2.dts
++++ b/arch/arm/boot/dts/mediatek/mt7623n-bananapi-bpi-r2.dts
+@@ -15,6 +15,8 @@
+
+ aliases {
+ serial2 = &uart2;
++ mmc0 = &mmc0;
++ mmc1 = &mmc1;
+ };
+
+ chosen {
--- /dev/null
+--- a/arch/arm/boot/dts/mediatek/mt7623n-bananapi-bpi-r2.dts
++++ b/arch/arm/boot/dts/mediatek/mt7623n-bananapi-bpi-r2.dts
+@@ -17,6 +17,10 @@
+ serial2 = &uart2;
+ mmc0 = &mmc0;
+ mmc1 = &mmc1;
++ led-boot = &led_system_green;
++ led-failsafe = &led_system_blue;
++ led-running = &led_system_green;
++ led-upgrade = &led_system_blue;
+ };
+
+ chosen {
+@@ -112,13 +116,13 @@
+ pinctrl-names = "default";
+ pinctrl-0 = <&led_pins_a>;
+
+- blue {
++ led_system_blue: blue {
+ label = "bpi-r2:pio:blue";
+ gpios = <&pio 240 GPIO_ACTIVE_LOW>;
+ default-state = "off";
+ };
+
+- green {
++ led_system_green: green {
+ label = "bpi-r2:pio:green";
+ gpios = <&pio 241 GPIO_ACTIVE_LOW>;
+ default-state = "off";
--- /dev/null
+--- a/arch/arm/boot/dts/mediatek/mt7623n-bananapi-bpi-r2.dts
++++ b/arch/arm/boot/dts/mediatek/mt7623n-bananapi-bpi-r2.dts
+@@ -15,6 +15,7 @@
+
+ aliases {
+ serial2 = &uart2;
++ ethernet0 = &gmac0;
+ mmc0 = &mmc0;
+ mmc1 = &mmc1;
+ led-boot = &led_system_green;
--- /dev/null
+--- a/arch/arm/boot/dts/mediatek/mt7623n-bananapi-bpi-r2.dts
++++ b/arch/arm/boot/dts/mediatek/mt7623n-bananapi-bpi-r2.dts
+@@ -26,7 +26,9 @@
+
+ chosen {
+ stdout-path = "serial2:115200n8";
+- bootargs = "earlycon=uart8250,mmio32,0x11004000 console=ttyS2,115200n8 console=tty1";
++ bootargs = "root=/dev/fit0 rootwait earlycon=uart8250,mmio32,0x11004000 console=ttyS2,115200n8 console=tty1";
++ rootdisk-emmc = <&emmc_rootdisk>;
++ rootdisk-sd = <&sd_rootdisk>;
+ };
+
+ connector {
+@@ -338,6 +340,22 @@
+ vmmc-supply = <®_3p3v>;
+ vqmmc-supply = <®_1p8v>;
+ non-removable;
++ #address-cells = <1>;
++ #size-cells = <0>;
++
++ card@0 {
++ compatible = "mmc-card";
++ reg = <0>;
++
++ block {
++ compatible = "block-device";
++ partitions {
++ emmc_rootdisk: block-partition-fit {
++ partno = <3>;
++ };
++ };
++ };
++ };
+ };
+
+ &mmc1 {
+@@ -351,6 +369,22 @@
+ cd-gpios = <&pio 261 GPIO_ACTIVE_LOW>;
+ vmmc-supply = <®_3p3v>;
+ vqmmc-supply = <®_3p3v>;
++ #address-cells = <1>;
++ #size-cells = <0>;
++
++ card@0 {
++ compatible = "mmc-card";
++ reg = <0>;
++
++ block {
++ compatible = "block-device";
++ partitions {
++ sd_rootdisk: block-partition-fit {
++ partno = <3>;
++ };
++ };
++ };
++ };
+ };
+
+ &mt6323keys {
--- /dev/null
+From patchwork Tue Apr 26 19:51:36 2022
+Content-Type: text/plain; charset="utf-8"
+MIME-Version: 1.0
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+ id 1njRDu-0006aF-4F; Tue, 26 Apr 2022 21:51:46 +0200
+Date: Tue, 26 Apr 2022 20:51:36 +0100
+From: Daniel Golle <daniel@makrotopia.org>
+To: devicetree@vger.kernel.org, linux-mediatek@lists.infradead.org,
+ linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org
+Cc: Rob Herring <robh+dt@kernel.org>,
+ Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
+ Matthias Brugger <matthias.bgg@gmail.com>
+Subject: [PATCH] arm64: dts: mediatek: mt7622: fix GICv2 range
+Message-ID: <YmhNSLgp/yg8Vr1F@makrotopia.org>
+MIME-Version: 1.0
+Content-Disposition: inline
+X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3
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+Errors-To:
+ linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org
+
+With the current range specified for the CPU interface there is an
+error message at boot:
+
+GIC: GICv2 detected, but range too small and irqchip.gicv2_force_probe not set
+
+Setting irqchip.gicv2_force_probe=1 in bootargs results in:
+
+GIC: Aliased GICv2 at 0x0000000010320000, trying to find the canonical range over 128kB
+GIC: Adjusting CPU interface base to 0x000000001032f000
+GIC: Using split EOI/Deactivate mode
+
+Using the adjusted CPU interface base and 8K size results in only the
+final line remaining and fully working system as well as /proc/interrupts
+showing additional IPI3,4,5,6:
+
+IPI3: 0 0 CPU stop (for crash dump) interrupts
+IPI4: 0 0 Timer broadcast interrupts
+IPI5: 0 0 IRQ work interrupts
+IPI6: 0 0 CPU wake-up interrupts
+
+Signed-off-by: Daniel Golle <daniel@makrotopia.org>
+---
+ arch/arm64/boot/dts/mediatek/mt7622.dtsi | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+--- a/arch/arm64/boot/dts/mediatek/mt7622.dtsi
++++ b/arch/arm64/boot/dts/mediatek/mt7622.dtsi
+@@ -345,7 +345,7 @@
+ #interrupt-cells = <3>;
+ interrupt-parent = <&gic>;
+ reg = <0 0x10310000 0 0x1000>,
+- <0 0x10320000 0 0x1000>,
++ <0 0x1032f000 0 0x2000>,
+ <0 0x10340000 0 0x2000>,
+ <0 0x10360000 0 0x2000>;
+ };
--- /dev/null
+From 824d56e753a588fcfd650db1822e34a02a48bb77 Mon Sep 17 00:00:00 2001
+From: Bruno Umuarama <anonimou_eu@hotmail.com>
+Date: Thu, 13 Oct 2022 21:18:21 +0000
+Subject: [PATCH] mediatek: mt7623: fix thermal zone
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Raising the temperatures for passive and active trips. @VA1DER
+proposed at issue 9396 to remove passive trip. This commit relates to
+his suggestion.
+
+Without this patch. the CPU will be throttled all the way down to 98MHz
+if the temperature rises even a degree above the trip point, and it was
+further discovered that if the internal temperature of the device is
+above the first trip point temperature when it boots then it will start
+in a throttled state and even
+$ echo disabled > /sys/class/thermal/thermal_zone0/mode
+will have no effect.
+
+The patch increases the passive trip point and active cooling map. The
+throttling temperature will then be at 77°C and 82°C, which is still a
+low enough temperature for ARM devices to not be in the real danger
+zone, and gives some operational headroom.
+
+Signed-off-by: Bruno Umuarama <anonimou_eu@hotmail.com>
+---
+ arch/arm/boot/dts/mediatek/mt7623.dtsi | 4 ++--
+ 1 file changed, 2 insertions(+), 2 deletions(-)
+
+--- a/arch/arm/boot/dts/mediatek/mt7623.dtsi
++++ b/arch/arm/boot/dts/mediatek/mt7623.dtsi
+@@ -160,13 +160,13 @@
+
+ trips {
+ cpu_passive: cpu-passive {
+- temperature = <57000>;
++ temperature = <77000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ cpu_active: cpu-active {
+- temperature = <67000>;
++ temperature = <82000>;
+ hysteresis = <2000>;
+ type = "active";
+ };
--- /dev/null
+--- a/arch/arm64/boot/dts/mediatek/mt7986a.dtsi
++++ b/arch/arm64/boot/dts/mediatek/mt7986a.dtsi
+@@ -68,6 +68,14 @@
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
++
++ /* 64 KiB reserved for ramoops/pstore */
++ ramoops@42ff0000 {
++ compatible = "ramoops";
++ reg = <0 0x42ff0000 0 0x10000>;
++ record-size = <0x1000>;
++ };
++
+ /* 192 KiB reserved for ARM Trusted Firmware (BL31) */
+ secmon_reserved: secmon@43000000 {
+ reg = <0 0x43000000 0 0x30000>;
--- /dev/null
+--- a/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3.dts
++++ b/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3.dts
+@@ -23,6 +23,10 @@
+ serial0 = &uart0;
+ ethernet0 = &gmac0;
+ ethernet1 = &gmac1;
++ led-boot = &green_led;
++ led-failsafe = &green_led;
++ led-running = &green_led;
++ led-upgrade = &blue_led;
+ };
+
+ chosen {
+@@ -419,27 +423,27 @@
+
+ port@1 {
+ reg = <1>;
+- label = "lan0";
++ label = "lan1";
+ };
+
+ port@2 {
+ reg = <2>;
+- label = "lan1";
++ label = "lan2";
+ };
+
+ port@3 {
+ reg = <3>;
+- label = "lan2";
++ label = "lan3";
+ };
+
+ port@4 {
+ reg = <4>;
+- label = "lan3";
++ label = "lan4";
+ };
+
+ port5: port@5 {
+ reg = <5>;
+- label = "lan4";
++ label = "sfp2";
+ phy-mode = "2500base-x";
+ sfp = <&sfp2>;
+ managed = "in-band-status";
+@@ -490,9 +494,137 @@
+
+ &wifi {
+ status = "okay";
+- pinctrl-names = "default", "dbdc";
++ pinctrl-names = "default";
+ pinctrl-0 = <&wf_2g_5g_pins>, <&wf_led_pins>;
+- pinctrl-1 = <&wf_dbdc_pins>, <&wf_led_pins>;
++
++ mediatek,eeprom-data = <0x86790900 0x000c4326 0x60000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
++ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
++ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x01000000
++ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
++ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
++ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
++ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
++ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
++ 0x00000000 0x00000800 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
++ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
++ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
++ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
++ 0x00000000 0x00000000 0x00000000 0x00000000 0x24649090 0x00280000 0x05100000 0x00000000
++ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
++ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
++ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
++ 0x00021e00 0x021e0002 0x1e00021e 0x00022800 0x02280002 0x28000228 0x00000000 0x00000000
++ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00008080 0x8080fdf7
++ 0x0903150d 0x80808080 0x80808080 0x05050d0d 0x1313c6c6 0xc3c3c200 0x00c200c2 0x00008182
++ 0x8585c2c2 0x82828282 0x858500c2 0xc2000081 0x82858587 0x87c2c200 0x81818285 0x858787c2
++ 0xc2000081 0x82858587 0x87c2c200 0x00818285 0x858787c2 0xc2000081 0x82858587 0x87c4c4c2
++ 0xc100c300 0xc3c3c100 0x818383c3 0xc3c3c100 0x81838300 0xc2c2c2c0 0x81828484 0x000000c3
++ 0xc3c3c100 0x81838386 0x86c3c3c3 0xc1008183 0x838686c2 0xc2c2c081 0x82848486 0x86c3c3c3
++ 0xc1008183 0x838686c3 0xc3c3c100 0x81838386 0x86c3c3c3 0xc1008183 0x83868622 0x28002228
++ 0x00222800 0x22280000 0xdddddddd 0xdddddddd 0xddbbbbbb 0xccccccdd 0xdddddddd 0xdddddddd
++ 0xeeeeeecc 0xccccdddd 0xdddddddd 0x004a5662 0x0000004a 0x56620000 0x004a5662 0x0000004a
++ 0x56620000 0x88888888 0x33333326 0x26262626 0x26262600 0x33333326 0x26262626 0x26262600
++ 0x33333326 0x26262626 0x26262600 0x33333326 0x26262626 0x26262600 0x00000000 0xf0f0cc00
++ 0x00000000 0x0000aaaa 0xaabbbbbb 0xcccccccc 0xccccbbbb 0xbbbbbbbb 0xbbbbbbaa 0xaaaabbbb
++ 0xbbaaaaaa 0x999999aa 0xaaaabbbb 0xbbcccccc 0x00000000 0x0000aaaa 0xaa000000 0xbbbbbbbb
++ 0xbbbbaaaa 0xaa999999 0xaaaaaaaa 0xaaaaaaaa 0xaaaaaaaa 0xaaaaaaaa 0xaaaabbbb 0xbbbbbbbb
++ 0x00000000 0x00000000 0x00000000 0x99999999 0x9999aaaa 0xaaaaaaaa 0x999999aa 0xaaaaaaaa
++ 0xaaaaaaaa 0xaaaaaaaa 0xaaaabbbb 0xbbbbbbbb 0x00000000 0x0000eeee 0xeeffffff 0xcccccccc
++ 0xccccdddd 0xddbbbbbb 0xccccccbb 0xbbbbbbbb 0xbbbbbbbb 0xbbbbbbbb 0xbbbbcccc 0xccdddddd
++ 0x00516200 0x686e0051 0x6200686e 0x00516200 0x686e0051 0x6200686e 0x00516200 0x686e0051
++ 0x6200686e 0x00516200 0x686e0051 0x6200686e 0x00516200 0x686e0051 0x6200686e 0x00516200
++ 0x686e0051 0x6200686e 0x00516200 0x686e0051 0x6200686e 0x00516200 0x686e0051 0x6200686e
++ 0x00516200 0x686e0051 0x6200686e 0x00516200 0x686e0051 0x6200686e 0x00516200 0x686e0051
++ 0x6200686e 0x00516200 0x686e0051 0x6200686e 0x00516200 0x686e0051 0x6200686e 0x00516200
++ 0x686e0051 0x6200686e 0x00516200 0x686e0051 0x6200686e 0x00516200 0x686e0051 0x6200686e
++ 0x88888888 0x88888888 0x88888888 0x88888888 0x88888888 0x88888888 0x88888888 0x88888888
++ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
++ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
++ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
++ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
++ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
++ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
++ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
++ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
++ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
++ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000001 0x06000100 0x01050002 0x00ff0300
++ 0xf900fe03 0x00000000 0x00000000 0x0000009b 0x6e370000 0x00000000 0x00fc0009 0x0a00fe00
++ 0x060700fe 0x00070800 0x05000b0a 0x00000000 0x00000000 0x000000e2 0x96460000 0x00000000
++ 0x000400f7 0xf8000300 0xfcfe0003 0x00fbfc00 0xee00e3f2 0x00000000 0x00000000 0x00000011
++ 0xbb550000 0x00000000 0x000600f6 0xfc000300 0xfbfe0004 0x00fafe00 0xf600ecf2 0x00000000
++ 0x00000000 0x0000001f 0xbf580000 0x00000000 0x000600f5 0xf6000400 0xf8f90004 0x00f7f800
++ 0xf700f0f4 0x00000000 0x00000000 0x00000024 0xbe570000 0x00000000 0x000800f8 0xfe000600
++ 0xf8fd0007 0x00f9fe00 0xf500f0f4 0x00000000 0x00000000 0x0000002d 0xd6610000 0x00000000
++ 0x000400f7 0xfc000500 0xf7fc0005 0x00f7fc00 0xf900f5f8 0x00000000 0x00000000 0x00000026
++ 0xd96e0000 0x00000000 0x000400f7 0xf9000600 0xf5f70005 0x00f5f800 0xf900f4f7 0x00000000
++ 0x00000000 0x0000001b 0xce690000 0x00000000 0x000300f8 0xf8000600 0xf6f60004 0x00f6f700
++ 0xf900f4f7 0x00000000 0x00000000 0x00000018 0xd8720000 0x00000000 0x00000000 0x02404002
++ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
++ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
++ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
++ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
++ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
++ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
++ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
++ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
++ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
++ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
++ 0xc1c2c1c2 0x41c341c3 0x3fc13fc1 0x40c13fc2 0x3fc240c1 0x41c040c0 0x3fc23fc2 0x40c13fc2
++ 0x3fc140c0 0x41c040c0 0x3fc33fc3 0x40c23fc2 0x3fc240c1 0x41c040c0 0x3fc23fc2 0x40c23fc2
++ 0x3fc140c1 0x41c040c0 0x00000000 0x00000000 0x41c741c7 0xc1c7c1c7 0x00000000 0x00000000
++ 0x3fc03fc0 0x3fc03fc0 0x3fc03fc0 0x3fc03fc0 0x3fc03fc0 0x3fc03fc0 0x3fc03fc0 0x3fc03fc0
++ 0x3fc03fc0 0x3fc03fc0 0x3fc03fc0 0x3fc03fc0 0x3fc03fc0 0x3fc03fc0 0x3fc03fc0 0x3fc03fc0
++ 0x00a0ce00 0x00000000 0xb6840000 0x00000000 0x00000000 0x00000000 0x18181818 0x18181818
++ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
++ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
++ 0x004b5763 0x0000004b 0x57630000 0x004b5763 0x0000004b 0x57630000 0x88888888 0x08474759
++ 0x69780849 0x49596d7a 0x0849495a 0x6d790848 0x48596c78 0x08484858 0x6a780848 0x48586a78
++ 0x08484858 0x6c78084a 0x4a5b6d79 0x08474759 0x697a0848 0x48596b79 0x08484859 0x6c7a0848
++ 0x48586c79 0x08484857 0x68770848 0x48576877 0x08484857 0x6a77084a 0x4a5a6a77 0x08464659
++ 0x69790848 0x48586b79 0x08484858 0x6c7a0848 0x48596c79 0x08484857 0x68770848 0x48576877
++ 0x08494958 0x6d7a084b 0x4b5c6c77 0x0847475a 0x6a7b0849 0x495a6e7c 0x0849495a 0x6e7c0849
++ 0x495b6e7c 0x08494959 0x6a7a0849 0x49596a7a 0x084a4a5a 0x6f7d084b 0x4b5c6e7b 0x00000000
++ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x85848484
++ 0xc3c4c4c5 0xc4c3c33f 0xc3c3c2c2 0xc2c2c03f 0xc3c3c3c4 0xc4c4c33f 0xc2c2c2c2 0xc1c3c1c1
++ 0xc0c08282 0x83848686 0x88880000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
++ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
++ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
++ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
++ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
++ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
++ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
++ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
++ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
++ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
++ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
++ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
++ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
++ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
++ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
++ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
++ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
++ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
++ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00001111 0x00000000
++ 0x8080f703 0x10808080 0x80050d13 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
++ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
++ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
++ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
++ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
++ 0x00000000 0x00000000 0x00000000 0x000000a4 0xce000000 0x0000b684 0x00000000 0x00000000
++ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
++ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
++ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
++ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
++ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
++ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
++ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
++ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
++ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
++ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
++ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
++ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
++ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
++ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000>;
+
+ led {
+ led-active-low;
+--- a/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-nor.dtso
++++ b/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-nor.dtso
+@@ -55,6 +55,7 @@
+ partition@c00000 {
+ label = "fit";
+ reg = <0xc00000 0x1400000>;
++ compatible = "denx,fit";
+ };
+ };
+ };
--- /dev/null
+--- a/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-emmc.dtso
++++ b/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-emmc.dtso
+@@ -23,7 +23,29 @@
+ no-sd;
+ no-sdio;
+ status = "okay";
++ #address-cells = <1>;
++ #size-cells = <0>;
++
++ card@0 {
++ compatible = "mmc-card";
++ reg = <0>;
++
++ block {
++ compatible = "block-device";
++ partitions {
++ emmc_rootdisk: block-partition-production {
++ partname = "production";
++ };
++ };
++ };
++ };
+ };
+ };
+-};
+
++ fragment@1 {
++ target-path = "/chosen";
++ __overlay__ {
++ rootdisk-emmc = <&emmc_rootdisk>;
++ };
++ };
++};
+--- a/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-nand.dtso
++++ b/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-nand.dtso
+@@ -29,27 +29,30 @@
+
+ partition@0 {
+ label = "bl2";
+- reg = <0x0 0x100000>;
++ reg = <0x0 0x200000>;
+ read-only;
+ };
+
+- partition@100000 {
+- label = "reserved";
+- reg = <0x100000 0x280000>;
+- };
+-
+- partition@380000 {
+- label = "fip";
+- reg = <0x380000 0x200000>;
+- read-only;
+- };
+-
+- partition@580000 {
++ partition@200000 {
+ label = "ubi";
+- reg = <0x580000 0x7a80000>;
++ reg = <0x200000 0x7e00000>;
++ compatible = "linux,ubi";
++
++ volumes {
++ nand_rootdisk: ubi-volume-fit {
++ volname = "fit";
++ };
++ };
+ };
+ };
+ };
+ };
+ };
++
++ fragment@1 {
++ target-path = "/chosen";
++ __overlay__ {
++ rootdisk-spim-nand = <&nand_rootdisk>;
++ };
++ };
+ };
+--- a/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-nor.dtso
++++ b/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-nor.dtso
+@@ -52,7 +52,7 @@
+ reg = <0x180000 0xa80000>;
+ };
+
+- partition@c00000 {
++ nor_rootdisk: partition@c00000 {
+ label = "fit";
+ reg = <0xc00000 0x1400000>;
+ compatible = "denx,fit";
+@@ -61,4 +61,11 @@
+ };
+ };
+ };
++
++ fragment@1 {
++ target-path = "/chosen";
++ __overlay__ {
++ rootdisk-nor = <&nor_rootdisk>;
++ };
++ };
+ };
+--- a/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-sd.dtso
++++ b/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-sd.dtso
+@@ -17,6 +17,29 @@
+ max-frequency = <52000000>;
+ cap-sd-highspeed;
+ status = "okay";
++ #address-cells = <1>;
++ #size-cells = <0>;
++
++ card@0 {
++ compatible = "mmc-card";
++ reg = <0>;
++
++ block {
++ compatible = "block-device";
++ partitions {
++ sd_rootdisk: block-partition-production {
++ partname = "production";
++ };
++ };
++ };
++ };
++ };
++ };
++
++ fragment@1 {
++ target-path = "/chosen";
++ __overlay__ {
++ rootdisk-sd = <&sd_rootdisk>;
+ };
+ };
+ };
--- /dev/null
+From 28f9a5e2a3f5441ab5594669ed82da11e32277a9 Mon Sep 17 00:00:00 2001
+From: Kristian Evensen <kristian.evensen@gmail.com>
+Date: Mon, 30 Apr 2018 14:38:01 +0200
+Subject: [PATCH] phy: phy-mtk-tphy: Add hifsys-support
+
+---
+ drivers/phy/mediatek/phy-mtk-tphy.c | 20 ++++++++++++++++++++
+ 1 file changed, 20 insertions(+)
+
+--- a/drivers/phy/mediatek/phy-mtk-tphy.c
++++ b/drivers/phy/mediatek/phy-mtk-tphy.c
+@@ -18,6 +18,8 @@
+ #include <linux/phy/phy.h>
+ #include <linux/platform_device.h>
+ #include <linux/regmap.h>
++#include <linux/mfd/syscon.h>
++#include <linux/regmap.h>
+
+ #include "phy-mtk-io.h"
+
+@@ -267,6 +269,9 @@
+
+ #define USER_BUF_LEN(count) min_t(size_t, 8, (count))
+
++#define HIF_SYSCFG1 0x14
++#define HIF_SYSCFG1_PHY2_MASK (0x3 << 20)
++
+ enum mtk_phy_version {
+ MTK_PHY_V1 = 1,
+ MTK_PHY_V2,
+@@ -334,6 +339,7 @@ struct mtk_tphy {
+ void __iomem *sif_base; /* only shared sif */
+ const struct mtk_phy_pdata *pdata;
+ struct mtk_phy_instance **phys;
++ struct regmap *hif;
+ int nphys;
+ int src_ref_clk; /* MHZ, reference clock for slew rate calibrate */
+ int src_coef; /* coefficient for slew rate calibrate */
+@@ -951,6 +957,10 @@ static void pcie_phy_instance_init(struc
+ if (tphy->pdata->version != MTK_PHY_V1)
+ return;
+
++ if (tphy->hif)
++ regmap_update_bits(tphy->hif, HIF_SYSCFG1,
++ HIF_SYSCFG1_PHY2_MASK, 0);
++
+ mtk_phy_update_bits(phya + U3P_U3_PHYA_DA_REG0,
+ P3A_RG_XTAL_EXT_PE1H | P3A_RG_XTAL_EXT_PE2H,
+ FIELD_PREP(P3A_RG_XTAL_EXT_PE1H, 0x2) |
+@@ -1597,6 +1607,16 @@ static int mtk_tphy_probe(struct platfor
+ &tphy->src_coef);
+ }
+
++ if (of_find_property(np, "mediatek,phy-switch", NULL)) {
++ tphy->hif = syscon_regmap_lookup_by_phandle(np,
++ "mediatek,phy-switch");
++ if (IS_ERR(tphy->hif)) {
++ dev_err(&pdev->dev,
++ "missing \"mediatek,phy-switch\" phandle\n");
++ return PTR_ERR(tphy->hif);
++ }
++ }
++
+ port = 0;
+ for_each_child_of_node(np, child_np) {
+ struct mtk_phy_instance *instance;
--- /dev/null
+From 11db447f257231e08065989100311df57b7f1f1c Mon Sep 17 00:00:00 2001
+From: Daniel Golle <daniel@makrotopia.org>
+Date: Sat, 26 Aug 2023 21:06:14 +0100
+Subject: [PATCH] pinctrl: mediatek: mt7981: add additional uart groups
+
+Add uart2_0_tx_rx (pin 4, 5) and uart1_2 (pins 9, 10) groups.
+
+Signed-off-by: Daniel Golle <daniel@makrotopia.org>
+---
+ drivers/pinctrl/mediatek/pinctrl-mt7981.c | 16 +++++++++++++---
+ 1 file changed, 13 insertions(+), 3 deletions(-)
+
+--- a/drivers/pinctrl/mediatek/pinctrl-mt7981.c
++++ b/drivers/pinctrl/mediatek/pinctrl-mt7981.c
+@@ -611,6 +611,9 @@ static int mt7981_wo0_jtag_1_funcs[] = {
+ static int mt7981_uart2_0_pins[] = { 4, 5, 6, 7, };
+ static int mt7981_uart2_0_funcs[] = { 3, 3, 3, 3, };
+
++static int mt7981_uart2_0_tx_rx_pins[] = { 4, 5, };
++static int mt7981_uart2_0_tx_rx_funcs[] = { 3, 3, };
++
+ /* GBE_LED0 */
+ static int mt7981_gbe_led0_pins[] = { 8, };
+ static int mt7981_gbe_led0_funcs[] = { 3, };
+@@ -731,6 +734,9 @@ static int mt7981_uart1_0_funcs[] = { 4,
+ static int mt7981_uart1_1_pins[] = { 26, 27, 28, 29, };
+ static int mt7981_uart1_1_funcs[] = { 2, 2, 2, 2, };
+
++static int mt7981_uart1_2_pins[] = { 9, 10, };
++static int mt7981_uart1_2_funcs[] = { 2, 2, };
++
+ /* UART2 */
+ static int mt7981_uart2_1_pins[] = { 22, 23, 24, 25, };
+ static int mt7981_uart2_1_funcs[] = { 3, 3, 3, 3, };
+@@ -805,6 +811,8 @@ static const struct group_desc mt7981_gr
+ PINCTRL_PIN_GROUP("wo0_jtag_0", mt7981_wo0_jtag_0),
+ /* @GPIO(4,7) WM_JTAG(3) */
+ PINCTRL_PIN_GROUP("uart2_0", mt7981_uart2_0),
++ /* @GPIO(4,5) WM_JTAG(4) */
++ PINCTRL_PIN_GROUP("uart2_0_tx_rx", mt7981_uart2_0_tx_rx),
+ /* @GPIO(8) GBE_LED0(3) */
+ PINCTRL_PIN_GROUP("gbe_led0", mt7981_gbe_led0),
+ /* @GPIO(4,6) PTA_EXT(4) */
+@@ -861,6 +869,8 @@ static const struct group_desc mt7981_gr
+ PINCTRL_PIN_GROUP("uart1_0", mt7981_uart1_0),
+ /* @GPIO(26,29): UART1(2) */
+ PINCTRL_PIN_GROUP("uart1_1", mt7981_uart1_1),
++ /* @GPIO(9,10): UART1(2) */
++ PINCTRL_PIN_GROUP("uart1_2", mt7981_uart1_2),
+ /* @GPIO(22,25): UART1(3) */
+ PINCTRL_PIN_GROUP("uart2_1", mt7981_uart2_1),
+ /* @GPIO(22,24) PTA_EXT(4) */
+@@ -922,9 +932,9 @@ static const struct group_desc mt7981_gr
+ */
+ static const char *mt7981_wa_aice_groups[] = { "wa_aice1", "wa_aice2", "wm_aice1_1",
+ "wa_aice3", "wm_aice1_2", };
+-static const char *mt7981_uart_groups[] = { "wm_uart_0", "uart2_0",
+- "net_wo0_uart_txd_0", "net_wo0_uart_txd_1", "net_wo0_uart_txd_2",
+- "uart1_0", "uart1_1", "uart2_1", "wm_aurt_1", "wm_aurt_2", "uart0", };
++static const char *mt7981_uart_groups[] = { "net_wo0_uart_txd_0", "net_wo0_uart_txd_1",
++ "net_wo0_uart_txd_2", "uart0", "uart1_0", "uart1_1", "uart1_2", "uart2_0",
++ "uart2_0_tx_rx", "uart2_1", "wm_uart_0", "wm_aurt_1", "wm_aurt_2", };
+ static const char *mt7981_dfd_groups[] = { "dfd", "dfd_ntrst", };
+ static const char *mt7981_wdt_groups[] = { "watchdog", "watchdog1", };
+ static const char *mt7981_pcie_groups[] = { "pcie_pereset", "pcie_clk", "pcie_wake", };
--- /dev/null
+--- a/drivers/pinctrl/mediatek/Kconfig
++++ b/drivers/pinctrl/mediatek/Kconfig
+@@ -187,6 +187,13 @@ config PINCTRL_MT7986
+ default ARM64 && ARCH_MEDIATEK
+ select PINCTRL_MTK_MOORE
+
++config PINCTRL_MT7988
++ bool "Mediatek MT7988 pin control"
++ depends on OF
++ depends on ARM64 || COMPILE_TEST
++ default ARCH_MEDIATEK
++ select PINCTRL_MTK_MOORE
++
+ config PINCTRL_MT8167
+ bool "MediaTek MT8167 pin control"
+ depends on OF
+--- a/drivers/pinctrl/mediatek/Makefile
++++ b/drivers/pinctrl/mediatek/Makefile
+@@ -27,6 +27,7 @@ obj-$(CONFIG_PINCTRL_MT7623) += pinctrl
+ obj-$(CONFIG_PINCTRL_MT7629) += pinctrl-mt7629.o
+ obj-$(CONFIG_PINCTRL_MT7981) += pinctrl-mt7981.o
+ obj-$(CONFIG_PINCTRL_MT7986) += pinctrl-mt7986.o
++obj-$(CONFIG_PINCTRL_MT7988) += pinctrl-mt7988.o
+ obj-$(CONFIG_PINCTRL_MT8167) += pinctrl-mt8167.o
+ obj-$(CONFIG_PINCTRL_MT8173) += pinctrl-mt8173.o
+ obj-$(CONFIG_PINCTRL_MT8183) += pinctrl-mt8183.o
--- /dev/null
+From 94b0f301f6ee92f79a2fe2c655dfdbdfe2aec536 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>
+Date: Sun, 19 Nov 2023 22:24:16 +0100
+Subject: [PATCH] dt-bindings: arm: mediatek: move ethsys controller & convert
+ to DT schema
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+DT schema helps validating DTS files. Binding was moved to clock/ as
+this hardware is a clock provider. Example required a small fix for
+"reg" value (1 address cell + 1 size cell).
+
+Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
+Reviewed-by: Rob Herring <robh@kernel.org>
+Link: https://lore.kernel.org/r/20231119212416.2682-1-zajec5@gmail.com
+Signed-off-by: Stephen Boyd <sboyd@kernel.org>
+---
+ .../bindings/arm/mediatek/mediatek,ethsys.txt | 29 ----------
+ .../bindings/clock/mediatek,ethsys.yaml | 54 +++++++++++++++++++
+ 2 files changed, 54 insertions(+), 29 deletions(-)
+ delete mode 100644 Documentation/devicetree/bindings/arm/mediatek/mediatek,ethsys.txt
+ create mode 100644 Documentation/devicetree/bindings/clock/mediatek,ethsys.yaml
+
+--- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,ethsys.txt
++++ /dev/null
+@@ -1,29 +0,0 @@
+-Mediatek ethsys controller
+-============================
+-
+-The Mediatek ethsys controller provides various clocks to the system.
+-
+-Required Properties:
+-
+-- compatible: Should be:
+- - "mediatek,mt2701-ethsys", "syscon"
+- - "mediatek,mt7622-ethsys", "syscon"
+- - "mediatek,mt7623-ethsys", "mediatek,mt2701-ethsys", "syscon"
+- - "mediatek,mt7629-ethsys", "syscon"
+- - "mediatek,mt7981-ethsys", "syscon"
+- - "mediatek,mt7986-ethsys", "syscon"
+-- #clock-cells: Must be 1
+-- #reset-cells: Must be 1
+-
+-The ethsys controller uses the common clk binding from
+-Documentation/devicetree/bindings/clock/clock-bindings.txt
+-The available clocks are defined in dt-bindings/clock/mt*-clk.h.
+-
+-Example:
+-
+-ethsys: clock-controller@1b000000 {
+- compatible = "mediatek,mt2701-ethsys", "syscon";
+- reg = <0 0x1b000000 0 0x1000>;
+- #clock-cells = <1>;
+- #reset-cells = <1>;
+-};
+--- /dev/null
++++ b/Documentation/devicetree/bindings/clock/mediatek,ethsys.yaml
+@@ -0,0 +1,54 @@
++# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
++%YAML 1.2
++---
++$id: http://devicetree.org/schemas/clock/mediatek,ethsys.yaml#
++$schema: http://devicetree.org/meta-schemas/core.yaml#
++
++title: Mediatek ethsys controller
++
++description:
++ The available clocks are defined in dt-bindings/clock/mt*-clk.h.
++
++maintainers:
++ - James Liao <jamesjj.liao@mediatek.com>
++
++properties:
++ compatible:
++ oneOf:
++ - items:
++ - enum:
++ - mediatek,mt2701-ethsys
++ - mediatek,mt7622-ethsys
++ - mediatek,mt7629-ethsys
++ - mediatek,mt7981-ethsys
++ - mediatek,mt7986-ethsys
++ - const: syscon
++ - items:
++ - const: mediatek,mt7623-ethsys
++ - const: mediatek,mt2701-ethsys
++ - const: syscon
++
++ reg:
++ maxItems: 1
++
++ "#clock-cells":
++ const: 1
++
++ "#reset-cells":
++ const: 1
++
++required:
++ - reg
++ - "#clock-cells"
++ - "#reset-cells"
++
++additionalProperties: false
++
++examples:
++ - |
++ clock-controller@1b000000 {
++ compatible = "mediatek,mt2701-ethsys", "syscon";
++ reg = <0x1b000000 0x1000>;
++ #clock-cells = <1>;
++ #reset-cells = <1>;
++ };
--- /dev/null
+From 5cfa3beb7761cb84be77225902e018d9d3f9b973 Mon Sep 17 00:00:00 2001
+From: Daniel Golle <daniel@makrotopia.org>
+Date: Sun, 17 Dec 2023 21:49:45 +0000
+Subject: [PATCH 1/4] dt-bindings: reset: mediatek: add MT7988 ethwarp reset
+ IDs
+
+Add reset ID for ethwarp subsystem allowing to reset the built-in
+Ethernet switch of the MediaTek MT7988 SoC.
+
+Signed-off-by: Daniel Golle <daniel@makrotopia.org>
+Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
+Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
+Link: https://lore.kernel.org/r/0c14bbacf471683af67ffa7572bfa1d5c45a0b5d.1702849494.git.daniel@makrotopia.org
+Signed-off-by: Stephen Boyd <sboyd@kernel.org>
+---
+ include/dt-bindings/reset/mediatek,mt7988-resets.h | 13 +++++++++++++
+ 1 file changed, 13 insertions(+)
+ create mode 100644 include/dt-bindings/reset/mediatek,mt7988-resets.h
+
+--- /dev/null
++++ b/include/dt-bindings/reset/mediatek,mt7988-resets.h
+@@ -0,0 +1,13 @@
++/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
++/*
++ * Copyright (c) 2023 Daniel Golle <daniel@makrotopia.org>
++ * Author: Daniel Golle <daniel@makrotopia.org>
++ */
++
++#ifndef _DT_BINDINGS_RESET_CONTROLLER_MT7988
++#define _DT_BINDINGS_RESET_CONTROLLER_MT7988
++
++/* ETHWARP resets */
++#define MT7988_ETHWARP_RST_SWITCH 0
++
++#endif /* _DT_BINDINGS_RESET_CONTROLLER_MT7988 */
--- /dev/null
+From 8187e001de156e99ef95366ffd10d627ed090826 Mon Sep 17 00:00:00 2001
+From: Sam Shih <sam.shih@mediatek.com>
+Date: Sun, 17 Dec 2023 21:49:33 +0000
+Subject: [PATCH] dt-bindings: clock: mediatek: add MT7988 clock IDs
+
+Add MT7988 clock dt-bindings for topckgen, apmixedsys, infracfg,
+ethernet and xfipll subsystem clocks.
+
+Signed-off-by: Sam Shih <sam.shih@mediatek.com>
+Signed-off-by: Daniel Golle <daniel@makrotopia.org>
+Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
+Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
+Link: https://lore.kernel.org/r/27f99db432e9ccc804cc5b6501d7d17d72cae879.1702849494.git.daniel@makrotopia.org
+Signed-off-by: Stephen Boyd <sboyd@kernel.org>
+---
+ .../dt-bindings/clock/mediatek,mt7988-clk.h | 280 ++++++++++++++++++
+ 1 file changed, 280 insertions(+)
+ create mode 100644 include/dt-bindings/clock/mediatek,mt7988-clk.h
+
+--- /dev/null
++++ b/include/dt-bindings/clock/mediatek,mt7988-clk.h
+@@ -0,0 +1,280 @@
++/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
++/*
++ * Copyright (c) 2023 MediaTek Inc.
++ * Author: Sam Shih <sam.shih@mediatek.com>
++ * Author: Xiufeng Li <Xiufeng.Li@mediatek.com>
++ */
++
++#ifndef _DT_BINDINGS_CLK_MT7988_H
++#define _DT_BINDINGS_CLK_MT7988_H
++
++/* APMIXEDSYS */
++
++#define CLK_APMIXED_NETSYSPLL 0
++#define CLK_APMIXED_MPLL 1
++#define CLK_APMIXED_MMPLL 2
++#define CLK_APMIXED_APLL2 3
++#define CLK_APMIXED_NET1PLL 4
++#define CLK_APMIXED_NET2PLL 5
++#define CLK_APMIXED_WEDMCUPLL 6
++#define CLK_APMIXED_SGMPLL 7
++#define CLK_APMIXED_ARM_B 8
++#define CLK_APMIXED_CCIPLL2_B 9
++#define CLK_APMIXED_USXGMIIPLL 10
++#define CLK_APMIXED_MSDCPLL 11
++
++/* TOPCKGEN */
++
++#define CLK_TOP_XTAL 0
++#define CLK_TOP_XTAL_D2 1
++#define CLK_TOP_RTC_32K 2
++#define CLK_TOP_RTC_32P7K 3
++#define CLK_TOP_MPLL_D2 4
++#define CLK_TOP_MPLL_D3_D2 5
++#define CLK_TOP_MPLL_D4 6
++#define CLK_TOP_MPLL_D8 7
++#define CLK_TOP_MPLL_D8_D2 8
++#define CLK_TOP_MMPLL_D2 9
++#define CLK_TOP_MMPLL_D3_D5 10
++#define CLK_TOP_MMPLL_D4 11
++#define CLK_TOP_MMPLL_D6_D2 12
++#define CLK_TOP_MMPLL_D8 13
++#define CLK_TOP_APLL2_D4 14
++#define CLK_TOP_NET1PLL_D4 15
++#define CLK_TOP_NET1PLL_D5 16
++#define CLK_TOP_NET1PLL_D5_D2 17
++#define CLK_TOP_NET1PLL_D5_D4 18
++#define CLK_TOP_NET1PLL_D8 19
++#define CLK_TOP_NET1PLL_D8_D2 20
++#define CLK_TOP_NET1PLL_D8_D4 21
++#define CLK_TOP_NET1PLL_D8_D8 22
++#define CLK_TOP_NET1PLL_D8_D16 23
++#define CLK_TOP_NET2PLL_D2 24
++#define CLK_TOP_NET2PLL_D4 25
++#define CLK_TOP_NET2PLL_D4_D4 26
++#define CLK_TOP_NET2PLL_D4_D8 27
++#define CLK_TOP_NET2PLL_D6 28
++#define CLK_TOP_NET2PLL_D8 29
++#define CLK_TOP_NETSYS_SEL 30
++#define CLK_TOP_NETSYS_500M_SEL 31
++#define CLK_TOP_NETSYS_2X_SEL 32
++#define CLK_TOP_NETSYS_GSW_SEL 33
++#define CLK_TOP_ETH_GMII_SEL 34
++#define CLK_TOP_NETSYS_MCU_SEL 35
++#define CLK_TOP_NETSYS_PAO_2X_SEL 36
++#define CLK_TOP_EIP197_SEL 37
++#define CLK_TOP_AXI_INFRA_SEL 38
++#define CLK_TOP_UART_SEL 39
++#define CLK_TOP_EMMC_250M_SEL 40
++#define CLK_TOP_EMMC_400M_SEL 41
++#define CLK_TOP_SPI_SEL 42
++#define CLK_TOP_SPIM_MST_SEL 43
++#define CLK_TOP_NFI1X_SEL 44
++#define CLK_TOP_SPINFI_SEL 45
++#define CLK_TOP_PWM_SEL 46
++#define CLK_TOP_I2C_SEL 47
++#define CLK_TOP_PCIE_MBIST_250M_SEL 48
++#define CLK_TOP_PEXTP_TL_SEL 49
++#define CLK_TOP_PEXTP_TL_P1_SEL 50
++#define CLK_TOP_PEXTP_TL_P2_SEL 51
++#define CLK_TOP_PEXTP_TL_P3_SEL 52
++#define CLK_TOP_USB_SYS_SEL 53
++#define CLK_TOP_USB_SYS_P1_SEL 54
++#define CLK_TOP_USB_XHCI_SEL 55
++#define CLK_TOP_USB_XHCI_P1_SEL 56
++#define CLK_TOP_USB_FRMCNT_SEL 57
++#define CLK_TOP_USB_FRMCNT_P1_SEL 58
++#define CLK_TOP_AUD_SEL 59
++#define CLK_TOP_A1SYS_SEL 60
++#define CLK_TOP_AUD_L_SEL 61
++#define CLK_TOP_A_TUNER_SEL 62
++#define CLK_TOP_SSPXTP_SEL 63
++#define CLK_TOP_USB_PHY_SEL 64
++#define CLK_TOP_USXGMII_SBUS_0_SEL 65
++#define CLK_TOP_USXGMII_SBUS_1_SEL 66
++#define CLK_TOP_SGM_0_SEL 67
++#define CLK_TOP_SGM_SBUS_0_SEL 68
++#define CLK_TOP_SGM_1_SEL 69
++#define CLK_TOP_SGM_SBUS_1_SEL 70
++#define CLK_TOP_XFI_PHY_0_XTAL_SEL 71
++#define CLK_TOP_XFI_PHY_1_XTAL_SEL 72
++#define CLK_TOP_SYSAXI_SEL 73
++#define CLK_TOP_SYSAPB_SEL 74
++#define CLK_TOP_ETH_REFCK_50M_SEL 75
++#define CLK_TOP_ETH_SYS_200M_SEL 76
++#define CLK_TOP_ETH_SYS_SEL 77
++#define CLK_TOP_ETH_XGMII_SEL 78
++#define CLK_TOP_BUS_TOPS_SEL 79
++#define CLK_TOP_NPU_TOPS_SEL 80
++#define CLK_TOP_DRAMC_SEL 81
++#define CLK_TOP_DRAMC_MD32_SEL 82
++#define CLK_TOP_INFRA_F26M_SEL 83
++#define CLK_TOP_PEXTP_P0_SEL 84
++#define CLK_TOP_PEXTP_P1_SEL 85
++#define CLK_TOP_PEXTP_P2_SEL 86
++#define CLK_TOP_PEXTP_P3_SEL 87
++#define CLK_TOP_DA_XTP_GLB_P0_SEL 88
++#define CLK_TOP_DA_XTP_GLB_P1_SEL 89
++#define CLK_TOP_DA_XTP_GLB_P2_SEL 90
++#define CLK_TOP_DA_XTP_GLB_P3_SEL 91
++#define CLK_TOP_CKM_SEL 92
++#define CLK_TOP_DA_SEL 93
++#define CLK_TOP_PEXTP_SEL 94
++#define CLK_TOP_TOPS_P2_26M_SEL 95
++#define CLK_TOP_MCUSYS_BACKUP_625M_SEL 96
++#define CLK_TOP_NETSYS_SYNC_250M_SEL 97
++#define CLK_TOP_MACSEC_SEL 98
++#define CLK_TOP_NETSYS_TOPS_400M_SEL 99
++#define CLK_TOP_NETSYS_PPEFB_250M_SEL 100
++#define CLK_TOP_NETSYS_WARP_SEL 101
++#define CLK_TOP_ETH_MII_SEL 102
++#define CLK_TOP_NPU_SEL 103
++#define CLK_TOP_AUD_I2S_M 104
++
++/* MCUSYS */
++
++#define CLK_MCU_BUS_DIV_SEL 0
++#define CLK_MCU_ARM_DIV_SEL 1
++
++/* INFRACFG_AO */
++
++#define CLK_INFRA_MUX_UART0_SEL 0
++#define CLK_INFRA_MUX_UART1_SEL 1
++#define CLK_INFRA_MUX_UART2_SEL 2
++#define CLK_INFRA_MUX_SPI0_SEL 3
++#define CLK_INFRA_MUX_SPI1_SEL 4
++#define CLK_INFRA_MUX_SPI2_SEL 5
++#define CLK_INFRA_PWM_SEL 6
++#define CLK_INFRA_PWM_CK1_SEL 7
++#define CLK_INFRA_PWM_CK2_SEL 8
++#define CLK_INFRA_PWM_CK3_SEL 9
++#define CLK_INFRA_PWM_CK4_SEL 10
++#define CLK_INFRA_PWM_CK5_SEL 11
++#define CLK_INFRA_PWM_CK6_SEL 12
++#define CLK_INFRA_PWM_CK7_SEL 13
++#define CLK_INFRA_PWM_CK8_SEL 14
++#define CLK_INFRA_PCIE_GFMUX_TL_O_P0_SEL 15
++#define CLK_INFRA_PCIE_GFMUX_TL_O_P1_SEL 16
++#define CLK_INFRA_PCIE_GFMUX_TL_O_P2_SEL 17
++#define CLK_INFRA_PCIE_GFMUX_TL_O_P3_SEL 18
++
++/* INFRACFG */
++
++#define CLK_INFRA_PCIE_PERI_26M_CK_P0 19
++#define CLK_INFRA_PCIE_PERI_26M_CK_P1 20
++#define CLK_INFRA_PCIE_PERI_26M_CK_P2 21
++#define CLK_INFRA_PCIE_PERI_26M_CK_P3 22
++#define CLK_INFRA_66M_GPT_BCK 23
++#define CLK_INFRA_66M_PWM_HCK 24
++#define CLK_INFRA_66M_PWM_BCK 25
++#define CLK_INFRA_66M_PWM_CK1 26
++#define CLK_INFRA_66M_PWM_CK2 27
++#define CLK_INFRA_66M_PWM_CK3 28
++#define CLK_INFRA_66M_PWM_CK4 29
++#define CLK_INFRA_66M_PWM_CK5 30
++#define CLK_INFRA_66M_PWM_CK6 31
++#define CLK_INFRA_66M_PWM_CK7 32
++#define CLK_INFRA_66M_PWM_CK8 33
++#define CLK_INFRA_133M_CQDMA_BCK 34
++#define CLK_INFRA_66M_AUD_SLV_BCK 35
++#define CLK_INFRA_AUD_26M 36
++#define CLK_INFRA_AUD_L 37
++#define CLK_INFRA_AUD_AUD 38
++#define CLK_INFRA_AUD_EG2 39
++#define CLK_INFRA_DRAMC_F26M 40
++#define CLK_INFRA_133M_DBG_ACKM 41
++#define CLK_INFRA_66M_AP_DMA_BCK 42
++#define CLK_INFRA_66M_SEJ_BCK 43
++#define CLK_INFRA_PRE_CK_SEJ_F13M 44
++#define CLK_INFRA_26M_THERM_SYSTEM 45
++#define CLK_INFRA_I2C_BCK 46
++#define CLK_INFRA_52M_UART0_CK 47
++#define CLK_INFRA_52M_UART1_CK 48
++#define CLK_INFRA_52M_UART2_CK 49
++#define CLK_INFRA_NFI 50
++#define CLK_INFRA_SPINFI 51
++#define CLK_INFRA_66M_NFI_HCK 52
++#define CLK_INFRA_104M_SPI0 53
++#define CLK_INFRA_104M_SPI1 54
++#define CLK_INFRA_104M_SPI2_BCK 55
++#define CLK_INFRA_66M_SPI0_HCK 56
++#define CLK_INFRA_66M_SPI1_HCK 57
++#define CLK_INFRA_66M_SPI2_HCK 58
++#define CLK_INFRA_66M_FLASHIF_AXI 59
++#define CLK_INFRA_RTC 60
++#define CLK_INFRA_26M_ADC_BCK 61
++#define CLK_INFRA_RC_ADC 62
++#define CLK_INFRA_MSDC400 63
++#define CLK_INFRA_MSDC2_HCK 64
++#define CLK_INFRA_133M_MSDC_0_HCK 65
++#define CLK_INFRA_66M_MSDC_0_HCK 66
++#define CLK_INFRA_133M_CPUM_BCK 67
++#define CLK_INFRA_BIST2FPC 68
++#define CLK_INFRA_I2C_X16W_MCK_CK_P1 69
++#define CLK_INFRA_I2C_X16W_PCK_CK_P1 70
++#define CLK_INFRA_133M_USB_HCK 71
++#define CLK_INFRA_133M_USB_HCK_CK_P1 72
++#define CLK_INFRA_66M_USB_HCK 73
++#define CLK_INFRA_66M_USB_HCK_CK_P1 74
++#define CLK_INFRA_USB_SYS 75
++#define CLK_INFRA_USB_SYS_CK_P1 76
++#define CLK_INFRA_USB_REF 77
++#define CLK_INFRA_USB_CK_P1 78
++#define CLK_INFRA_USB_FRMCNT 79
++#define CLK_INFRA_USB_FRMCNT_CK_P1 80
++#define CLK_INFRA_USB_PIPE 81
++#define CLK_INFRA_USB_PIPE_CK_P1 82
++#define CLK_INFRA_USB_UTMI 83
++#define CLK_INFRA_USB_UTMI_CK_P1 84
++#define CLK_INFRA_USB_XHCI 85
++#define CLK_INFRA_USB_XHCI_CK_P1 86
++#define CLK_INFRA_PCIE_GFMUX_TL_P0 87
++#define CLK_INFRA_PCIE_GFMUX_TL_P1 88
++#define CLK_INFRA_PCIE_GFMUX_TL_P2 89
++#define CLK_INFRA_PCIE_GFMUX_TL_P3 90
++#define CLK_INFRA_PCIE_PIPE_P0 91
++#define CLK_INFRA_PCIE_PIPE_P1 92
++#define CLK_INFRA_PCIE_PIPE_P2 93
++#define CLK_INFRA_PCIE_PIPE_P3 94
++#define CLK_INFRA_133M_PCIE_CK_P0 95
++#define CLK_INFRA_133M_PCIE_CK_P1 96
++#define CLK_INFRA_133M_PCIE_CK_P2 97
++#define CLK_INFRA_133M_PCIE_CK_P3 98
++
++/* ETHDMA */
++
++#define CLK_ETHDMA_XGP1_EN 0
++#define CLK_ETHDMA_XGP2_EN 1
++#define CLK_ETHDMA_XGP3_EN 2
++#define CLK_ETHDMA_FE_EN 3
++#define CLK_ETHDMA_GP2_EN 4
++#define CLK_ETHDMA_GP1_EN 5
++#define CLK_ETHDMA_GP3_EN 6
++#define CLK_ETHDMA_ESW_EN 7
++#define CLK_ETHDMA_CRYPT0_EN 8
++#define CLK_ETHDMA_NR_CLK 9
++
++/* SGMIISYS_0 */
++
++#define CLK_SGM0_TX_EN 0
++#define CLK_SGM0_RX_EN 1
++#define CLK_SGMII0_NR_CLK 2
++
++/* SGMIISYS_1 */
++
++#define CLK_SGM1_TX_EN 0
++#define CLK_SGM1_RX_EN 1
++#define CLK_SGMII1_NR_CLK 2
++
++/* ETHWARP */
++
++#define CLK_ETHWARP_WOCPU2_EN 0
++#define CLK_ETHWARP_WOCPU1_EN 1
++#define CLK_ETHWARP_WOCPU0_EN 2
++#define CLK_ETHWARP_NR_CLK 3
++
++/* XFIPLL */
++#define CLK_XFIPLL_PLL 0
++#define CLK_XFIPLL_PLL_EN 1
++
++#endif /* _DT_BINDINGS_CLK_MT7988_H */
--- /dev/null
+From afd36e9d91b0a840983b829a9e95407d8151f7e7 Mon Sep 17 00:00:00 2001
+From: Daniel Golle <daniel@makrotopia.org>
+Date: Sun, 17 Dec 2023 21:49:55 +0000
+Subject: [PATCH 2/4] dt-bindings: clock: mediatek: add clock controllers of
+ MT7988
+
+Add various clock controllers found in the MT7988 SoC to existing
+bindings (if applicable) and add files for the new ethwarp, mcusys
+and xfi-pll clock controllers not previously present in any SoC.
+
+Signed-off-by: Daniel Golle <daniel@makrotopia.org>
+Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
+Link: https://lore.kernel.org/r/07e76a544ce4392bcb88e34d5480e99bb7994618.1702849494.git.daniel@makrotopia.org
+Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
+Signed-off-by: Stephen Boyd <sboyd@kernel.org>
+---
+ .../arm/mediatek/mediatek,infracfg.yaml | 1 +
+ .../bindings/clock/mediatek,apmixedsys.yaml | 1 +
+ .../bindings/clock/mediatek,ethsys.yaml | 1 +
+ .../clock/mediatek,mt7988-ethwarp.yaml | 52 +++++++++++++++
+ .../clock/mediatek,mt7988-xfi-pll.yaml | 48 ++++++++++++++
+ .../bindings/clock/mediatek,topckgen.yaml | 2 +
+ .../bindings/net/pcs/mediatek,sgmiisys.yaml | 65 ++++++++++++++++---
+ 7 files changed, 161 insertions(+), 9 deletions(-)
+ create mode 100644 Documentation/devicetree/bindings/clock/mediatek,mt7988-ethwarp.yaml
+ create mode 100644 Documentation/devicetree/bindings/clock/mediatek,mt7988-xfi-pll.yaml
+
+--- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,infracfg.yaml
++++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,infracfg.yaml
+@@ -30,6 +30,7 @@ properties:
+ - mediatek,mt7629-infracfg
+ - mediatek,mt7981-infracfg
+ - mediatek,mt7986-infracfg
++ - mediatek,mt7988-infracfg
+ - mediatek,mt8135-infracfg
+ - mediatek,mt8167-infracfg
+ - mediatek,mt8173-infracfg
+--- a/Documentation/devicetree/bindings/clock/mediatek,apmixedsys.yaml
++++ b/Documentation/devicetree/bindings/clock/mediatek,apmixedsys.yaml
+@@ -22,6 +22,7 @@ properties:
+ - mediatek,mt7622-apmixedsys
+ - mediatek,mt7981-apmixedsys
+ - mediatek,mt7986-apmixedsys
++ - mediatek,mt7988-apmixedsys
+ - mediatek,mt8135-apmixedsys
+ - mediatek,mt8173-apmixedsys
+ - mediatek,mt8516-apmixedsys
+--- a/Documentation/devicetree/bindings/clock/mediatek,ethsys.yaml
++++ b/Documentation/devicetree/bindings/clock/mediatek,ethsys.yaml
+@@ -22,6 +22,7 @@ properties:
+ - mediatek,mt7629-ethsys
+ - mediatek,mt7981-ethsys
+ - mediatek,mt7986-ethsys
++ - mediatek,mt7988-ethsys
+ - const: syscon
+ - items:
+ - const: mediatek,mt7623-ethsys
+--- /dev/null
++++ b/Documentation/devicetree/bindings/clock/mediatek,mt7988-ethwarp.yaml
+@@ -0,0 +1,52 @@
++# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
++%YAML 1.2
++---
++$id: http://devicetree.org/schemas/clock/mediatek,mt7988-ethwarp.yaml#
++$schema: http://devicetree.org/meta-schemas/core.yaml#
++
++title: MediaTek MT7988 ethwarp Controller
++
++maintainers:
++ - Daniel Golle <daniel@makrotopia.org>
++
++description:
++ The Mediatek MT7988 ethwarp controller provides clocks and resets for the
++ Ethernet related subsystems found the MT7988 SoC.
++ The clock values can be found in <dt-bindings/clock/mt*-clk.h>.
++
++properties:
++ compatible:
++ items:
++ - const: mediatek,mt7988-ethwarp
++
++ reg:
++ maxItems: 1
++
++ '#clock-cells':
++ const: 1
++
++ '#reset-cells':
++ const: 1
++
++required:
++ - compatible
++ - reg
++ - '#clock-cells'
++ - '#reset-cells'
++
++additionalProperties: false
++
++examples:
++ - |
++ #include <dt-bindings/reset/ti-syscon.h>
++ soc {
++ #address-cells = <2>;
++ #size-cells = <2>;
++
++ clock-controller@15031000 {
++ compatible = "mediatek,mt7988-ethwarp";
++ reg = <0 0x15031000 0 0x1000>;
++ #clock-cells = <1>;
++ #reset-cells = <1>;
++ };
++ };
+--- /dev/null
++++ b/Documentation/devicetree/bindings/clock/mediatek,mt7988-xfi-pll.yaml
+@@ -0,0 +1,48 @@
++# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
++%YAML 1.2
++---
++$id: http://devicetree.org/schemas/clock/mediatek,mt7988-xfi-pll.yaml#
++$schema: http://devicetree.org/meta-schemas/core.yaml#
++
++title: MediaTek MT7988 XFI PLL Clock Controller
++
++maintainers:
++ - Daniel Golle <daniel@makrotopia.org>
++
++description:
++ The MediaTek XFI PLL controller provides the 156.25MHz clock for the
++ Ethernet SerDes PHY from the 40MHz top_xtal clock.
++
++properties:
++ compatible:
++ const: mediatek,mt7988-xfi-pll
++
++ reg:
++ maxItems: 1
++
++ resets:
++ maxItems: 1
++
++ '#clock-cells':
++ const: 1
++
++required:
++ - compatible
++ - reg
++ - resets
++ - '#clock-cells'
++
++additionalProperties: false
++
++examples:
++ - |
++ soc {
++ #address-cells = <2>;
++ #size-cells = <2>;
++ clock-controller@11f40000 {
++ compatible = "mediatek,mt7988-xfi-pll";
++ reg = <0 0x11f40000 0 0x1000>;
++ resets = <&watchdog 16>;
++ #clock-cells = <1>;
++ };
++ };
+--- a/Documentation/devicetree/bindings/clock/mediatek,topckgen.yaml
++++ b/Documentation/devicetree/bindings/clock/mediatek,topckgen.yaml
+@@ -37,6 +37,8 @@ properties:
+ - mediatek,mt7629-topckgen
+ - mediatek,mt7981-topckgen
+ - mediatek,mt7986-topckgen
++ - mediatek,mt7988-mcusys
++ - mediatek,mt7988-topckgen
+ - mediatek,mt8167-topckgen
+ - mediatek,mt8183-topckgen
+ - const: syscon
+--- a/Documentation/devicetree/bindings/net/pcs/mediatek,sgmiisys.yaml
++++ b/Documentation/devicetree/bindings/net/pcs/mediatek,sgmiisys.yaml
+@@ -15,15 +15,22 @@ description:
+
+ properties:
+ compatible:
+- items:
+- - enum:
+- - mediatek,mt7622-sgmiisys
+- - mediatek,mt7629-sgmiisys
+- - mediatek,mt7981-sgmiisys_0
+- - mediatek,mt7981-sgmiisys_1
+- - mediatek,mt7986-sgmiisys_0
+- - mediatek,mt7986-sgmiisys_1
+- - const: syscon
++ oneOf:
++ - items:
++ - enum:
++ - mediatek,mt7622-sgmiisys
++ - mediatek,mt7629-sgmiisys
++ - mediatek,mt7981-sgmiisys_0
++ - mediatek,mt7981-sgmiisys_1
++ - mediatek,mt7986-sgmiisys_0
++ - mediatek,mt7986-sgmiisys_1
++ - const: syscon
++ - items:
++ - enum:
++ - mediatek,mt7988-sgmiisys0
++ - mediatek,mt7988-sgmiisys1
++ - const: simple-mfd
++ - const: syscon
+
+ reg:
+ maxItems: 1
+@@ -35,11 +42,51 @@ properties:
+ description: Invert polarity of the SGMII data lanes
+ type: boolean
+
++ pcs:
++ type: object
++ description: MediaTek LynxI HSGMII PCS
++ properties:
++ compatible:
++ const: mediatek,mt7988-sgmii
++
++ clocks:
++ maxItems: 3
++
++ clock-names:
++ items:
++ - const: sgmii_sel
++ - const: sgmii_tx
++ - const: sgmii_rx
++
++ required:
++ - compatible
++ - clocks
++ - clock-names
++
++ additionalProperties: false
++
+ required:
+ - compatible
+ - reg
+ - '#clock-cells'
+
++allOf:
++ - if:
++ properties:
++ compatible:
++ contains:
++ enum:
++ - mediatek,mt7988-sgmiisys0
++ - mediatek,mt7988-sgmiisys1
++
++ then:
++ required:
++ - pcs
++
++ else:
++ properties:
++ pcs: false
++
+ additionalProperties: false
+
+ examples:
--- /dev/null
+From d9bf944beaaad1890ad3fcb755c61e1c7e4c5630 Mon Sep 17 00:00:00 2001
+From: Sam Shih <sam.shih@mediatek.com>
+Date: Sun, 17 Dec 2023 21:50:07 +0000
+Subject: [PATCH 3/4] clk: mediatek: add pcw_chg_bit control for PLLs of MT7988
+
+Introduce pcw_chg_bit member to struct mtk_pll_data and use it instead
+of the previously hardcoded PCW_CHG_MASK macro if set.
+This will needed for clocks on the MT7988 SoC.
+
+Signed-off-by: Sam Shih <sam.shih@mediatek.com>
+Signed-off-by: Daniel Golle <daniel@makrotopia.org>
+Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
+Link: https://lore.kernel.org/r/3b9c65ddb08c8bedf790aacf29871af026b6f0b7.1702849494.git.daniel@makrotopia.org
+Signed-off-by: Stephen Boyd <sboyd@kernel.org>
+---
+ drivers/clk/mediatek/clk-pll.c | 5 +++--
+ drivers/clk/mediatek/clk-pll.h | 1 +
+ 2 files changed, 4 insertions(+), 2 deletions(-)
+
+--- a/drivers/clk/mediatek/clk-pll.c
++++ b/drivers/clk/mediatek/clk-pll.c
+@@ -23,7 +23,7 @@
+ #define CON0_BASE_EN BIT(0)
+ #define CON0_PWR_ON BIT(0)
+ #define CON0_ISO_EN BIT(1)
+-#define PCW_CHG_MASK BIT(31)
++#define PCW_CHG_BIT 31
+
+ #define AUDPLL_TUNER_EN BIT(31)
+
+@@ -114,7 +114,8 @@ static void mtk_pll_set_rate_regs(struct
+ pll->data->pcw_shift);
+ val |= pcw << pll->data->pcw_shift;
+ writel(val, pll->pcw_addr);
+- chg = readl(pll->pcw_chg_addr) | PCW_CHG_MASK;
++ chg = readl(pll->pcw_chg_addr) |
++ BIT(pll->data->pcw_chg_bit ? : PCW_CHG_BIT);
+ writel(chg, pll->pcw_chg_addr);
+ if (pll->tuner_addr)
+ writel(val + 1, pll->tuner_addr);
+--- a/drivers/clk/mediatek/clk-pll.h
++++ b/drivers/clk/mediatek/clk-pll.h
+@@ -48,6 +48,7 @@ struct mtk_pll_data {
+ const char *parent_name;
+ u32 en_reg;
+ u8 pll_en_bit; /* Assume 0, indicates BIT(0) by default */
++ u8 pcw_chg_bit;
+ };
+
+ /*
--- /dev/null
+From 4b4719437d85f0173d344f2c76fa1a5b7f7d184b Mon Sep 17 00:00:00 2001
+From: Sam Shih <sam.shih@mediatek.com>
+Date: Sun, 17 Dec 2023 21:50:15 +0000
+Subject: [PATCH 4/4] clk: mediatek: add drivers for MT7988 SoC
+
+Add APMIXED, ETH, INFRACFG and TOPCKGEN clock drivers which are
+typical MediaTek designs.
+
+Also add driver for XFIPLL clock generating the 156.25MHz clock for
+the XFI SerDes. It needs an undocumented software workaround and has
+an unknown internal design.
+
+Signed-off-by: Sam Shih <sam.shih@mediatek.com>
+Signed-off-by: Daniel Golle <daniel@makrotopia.org>
+Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
+Link: https://lore.kernel.org/r/c7574d808e2da1a530182f0fd790c1337c336e1b.1702849494.git.daniel@makrotopia.org
+[sboyd@kernel.org: Add module license to infracfg file]
+Signed-off-by: Stephen Boyd <sboyd@kernel.org>
+---
+ drivers/clk/mediatek/Kconfig | 9 +
+ drivers/clk/mediatek/Makefile | 5 +
+ drivers/clk/mediatek/clk-mt7988-apmixed.c | 114 ++++++++
+ drivers/clk/mediatek/clk-mt7988-eth.c | 150 ++++++++++
+ drivers/clk/mediatek/clk-mt7988-infracfg.c | 275 +++++++++++++++++
+ drivers/clk/mediatek/clk-mt7988-topckgen.c | 325 +++++++++++++++++++++
+ drivers/clk/mediatek/clk-mt7988-xfipll.c | 82 ++++++
+ 7 files changed, 960 insertions(+)
+ create mode 100644 drivers/clk/mediatek/clk-mt7988-apmixed.c
+ create mode 100644 drivers/clk/mediatek/clk-mt7988-eth.c
+ create mode 100644 drivers/clk/mediatek/clk-mt7988-infracfg.c
+ create mode 100644 drivers/clk/mediatek/clk-mt7988-topckgen.c
+ create mode 100644 drivers/clk/mediatek/clk-mt7988-xfipll.c
+
+--- a/drivers/clk/mediatek/Kconfig
++++ b/drivers/clk/mediatek/Kconfig
+@@ -423,6 +423,15 @@ config COMMON_CLK_MT7986_ETHSYS
+ This driver adds support for clocks for Ethernet and SGMII
+ required on MediaTek MT7986 SoC.
+
++config COMMON_CLK_MT7988
++ tristate "Clock driver for MediaTek MT7988"
++ depends on ARCH_MEDIATEK || COMPILE_TEST
++ select COMMON_CLK_MEDIATEK
++ default ARCH_MEDIATEK
++ help
++ This driver supports MediaTek MT7988 basic clocks and clocks
++ required for various periperals found on this SoC.
++
+ config COMMON_CLK_MT8135
+ tristate "Clock driver for MediaTek MT8135"
+ depends on (ARCH_MEDIATEK && ARM) || COMPILE_TEST
+--- a/drivers/clk/mediatek/Makefile
++++ b/drivers/clk/mediatek/Makefile
+@@ -62,6 +62,11 @@ obj-$(CONFIG_COMMON_CLK_MT7986) += clk-m
+ obj-$(CONFIG_COMMON_CLK_MT7986) += clk-mt7986-topckgen.o
+ obj-$(CONFIG_COMMON_CLK_MT7986) += clk-mt7986-infracfg.o
+ obj-$(CONFIG_COMMON_CLK_MT7986_ETHSYS) += clk-mt7986-eth.o
++obj-$(CONFIG_COMMON_CLK_MT7988) += clk-mt7988-apmixed.o
++obj-$(CONFIG_COMMON_CLK_MT7988) += clk-mt7988-topckgen.o
++obj-$(CONFIG_COMMON_CLK_MT7988) += clk-mt7988-infracfg.o
++obj-$(CONFIG_COMMON_CLK_MT7988) += clk-mt7988-eth.o
++obj-$(CONFIG_COMMON_CLK_MT7988) += clk-mt7988-xfipll.o
+ obj-$(CONFIG_COMMON_CLK_MT8135) += clk-mt8135-apmixedsys.o clk-mt8135.o
+ obj-$(CONFIG_COMMON_CLK_MT8167) += clk-mt8167-apmixedsys.o clk-mt8167.o
+ obj-$(CONFIG_COMMON_CLK_MT8167_AUDSYS) += clk-mt8167-aud.o
+--- /dev/null
++++ b/drivers/clk/mediatek/clk-mt7988-apmixed.c
+@@ -0,0 +1,114 @@
++// SPDX-License-Identifier: GPL-2.0
++/*
++ * Copyright (c) 2023 MediaTek Inc.
++ * Author: Sam Shih <sam.shih@mediatek.com>
++ * Author: Xiufeng Li <Xiufeng.Li@mediatek.com>
++ */
++
++#include <linux/clk-provider.h>
++#include <linux/of.h>
++#include <linux/of_address.h>
++#include <linux/of_device.h>
++#include <linux/platform_device.h>
++#include "clk-mtk.h"
++#include "clk-gate.h"
++#include "clk-mux.h"
++#include "clk-pll.h"
++#include <dt-bindings/clock/mediatek,mt7988-clk.h>
++
++#define MT7988_PLL_FMAX (2500UL * MHZ)
++#define MT7988_PCW_CHG_BIT 2
++
++#define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _rst_bar_mask, _pcwbits, _pd_reg, \
++ _pd_shift, _tuner_reg, _tuner_en_reg, _tuner_en_bit, _pcw_reg, _pcw_shift, \
++ _pcw_chg_reg) \
++ { \
++ .id = _id, \
++ .name = _name, \
++ .reg = _reg, \
++ .pwr_reg = _pwr_reg, \
++ .en_mask = _en_mask, \
++ .flags = _flags, \
++ .rst_bar_mask = BIT(_rst_bar_mask), \
++ .fmax = MT7988_PLL_FMAX, \
++ .pcwbits = _pcwbits, \
++ .pd_reg = _pd_reg, \
++ .pd_shift = _pd_shift, \
++ .tuner_reg = _tuner_reg, \
++ .tuner_en_reg = _tuner_en_reg, \
++ .tuner_en_bit = _tuner_en_bit, \
++ .pcw_reg = _pcw_reg, \
++ .pcw_shift = _pcw_shift, \
++ .pcw_chg_reg = _pcw_chg_reg, \
++ .pcw_chg_bit = MT7988_PCW_CHG_BIT, \
++ .parent_name = "clkxtal", \
++ }
++
++static const struct mtk_pll_data plls[] = {
++ PLL(CLK_APMIXED_NETSYSPLL, "netsyspll", 0x0104, 0x0110, 0x00000001, 0, 0, 32, 0x0104, 4, 0,
++ 0, 0, 0x0108, 0, 0x0104),
++ PLL(CLK_APMIXED_MPLL, "mpll", 0x0114, 0x0120, 0xff000001, HAVE_RST_BAR, 23, 32, 0x0114, 4,
++ 0, 0, 0, 0x0118, 0, 0x0114),
++ PLL(CLK_APMIXED_MMPLL, "mmpll", 0x0124, 0x0130, 0xff000001, HAVE_RST_BAR, 23, 32, 0x0124, 4,
++ 0, 0, 0, 0x0128, 0, 0x0124),
++ PLL(CLK_APMIXED_APLL2, "apll2", 0x0134, 0x0140, 0x00000001, 0, 0, 32, 0x0134, 4, 0x0704,
++ 0x0700, 1, 0x0138, 0, 0x0134),
++ PLL(CLK_APMIXED_NET1PLL, "net1pll", 0x0144, 0x0150, 0xff000001, HAVE_RST_BAR, 23, 32,
++ 0x0144, 4, 0, 0, 0, 0x0148, 0, 0x0144),
++ PLL(CLK_APMIXED_NET2PLL, "net2pll", 0x0154, 0x0160, 0xff000001, (HAVE_RST_BAR | PLL_AO), 23,
++ 32, 0x0154, 4, 0, 0, 0, 0x0158, 0, 0x0154),
++ PLL(CLK_APMIXED_WEDMCUPLL, "wedmcupll", 0x0164, 0x0170, 0x00000001, 0, 0, 32, 0x0164, 4, 0,
++ 0, 0, 0x0168, 0, 0x0164),
++ PLL(CLK_APMIXED_SGMPLL, "sgmpll", 0x0174, 0x0180, 0x00000001, 0, 0, 32, 0x0174, 4, 0, 0, 0,
++ 0x0178, 0, 0x0174),
++ PLL(CLK_APMIXED_ARM_B, "arm_b", 0x0204, 0x0210, 0xff000001, (HAVE_RST_BAR | PLL_AO), 23, 32,
++ 0x0204, 4, 0, 0, 0, 0x0208, 0, 0x0204),
++ PLL(CLK_APMIXED_CCIPLL2_B, "ccipll2_b", 0x0214, 0x0220, 0xff000001, HAVE_RST_BAR, 23, 32,
++ 0x0214, 4, 0, 0, 0, 0x0218, 0, 0x0214),
++ PLL(CLK_APMIXED_USXGMIIPLL, "usxgmiipll", 0x0304, 0x0310, 0xff000001, HAVE_RST_BAR, 23, 32,
++ 0x0304, 4, 0, 0, 0, 0x0308, 0, 0x0304),
++ PLL(CLK_APMIXED_MSDCPLL, "msdcpll", 0x0314, 0x0320, 0x00000001, 0, 0, 32, 0x0314, 4, 0, 0,
++ 0, 0x0318, 0, 0x0314),
++};
++
++static const struct of_device_id of_match_clk_mt7988_apmixed[] = {
++ { .compatible = "mediatek,mt7988-apmixedsys" },
++ { /* sentinel */ }
++};
++
++static int clk_mt7988_apmixed_probe(struct platform_device *pdev)
++{
++ struct clk_hw_onecell_data *clk_data;
++ struct device_node *node = pdev->dev.of_node;
++ int r;
++
++ clk_data = mtk_alloc_clk_data(ARRAY_SIZE(plls));
++ if (!clk_data)
++ return -ENOMEM;
++
++ r = mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data);
++ if (r)
++ goto free_apmixed_data;
++
++ r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
++ if (r)
++ goto unregister_plls;
++
++ return r;
++
++unregister_plls:
++ mtk_clk_unregister_plls(plls, ARRAY_SIZE(plls), clk_data);
++free_apmixed_data:
++ mtk_free_clk_data(clk_data);
++ return r;
++}
++
++static struct platform_driver clk_mt7988_apmixed_drv = {
++ .probe = clk_mt7988_apmixed_probe,
++ .driver = {
++ .name = "clk-mt7988-apmixed",
++ .of_match_table = of_match_clk_mt7988_apmixed,
++ },
++};
++builtin_platform_driver(clk_mt7988_apmixed_drv);
++MODULE_LICENSE("GPL");
+--- /dev/null
++++ b/drivers/clk/mediatek/clk-mt7988-eth.c
+@@ -0,0 +1,150 @@
++// SPDX-License-Identifier: GPL-2.0
++/*
++ * Copyright (c) 2023 MediaTek Inc.
++ * Author: Sam Shih <sam.shih@mediatek.com>
++ * Author: Xiufeng Li <Xiufeng.Li@mediatek.com>
++ */
++
++#include <linux/clk-provider.h>
++#include <linux/of.h>
++#include <linux/of_address.h>
++#include <linux/of_device.h>
++#include <linux/platform_device.h>
++#include "clk-mtk.h"
++#include "clk-gate.h"
++#include "reset.h"
++#include <dt-bindings/clock/mediatek,mt7988-clk.h>
++#include <dt-bindings/reset/mediatek,mt7988-resets.h>
++
++static const struct mtk_gate_regs ethdma_cg_regs = {
++ .set_ofs = 0x30,
++ .clr_ofs = 0x30,
++ .sta_ofs = 0x30,
++};
++
++#define GATE_ETHDMA(_id, _name, _parent, _shift) \
++ { \
++ .id = _id, \
++ .name = _name, \
++ .parent_name = _parent, \
++ .regs = ðdma_cg_regs, \
++ .shift = _shift, \
++ .ops = &mtk_clk_gate_ops_no_setclr_inv, \
++ }
++
++static const struct mtk_gate ethdma_clks[] = {
++ GATE_ETHDMA(CLK_ETHDMA_XGP1_EN, "ethdma_xgp1_en", "top_xtal", 0),
++ GATE_ETHDMA(CLK_ETHDMA_XGP2_EN, "ethdma_xgp2_en", "top_xtal", 1),
++ GATE_ETHDMA(CLK_ETHDMA_XGP3_EN, "ethdma_xgp3_en", "top_xtal", 2),
++ GATE_ETHDMA(CLK_ETHDMA_FE_EN, "ethdma_fe_en", "netsys_2x_sel", 6),
++ GATE_ETHDMA(CLK_ETHDMA_GP2_EN, "ethdma_gp2_en", "top_xtal", 7),
++ GATE_ETHDMA(CLK_ETHDMA_GP1_EN, "ethdma_gp1_en", "top_xtal", 8),
++ GATE_ETHDMA(CLK_ETHDMA_GP3_EN, "ethdma_gp3_en", "top_xtal", 10),
++ GATE_ETHDMA(CLK_ETHDMA_ESW_EN, "ethdma_esw_en", "netsys_gsw_sel", 16),
++ GATE_ETHDMA(CLK_ETHDMA_CRYPT0_EN, "ethdma_crypt0_en", "eip197_sel", 29),
++};
++
++static const struct mtk_clk_desc ethdma_desc = {
++ .clks = ethdma_clks,
++ .num_clks = ARRAY_SIZE(ethdma_clks),
++};
++
++static const struct mtk_gate_regs sgmii_cg_regs = {
++ .set_ofs = 0xe4,
++ .clr_ofs = 0xe4,
++ .sta_ofs = 0xe4,
++};
++
++#define GATE_SGMII(_id, _name, _parent, _shift) \
++ { \
++ .id = _id, \
++ .name = _name, \
++ .parent_name = _parent, \
++ .regs = &sgmii_cg_regs, \
++ .shift = _shift, \
++ .ops = &mtk_clk_gate_ops_no_setclr_inv, \
++ }
++
++static const struct mtk_gate sgmii0_clks[] = {
++ GATE_SGMII(CLK_SGM0_TX_EN, "sgm0_tx_en", "top_xtal", 2),
++ GATE_SGMII(CLK_SGM0_RX_EN, "sgm0_rx_en", "top_xtal", 3),
++};
++
++static const struct mtk_clk_desc sgmii0_desc = {
++ .clks = sgmii0_clks,
++ .num_clks = ARRAY_SIZE(sgmii0_clks),
++};
++
++static const struct mtk_gate sgmii1_clks[] = {
++ GATE_SGMII(CLK_SGM1_TX_EN, "sgm1_tx_en", "top_xtal", 2),
++ GATE_SGMII(CLK_SGM1_RX_EN, "sgm1_rx_en", "top_xtal", 3),
++};
++
++static const struct mtk_clk_desc sgmii1_desc = {
++ .clks = sgmii1_clks,
++ .num_clks = ARRAY_SIZE(sgmii1_clks),
++};
++
++static const struct mtk_gate_regs ethwarp_cg_regs = {
++ .set_ofs = 0x14,
++ .clr_ofs = 0x14,
++ .sta_ofs = 0x14,
++};
++
++#define GATE_ETHWARP(_id, _name, _parent, _shift) \
++ { \
++ .id = _id, \
++ .name = _name, \
++ .parent_name = _parent, \
++ .regs = ðwarp_cg_regs, \
++ .shift = _shift, \
++ .ops = &mtk_clk_gate_ops_no_setclr_inv, \
++ }
++
++static const struct mtk_gate ethwarp_clks[] = {
++ GATE_ETHWARP(CLK_ETHWARP_WOCPU2_EN, "ethwarp_wocpu2_en", "netsys_mcu_sel", 13),
++ GATE_ETHWARP(CLK_ETHWARP_WOCPU1_EN, "ethwarp_wocpu1_en", "netsys_mcu_sel", 14),
++ GATE_ETHWARP(CLK_ETHWARP_WOCPU0_EN, "ethwarp_wocpu0_en", "netsys_mcu_sel", 15),
++};
++
++static u16 ethwarp_rst_ofs[] = { 0x8 };
++
++static u16 ethwarp_idx_map[] = {
++ [MT7988_ETHWARP_RST_SWITCH] = 9,
++};
++
++static const struct mtk_clk_rst_desc ethwarp_rst_desc = {
++ .version = MTK_RST_SIMPLE,
++ .rst_bank_ofs = ethwarp_rst_ofs,
++ .rst_bank_nr = ARRAY_SIZE(ethwarp_rst_ofs),
++ .rst_idx_map = ethwarp_idx_map,
++ .rst_idx_map_nr = ARRAY_SIZE(ethwarp_idx_map),
++};
++
++static const struct mtk_clk_desc ethwarp_desc = {
++ .clks = ethwarp_clks,
++ .num_clks = ARRAY_SIZE(ethwarp_clks),
++ .rst_desc = ðwarp_rst_desc,
++};
++
++static const struct of_device_id of_match_clk_mt7988_eth[] = {
++ { .compatible = "mediatek,mt7988-ethsys", .data = ðdma_desc },
++ { .compatible = "mediatek,mt7988-sgmiisys0", .data = &sgmii0_desc },
++ { .compatible = "mediatek,mt7988-sgmiisys1", .data = &sgmii1_desc },
++ { .compatible = "mediatek,mt7988-ethwarp", .data = ðwarp_desc },
++ { /* sentinel */ }
++};
++MODULE_DEVICE_TABLE(of, of_match_clk_mt7988_eth);
++
++static struct platform_driver clk_mt7988_eth_drv = {
++ .driver = {
++ .name = "clk-mt7988-eth",
++ .of_match_table = of_match_clk_mt7988_eth,
++ },
++ .probe = mtk_clk_simple_probe,
++ .remove_new = mtk_clk_simple_remove,
++};
++module_platform_driver(clk_mt7988_eth_drv);
++
++MODULE_DESCRIPTION("MediaTek MT7988 Ethernet clocks driver");
++MODULE_LICENSE("GPL");
+--- /dev/null
++++ b/drivers/clk/mediatek/clk-mt7988-infracfg.c
+@@ -0,0 +1,275 @@
++// SPDX-License-Identifier: GPL-2.0
++/*
++ * Copyright (c) 2023 MediaTek Inc.
++ * Author: Sam Shih <sam.shih@mediatek.com>
++ * Author: Xiufeng Li <Xiufeng.Li@mediatek.com>
++ */
++
++#include <linux/clk-provider.h>
++#include <linux/of.h>
++#include <linux/of_address.h>
++#include <linux/of_device.h>
++#include <linux/platform_device.h>
++#include "clk-mtk.h"
++#include "clk-gate.h"
++#include "clk-mux.h"
++#include <dt-bindings/clock/mediatek,mt7988-clk.h>
++
++static DEFINE_SPINLOCK(mt7988_clk_lock);
++
++static const char *const infra_mux_uart0_parents[] __initconst = { "csw_infra_f26m_sel",
++ "uart_sel" };
++
++static const char *const infra_mux_uart1_parents[] __initconst = { "csw_infra_f26m_sel",
++ "uart_sel" };
++
++static const char *const infra_mux_uart2_parents[] __initconst = { "csw_infra_f26m_sel",
++ "uart_sel" };
++
++static const char *const infra_mux_spi0_parents[] __initconst = { "i2c_sel", "spi_sel" };
++
++static const char *const infra_mux_spi1_parents[] __initconst = { "i2c_sel", "spim_mst_sel" };
++
++static const char *const infra_pwm_bck_parents[] __initconst = { "top_rtc_32p7k",
++ "csw_infra_f26m_sel", "sysaxi_sel",
++ "pwm_sel" };
++
++static const char *const infra_pcie_gfmux_tl_ck_o_p0_parents[] __initconst = {
++ "top_rtc_32p7k", "csw_infra_f26m_sel", "csw_infra_f26m_sel", "pextp_tl_sel"
++};
++
++static const char *const infra_pcie_gfmux_tl_ck_o_p1_parents[] __initconst = {
++ "top_rtc_32p7k", "csw_infra_f26m_sel", "csw_infra_f26m_sel", "pextp_tl_p1_sel"
++};
++
++static const char *const infra_pcie_gfmux_tl_ck_o_p2_parents[] __initconst = {
++ "top_rtc_32p7k", "csw_infra_f26m_sel", "csw_infra_f26m_sel", "pextp_tl_p2_sel"
++};
++
++static const char *const infra_pcie_gfmux_tl_ck_o_p3_parents[] __initconst = {
++ "top_rtc_32p7k", "csw_infra_f26m_sel", "csw_infra_f26m_sel", "pextp_tl_p3_sel"
++};
++
++static const struct mtk_mux infra_muxes[] = {
++ /* MODULE_CLK_SEL_0 */
++ MUX_GATE_CLR_SET_UPD(CLK_INFRA_MUX_UART0_SEL, "infra_mux_uart0_sel",
++ infra_mux_uart0_parents, 0x0018, 0x0010, 0x0014, 0, 1, -1, -1, -1),
++ MUX_GATE_CLR_SET_UPD(CLK_INFRA_MUX_UART1_SEL, "infra_mux_uart1_sel",
++ infra_mux_uart1_parents, 0x0018, 0x0010, 0x0014, 1, 1, -1, -1, -1),
++ MUX_GATE_CLR_SET_UPD(CLK_INFRA_MUX_UART2_SEL, "infra_mux_uart2_sel",
++ infra_mux_uart2_parents, 0x0018, 0x0010, 0x0014, 2, 1, -1, -1, -1),
++ MUX_GATE_CLR_SET_UPD(CLK_INFRA_MUX_SPI0_SEL, "infra_mux_spi0_sel", infra_mux_spi0_parents,
++ 0x0018, 0x0010, 0x0014, 4, 1, -1, -1, -1),
++ MUX_GATE_CLR_SET_UPD(CLK_INFRA_MUX_SPI1_SEL, "infra_mux_spi1_sel", infra_mux_spi1_parents,
++ 0x0018, 0x0010, 0x0014, 5, 1, -1, -1, -1),
++ MUX_GATE_CLR_SET_UPD(CLK_INFRA_MUX_SPI2_SEL, "infra_mux_spi2_sel", infra_mux_spi0_parents,
++ 0x0018, 0x0010, 0x0014, 6, 1, -1, -1, -1),
++ MUX_GATE_CLR_SET_UPD(CLK_INFRA_PWM_SEL, "infra_pwm_sel", infra_pwm_bck_parents, 0x0018,
++ 0x0010, 0x0014, 14, 2, -1, -1, -1),
++ MUX_GATE_CLR_SET_UPD(CLK_INFRA_PWM_CK1_SEL, "infra_pwm_ck1_sel", infra_pwm_bck_parents,
++ 0x0018, 0x0010, 0x0014, 16, 2, -1, -1, -1),
++ MUX_GATE_CLR_SET_UPD(CLK_INFRA_PWM_CK2_SEL, "infra_pwm_ck2_sel", infra_pwm_bck_parents,
++ 0x0018, 0x0010, 0x0014, 18, 2, -1, -1, -1),
++ MUX_GATE_CLR_SET_UPD(CLK_INFRA_PWM_CK3_SEL, "infra_pwm_ck3_sel", infra_pwm_bck_parents,
++ 0x0018, 0x0010, 0x0014, 20, 2, -1, -1, -1),
++ MUX_GATE_CLR_SET_UPD(CLK_INFRA_PWM_CK4_SEL, "infra_pwm_ck4_sel", infra_pwm_bck_parents,
++ 0x0018, 0x0010, 0x0014, 22, 2, -1, -1, -1),
++ MUX_GATE_CLR_SET_UPD(CLK_INFRA_PWM_CK5_SEL, "infra_pwm_ck5_sel", infra_pwm_bck_parents,
++ 0x0018, 0x0010, 0x0014, 24, 2, -1, -1, -1),
++ MUX_GATE_CLR_SET_UPD(CLK_INFRA_PWM_CK6_SEL, "infra_pwm_ck6_sel", infra_pwm_bck_parents,
++ 0x0018, 0x0010, 0x0014, 26, 2, -1, -1, -1),
++ MUX_GATE_CLR_SET_UPD(CLK_INFRA_PWM_CK7_SEL, "infra_pwm_ck7_sel", infra_pwm_bck_parents,
++ 0x0018, 0x0010, 0x0014, 28, 2, -1, -1, -1),
++ MUX_GATE_CLR_SET_UPD(CLK_INFRA_PWM_CK8_SEL, "infra_pwm_ck8_sel", infra_pwm_bck_parents,
++ 0x0018, 0x0010, 0x0014, 30, 2, -1, -1, -1),
++ /* MODULE_CLK_SEL_1 */
++ MUX_GATE_CLR_SET_UPD(CLK_INFRA_PCIE_GFMUX_TL_O_P0_SEL, "infra_pcie_gfmux_tl_o_p0_sel",
++ infra_pcie_gfmux_tl_ck_o_p0_parents, 0x0028, 0x0020, 0x0024, 0, 2, -1,
++ -1, -1),
++ MUX_GATE_CLR_SET_UPD(CLK_INFRA_PCIE_GFMUX_TL_O_P1_SEL, "infra_pcie_gfmux_tl_o_p1_sel",
++ infra_pcie_gfmux_tl_ck_o_p1_parents, 0x0028, 0x0020, 0x0024, 2, 2, -1,
++ -1, -1),
++ MUX_GATE_CLR_SET_UPD(CLK_INFRA_PCIE_GFMUX_TL_O_P2_SEL, "infra_pcie_gfmux_tl_o_p2_sel",
++ infra_pcie_gfmux_tl_ck_o_p2_parents, 0x0028, 0x0020, 0x0024, 4, 2, -1,
++ -1, -1),
++ MUX_GATE_CLR_SET_UPD(CLK_INFRA_PCIE_GFMUX_TL_O_P3_SEL, "infra_pcie_gfmux_tl_o_p3_sel",
++ infra_pcie_gfmux_tl_ck_o_p3_parents, 0x0028, 0x0020, 0x0024, 6, 2, -1,
++ -1, -1),
++};
++
++static const struct mtk_gate_regs infra0_cg_regs = {
++ .set_ofs = 0x10,
++ .clr_ofs = 0x14,
++ .sta_ofs = 0x18,
++};
++
++static const struct mtk_gate_regs infra1_cg_regs = {
++ .set_ofs = 0x40,
++ .clr_ofs = 0x44,
++ .sta_ofs = 0x48,
++};
++
++static const struct mtk_gate_regs infra2_cg_regs = {
++ .set_ofs = 0x50,
++ .clr_ofs = 0x54,
++ .sta_ofs = 0x58,
++};
++
++static const struct mtk_gate_regs infra3_cg_regs = {
++ .set_ofs = 0x60,
++ .clr_ofs = 0x64,
++ .sta_ofs = 0x68,
++};
++
++#define GATE_INFRA0_FLAGS(_id, _name, _parent, _shift, _flags) \
++ GATE_MTK_FLAGS(_id, _name, _parent, &infra0_cg_regs, _shift, &mtk_clk_gate_ops_setclr, \
++ _flags)
++
++#define GATE_INFRA1_FLAGS(_id, _name, _parent, _shift, _flags) \
++ GATE_MTK_FLAGS(_id, _name, _parent, &infra1_cg_regs, _shift, &mtk_clk_gate_ops_setclr, \
++ _flags)
++
++#define GATE_INFRA2_FLAGS(_id, _name, _parent, _shift, _flags) \
++ GATE_MTK_FLAGS(_id, _name, _parent, &infra2_cg_regs, _shift, &mtk_clk_gate_ops_setclr, \
++ _flags)
++
++#define GATE_INFRA3_FLAGS(_id, _name, _parent, _shift, _flags) \
++ GATE_MTK_FLAGS(_id, _name, _parent, &infra3_cg_regs, _shift, &mtk_clk_gate_ops_setclr, \
++ _flags)
++
++#define GATE_INFRA0(_id, _name, _parent, _shift) GATE_INFRA0_FLAGS(_id, _name, _parent, _shift, 0)
++
++#define GATE_INFRA1(_id, _name, _parent, _shift) GATE_INFRA1_FLAGS(_id, _name, _parent, _shift, 0)
++
++#define GATE_INFRA2(_id, _name, _parent, _shift) GATE_INFRA2_FLAGS(_id, _name, _parent, _shift, 0)
++
++#define GATE_INFRA3(_id, _name, _parent, _shift) GATE_INFRA3_FLAGS(_id, _name, _parent, _shift, 0)
++
++static const struct mtk_gate infra_clks[] = {
++ /* INFRA0 */
++ GATE_INFRA0(CLK_INFRA_PCIE_PERI_26M_CK_P0, "infra_pcie_peri_ck_26m_ck_p0",
++ "csw_infra_f26m_sel", 7),
++ GATE_INFRA0(CLK_INFRA_PCIE_PERI_26M_CK_P1, "infra_pcie_peri_ck_26m_ck_p1",
++ "csw_infra_f26m_sel", 8),
++ GATE_INFRA0(CLK_INFRA_PCIE_PERI_26M_CK_P2, "infra_pcie_peri_ck_26m_ck_p2",
++ "csw_infra_f26m_sel", 9),
++ GATE_INFRA0(CLK_INFRA_PCIE_PERI_26M_CK_P3, "infra_pcie_peri_ck_26m_ck_p3",
++ "csw_infra_f26m_sel", 10),
++ /* INFRA1 */
++ GATE_INFRA1(CLK_INFRA_66M_GPT_BCK, "infra_hf_66m_gpt_bck", "sysaxi_sel", 0),
++ GATE_INFRA1(CLK_INFRA_66M_PWM_HCK, "infra_hf_66m_pwm_hck", "sysaxi_sel", 1),
++ GATE_INFRA1(CLK_INFRA_66M_PWM_BCK, "infra_hf_66m_pwm_bck", "infra_pwm_sel", 2),
++ GATE_INFRA1(CLK_INFRA_66M_PWM_CK1, "infra_hf_66m_pwm_ck1", "infra_pwm_ck1_sel", 3),
++ GATE_INFRA1(CLK_INFRA_66M_PWM_CK2, "infra_hf_66m_pwm_ck2", "infra_pwm_ck2_sel", 4),
++ GATE_INFRA1(CLK_INFRA_66M_PWM_CK3, "infra_hf_66m_pwm_ck3", "infra_pwm_ck3_sel", 5),
++ GATE_INFRA1(CLK_INFRA_66M_PWM_CK4, "infra_hf_66m_pwm_ck4", "infra_pwm_ck4_sel", 6),
++ GATE_INFRA1(CLK_INFRA_66M_PWM_CK5, "infra_hf_66m_pwm_ck5", "infra_pwm_ck5_sel", 7),
++ GATE_INFRA1(CLK_INFRA_66M_PWM_CK6, "infra_hf_66m_pwm_ck6", "infra_pwm_ck6_sel", 8),
++ GATE_INFRA1(CLK_INFRA_66M_PWM_CK7, "infra_hf_66m_pwm_ck7", "infra_pwm_ck7_sel", 9),
++ GATE_INFRA1(CLK_INFRA_66M_PWM_CK8, "infra_hf_66m_pwm_ck8", "infra_pwm_ck8_sel", 10),
++ GATE_INFRA1(CLK_INFRA_133M_CQDMA_BCK, "infra_hf_133m_cqdma_bck", "sysaxi_sel", 12),
++ GATE_INFRA1(CLK_INFRA_66M_AUD_SLV_BCK, "infra_66m_aud_slv_bck", "sysaxi_sel", 13),
++ GATE_INFRA1(CLK_INFRA_AUD_26M, "infra_f_faud_26m", "csw_infra_f26m_sel", 14),
++ GATE_INFRA1(CLK_INFRA_AUD_L, "infra_f_faud_l", "aud_l_sel", 15),
++ GATE_INFRA1(CLK_INFRA_AUD_AUD, "infra_f_aud_aud", "a1sys_sel", 16),
++ GATE_INFRA1(CLK_INFRA_AUD_EG2, "infra_f_faud_eg2", "a_tuner_sel", 18),
++ GATE_INFRA1_FLAGS(CLK_INFRA_DRAMC_F26M, "infra_dramc_f26m", "csw_infra_f26m_sel", 19,
++ CLK_IS_CRITICAL),
++ /* JTAG */
++ GATE_INFRA1_FLAGS(CLK_INFRA_133M_DBG_ACKM, "infra_hf_133m_dbg_ackm", "sysaxi_sel", 20,
++ CLK_IS_CRITICAL),
++ GATE_INFRA1(CLK_INFRA_66M_AP_DMA_BCK, "infra_66m_ap_dma_bck", "sysaxi_sel", 21),
++ GATE_INFRA1(CLK_INFRA_66M_SEJ_BCK, "infra_hf_66m_sej_bck", "sysaxi_sel", 29),
++ GATE_INFRA1(CLK_INFRA_PRE_CK_SEJ_F13M, "infra_pre_ck_sej_f13m", "csw_infra_f26m_sel", 30),
++ /* INFRA2 */
++ GATE_INFRA2(CLK_INFRA_26M_THERM_SYSTEM, "infra_hf_26m_therm_system", "csw_infra_f26m_sel",
++ 0),
++ GATE_INFRA2(CLK_INFRA_I2C_BCK, "infra_i2c_bck", "i2c_sel", 1),
++ GATE_INFRA2(CLK_INFRA_52M_UART0_CK, "infra_f_52m_uart0", "infra_mux_uart0_sel", 3),
++ GATE_INFRA2(CLK_INFRA_52M_UART1_CK, "infra_f_52m_uart1", "infra_mux_uart1_sel", 4),
++ GATE_INFRA2(CLK_INFRA_52M_UART2_CK, "infra_f_52m_uart2", "infra_mux_uart2_sel", 5),
++ GATE_INFRA2(CLK_INFRA_NFI, "infra_f_fnfi", "nfi1x_sel", 9),
++ GATE_INFRA2(CLK_INFRA_SPINFI, "infra_f_fspinfi", "spinfi_sel", 10),
++ GATE_INFRA2_FLAGS(CLK_INFRA_66M_NFI_HCK, "infra_hf_66m_nfi_hck", "sysaxi_sel", 11,
++ CLK_IS_CRITICAL),
++ GATE_INFRA2_FLAGS(CLK_INFRA_104M_SPI0, "infra_hf_104m_spi0", "infra_mux_spi0_sel", 12,
++ CLK_IS_CRITICAL),
++ GATE_INFRA2(CLK_INFRA_104M_SPI1, "infra_hf_104m_spi1", "infra_mux_spi1_sel", 13),
++ GATE_INFRA2(CLK_INFRA_104M_SPI2_BCK, "infra_hf_104m_spi2_bck", "infra_mux_spi2_sel", 14),
++ GATE_INFRA2_FLAGS(CLK_INFRA_66M_SPI0_HCK, "infra_hf_66m_spi0_hck", "sysaxi_sel", 15,
++ CLK_IS_CRITICAL),
++ GATE_INFRA2(CLK_INFRA_66M_SPI1_HCK, "infra_hf_66m_spi1_hck", "sysaxi_sel", 16),
++ GATE_INFRA2(CLK_INFRA_66M_SPI2_HCK, "infra_hf_66m_spi2_hck", "sysaxi_sel", 17),
++ GATE_INFRA2(CLK_INFRA_66M_FLASHIF_AXI, "infra_hf_66m_flashif_axi", "sysaxi_sel", 18),
++ GATE_INFRA2_FLAGS(CLK_INFRA_RTC, "infra_f_frtc", "top_rtc_32k", 19, CLK_IS_CRITICAL),
++ GATE_INFRA2(CLK_INFRA_26M_ADC_BCK, "infra_f_26m_adc_bck", "csw_infra_f26m_sel", 20),
++ GATE_INFRA2(CLK_INFRA_RC_ADC, "infra_f_frc_adc", "infra_f_26m_adc_bck", 21),
++ GATE_INFRA2(CLK_INFRA_MSDC400, "infra_f_fmsdc400", "emmc_400m_sel", 22),
++ GATE_INFRA2(CLK_INFRA_MSDC2_HCK, "infra_f_fmsdc2_hck", "emmc_250m_sel", 23),
++ GATE_INFRA2(CLK_INFRA_133M_MSDC_0_HCK, "infra_hf_133m_msdc_0_hck", "sysaxi_sel", 24),
++ GATE_INFRA2(CLK_INFRA_66M_MSDC_0_HCK, "infra_66m_msdc_0_hck", "sysaxi_sel", 25),
++ GATE_INFRA2(CLK_INFRA_133M_CPUM_BCK, "infra_hf_133m_cpum_bck", "sysaxi_sel", 26),
++ GATE_INFRA2(CLK_INFRA_BIST2FPC, "infra_hf_fbist2fpc", "nfi1x_sel", 27),
++ GATE_INFRA2(CLK_INFRA_I2C_X16W_MCK_CK_P1, "infra_hf_i2c_x16w_mck_ck_p1", "sysaxi_sel", 29),
++ GATE_INFRA2(CLK_INFRA_I2C_X16W_PCK_CK_P1, "infra_hf_i2c_x16w_pck_ck_p1", "sysaxi_sel", 31),
++ /* INFRA3 */
++ GATE_INFRA3(CLK_INFRA_133M_USB_HCK, "infra_133m_usb_hck", "sysaxi_sel", 0),
++ GATE_INFRA3(CLK_INFRA_133M_USB_HCK_CK_P1, "infra_133m_usb_hck_ck_p1", "sysaxi_sel", 1),
++ GATE_INFRA3(CLK_INFRA_66M_USB_HCK, "infra_66m_usb_hck", "sysaxi_sel", 2),
++ GATE_INFRA3(CLK_INFRA_66M_USB_HCK_CK_P1, "infra_66m_usb_hck_ck_p1", "sysaxi_sel", 3),
++ GATE_INFRA3(CLK_INFRA_USB_SYS, "infra_usb_sys", "usb_sys_sel", 4),
++ GATE_INFRA3(CLK_INFRA_USB_SYS_CK_P1, "infra_usb_sys_ck_p1", "usb_sys_p1_sel", 5),
++ GATE_INFRA3(CLK_INFRA_USB_REF, "infra_usb_ref", "top_xtal", 6),
++ GATE_INFRA3(CLK_INFRA_USB_CK_P1, "infra_usb_ck_p1", "top_xtal", 7),
++ GATE_INFRA3_FLAGS(CLK_INFRA_USB_FRMCNT, "infra_usb_frmcnt", "usb_frmcnt_sel", 8,
++ CLK_IS_CRITICAL),
++ GATE_INFRA3_FLAGS(CLK_INFRA_USB_FRMCNT_CK_P1, "infra_usb_frmcnt_ck_p1", "usb_frmcnt_p1_sel",
++ 9, CLK_IS_CRITICAL),
++ GATE_INFRA3(CLK_INFRA_USB_PIPE, "infra_usb_pipe", "sspxtp_sel", 10),
++ GATE_INFRA3(CLK_INFRA_USB_PIPE_CK_P1, "infra_usb_pipe_ck_p1", "usb_phy_sel", 11),
++ GATE_INFRA3(CLK_INFRA_USB_UTMI, "infra_usb_utmi", "top_xtal", 12),
++ GATE_INFRA3(CLK_INFRA_USB_UTMI_CK_P1, "infra_usb_utmi_ck_p1", "top_xtal", 13),
++ GATE_INFRA3(CLK_INFRA_USB_XHCI, "infra_usb_xhci", "usb_xhci_sel", 14),
++ GATE_INFRA3(CLK_INFRA_USB_XHCI_CK_P1, "infra_usb_xhci_ck_p1", "usb_xhci_p1_sel", 15),
++ GATE_INFRA3(CLK_INFRA_PCIE_GFMUX_TL_P0, "infra_pcie_gfmux_tl_ck_p0",
++ "infra_pcie_gfmux_tl_o_p0_sel", 20),
++ GATE_INFRA3(CLK_INFRA_PCIE_GFMUX_TL_P1, "infra_pcie_gfmux_tl_ck_p1",
++ "infra_pcie_gfmux_tl_o_p1_sel", 21),
++ GATE_INFRA3(CLK_INFRA_PCIE_GFMUX_TL_P2, "infra_pcie_gfmux_tl_ck_p2",
++ "infra_pcie_gfmux_tl_o_p2_sel", 22),
++ GATE_INFRA3(CLK_INFRA_PCIE_GFMUX_TL_P3, "infra_pcie_gfmux_tl_ck_p3",
++ "infra_pcie_gfmux_tl_o_p3_sel", 23),
++ GATE_INFRA3(CLK_INFRA_PCIE_PIPE_P0, "infra_pcie_pipe_ck_p0", "top_xtal", 24),
++ GATE_INFRA3(CLK_INFRA_PCIE_PIPE_P1, "infra_pcie_pipe_ck_p1", "top_xtal", 25),
++ GATE_INFRA3(CLK_INFRA_PCIE_PIPE_P2, "infra_pcie_pipe_ck_p2", "top_xtal", 26),
++ GATE_INFRA3(CLK_INFRA_PCIE_PIPE_P3, "infra_pcie_pipe_ck_p3", "top_xtal", 27),
++ GATE_INFRA3(CLK_INFRA_133M_PCIE_CK_P0, "infra_133m_pcie_ck_p0", "sysaxi_sel", 28),
++ GATE_INFRA3(CLK_INFRA_133M_PCIE_CK_P1, "infra_133m_pcie_ck_p1", "sysaxi_sel", 29),
++ GATE_INFRA3(CLK_INFRA_133M_PCIE_CK_P2, "infra_133m_pcie_ck_p2", "sysaxi_sel", 30),
++ GATE_INFRA3(CLK_INFRA_133M_PCIE_CK_P3, "infra_133m_pcie_ck_p3", "sysaxi_sel", 31),
++};
++
++static const struct mtk_clk_desc infra_desc = {
++ .clks = infra_clks,
++ .num_clks = ARRAY_SIZE(infra_clks),
++ .mux_clks = infra_muxes,
++ .num_mux_clks = ARRAY_SIZE(infra_muxes),
++ .clk_lock = &mt7988_clk_lock,
++};
++
++static const struct of_device_id of_match_clk_mt7988_infracfg[] = {
++ { .compatible = "mediatek,mt7988-infracfg", .data = &infra_desc },
++ { /* sentinel */ }
++};
++MODULE_DEVICE_TABLE(of, of_match_clk_mt7988_infracfg);
++
++static struct platform_driver clk_mt7988_infracfg_drv = {
++ .driver = {
++ .name = "clk-mt7988-infracfg",
++ .of_match_table = of_match_clk_mt7988_infracfg,
++ },
++ .probe = mtk_clk_simple_probe,
++ .remove_new = mtk_clk_simple_remove,
++};
++module_platform_driver(clk_mt7988_infracfg_drv);
++MODULE_LICENSE("GPL");
+--- /dev/null
++++ b/drivers/clk/mediatek/clk-mt7988-topckgen.c
+@@ -0,0 +1,325 @@
++// SPDX-License-Identifier: GPL-2.0
++/*
++ * Copyright (c) 2023 MediaTek Inc.
++ * Author: Sam Shih <sam.shih@mediatek.com>
++ * Author: Xiufeng Li <Xiufeng.Li@mediatek.com>
++ */
++
++#include <linux/clk-provider.h>
++#include <linux/of.h>
++#include <linux/of_address.h>
++#include <linux/of_device.h>
++#include <linux/platform_device.h>
++#include "clk-mtk.h"
++#include "clk-gate.h"
++#include "clk-mux.h"
++#include <dt-bindings/clock/mediatek,mt7988-clk.h>
++
++static DEFINE_SPINLOCK(mt7988_clk_lock);
++
++static const struct mtk_fixed_clk top_fixed_clks[] = {
++ FIXED_CLK(CLK_TOP_XTAL, "top_xtal", "clkxtal", 40000000),
++};
++
++static const struct mtk_fixed_factor top_divs[] = {
++ FACTOR(CLK_TOP_XTAL_D2, "top_xtal_d2", "top_xtal", 1, 2),
++ FACTOR(CLK_TOP_RTC_32K, "top_rtc_32k", "top_xtal", 1, 1250),
++ FACTOR(CLK_TOP_RTC_32P7K, "top_rtc_32p7k", "top_xtal", 1, 1220),
++ FACTOR(CLK_TOP_MPLL_D2, "mpll_d2", "mpll", 1, 2),
++ FACTOR(CLK_TOP_MPLL_D3_D2, "mpll_d3_d2", "mpll", 1, 2),
++ FACTOR(CLK_TOP_MPLL_D4, "mpll_d4", "mpll", 1, 4),
++ FACTOR(CLK_TOP_MPLL_D8, "mpll_d8", "mpll", 1, 8),
++ FACTOR(CLK_TOP_MPLL_D8_D2, "mpll_d8_d2", "mpll", 1, 16),
++ FACTOR(CLK_TOP_MMPLL_D2, "mmpll_d2", "mmpll", 1, 2),
++ FACTOR(CLK_TOP_MMPLL_D3_D5, "mmpll_d3_d5", "mmpll", 1, 15),
++ FACTOR(CLK_TOP_MMPLL_D4, "mmpll_d4", "mmpll", 1, 4),
++ FACTOR(CLK_TOP_MMPLL_D6_D2, "mmpll_d6_d2", "mmpll", 1, 12),
++ FACTOR(CLK_TOP_MMPLL_D8, "mmpll_d8", "mmpll", 1, 8),
++ FACTOR(CLK_TOP_APLL2_D4, "apll2_d4", "apll2", 1, 4),
++ FACTOR(CLK_TOP_NET1PLL_D4, "net1pll_d4", "net1pll", 1, 4),
++ FACTOR(CLK_TOP_NET1PLL_D5, "net1pll_d5", "net1pll", 1, 5),
++ FACTOR(CLK_TOP_NET1PLL_D5_D2, "net1pll_d5_d2", "net1pll", 1, 10),
++ FACTOR(CLK_TOP_NET1PLL_D5_D4, "net1pll_d5_d4", "net1pll", 1, 20),
++ FACTOR(CLK_TOP_NET1PLL_D8, "net1pll_d8", "net1pll", 1, 8),
++ FACTOR(CLK_TOP_NET1PLL_D8_D2, "net1pll_d8_d2", "net1pll", 1, 16),
++ FACTOR(CLK_TOP_NET1PLL_D8_D4, "net1pll_d8_d4", "net1pll", 1, 32),
++ FACTOR(CLK_TOP_NET1PLL_D8_D8, "net1pll_d8_d8", "net1pll", 1, 64),
++ FACTOR(CLK_TOP_NET1PLL_D8_D16, "net1pll_d8_d16", "net1pll", 1, 128),
++ FACTOR(CLK_TOP_NET2PLL_D2, "net2pll_d2", "net2pll", 1, 2),
++ FACTOR(CLK_TOP_NET2PLL_D4, "net2pll_d4", "net2pll", 1, 4),
++ FACTOR(CLK_TOP_NET2PLL_D4_D4, "net2pll_d4_d4", "net2pll", 1, 16),
++ FACTOR(CLK_TOP_NET2PLL_D4_D8, "net2pll_d4_d8", "net2pll", 1, 32),
++ FACTOR(CLK_TOP_NET2PLL_D6, "net2pll_d6", "net2pll", 1, 6),
++ FACTOR(CLK_TOP_NET2PLL_D8, "net2pll_d8", "net2pll", 1, 8),
++};
++
++static const char *const netsys_parents[] = { "top_xtal", "net2pll_d2", "mmpll_d2" };
++static const char *const netsys_500m_parents[] = { "top_xtal", "net1pll_d5", "net1pll_d5_d2" };
++static const char *const netsys_2x_parents[] = { "top_xtal", "net2pll", "mmpll" };
++static const char *const netsys_gsw_parents[] = { "top_xtal", "net1pll_d4", "net1pll_d5" };
++static const char *const eth_gmii_parents[] = { "top_xtal", "net1pll_d5_d4" };
++static const char *const netsys_mcu_parents[] = { "top_xtal", "net2pll", "mmpll",
++ "net1pll_d4", "net1pll_d5", "mpll" };
++static const char *const eip197_parents[] = { "top_xtal", "netsyspll", "net2pll",
++ "mmpll", "net1pll_d4", "net1pll_d5" };
++static const char *const axi_infra_parents[] = { "top_xtal", "net1pll_d8_d2" };
++static const char *const uart_parents[] = { "top_xtal", "mpll_d8", "mpll_d8_d2" };
++static const char *const emmc_250m_parents[] = { "top_xtal", "net1pll_d5_d2", "mmpll_d4" };
++static const char *const emmc_400m_parents[] = { "top_xtal", "msdcpll", "mmpll_d2",
++ "mpll_d2", "mmpll_d4", "net1pll_d8_d2" };
++static const char *const spi_parents[] = { "top_xtal", "mpll_d2", "mmpll_d4",
++ "net1pll_d8_d2", "net2pll_d6", "net1pll_d5_d4",
++ "mpll_d4", "net1pll_d8_d4" };
++static const char *const nfi1x_parents[] = { "top_xtal", "mmpll_d4", "net1pll_d8_d2", "net2pll_d6",
++ "mpll_d4", "mmpll_d8", "net1pll_d8_d4", "mpll_d8" };
++static const char *const spinfi_parents[] = { "top_xtal_d2", "top_xtal", "net1pll_d5_d4",
++ "mpll_d4", "mmpll_d8", "net1pll_d8_d4",
++ "mmpll_d6_d2", "mpll_d8" };
++static const char *const pwm_parents[] = { "top_xtal", "net1pll_d8_d2", "net1pll_d5_d4",
++ "mpll_d4", "mpll_d8_d2", "top_rtc_32k" };
++static const char *const i2c_parents[] = { "top_xtal", "net1pll_d5_d4", "mpll_d4",
++ "net1pll_d8_d4" };
++static const char *const pcie_mbist_250m_parents[] = { "top_xtal", "net1pll_d5_d2" };
++static const char *const pextp_tl_ck_parents[] = { "top_xtal", "net2pll_d6", "mmpll_d8",
++ "mpll_d8_d2", "top_rtc_32k" };
++static const char *const usb_frmcnt_parents[] = { "top_xtal", "mmpll_d3_d5" };
++static const char *const aud_parents[] = { "top_xtal", "apll2" };
++static const char *const a1sys_parents[] = { "top_xtal", "apll2_d4" };
++static const char *const aud_l_parents[] = { "top_xtal", "apll2", "mpll_d8_d2" };
++static const char *const sspxtp_parents[] = { "top_xtal_d2", "mpll_d8_d2" };
++static const char *const usxgmii_sbus_0_parents[] = { "top_xtal", "net1pll_d8_d4" };
++static const char *const sgm_0_parents[] = { "top_xtal", "sgmpll" };
++static const char *const sysapb_parents[] = { "top_xtal", "mpll_d3_d2" };
++static const char *const eth_refck_50m_parents[] = { "top_xtal", "net2pll_d4_d4" };
++static const char *const eth_sys_200m_parents[] = { "top_xtal", "net2pll_d4" };
++static const char *const eth_xgmii_parents[] = { "top_xtal_d2", "net1pll_d8_d8", "net1pll_d8_d16" };
++static const char *const bus_tops_parents[] = { "top_xtal", "net1pll_d5", "net2pll_d2" };
++static const char *const npu_tops_parents[] = { "top_xtal", "net2pll" };
++static const char *const dramc_md32_parents[] = { "top_xtal", "mpll_d2", "wedmcupll" };
++static const char *const da_xtp_glb_p0_parents[] = { "top_xtal", "net2pll_d8" };
++static const char *const mcusys_backup_625m_parents[] = { "top_xtal", "net1pll_d4" };
++static const char *const macsec_parents[] = { "top_xtal", "sgmpll", "net1pll_d8" };
++static const char *const netsys_tops_400m_parents[] = { "top_xtal", "net2pll_d2" };
++static const char *const eth_mii_parents[] = { "top_xtal_d2", "net2pll_d4_d8" };
++
++static const struct mtk_mux top_muxes[] = {
++ /* CLK_CFG_0 */
++ MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_SEL, "netsys_sel", netsys_parents, 0x000, 0x004, 0x008,
++ 0, 2, 7, 0x1c0, 0),
++ MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_500M_SEL, "netsys_500m_sel", netsys_500m_parents, 0x000,
++ 0x004, 0x008, 8, 2, 15, 0x1C0, 1),
++ MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_2X_SEL, "netsys_2x_sel", netsys_2x_parents, 0x000,
++ 0x004, 0x008, 16, 2, 23, 0x1C0, 2),
++ MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_GSW_SEL, "netsys_gsw_sel", netsys_gsw_parents, 0x000,
++ 0x004, 0x008, 24, 2, 31, 0x1C0, 3),
++ /* CLK_CFG_1 */
++ MUX_GATE_CLR_SET_UPD(CLK_TOP_ETH_GMII_SEL, "eth_gmii_sel", eth_gmii_parents, 0x010, 0x014,
++ 0x018, 0, 1, 7, 0x1C0, 4),
++ MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_MCU_SEL, "netsys_mcu_sel", netsys_mcu_parents, 0x010,
++ 0x014, 0x018, 8, 3, 15, 0x1C0, 5),
++ MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_PAO_2X_SEL, "netsys_pao_2x_sel", netsys_mcu_parents,
++ 0x010, 0x014, 0x018, 16, 3, 23, 0x1C0, 6),
++ MUX_GATE_CLR_SET_UPD(CLK_TOP_EIP197_SEL, "eip197_sel", eip197_parents, 0x010, 0x014, 0x018,
++ 24, 3, 31, 0x1c0, 7),
++ /* CLK_CFG_2 */
++ MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_AXI_INFRA_SEL, "axi_infra_sel", axi_infra_parents, 0x020,
++ 0x024, 0x028, 0, 1, 7, 0x1C0, 8, CLK_IS_CRITICAL),
++ MUX_GATE_CLR_SET_UPD(CLK_TOP_UART_SEL, "uart_sel", uart_parents, 0x020, 0x024, 0x028, 8, 2,
++ 15, 0x1c0, 9),
++ MUX_GATE_CLR_SET_UPD(CLK_TOP_EMMC_250M_SEL, "emmc_250m_sel", emmc_250m_parents, 0x020,
++ 0x024, 0x028, 16, 2, 23, 0x1C0, 10),
++ MUX_GATE_CLR_SET_UPD(CLK_TOP_EMMC_400M_SEL, "emmc_400m_sel", emmc_400m_parents, 0x020,
++ 0x024, 0x028, 24, 3, 31, 0x1C0, 11),
++ /* CLK_CFG_3 */
++ MUX_GATE_CLR_SET_UPD(CLK_TOP_SPI_SEL, "spi_sel", spi_parents, 0x030, 0x034, 0x038, 0, 3, 7,
++ 0x1c0, 12),
++ MUX_GATE_CLR_SET_UPD(CLK_TOP_SPIM_MST_SEL, "spim_mst_sel", spi_parents, 0x030, 0x034, 0x038,
++ 8, 3, 15, 0x1c0, 13),
++ MUX_GATE_CLR_SET_UPD(CLK_TOP_NFI1X_SEL, "nfi1x_sel", nfi1x_parents, 0x030, 0x034, 0x038, 16,
++ 3, 23, 0x1c0, 14),
++ MUX_GATE_CLR_SET_UPD(CLK_TOP_SPINFI_SEL, "spinfi_sel", spinfi_parents, 0x030, 0x034, 0x038,
++ 24, 3, 31, 0x1c0, 15),
++ /* CLK_CFG_4 */
++ MUX_GATE_CLR_SET_UPD(CLK_TOP_PWM_SEL, "pwm_sel", pwm_parents, 0x040, 0x044, 0x048, 0, 3, 7,
++ 0x1c0, 16),
++ MUX_GATE_CLR_SET_UPD(CLK_TOP_I2C_SEL, "i2c_sel", i2c_parents, 0x040, 0x044, 0x048, 8, 2, 15,
++ 0x1c0, 17),
++ MUX_GATE_CLR_SET_UPD(CLK_TOP_PCIE_MBIST_250M_SEL, "pcie_mbist_250m_sel",
++ pcie_mbist_250m_parents, 0x040, 0x044, 0x048, 16, 1, 23, 0x1C0, 18),
++ MUX_GATE_CLR_SET_UPD(CLK_TOP_PEXTP_TL_SEL, "pextp_tl_sel", pextp_tl_ck_parents, 0x040,
++ 0x044, 0x048, 24, 3, 31, 0x1C0, 19),
++ /* CLK_CFG_5 */
++ MUX_GATE_CLR_SET_UPD(CLK_TOP_PEXTP_TL_P1_SEL, "pextp_tl_p1_sel", pextp_tl_ck_parents, 0x050,
++ 0x054, 0x058, 0, 3, 7, 0x1C0, 20),
++ MUX_GATE_CLR_SET_UPD(CLK_TOP_PEXTP_TL_P2_SEL, "pextp_tl_p2_sel", pextp_tl_ck_parents, 0x050,
++ 0x054, 0x058, 8, 3, 15, 0x1C0, 21),
++ MUX_GATE_CLR_SET_UPD(CLK_TOP_PEXTP_TL_P3_SEL, "pextp_tl_p3_sel", pextp_tl_ck_parents, 0x050,
++ 0x054, 0x058, 16, 3, 23, 0x1C0, 22),
++ MUX_GATE_CLR_SET_UPD(CLK_TOP_USB_SYS_SEL, "usb_sys_sel", eth_gmii_parents, 0x050, 0x054,
++ 0x058, 24, 1, 31, 0x1C0, 23),
++ /* CLK_CFG_6 */
++ MUX_GATE_CLR_SET_UPD(CLK_TOP_USB_SYS_P1_SEL, "usb_sys_p1_sel", eth_gmii_parents, 0x060,
++ 0x064, 0x068, 0, 1, 7, 0x1C0, 24),
++ MUX_GATE_CLR_SET_UPD(CLK_TOP_USB_XHCI_SEL, "usb_xhci_sel", eth_gmii_parents, 0x060, 0x064,
++ 0x068, 8, 1, 15, 0x1C0, 25),
++ MUX_GATE_CLR_SET_UPD(CLK_TOP_USB_XHCI_P1_SEL, "usb_xhci_p1_sel", eth_gmii_parents, 0x060,
++ 0x064, 0x068, 16, 1, 23, 0x1C0, 26),
++ MUX_GATE_CLR_SET_UPD(CLK_TOP_USB_FRMCNT_SEL, "usb_frmcnt_sel", usb_frmcnt_parents, 0x060,
++ 0x064, 0x068, 24, 1, 31, 0x1C0, 27),
++ /* CLK_CFG_7 */
++ MUX_GATE_CLR_SET_UPD(CLK_TOP_USB_FRMCNT_P1_SEL, "usb_frmcnt_p1_sel", usb_frmcnt_parents,
++ 0x070, 0x074, 0x078, 0, 1, 7, 0x1C0, 28),
++ MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_SEL, "aud_sel", aud_parents, 0x070, 0x074, 0x078, 8, 1, 15,
++ 0x1c0, 29),
++ MUX_GATE_CLR_SET_UPD(CLK_TOP_A1SYS_SEL, "a1sys_sel", a1sys_parents, 0x070, 0x074, 0x078, 16,
++ 1, 23, 0x1c0, 30),
++ MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_L_SEL, "aud_l_sel", aud_l_parents, 0x070, 0x074, 0x078, 24,
++ 2, 31, 0x1c4, 0),
++ /* CLK_CFG_8 */
++ MUX_GATE_CLR_SET_UPD(CLK_TOP_A_TUNER_SEL, "a_tuner_sel", a1sys_parents, 0x080, 0x084, 0x088,
++ 0, 1, 7, 0x1c4, 1),
++ MUX_GATE_CLR_SET_UPD(CLK_TOP_SSPXTP_SEL, "sspxtp_sel", sspxtp_parents, 0x080, 0x084, 0x088,
++ 8, 1, 15, 0x1c4, 2),
++ MUX_GATE_CLR_SET_UPD(CLK_TOP_USB_PHY_SEL, "usb_phy_sel", sspxtp_parents, 0x080, 0x084,
++ 0x088, 16, 1, 23, 0x1c4, 3),
++ MUX_GATE_CLR_SET_UPD(CLK_TOP_USXGMII_SBUS_0_SEL, "usxgmii_sbus_0_sel",
++ usxgmii_sbus_0_parents, 0x080, 0x084, 0x088, 24, 1, 31, 0x1C4, 4),
++ /* CLK_CFG_9 */
++ MUX_GATE_CLR_SET_UPD(CLK_TOP_USXGMII_SBUS_1_SEL, "usxgmii_sbus_1_sel",
++ usxgmii_sbus_0_parents, 0x090, 0x094, 0x098, 0, 1, 7, 0x1C4, 5),
++ MUX_GATE_CLR_SET_UPD(CLK_TOP_SGM_0_SEL, "sgm_0_sel", sgm_0_parents, 0x090, 0x094, 0x098, 8,
++ 1, 15, 0x1c4, 6),
++ MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_SGM_SBUS_0_SEL, "sgm_sbus_0_sel", usxgmii_sbus_0_parents,
++ 0x090, 0x094, 0x098, 16, 1, 23, 0x1C4, 7, CLK_IS_CRITICAL),
++ MUX_GATE_CLR_SET_UPD(CLK_TOP_SGM_1_SEL, "sgm_1_sel", sgm_0_parents, 0x090, 0x094, 0x098, 24,
++ 1, 31, 0x1c4, 8),
++ /* CLK_CFG_10 */
++ MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_SGM_SBUS_1_SEL, "sgm_sbus_1_sel", usxgmii_sbus_0_parents,
++ 0x0a0, 0x0a4, 0x0a8, 0, 1, 7, 0x1C4, 9, CLK_IS_CRITICAL),
++ MUX_GATE_CLR_SET_UPD(CLK_TOP_XFI_PHY_0_XTAL_SEL, "xfi_phy_0_xtal_sel", sspxtp_parents,
++ 0x0a0, 0x0a4, 0x0a8, 8, 1, 15, 0x1C4, 10),
++ MUX_GATE_CLR_SET_UPD(CLK_TOP_XFI_PHY_1_XTAL_SEL, "xfi_phy_1_xtal_sel", sspxtp_parents,
++ 0x0a0, 0x0a4, 0x0a8, 16, 1, 23, 0x1C4, 11),
++ /* CLK_CFG_11 */
++ MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_SYSAXI_SEL, "sysaxi_sel", axi_infra_parents, 0x0a0,
++ 0x0a4, 0x0a8, 24, 1, 31, 0x1C4, 12, CLK_IS_CRITICAL),
++ MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_SYSAPB_SEL, "sysapb_sel", sysapb_parents, 0x0b0, 0x0b4,
++ 0x0b8, 0, 1, 7, 0x1c4, 13, CLK_IS_CRITICAL),
++ MUX_GATE_CLR_SET_UPD(CLK_TOP_ETH_REFCK_50M_SEL, "eth_refck_50m_sel", eth_refck_50m_parents,
++ 0x0b0, 0x0b4, 0x0b8, 8, 1, 15, 0x1C4, 14),
++ MUX_GATE_CLR_SET_UPD(CLK_TOP_ETH_SYS_200M_SEL, "eth_sys_200m_sel", eth_sys_200m_parents,
++ 0x0b0, 0x0b4, 0x0b8, 16, 1, 23, 0x1C4, 15),
++ MUX_GATE_CLR_SET_UPD(CLK_TOP_ETH_SYS_SEL, "eth_sys_sel", pcie_mbist_250m_parents, 0x0b0,
++ 0x0b4, 0x0b8, 24, 1, 31, 0x1C4, 16),
++ /* CLK_CFG_12 */
++ MUX_GATE_CLR_SET_UPD(CLK_TOP_ETH_XGMII_SEL, "eth_xgmii_sel", eth_xgmii_parents, 0x0c0,
++ 0x0c4, 0x0c8, 0, 2, 7, 0x1C4, 17),
++ MUX_GATE_CLR_SET_UPD(CLK_TOP_BUS_TOPS_SEL, "bus_tops_sel", bus_tops_parents, 0x0c0, 0x0c4,
++ 0x0c8, 8, 2, 15, 0x1C4, 18),
++ MUX_GATE_CLR_SET_UPD(CLK_TOP_NPU_TOPS_SEL, "npu_tops_sel", npu_tops_parents, 0x0c0, 0x0c4,
++ 0x0c8, 16, 1, 23, 0x1C4, 19),
++ MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_DRAMC_SEL, "dramc_sel", sspxtp_parents, 0x0c0, 0x0c4,
++ 0x0c8, 24, 1, 31, 0x1C4, 20, CLK_IS_CRITICAL),
++ /* CLK_CFG_13 */
++ MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_DRAMC_MD32_SEL, "dramc_md32_sel", dramc_md32_parents,
++ 0x0d0, 0x0d4, 0x0d8, 0, 2, 7, 0x1C4, 21, CLK_IS_CRITICAL),
++ MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_INFRA_F26M_SEL, "csw_infra_f26m_sel", sspxtp_parents,
++ 0x0d0, 0x0d4, 0x0d8, 8, 1, 15, 0x1C4, 22, CLK_IS_CRITICAL),
++ MUX_GATE_CLR_SET_UPD(CLK_TOP_PEXTP_P0_SEL, "pextp_p0_sel", sspxtp_parents, 0x0d0, 0x0d4,
++ 0x0d8, 16, 1, 23, 0x1C4, 23),
++ MUX_GATE_CLR_SET_UPD(CLK_TOP_PEXTP_P1_SEL, "pextp_p1_sel", sspxtp_parents, 0x0d0, 0x0d4,
++ 0x0d8, 24, 1, 31, 0x1C4, 24),
++ /* CLK_CFG_14 */
++ MUX_GATE_CLR_SET_UPD(CLK_TOP_PEXTP_P2_SEL, "pextp_p2_sel", sspxtp_parents, 0x0e0, 0x0e4,
++ 0x0e8, 0, 1, 7, 0x1C4, 25),
++ MUX_GATE_CLR_SET_UPD(CLK_TOP_PEXTP_P3_SEL, "pextp_p3_sel", sspxtp_parents, 0x0e0, 0x0e4,
++ 0x0e8, 8, 1, 15, 0x1C4, 26),
++ MUX_GATE_CLR_SET_UPD(CLK_TOP_DA_XTP_GLB_P0_SEL, "da_xtp_glb_p0_sel", da_xtp_glb_p0_parents,
++ 0x0e0, 0x0e4, 0x0e8, 16, 1, 23, 0x1C4, 27),
++ MUX_GATE_CLR_SET_UPD(CLK_TOP_DA_XTP_GLB_P1_SEL, "da_xtp_glb_p1_sel", da_xtp_glb_p0_parents,
++ 0x0e0, 0x0e4, 0x0e8, 24, 1, 31, 0x1C4, 28),
++ /* CLK_CFG_15 */
++ MUX_GATE_CLR_SET_UPD(CLK_TOP_DA_XTP_GLB_P2_SEL, "da_xtp_glb_p2_sel", da_xtp_glb_p0_parents,
++ 0x0f0, 0x0f4, 0x0f8, 0, 1, 7, 0x1C4, 29),
++ MUX_GATE_CLR_SET_UPD(CLK_TOP_DA_XTP_GLB_P3_SEL, "da_xtp_glb_p3_sel", da_xtp_glb_p0_parents,
++ 0x0f0, 0x0f4, 0x0f8, 8, 1, 15, 0x1C4, 30),
++ MUX_GATE_CLR_SET_UPD(CLK_TOP_CKM_SEL, "ckm_sel", sspxtp_parents, 0x0F0, 0x0f4, 0x0f8, 16, 1,
++ 23, 0x1c8, 0),
++ MUX_GATE_CLR_SET_UPD(CLK_TOP_DA_SEL, "da_sel", sspxtp_parents, 0x0f0, 0x0f4, 0x0f8, 24, 1,
++ 31, 0x1C8, 1),
++ /* CLK_CFG_16 */
++ MUX_GATE_CLR_SET_UPD(CLK_TOP_PEXTP_SEL, "pextp_sel", sspxtp_parents, 0x0100, 0x104, 0x108,
++ 0, 1, 7, 0x1c8, 2),
++ MUX_GATE_CLR_SET_UPD(CLK_TOP_TOPS_P2_26M_SEL, "tops_p2_26m_sel", sspxtp_parents, 0x0100,
++ 0x104, 0x108, 8, 1, 15, 0x1C8, 3),
++ MUX_GATE_CLR_SET_UPD(CLK_TOP_MCUSYS_BACKUP_625M_SEL, "mcusys_backup_625m_sel",
++ mcusys_backup_625m_parents, 0x0100, 0x104, 0x108, 16, 1, 23, 0x1C8, 4),
++ MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_SYNC_250M_SEL, "netsys_sync_250m_sel",
++ pcie_mbist_250m_parents, 0x0100, 0x104, 0x108, 24, 1, 31, 0x1c8, 5),
++ /* CLK_CFG_17 */
++ MUX_GATE_CLR_SET_UPD(CLK_TOP_MACSEC_SEL, "macsec_sel", macsec_parents, 0x0110, 0x114, 0x118,
++ 0, 2, 7, 0x1c8, 6),
++ MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_TOPS_400M_SEL, "netsys_tops_400m_sel",
++ netsys_tops_400m_parents, 0x0110, 0x114, 0x118, 8, 1, 15, 0x1c8, 7),
++ MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_PPEFB_250M_SEL, "netsys_ppefb_250m_sel",
++ pcie_mbist_250m_parents, 0x0110, 0x114, 0x118, 16, 1, 23, 0x1c8, 8),
++ MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_WARP_SEL, "netsys_warp_sel", netsys_parents, 0x0110,
++ 0x114, 0x118, 24, 2, 31, 0x1C8, 9),
++ /* CLK_CFG_18 */
++ MUX_GATE_CLR_SET_UPD(CLK_TOP_ETH_MII_SEL, "eth_mii_sel", eth_mii_parents, 0x0120, 0x124,
++ 0x128, 0, 1, 7, 0x1c8, 10),
++ MUX_GATE_CLR_SET_UPD(CLK_TOP_NPU_SEL, "ck_npu_sel", netsys_2x_parents, 0x0120, 0x124, 0x128,
++ 8, 2, 15, 0x1c8, 11),
++};
++
++static const struct mtk_composite top_aud_divs[] = {
++ DIV_GATE(CLK_TOP_AUD_I2S_M, "aud_i2s_m", "aud_sel", 0x0420, 0, 0x0420, 8, 8),
++};
++
++static const struct mtk_clk_desc topck_desc = {
++ .fixed_clks = top_fixed_clks,
++ .num_fixed_clks = ARRAY_SIZE(top_fixed_clks),
++ .factor_clks = top_divs,
++ .num_factor_clks = ARRAY_SIZE(top_divs),
++ .mux_clks = top_muxes,
++ .num_mux_clks = ARRAY_SIZE(top_muxes),
++ .composite_clks = top_aud_divs,
++ .num_composite_clks = ARRAY_SIZE(top_aud_divs),
++ .clk_lock = &mt7988_clk_lock,
++};
++
++static const char *const mcu_bus_div_parents[] = { "top_xtal", "ccipll2_b", "net1pll_d4" };
++
++static const char *const mcu_arm_div_parents[] = { "top_xtal", "arm_b", "net1pll_d4" };
++
++static struct mtk_composite mcu_muxes[] = {
++ /* bus_pll_divider_cfg */
++ MUX_GATE_FLAGS(CLK_MCU_BUS_DIV_SEL, "mcu_bus_div_sel", mcu_bus_div_parents, 0x7C0, 9, 2, -1,
++ CLK_IS_CRITICAL),
++ /* mp2_pll_divider_cfg */
++ MUX_GATE_FLAGS(CLK_MCU_ARM_DIV_SEL, "mcu_arm_div_sel", mcu_arm_div_parents, 0x7A8, 9, 2, -1,
++ CLK_IS_CRITICAL),
++};
++
++static const struct mtk_clk_desc mcusys_desc = {
++ .composite_clks = mcu_muxes,
++ .num_composite_clks = ARRAY_SIZE(mcu_muxes),
++};
++
++static const struct of_device_id of_match_clk_mt7988_topckgen[] = {
++ { .compatible = "mediatek,mt7988-topckgen", .data = &topck_desc },
++ { .compatible = "mediatek,mt7988-mcusys", .data = &mcusys_desc },
++ { /* sentinel */ }
++};
++MODULE_DEVICE_TABLE(of, of_match_clk_mt7988_topckgen);
++
++static struct platform_driver clk_mt7988_topckgen_drv = {
++ .probe = mtk_clk_simple_probe,
++ .remove_new = mtk_clk_simple_remove,
++ .driver = {
++ .name = "clk-mt7988-topckgen",
++ .of_match_table = of_match_clk_mt7988_topckgen,
++ },
++};
++module_platform_driver(clk_mt7988_topckgen_drv);
++MODULE_LICENSE("GPL");
+--- /dev/null
++++ b/drivers/clk/mediatek/clk-mt7988-xfipll.c
+@@ -0,0 +1,82 @@
++// SPDX-License-Identifier: GPL-2.0
++/*
++ * Copyright (c) 2023 Daniel Golle <daniel@makrotopia.org>
++ */
++
++#include <linux/clk-provider.h>
++#include <linux/of.h>
++#include <linux/of_address.h>
++#include <linux/of_device.h>
++#include <linux/platform_device.h>
++#include "clk-mtk.h"
++#include "clk-gate.h"
++#include <dt-bindings/clock/mediatek,mt7988-clk.h>
++
++/* Register to control USXGMII XFI PLL analog */
++#define XFI_PLL_ANA_GLB8 0x108
++#define RG_XFI_PLL_ANA_SWWA 0x02283248
++
++static const struct mtk_gate_regs xfipll_cg_regs = {
++ .set_ofs = 0x8,
++ .clr_ofs = 0x8,
++ .sta_ofs = 0x8,
++};
++
++#define GATE_XFIPLL(_id, _name, _parent, _shift) \
++ { \
++ .id = _id, \
++ .name = _name, \
++ .parent_name = _parent, \
++ .regs = &xfipll_cg_regs, \
++ .shift = _shift, \
++ .ops = &mtk_clk_gate_ops_no_setclr_inv, \
++ }
++
++static const struct mtk_fixed_factor xfipll_divs[] = {
++ FACTOR(CLK_XFIPLL_PLL, "xfipll_pll", "top_xtal", 125, 32),
++};
++
++static const struct mtk_gate xfipll_clks[] = {
++ GATE_XFIPLL(CLK_XFIPLL_PLL_EN, "xfipll_pll_en", "xfipll_pll", 31),
++};
++
++static const struct mtk_clk_desc xfipll_desc = {
++ .clks = xfipll_clks,
++ .num_clks = ARRAY_SIZE(xfipll_clks),
++ .factor_clks = xfipll_divs,
++ .num_factor_clks = ARRAY_SIZE(xfipll_divs),
++};
++
++static int clk_mt7988_xfipll_probe(struct platform_device *pdev)
++{
++ struct device_node *node = pdev->dev.of_node;
++ void __iomem *base = of_iomap(node, 0);
++
++ if (!base)
++ return -ENOMEM;
++
++ /* Apply software workaround for USXGMII PLL TCL issue */
++ writel(RG_XFI_PLL_ANA_SWWA, base + XFI_PLL_ANA_GLB8);
++ iounmap(base);
++
++ return mtk_clk_simple_probe(pdev);
++};
++
++static const struct of_device_id of_match_clk_mt7988_xfipll[] = {
++ { .compatible = "mediatek,mt7988-xfi-pll", .data = &xfipll_desc },
++ { /* sentinel */ }
++};
++MODULE_DEVICE_TABLE(of, of_match_clk_mt7988_xfipll);
++
++static struct platform_driver clk_mt7988_xfipll_drv = {
++ .driver = {
++ .name = "clk-mt7988-xfipll",
++ .of_match_table = of_match_clk_mt7988_xfipll,
++ },
++ .probe = clk_mt7988_xfipll_probe,
++ .remove_new = mtk_clk_simple_remove,
++};
++module_platform_driver(clk_mt7988_xfipll_drv);
++
++MODULE_DESCRIPTION("MediaTek MT7988 XFI PLL clock driver");
++MODULE_LICENSE("GPL");
--- /dev/null
+From 26ced94177b150710d94cf365002a09cc48950e9 Mon Sep 17 00:00:00 2001
+From: Frank Wunderlich <frank-w@public-files.de>
+Date: Wed, 17 Jan 2024 19:41:11 +0100
+Subject: [PATCH] clk: mediatek: add infracfg reset controller for mt7988
+
+Infracfg can also operate as reset controller, add support for it.
+
+Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
+---
+ drivers/clk/mediatek/clk-mt7988-infracfg.c | 23 ++++++++++++++++++++++
+ 1 file changed, 23 insertions(+)
+
+--- a/drivers/clk/mediatek/clk-mt7988-infracfg.c
++++ b/drivers/clk/mediatek/clk-mt7988-infracfg.c
+@@ -14,6 +14,10 @@
+ #include "clk-gate.h"
+ #include "clk-mux.h"
+ #include <dt-bindings/clock/mediatek,mt7988-clk.h>
++#include <dt-bindings/reset/mediatek,mt7988-resets.h>
++
++#define MT7988_INFRA_RST0_SET_OFFSET 0x70
++#define MT7988_INFRA_RST1_SET_OFFSET 0x80
+
+ static DEFINE_SPINLOCK(mt7988_clk_lock);
+
+@@ -249,12 +253,31 @@ static const struct mtk_gate infra_clks[
+ GATE_INFRA3(CLK_INFRA_133M_PCIE_CK_P3, "infra_133m_pcie_ck_p3", "sysaxi_sel", 31),
+ };
+
++static u16 infra_rst_ofs[] = {
++ MT7988_INFRA_RST0_SET_OFFSET,
++ MT7988_INFRA_RST1_SET_OFFSET,
++};
++
++static u16 infra_idx_map[] = {
++ [MT7988_INFRA_RST0_PEXTP_MAC_SWRST] = 0 * RST_NR_PER_BANK + 6,
++ [MT7988_INFRA_RST1_THERM_CTRL_SWRST] = 1 * RST_NR_PER_BANK + 9,
++};
++
++static struct mtk_clk_rst_desc infra_rst_desc = {
++ .version = MTK_RST_SET_CLR,
++ .rst_bank_ofs = infra_rst_ofs,
++ .rst_bank_nr = ARRAY_SIZE(infra_rst_ofs),
++ .rst_idx_map = infra_idx_map,
++ .rst_idx_map_nr = ARRAY_SIZE(infra_idx_map),
++};
++
+ static const struct mtk_clk_desc infra_desc = {
+ .clks = infra_clks,
+ .num_clks = ARRAY_SIZE(infra_clks),
+ .mux_clks = infra_muxes,
+ .num_mux_clks = ARRAY_SIZE(infra_muxes),
+ .clk_lock = &mt7988_clk_lock,
++ .rst_desc = &infra_rst_desc,
+ };
+
+ static const struct of_device_id of_match_clk_mt7988_infracfg[] = {
--- /dev/null
+From 3c810da3206f2e52c92f9f15a87f05db4bbba734 Mon Sep 17 00:00:00 2001
+From: Frank Wunderlich <frank-w@public-files.de>
+Date: Wed, 17 Jan 2024 19:41:10 +0100
+Subject: [PATCH] dt-bindings: reset: mediatek: add MT7988 reset IDs
+
+Add reset constants for using as index in driver and dts.
+
+Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
+---
+ include/dt-bindings/reset/mediatek,mt7988-resets.h | 6 ++++++
+ 1 file changed, 6 insertions(+)
+
+--- a/include/dt-bindings/reset/mediatek,mt7988-resets.h
++++ b/include/dt-bindings/reset/mediatek,mt7988-resets.h
+@@ -10,4 +10,10 @@
+ /* ETHWARP resets */
+ #define MT7988_ETHWARP_RST_SWITCH 0
+
++/* INFRA resets */
++#define MT7988_INFRA_RST0_PEXTP_MAC_SWRST 0
++#define MT7988_INFRA_RST1_THERM_CTRL_SWRST 1
++
++
+ #endif /* _DT_BINDINGS_RESET_CONTROLLER_MT7988 */
++
--- /dev/null
+From 137c9e08e5e542d58aa606b0bb4f0990117309a0 Mon Sep 17 00:00:00 2001
+From: Daniel Golle <daniel@makrotopia.org>
+Date: Mon, 20 Nov 2023 18:22:31 +0000
+Subject: [PATCH] watchdog: mediatek: mt7988: add wdt support
+
+Add support for watchdog and reset generator unit of the MediaTek
+MT7988 SoC.
+
+Signed-off-by: Daniel Golle <daniel@makrotopia.org>
+Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
+Reviewed-by: Guenter Roeck <linux@roeck-us.net>
+Link: https://lore.kernel.org/r/c0cf5f701801cce60470853fa15f1d9dced78c4f.1700504385.git.daniel@makrotopia.org
+Signed-off-by: Guenter Roeck <linux@roeck-us.net>
+Signed-off-by: Wim Van Sebroeck <wim@linux-watchdog.org>
+---
+ drivers/watchdog/mtk_wdt.c | 42 ++++++++++++++++++++++++++++++++++++++
+ 1 file changed, 42 insertions(+)
+
+--- a/drivers/watchdog/mtk_wdt.c
++++ b/drivers/watchdog/mtk_wdt.c
+@@ -59,9 +59,13 @@
+ #define WDT_SWSYSRST 0x18U
+ #define WDT_SWSYS_RST_KEY 0x88000000
+
++#define WDT_SWSYSRST_EN 0xfc
++
+ #define DRV_NAME "mtk-wdt"
+ #define DRV_VERSION "1.0"
+
++#define MT7988_TOPRGU_SW_RST_NUM 24
++
+ static bool nowayout = WATCHDOG_NOWAYOUT;
+ static unsigned int timeout;
+
+@@ -72,10 +76,12 @@ struct mtk_wdt_dev {
+ struct reset_controller_dev rcdev;
+ bool disable_wdt_extrst;
+ bool reset_by_toprgu;
++ bool has_swsysrst_en;
+ };
+
+ struct mtk_wdt_data {
+ int toprgu_sw_rst_num;
++ bool has_swsysrst_en;
+ };
+
+ static const struct mtk_wdt_data mt2712_data = {
+@@ -94,6 +100,11 @@ static const struct mtk_wdt_data mt7986_
+ .toprgu_sw_rst_num = MT7986_TOPRGU_SW_RST_NUM,
+ };
+
++static const struct mtk_wdt_data mt7988_data = {
++ .toprgu_sw_rst_num = MT7988_TOPRGU_SW_RST_NUM,
++ .has_swsysrst_en = true,
++};
++
+ static const struct mtk_wdt_data mt8183_data = {
+ .toprgu_sw_rst_num = MT8183_TOPRGU_SW_RST_NUM,
+ };
+@@ -114,6 +125,28 @@ static const struct mtk_wdt_data mt8195_
+ .toprgu_sw_rst_num = MT8195_TOPRGU_SW_RST_NUM,
+ };
+
++/**
++ * toprgu_reset_sw_en_unlocked() - enable/disable software control for reset bit
++ * @data: Pointer to instance of driver data.
++ * @id: Bit number identifying the reset to be enabled or disabled.
++ * @enable: If true, enable software control for that bit, disable otherwise.
++ *
++ * Context: The caller must hold lock of struct mtk_wdt_dev.
++ */
++static void toprgu_reset_sw_en_unlocked(struct mtk_wdt_dev *data,
++ unsigned long id, bool enable)
++{
++ u32 tmp;
++
++ tmp = readl(data->wdt_base + WDT_SWSYSRST_EN);
++ if (enable)
++ tmp |= BIT(id);
++ else
++ tmp &= ~BIT(id);
++
++ writel(tmp, data->wdt_base + WDT_SWSYSRST_EN);
++}
++
+ static int toprgu_reset_update(struct reset_controller_dev *rcdev,
+ unsigned long id, bool assert)
+ {
+@@ -124,6 +157,9 @@ static int toprgu_reset_update(struct re
+
+ spin_lock_irqsave(&data->lock, flags);
+
++ if (assert && data->has_swsysrst_en)
++ toprgu_reset_sw_en_unlocked(data, id, true);
++
+ tmp = readl(data->wdt_base + WDT_SWSYSRST);
+ if (assert)
+ tmp |= BIT(id);
+@@ -132,6 +168,9 @@ static int toprgu_reset_update(struct re
+ tmp |= WDT_SWSYS_RST_KEY;
+ writel(tmp, data->wdt_base + WDT_SWSYSRST);
+
++ if (!assert && data->has_swsysrst_en)
++ toprgu_reset_sw_en_unlocked(data, id, false);
++
+ spin_unlock_irqrestore(&data->lock, flags);
+
+ return 0;
+@@ -417,6 +456,8 @@ static int mtk_wdt_probe(struct platform
+ wdt_data->toprgu_sw_rst_num);
+ if (err)
+ return err;
++
++ mtk_wdt->has_swsysrst_en = wdt_data->has_swsysrst_en;
+ }
+
+ mtk_wdt->disable_wdt_extrst =
+@@ -456,6 +497,7 @@ static const struct of_device_id mtk_wdt
+ { .compatible = "mediatek,mt6735-wdt", .data = &mt6735_data },
+ { .compatible = "mediatek,mt6795-wdt", .data = &mt6795_data },
+ { .compatible = "mediatek,mt7986-wdt", .data = &mt7986_data },
++ { .compatible = "mediatek,mt7988-wdt", .data = &mt7988_data },
+ { .compatible = "mediatek,mt8183-wdt", .data = &mt8183_data },
+ { .compatible = "mediatek,mt8186-wdt", .data = &mt8186_data },
+ { .compatible = "mediatek,mt8188-wdt", .data = &mt8188_data },
--- /dev/null
+From c202f510bbaa34ab5d65a69a61e0e72761374b17 Mon Sep 17 00:00:00 2001
+From: Daniel Golle <daniel@makrotopia.org>
+Date: Mon, 11 Mar 2024 17:14:19 +0000
+Subject: [PATCH] clk: mediatek: mt7988-infracfg: fix clocks for 2nd PCIe port
+
+Due to what seems to be an undocumented oddity in MediaTek's MT7988
+SoC design the CLK_INFRA_PCIE_PERI_26M_CK_P2 clock requires
+CLK_INFRA_PCIE_PERI_26M_CK_P3 to be enabled.
+
+This currently leads to PCIe port 2 not working in Linux.
+
+Reflect the apparent relationship in the clk driver to make sure PCIe
+port 2 of the MT7988 SoC works.
+
+Suggested-by: Sam Shih <sam.shih@mediatek.com>
+Signed-off-by: Daniel Golle <daniel@makrotopia.org>
+---
+ drivers/clk/mediatek/clk-mt7988-infracfg.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+--- a/drivers/clk/mediatek/clk-mt7988-infracfg.c
++++ b/drivers/clk/mediatek/clk-mt7988-infracfg.c
+@@ -156,7 +156,7 @@ static const struct mtk_gate infra_clks[
+ GATE_INFRA0(CLK_INFRA_PCIE_PERI_26M_CK_P1, "infra_pcie_peri_ck_26m_ck_p1",
+ "csw_infra_f26m_sel", 8),
+ GATE_INFRA0(CLK_INFRA_PCIE_PERI_26M_CK_P2, "infra_pcie_peri_ck_26m_ck_p2",
+- "csw_infra_f26m_sel", 9),
++ "infra_pcie_peri_ck_26m_ck_p3", 9),
+ GATE_INFRA0(CLK_INFRA_PCIE_PERI_26M_CK_P3, "infra_pcie_peri_ck_26m_ck_p3",
+ "csw_infra_f26m_sel", 10),
+ /* INFRA1 */
--- /dev/null
+From patchwork Wed Jan 17 12:42:33 2024
+Content-Type: text/plain; charset="utf-8"
+MIME-Version: 1.0
+Content-Transfer-Encoding: 7bit
+X-Patchwork-Submitter: Jean Thomas <jean.thomas@wifirst.fr>
+X-Patchwork-Id: 13521682
+Return-Path:
+ <linux-mediatek-bounces+linux-mediatek=archiver.kernel.org@lists.infradead.org>
+From: Jean Thomas <jean.thomas@wifirst.fr>
+To: sean.wang@kernel.org,
+ linus.walleij@linaro.org,
+ matthias.bgg@gmail.com,
+ angelogioacchino.delregno@collabora.com,
+ linux-mediatek@lists.infradead.org,
+ linux-gpio@vger.kernel.org,
+ linux-kernel@vger.kernel.org,
+ linux-arm-kernel@lists.infradead.org
+Cc: Jean Thomas <jean.thomas@wifirst.fr>
+Subject: [PATCH 1/2] pinctrl: mediatek: mt7981: add additional uart group
+Date: Wed, 17 Jan 2024 13:42:33 +0100
+Message-Id: <20240117124234.3137050-1-jean.thomas@wifirst.fr>
+MIME-Version: 1.0
+List-Id: <linux-mediatek.lists.infradead.org>
+
+Add uart1_3 (pins 26, 27) group to the pinctrl driver for the
+MediaTek MT7981 SoC.
+
+Signed-off-by: Jean Thomas <jean.thomas@wifirst.fr>
+Reviewed-by: Daniel Golle <daniel@makrotopia.org>
+---
+ drivers/pinctrl/mediatek/pinctrl-mt7981.c | 7 ++++++-
+ 1 file changed, 6 insertions(+), 1 deletion(-)
+
+--- a/drivers/pinctrl/mediatek/pinctrl-mt7981.c
++++ b/drivers/pinctrl/mediatek/pinctrl-mt7981.c
+@@ -737,6 +737,9 @@ static int mt7981_uart1_1_funcs[] = { 2,
+ static int mt7981_uart1_2_pins[] = { 9, 10, };
+ static int mt7981_uart1_2_funcs[] = { 2, 2, };
+
++static int mt7981_uart1_3_pins[] = { 26, 27, };
++static int mt7981_uart1_3_funcs[] = { 2, 2, };
++
+ /* UART2 */
+ static int mt7981_uart2_1_pins[] = { 22, 23, 24, 25, };
+ static int mt7981_uart2_1_funcs[] = { 3, 3, 3, 3, };
+@@ -871,6 +874,8 @@ static const struct group_desc mt7981_gr
+ PINCTRL_PIN_GROUP("uart1_1", mt7981_uart1_1),
+ /* @GPIO(9,10): UART1(2) */
+ PINCTRL_PIN_GROUP("uart1_2", mt7981_uart1_2),
++ /* @GPIO(26,27): UART1(2) */
++ PINCTRL_PIN_GROUP("uart1_3", mt7981_uart1_3),
+ /* @GPIO(22,25): UART1(3) */
+ PINCTRL_PIN_GROUP("uart2_1", mt7981_uart2_1),
+ /* @GPIO(22,24) PTA_EXT(4) */
+@@ -933,7 +938,7 @@ static const struct group_desc mt7981_gr
+ static const char *mt7981_wa_aice_groups[] = { "wa_aice1", "wa_aice2", "wm_aice1_1",
+ "wa_aice3", "wm_aice1_2", };
+ static const char *mt7981_uart_groups[] = { "net_wo0_uart_txd_0", "net_wo0_uart_txd_1",
+- "net_wo0_uart_txd_2", "uart0", "uart1_0", "uart1_1", "uart1_2", "uart2_0",
++ "net_wo0_uart_txd_2", "uart0", "uart1_0", "uart1_1", "uart1_2", "uart1_3", "uart2_0",
+ "uart2_0_tx_rx", "uart2_1", "wm_uart_0", "wm_aurt_1", "wm_aurt_2", };
+ static const char *mt7981_dfd_groups[] = { "dfd", "dfd_ntrst", };
+ static const char *mt7981_wdt_groups[] = { "watchdog", "watchdog1", };
--- /dev/null
+From patchwork Wed Jan 17 14:55:47 2024
+Content-Type: text/plain; charset="utf-8"
+MIME-Version: 1.0
+Content-Transfer-Encoding: 7bit
+X-Patchwork-Submitter: Jean Thomas <jean.thomas@wifirst.fr>
+X-Patchwork-Id: 13521855
+Return-Path:
+ <linux-mediatek-bounces+linux-mediatek=archiver.kernel.org@lists.infradead.org>
+From: Jean Thomas <jean.thomas@wifirst.fr>
+To: sean.wang@kernel.org,
+ linus.walleij@linaro.org,
+ matthias.bgg@gmail.com,
+ angelogioacchino.delregno@collabora.com,
+ linux-mediatek@lists.infradead.org,
+ linux-gpio@vger.kernel.org,
+ linux-kernel@vger.kernel.org,
+ linux-arm-kernel@lists.infradead.org
+Cc: Jean Thomas <jean.thomas@wifirst.fr>,
+ Daniel Golle <daniel@makrotopia.org>
+Subject: [PATCH v2 2/2] pinctrl: mediatek: mt7981: add additional emmc groups
+Date: Wed, 17 Jan 2024 15:55:47 +0100
+Message-Id: <20240117145547.3354242-1-jean.thomas@wifirst.fr>
+List-Id: <linux-mediatek.lists.infradead.org>
+
+Add new emmc groups in the pinctrl driver for the
+MediaTek MT7981 SoC:
+* emmc reset, with pin 15.
+* emmc 4-bit bus-width, with pins 16 to 19, and 24 to 25.
+* emmc 8-bit bus-width, with pins 16 to 25.
+
+The existing emmc_45 group is kept for legacy reasons, even
+if this is the union of emmc_reset and emmc_8 groups.
+
+Signed-off-by: Jean Thomas <jean.thomas@wifirst.fr>
+Reviewed-by: Daniel Golle <daniel@makrotopia.org>
+---
+ drivers/pinctrl/mediatek/pinctrl-mt7981.c | 17 ++++++++++++++++-
+ 1 file changed, 16 insertions(+), 1 deletion(-)
+
+--
+2.39.2
+
+--- a/drivers/pinctrl/mediatek/pinctrl-mt7981.c
++++ b/drivers/pinctrl/mediatek/pinctrl-mt7981.c
+@@ -700,6 +700,15 @@ static int mt7981_drv_vbus_pins[] = { 14
+ static int mt7981_drv_vbus_funcs[] = { 1, };
+
+ /* EMMC */
++static int mt7981_emmc_reset_pins[] = { 15, };
++static int mt7981_emmc_reset_funcs[] = { 2, };
++
++static int mt7981_emmc_4_pins[] = { 16, 17, 18, 19, 24, 25, };
++static int mt7981_emmc_4_funcs[] = { 2, 2, 2, 2, 2, 2, };
++
++static int mt7981_emmc_8_pins[] = { 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, };
++static int mt7981_emmc_8_funcs[] = { 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, };
++
+ static int mt7981_emmc_45_pins[] = { 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, };
+ static int mt7981_emmc_45_funcs[] = { 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, };
+
+@@ -854,6 +863,12 @@ static const struct group_desc mt7981_gr
+ PINCTRL_PIN_GROUP("udi", mt7981_udi),
+ /* @GPIO(14) DRV_VBUS(1) */
+ PINCTRL_PIN_GROUP("drv_vbus", mt7981_drv_vbus),
++ /* @GPIO(15): EMMC_RSTB(2) */
++ PINCTRL_PIN_GROUP("emmc_reset", mt7981_emmc_reset),
++ /* @GPIO(16,17,18,19,24,25): EMMC_DATx, EMMC_CLK, EMMC_CMD */
++ PINCTRL_PIN_GROUP("emmc_4", mt7981_emmc_4),
++ /* @GPIO(16,17,18,19,20,21,22,23,24,25): EMMC_DATx, EMMC_CLK, EMMC_CMD */
++ PINCTRL_PIN_GROUP("emmc_8", mt7981_emmc_8),
+ /* @GPIO(15,25): EMMC(2) */
+ PINCTRL_PIN_GROUP("emmc_45", mt7981_emmc_45),
+ /* @GPIO(16,21): SNFI(3) */
+@@ -957,7 +972,7 @@ static const char *mt7981_i2c_groups[] =
+ static const char *mt7981_pcm_groups[] = { "pcm", };
+ static const char *mt7981_udi_groups[] = { "udi", };
+ static const char *mt7981_usb_groups[] = { "drv_vbus", };
+-static const char *mt7981_flash_groups[] = { "emmc_45", "snfi", };
++static const char *mt7981_flash_groups[] = { "emmc_reset", "emmc_4", "emmc_8", "emmc_45", "snfi", };
+ static const char *mt7981_ethernet_groups[] = { "smi_mdc_mdio", "gbe_ext_mdc_mdio",
+ "wf0_mode1", "wf0_mode3", "mt7531_int", };
+ static const char *mt7981_ant_groups[] = { "ant_sel", };
--- /dev/null
+From patchwork Fri Nov 1 03:19:39 2024
+Content-Type: text/plain; charset="utf-8"
+MIME-Version: 1.0
+Content-Transfer-Encoding: 7bit
+X-Patchwork-Submitter: Daniel Golle <daniel@makrotopia.org>
+X-Patchwork-Id: 13858671
+Return-Path:
+ <linux-mediatek-bounces+linux-mediatek=archiver.kernel.org@lists.infradead.org>
+Date: Fri, 1 Nov 2024 03:19:39 +0000
+From: Daniel Golle <daniel@makrotopia.org>
+To: linux-mediatek@lists.infradead.org, linux-arm-kernel@lists.infradead.org,
+ linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, Uwe
+ =?iso-8859-1?q?Kleine-K=F6nig?= <u.kleine-koenig@baylibre.com>,
+ Sam Shih <sam.shih@mediatek.com>, Frank Wunderlich <frank-w@public-files.de>,
+ Daniel Golle <daniel@makrotopia.org>,
+ AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>,
+ Matthias Brugger <matthias.bgg@gmail.com>, Stephen Boyd <sboyd@kernel.org>,
+ Michael Turquette <mturquette@baylibre.com>
+Subject: [PATCH] clk: mediatek: mt7988-infracfg: SPI0 clocks are not critical
+Message-ID: <ZyRIy22aS_Yjoavg@pidgin.makrotopia.org>
+MIME-Version: 1.0
+Content-Disposition: inline
+X-BeenThere: linux-mediatek@lists.infradead.org
+X-Mailman-Version: 2.1.34
+Precedence: list
+List-Id: <linux-mediatek.lists.infradead.org>
+List-Unsubscribe: <http://lists.infradead.org/mailman/options/linux-mediatek>,
+ <mailto:linux-mediatek-request@lists.infradead.org?subject=unsubscribe>
+List-Archive: <http://lists.infradead.org/pipermail/linux-mediatek/>
+List-Post: <mailto:linux-mediatek@lists.infradead.org>
+List-Help: <mailto:linux-mediatek-request@lists.infradead.org?subject=help>
+List-Subscribe: <http://lists.infradead.org/mailman/listinfo/linux-mediatek>,
+ <mailto:linux-mediatek-request@lists.infradead.org?subject=subscribe>
+Sender: "Linux-mediatek" <linux-mediatek-bounces@lists.infradead.org>
+Errors-To:
+ linux-mediatek-bounces+linux-mediatek=archiver.kernel.org@lists.infradead.org
+
+SPI0 clocks have wrongly been marked as critical while, probably due
+to the SPI driver not requesting them. This can (and should) be addressed
+in device tree instead.
+Remove CLK_IS_CRITICAL flag from clocks related to SPI0.
+
+Fixes: 4b4719437d85 ("clk: mediatek: add drivers for MT7988 SoC")
+Signed-off-by: Daniel Golle <daniel@makrotopia.org>
+---
+ drivers/clk/mediatek/clk-mt7988-infracfg.c | 6 ++----
+ 1 file changed, 2 insertions(+), 4 deletions(-)
+
+--- a/drivers/clk/mediatek/clk-mt7988-infracfg.c
++++ b/drivers/clk/mediatek/clk-mt7988-infracfg.c
+@@ -196,12 +196,10 @@ static const struct mtk_gate infra_clks[
+ GATE_INFRA2(CLK_INFRA_SPINFI, "infra_f_fspinfi", "spinfi_sel", 10),
+ GATE_INFRA2_FLAGS(CLK_INFRA_66M_NFI_HCK, "infra_hf_66m_nfi_hck", "sysaxi_sel", 11,
+ CLK_IS_CRITICAL),
+- GATE_INFRA2_FLAGS(CLK_INFRA_104M_SPI0, "infra_hf_104m_spi0", "infra_mux_spi0_sel", 12,
+- CLK_IS_CRITICAL),
++ GATE_INFRA2(CLK_INFRA_104M_SPI0, "infra_hf_104m_spi0", "infra_mux_spi0_sel", 12),
+ GATE_INFRA2(CLK_INFRA_104M_SPI1, "infra_hf_104m_spi1", "infra_mux_spi1_sel", 13),
+ GATE_INFRA2(CLK_INFRA_104M_SPI2_BCK, "infra_hf_104m_spi2_bck", "infra_mux_spi2_sel", 14),
+- GATE_INFRA2_FLAGS(CLK_INFRA_66M_SPI0_HCK, "infra_hf_66m_spi0_hck", "sysaxi_sel", 15,
+- CLK_IS_CRITICAL),
++ GATE_INFRA2(CLK_INFRA_66M_SPI0_HCK, "infra_hf_66m_spi0_hck", "sysaxi_sel", 15),
+ GATE_INFRA2(CLK_INFRA_66M_SPI1_HCK, "infra_hf_66m_spi1_hck", "sysaxi_sel", 16),
+ GATE_INFRA2(CLK_INFRA_66M_SPI2_HCK, "infra_hf_66m_spi2_hck", "sysaxi_sel", 17),
+ GATE_INFRA2(CLK_INFRA_66M_FLASHIF_AXI, "infra_hf_66m_flashif_axi", "sysaxi_sel", 18),
--- /dev/null
+--- a/drivers/mtd/nand/spi/core.c
++++ b/drivers/mtd/nand/spi/core.c
+@@ -19,6 +19,7 @@
+ #include <linux/string.h>
+ #include <linux/spi/spi.h>
+ #include <linux/spi/spi-mem.h>
++#include <linux/mtd/mtk_bmt.h>
+
+ static int spinand_read_reg_op(struct spinand_device *spinand, u8 reg, u8 *val)
+ {
+@@ -1347,6 +1348,7 @@ static int spinand_probe(struct spi_mem
+ if (ret)
+ return ret;
+
++ mtk_bmt_attach(mtd);
+ ret = mtd_device_register(mtd, NULL, 0);
+ if (ret)
+ goto err_spinand_cleanup;
+@@ -1354,6 +1356,7 @@ static int spinand_probe(struct spi_mem
+ return 0;
+
+ err_spinand_cleanup:
++ mtk_bmt_detach(mtd);
+ spinand_cleanup(spinand);
+
+ return ret;
+@@ -1372,6 +1375,7 @@ static int spinand_remove(struct spi_mem
+ if (ret)
+ return ret;
+
++ mtk_bmt_detach(mtd);
+ spinand_cleanup(spinand);
+
+ return 0;
--- /dev/null
+--- a/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts
++++ b/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts
+@@ -548,6 +548,7 @@
+ spi-tx-bus-width = <4>;
+ spi-rx-bus-width = <4>;
+ nand-ecc-engine = <&snfi>;
++ mediatek,bmt-v2;
+
+ partitions {
+ compatible = "fixed-partitions";
--- /dev/null
+From 5f49a5c9b16330e0df8f639310e4715dcad71947 Mon Sep 17 00:00:00 2001
+From: Davide Fioravanti <pantanastyle@gmail.com>
+Date: Fri, 8 Jan 2021 15:35:24 +0100
+Subject: [PATCH] mtd: spinand: Add support for the Fidelix FM35X1GA
+
+Datasheet: http://www.hobos.com.cn/upload/datasheet/DS35X1GAXXX_100_rev00.pdf
+
+Signed-off-by: Davide Fioravanti <pantanastyle@gmail.com>
+---
+ drivers/mtd/nand/spi/Makefile | 2 +-
+ drivers/mtd/nand/spi/core.c | 1 +
+ drivers/mtd/nand/spi/fidelix.c | 76 ++++++++++++++++++++++++++++++++++
+ include/linux/mtd/spinand.h | 1 +
+ 4 files changed, 79 insertions(+), 1 deletion(-)
+ create mode 100644 drivers/mtd/nand/spi/fidelix.c
+
+--- a/drivers/mtd/nand/spi/Makefile
++++ b/drivers/mtd/nand/spi/Makefile
+@@ -1,4 +1,4 @@
+ # SPDX-License-Identifier: GPL-2.0
+-spinand-objs := core.o alliancememory.o ato.o esmt.o etron.o foresee.o gigadevice.o
++spinand-objs := core.o alliancememory.o ato.o esmt.o etron.o fidelix.o foresee.o gigadevice.o
+ spinand-objs += macronix.o micron.o paragon.o toshiba.o winbond.o xtx.o
+ obj-$(CONFIG_MTD_SPI_NAND) += spinand.o
+--- a/drivers/mtd/nand/spi/core.c
++++ b/drivers/mtd/nand/spi/core.c
+@@ -942,6 +942,7 @@ static const struct spinand_manufacturer
+ &ato_spinand_manufacturer,
+ &esmt_c8_spinand_manufacturer,
+ &etron_spinand_manufacturer,
++ &fidelix_spinand_manufacturer,
+ &foresee_spinand_manufacturer,
+ &gigadevice_spinand_manufacturer,
+ ¯onix_spinand_manufacturer,
+--- /dev/null
++++ b/drivers/mtd/nand/spi/fidelix.c
+@@ -0,0 +1,76 @@
++// SPDX-License-Identifier: GPL-2.0
++/*
++ * Copyright (c) 2020 Davide Fioravanti <pantanastyle@gmail.com>
++ */
++
++#include <linux/device.h>
++#include <linux/kernel.h>
++#include <linux/mtd/spinand.h>
++
++#define SPINAND_MFR_FIDELIX 0xE5
++#define FIDELIX_ECCSR_MASK 0x0F
++
++static SPINAND_OP_VARIANTS(read_cache_variants,
++ SPINAND_PAGE_READ_FROM_CACHE_X4_OP(0, 1, NULL, 0),
++ SPINAND_PAGE_READ_FROM_CACHE_OP(true, 0, 1, NULL, 0),
++ SPINAND_PAGE_READ_FROM_CACHE_OP(false, 0, 1, NULL, 0));
++
++static SPINAND_OP_VARIANTS(write_cache_variants,
++ SPINAND_PROG_LOAD_X4(true, 0, NULL, 0),
++ SPINAND_PROG_LOAD(true, 0, NULL, 0));
++
++static SPINAND_OP_VARIANTS(update_cache_variants,
++ SPINAND_PROG_LOAD_X4(true, 0, NULL, 0),
++ SPINAND_PROG_LOAD(true, 0, NULL, 0));
++
++static int fm35x1ga_ooblayout_ecc(struct mtd_info *mtd, int section,
++ struct mtd_oob_region *region)
++{
++ if (section > 3)
++ return -ERANGE;
++
++ region->offset = (16 * section) + 8;
++ region->length = 8;
++
++ return 0;
++}
++
++static int fm35x1ga_ooblayout_free(struct mtd_info *mtd, int section,
++ struct mtd_oob_region *region)
++{
++ if (section > 3)
++ return -ERANGE;
++
++ region->offset = (16 * section) + 2;
++ region->length = 6;
++
++ return 0;
++}
++
++static const struct mtd_ooblayout_ops fm35x1ga_ooblayout = {
++ .ecc = fm35x1ga_ooblayout_ecc,
++ .free = fm35x1ga_ooblayout_free,
++};
++
++static const struct spinand_info fidelix_spinand_table[] = {
++ SPINAND_INFO("FM35X1GA",
++ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x71),
++ NAND_MEMORG(1, 2048, 64, 64, 1024, 20, 1, 1, 1),
++ NAND_ECCREQ(4, 512),
++ SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
++ &write_cache_variants,
++ &update_cache_variants),
++ SPINAND_HAS_QE_BIT,
++ SPINAND_ECCINFO(&fm35x1ga_ooblayout, NULL)),
++};
++
++static const struct spinand_manufacturer_ops fidelix_spinand_manuf_ops = {
++};
++
++const struct spinand_manufacturer fidelix_spinand_manufacturer = {
++ .id = SPINAND_MFR_FIDELIX,
++ .name = "Fidelix",
++ .chips = fidelix_spinand_table,
++ .nchips = ARRAY_SIZE(fidelix_spinand_table),
++ .ops = &fidelix_spinand_manuf_ops,
++};
+--- a/include/linux/mtd/spinand.h
++++ b/include/linux/mtd/spinand.h
+@@ -264,6 +264,7 @@ extern const struct spinand_manufacturer
+ extern const struct spinand_manufacturer ato_spinand_manufacturer;
+ extern const struct spinand_manufacturer esmt_c8_spinand_manufacturer;
+ extern const struct spinand_manufacturer etron_spinand_manufacturer;
++extern const struct spinand_manufacturer fidelix_spinand_manufacturer;
+ extern const struct spinand_manufacturer foresee_spinand_manufacturer;
+ extern const struct spinand_manufacturer gigadevice_spinand_manufacturer;
+ extern const struct spinand_manufacturer macronix_spinand_manufacturer;
--- /dev/null
+From patchwork Fri Apr 19 16:59:07 2024
+Content-Type: text/plain; charset="utf-8"
+MIME-Version: 1.0
+Content-Transfer-Encoding: 7bit
+X-Patchwork-Submitter: Daniel Golle <daniel@makrotopia.org>
+X-Patchwork-Id: 13636668
+Return-Path:
+ <linux-mediatek-bounces+linux-mediatek=archiver.kernel.org@lists.infradead.org>
+Date: Fri, 19 Apr 2024 17:59:07 +0100
+From: Daniel Golle <daniel@makrotopia.org>
+To: "Rafael J. Wysocki" <rafael@kernel.org>,
+ Viresh Kumar <viresh.kumar@linaro.org>,
+ Matthias Brugger <matthias.bgg@gmail.com>,
+ AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>,
+ linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org,
+ linux-arm-kernel@lists.infradead.org,
+ linux-mediatek@lists.infradead.org
+Subject: [PATCH] cpufreq: mediatek: Add support for MT7988A
+Message-ID:
+ <acf4fb446aacfbf6ce7b6e94bf3aad303e0ad4d1.1713545923.git.daniel@makrotopia.org>
+Content-Disposition: inline
+List-Id: <linux-mediatek.lists.infradead.org>
+
+From: Sam Shih <sam.shih@mediatek.com>
+
+This add cpufreq support for mediatek MT7988A SoC.
+
+The platform data of MT7988A is different from previous MediaTek SoCs,
+so we add a new compatible and platform data for it.
+
+Signed-off-by: Sam Shih <sam.shih@mediatek.com>
+---
+ drivers/cpufreq/mediatek-cpufreq.c | 10 ++++++++++
+ 1 file changed, 10 insertions(+)
+
+--- a/drivers/cpufreq/mediatek-cpufreq.c
++++ b/drivers/cpufreq/mediatek-cpufreq.c
+@@ -707,6 +707,15 @@ static const struct mtk_cpufreq_platform
+ .ccifreq_supported = false,
+ };
+
++static const struct mtk_cpufreq_platform_data mt7988_platform_data = {
++ .min_volt_shift = 100000,
++ .max_volt_shift = 200000,
++ .proc_max_volt = 900000,
++ .sram_min_volt = 0,
++ .sram_max_volt = 1150000,
++ .ccifreq_supported = true,
++};
++
+ static const struct mtk_cpufreq_platform_data mt8183_platform_data = {
+ .min_volt_shift = 100000,
+ .max_volt_shift = 200000,
+@@ -740,6 +749,8 @@ static const struct of_device_id mtk_cpu
+ { .compatible = "mediatek,mt2712", .data = &mt2701_platform_data },
+ { .compatible = "mediatek,mt7622", .data = &mt7622_platform_data },
+ { .compatible = "mediatek,mt7623", .data = &mt7623_platform_data },
++ { .compatible = "mediatek,mt7988a", .data = &mt7988_platform_data },
++ { .compatible = "mediatek,mt7988d", .data = &mt7988_platform_data },
+ { .compatible = "mediatek,mt8167", .data = &mt8516_platform_data },
+ { .compatible = "mediatek,mt817x", .data = &mt2701_platform_data },
+ { .compatible = "mediatek,mt8173", .data = &mt2701_platform_data },
--- /dev/null
+--- a/drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.c
++++ b/drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.c
+@@ -601,6 +601,30 @@ out:
+ return err;
+ }
+
++static int mtk_pinconf_bias_set_pd(struct mtk_pinctrl *hw,
++ const struct mtk_pin_desc *desc,
++ u32 pullup, u32 arg)
++{
++ int err, pd;
++
++ if (arg == MTK_DISABLE)
++ pd = 0;
++ else if ((arg == MTK_ENABLE) && pullup)
++ pd = 0;
++ else if ((arg == MTK_ENABLE) && !pullup)
++ pd = 1;
++ else {
++ err = -EINVAL;
++ goto out;
++ }
++
++ err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_PD, pd);
++
++out:
++ return err;
++
++}
++
+ static int mtk_pinconf_bias_set_pullsel_pullen(struct mtk_pinctrl *hw,
+ const struct mtk_pin_desc *desc,
+ u32 pullup, u32 arg)
+@@ -758,6 +782,12 @@ int mtk_pinconf_bias_set_combo(struct mt
+ return 0;
+ }
+
++ if (try_all_type & MTK_PULL_PD_TYPE) {
++ err = mtk_pinconf_bias_set_pd(hw, desc, pullup, arg);
++ if (!err)
++ return err;
++ }
++
+ if (try_all_type & MTK_PULL_PU_PD_TYPE) {
+ err = mtk_pinconf_bias_set_pu_pd(hw, desc, pullup, arg);
+ if (!err)
+@@ -878,6 +908,29 @@ out:
+ return err;
+ }
+
++static int mtk_pinconf_bias_get_pd(struct mtk_pinctrl *hw,
++ const struct mtk_pin_desc *desc,
++ u32 *pullup, u32 *enable)
++{
++ int err, pd;
++
++ err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_PD, &pd);
++ if (err)
++ goto out;
++
++ if (pd == 0) {
++ *pullup = 0;
++ *enable = MTK_DISABLE;
++ } else if (pd == 1) {
++ *pullup = 0;
++ *enable = MTK_ENABLE;
++ } else
++ err = -EINVAL;
++
++out:
++ return err;
++}
++
+ static int mtk_pinconf_bias_get_pullsel_pullen(struct mtk_pinctrl *hw,
+ const struct mtk_pin_desc *desc,
+ u32 *pullup, u32 *enable)
+@@ -947,6 +1000,12 @@ int mtk_pinconf_bias_get_combo(struct mt
+ return 0;
+ }
+
++ if (try_all_type & MTK_PULL_PD_TYPE) {
++ err = mtk_pinconf_bias_get_pd(hw, desc, pullup, enable);
++ if (!err)
++ return err;
++ }
++
+ if (try_all_type & MTK_PULL_PU_PD_TYPE) {
+ err = mtk_pinconf_bias_get_pu_pd(hw, desc, pullup, enable);
+ if (!err)
+--- a/drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.h
++++ b/drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.h
+@@ -24,6 +24,7 @@
+ * turned on/off itself. But it can't be selected pull up/down
+ */
+ #define MTK_PULL_RSEL_TYPE BIT(3)
++#define MTK_PULL_PD_TYPE BIT(4)
+ /* MTK_PULL_PU_PD_RSEL_TYPE is a type which is controlled by
+ * MTK_PULL_PU_PD_TYPE and MTK_PULL_RSEL_TYPE.
+ */
--- /dev/null
+--- a/drivers/crypto/inside-secure/safexcel.c
++++ b/drivers/crypto/inside-secure/safexcel.c
+@@ -608,6 +608,14 @@ static int safexcel_hw_init(struct safex
+ val |= EIP197_MST_CTRL_TX_MAX_CMD(5);
+ writel(val, EIP197_HIA_AIC(priv) + EIP197_HIA_MST_CTRL);
+ }
++ /*
++ * Set maximum number of TX commands to 2^4 = 16 for EIP97 HW2.1/HW2.3
++ */
++ else {
++ val = 0;
++ val |= EIP97_MST_CTRL_TX_MAX_CMD(4);
++ writel(val, EIP197_HIA_AIC(priv) + EIP197_HIA_MST_CTRL);
++ }
+
+ /* Configure wr/rd cache values */
+ writel(EIP197_MST_CTRL_RD_CACHE(RD_CACHE_4BITS) |
+--- a/drivers/crypto/inside-secure/safexcel.h
++++ b/drivers/crypto/inside-secure/safexcel.h
+@@ -315,6 +315,7 @@
+ #define EIP197_MST_CTRL_RD_CACHE(n) (((n) & 0xf) << 0)
+ #define EIP197_MST_CTRL_WD_CACHE(n) (((n) & 0xf) << 4)
+ #define EIP197_MST_CTRL_TX_MAX_CMD(n) (((n) & 0xf) << 20)
++#define EIP97_MST_CTRL_TX_MAX_CMD(n) (((n) & 0xf) << 4)
+ #define EIP197_MST_CTRL_BYTE_SWAP BIT(24)
+ #define EIP197_MST_CTRL_NO_BYTE_SWAP BIT(25)
+ #define EIP197_MST_CTRL_BYTE_SWAP_BITS GENMASK(25, 24)
--- /dev/null
+--- a/drivers/crypto/inside-secure/safexcel.h
++++ b/drivers/crypto/inside-secure/safexcel.h
+@@ -743,6 +743,9 @@ struct safexcel_priv_data {
+ /* Priority we use for advertising our algorithms */
+ #define SAFEXCEL_CRA_PRIORITY 300
+
++/* System cache line size */
++#define SYSTEM_CACHELINE_SIZE 64
++
+ /* SM3 digest result for zero length message */
+ #define EIP197_SM3_ZEROM_HASH "\x1A\xB2\x1D\x83\x55\xCF\xA1\x7F" \
+ "\x8E\x61\x19\x48\x31\xE8\x1A\x8F" \
+--- a/drivers/crypto/inside-secure/safexcel_hash.c
++++ b/drivers/crypto/inside-secure/safexcel_hash.c
+@@ -55,9 +55,9 @@ struct safexcel_ahash_req {
+ u8 block_sz; /* block size, only set once */
+ u8 digest_sz; /* output digest size, only set once */
+ __le32 state[SHA3_512_BLOCK_SIZE /
+- sizeof(__le32)] __aligned(sizeof(__le32));
++ sizeof(__le32)] __aligned(SYSTEM_CACHELINE_SIZE);
+
+- u64 len;
++ u64 len __aligned(SYSTEM_CACHELINE_SIZE);
+ u64 processed;
+
+ u8 cache[HASH_CACHE_SIZE] __aligned(sizeof(u32));
--- /dev/null
+--- a/drivers/tty/serial/8250/8250.h
++++ b/drivers/tty/serial/8250/8250.h
+@@ -86,6 +86,7 @@ struct serial8250_config {
+ * STOP PARITY EPAR SPAR WLEN5 WLEN6
+ */
+ #define UART_CAP_NOTEMT BIT(18) /* UART without interrupt on TEMT available */
++#define UART_CAP_NMOD BIT(19) /* UART doesn't do termios */
+
+ #define UART_BUG_QUOT BIT(0) /* UART has buggy quot LSB */
+ #define UART_BUG_TXEN BIT(1) /* UART has buggy TX IIR status */
+--- a/drivers/tty/serial/8250/8250_port.c
++++ b/drivers/tty/serial/8250/8250_port.c
+@@ -287,7 +287,7 @@ static const struct serial8250_config ua
+ .tx_loadsz = 16,
+ .fcr = UART_FCR_ENABLE_FIFO |
+ UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT,
+- .flags = UART_CAP_FIFO,
++ .flags = UART_CAP_FIFO | UART_CAP_NMOD,
+ },
+ [PORT_NPCM] = {
+ .name = "Nuvoton 16550",
+@@ -2783,6 +2783,11 @@ serial8250_do_set_termios(struct uart_po
+ unsigned long flags;
+ unsigned int baud, quot, frac = 0;
+
++ if (up->capabilities & UART_CAP_NMOD) {
++ termios->c_cflag = 0;
++ return;
++ }
++
+ if (up->capabilities & UART_CAP_MINI) {
+ termios->c_cflag &= ~(CSTOPB | PARENB | PARODD | CMSPAR);
+ if ((termios->c_cflag & CSIZE) == CS5 ||
--- /dev/null
+From bfd3acc428085742d754a6d328d1a93ebf9451df Mon Sep 17 00:00:00 2001
+From: "SkyLake.Huang" <skylake.huang@mediatek.com>
+Date: Thu, 23 Jun 2022 18:29:51 +0800
+Subject: [PATCH 1/6] drivers: spi-mt65xx: Move chip_config to driver's private
+ data
+
+Signed-off-by: SkyLake.Huang <skylake.huang@mediatek.com>
+---
+ drivers/spi/spi-mt65xx.c | 29 +++++++++---------------
+ include/linux/platform_data/spi-mt65xx.h | 17 --------------
+ 2 files changed, 11 insertions(+), 35 deletions(-)
+ delete mode 100644 include/linux/platform_data/spi-mt65xx.h
+
+--- a/drivers/spi/spi-mt65xx.c
++++ b/drivers/spi/spi-mt65xx.c
+@@ -14,7 +14,6 @@
+ #include <linux/of.h>
+ #include <linux/gpio/consumer.h>
+ #include <linux/platform_device.h>
+-#include <linux/platform_data/spi-mt65xx.h>
+ #include <linux/pm_runtime.h>
+ #include <linux/spi/spi.h>
+ #include <linux/spi/spi-mem.h>
+@@ -171,6 +170,8 @@ struct mtk_spi {
+ struct device *dev;
+ dma_addr_t tx_dma;
+ dma_addr_t rx_dma;
++ u32 sample_sel;
++ u32 get_tick_dly;
+ };
+
+ static const struct mtk_spi_compatible mtk_common_compat;
+@@ -216,15 +217,6 @@ static const struct mtk_spi_compatible m
+ .no_need_unprepare = true,
+ };
+
+-/*
+- * A piece of default chip info unless the platform
+- * supplies it.
+- */
+-static const struct mtk_chip_config mtk_default_chip_info = {
+- .sample_sel = 0,
+- .tick_delay = 0,
+-};
+-
+ static const struct of_device_id mtk_spi_of_match[] = {
+ { .compatible = "mediatek,spi-ipm",
+ .data = (void *)&mtk_ipm_compat,
+@@ -352,7 +344,6 @@ static int mtk_spi_hw_init(struct spi_ma
+ {
+ u16 cpha, cpol;
+ u32 reg_val;
+- struct mtk_chip_config *chip_config = spi->controller_data;
+ struct mtk_spi *mdata = spi_master_get_devdata(master);
+
+ cpha = spi->mode & SPI_CPHA ? 1 : 0;
+@@ -402,7 +393,7 @@ static int mtk_spi_hw_init(struct spi_ma
+ else
+ reg_val &= ~SPI_CMD_CS_POL;
+
+- if (chip_config->sample_sel)
++ if (mdata->sample_sel)
+ reg_val |= SPI_CMD_SAMPLE_SEL;
+ else
+ reg_val &= ~SPI_CMD_SAMPLE_SEL;
+@@ -429,20 +420,20 @@ static int mtk_spi_hw_init(struct spi_ma
+ if (mdata->dev_comp->ipm_design) {
+ reg_val = readl(mdata->base + SPI_CMD_REG);
+ reg_val &= ~SPI_CMD_IPM_GET_TICKDLY_MASK;
+- reg_val |= ((chip_config->tick_delay & 0x7)
++ reg_val |= ((mdata->get_tick_dly & 0x7)
+ << SPI_CMD_IPM_GET_TICKDLY_OFFSET);
+ writel(reg_val, mdata->base + SPI_CMD_REG);
+ } else {
+ reg_val = readl(mdata->base + SPI_CFG1_REG);
+ reg_val &= ~SPI_CFG1_GET_TICK_DLY_MASK;
+- reg_val |= ((chip_config->tick_delay & 0x7)
++ reg_val |= ((mdata->get_tick_dly & 0x7)
+ << SPI_CFG1_GET_TICK_DLY_OFFSET);
+ writel(reg_val, mdata->base + SPI_CFG1_REG);
+ }
+ } else {
+ reg_val = readl(mdata->base + SPI_CFG1_REG);
+ reg_val &= ~SPI_CFG1_GET_TICK_DLY_MASK_V1;
+- reg_val |= ((chip_config->tick_delay & 0x3)
++ reg_val |= ((mdata->get_tick_dly & 0x3)
+ << SPI_CFG1_GET_TICK_DLY_OFFSET_V1);
+ writel(reg_val, mdata->base + SPI_CFG1_REG);
+ }
+@@ -732,9 +723,6 @@ static int mtk_spi_setup(struct spi_devi
+ {
+ struct mtk_spi *mdata = spi_master_get_devdata(spi->master);
+
+- if (!spi->controller_data)
+- spi->controller_data = (void *)&mtk_default_chip_info;
+-
+ if (mdata->dev_comp->need_pad_sel && spi_get_csgpiod(spi, 0))
+ /* CS de-asserted, gpiolib will handle inversion */
+ gpiod_direction_output(spi_get_csgpiod(spi, 0), 0);
+@@ -1140,6 +1128,10 @@ static int mtk_spi_probe(struct platform
+ mdata = spi_master_get_devdata(master);
+ mdata->dev_comp = device_get_match_data(dev);
+
++ /* Set device configs to default first. Calibrate it later. */
++ mdata->sample_sel = 0;
++ mdata->get_tick_dly = 2;
++
+ if (mdata->dev_comp->enhance_timing)
+ master->mode_bits |= SPI_CS_HIGH;
+
+--- a/include/linux/platform_data/spi-mt65xx.h
++++ /dev/null
+@@ -1,17 +0,0 @@
+-/* SPDX-License-Identifier: GPL-2.0-only */
+-/*
+- * MTK SPI bus driver definitions
+- *
+- * Copyright (c) 2015 MediaTek Inc.
+- * Author: Leilk Liu <leilk.liu@mediatek.com>
+- */
+-
+-#ifndef ____LINUX_PLATFORM_DATA_SPI_MTK_H
+-#define ____LINUX_PLATFORM_DATA_SPI_MTK_H
+-
+-/* Board specific platform_data */
+-struct mtk_chip_config {
+- u32 sample_sel;
+- u32 tick_delay;
+-};
+-#endif
--- /dev/null
+From 2ade0172154e50c8a2bfd8634c6eff943cffea29 Mon Sep 17 00:00:00 2001
+From: "SkyLake.Huang" <skylake.huang@mediatek.com>
+Date: Thu, 23 Jun 2022 18:35:52 +0800
+Subject: [PATCH 2/6] drivers: spi: Add support for dynamic calibration
+
+Signed-off-by: SkyLake.Huang <skylake.huang@mediatek.com>
+---
+ drivers/spi/spi.c | 137 ++++++++++++++++++++++++++++++++++++++++
+ include/linux/spi/spi.h | 42 ++++++++++++
+ 2 files changed, 179 insertions(+)
+
+--- a/drivers/spi/spi.c
++++ b/drivers/spi/spi.c
+@@ -1380,6 +1380,70 @@ static int spi_transfer_wait(struct spi_
+ return 0;
+ }
+
++int spi_do_calibration(struct spi_controller *ctlr, struct spi_device *spi,
++ int (*cal_read)(void *priv, u32 *addr, int addrlen, u8 *buf, int readlen), void *drv_priv)
++{
++ int datalen = ctlr->cal_rule->datalen;
++ int addrlen = ctlr->cal_rule->addrlen;
++ u8 *buf;
++ int ret;
++ int i;
++ struct list_head *cal_head, *listptr;
++ struct spi_cal_target *target;
++
++ /* Calculate calibration result */
++ int hit_val, total_hit, origin;
++ bool hit;
++
++ /* Make sure we can start calibration */
++ if(!ctlr->cal_target || !ctlr->cal_rule || !ctlr->append_caldata)
++ return 0;
++
++ buf = kzalloc(datalen * sizeof(u8), GFP_KERNEL);
++ if(!buf)
++ return -ENOMEM;
++
++ ret = ctlr->append_caldata(ctlr);
++ if (ret)
++ goto cal_end;
++
++ cal_head = ctlr->cal_target;
++ list_for_each(listptr, cal_head) {
++ target = list_entry(listptr, struct spi_cal_target, list);
++
++ hit = false;
++ hit_val = 0;
++ total_hit = 0;
++ origin = *target->cal_item;
++
++ for(i=target->cal_min; i<=target->cal_max; i+=target->step) {
++ *target->cal_item = i;
++ ret = (*cal_read)(drv_priv, ctlr->cal_rule->addr, addrlen, buf, datalen);
++ if(ret)
++ break;
++ dev_dbg(&spi->dev, "controller cal item value: 0x%x\n", i);
++ if(memcmp(ctlr->cal_rule->match_data, buf, datalen * sizeof(u8)) == 0) {
++ hit = true;
++ hit_val += i;
++ total_hit++;
++ dev_dbg(&spi->dev, "golden data matches data read!\n");
++ }
++ }
++ if(hit) {
++ *target->cal_item = DIV_ROUND_CLOSEST(hit_val, total_hit);
++ dev_info(&spi->dev, "calibration result: 0x%x", *target->cal_item);
++ } else {
++ *target->cal_item = origin;
++ dev_warn(&spi->dev, "calibration failed, fallback to default: 0x%x", origin);
++ }
++ }
++
++cal_end:
++ kfree(buf);
++ return ret? ret: 0;
++}
++EXPORT_SYMBOL_GPL(spi_do_calibration);
++
+ static void _spi_transfer_delay_ns(u32 ns)
+ {
+ if (!ns)
+@@ -2225,6 +2289,75 @@ void spi_flush_queue(struct spi_controll
+ /*-------------------------------------------------------------------------*/
+
+ #if defined(CONFIG_OF)
++static inline void alloc_cal_data(struct list_head **cal_target,
++ struct spi_cal_rule **cal_rule, bool enable)
++{
++ if(enable) {
++ *cal_target = kmalloc(sizeof(struct list_head), GFP_KERNEL);
++ INIT_LIST_HEAD(*cal_target);
++ *cal_rule = kmalloc(sizeof(struct spi_cal_rule), GFP_KERNEL);
++ } else {
++ kfree(*cal_target);
++ kfree(*cal_rule);
++ }
++}
++
++static int of_spi_parse_cal_dt(struct spi_controller *ctlr, struct spi_device *spi,
++ struct device_node *nc)
++{
++ u32 value;
++ int rc;
++ const char *cal_mode;
++
++ rc = of_property_read_bool(nc, "spi-cal-enable");
++ if (rc)
++ alloc_cal_data(&ctlr->cal_target, &ctlr->cal_rule, true);
++ else
++ return 0;
++
++ rc = of_property_read_string(nc, "spi-cal-mode", &cal_mode);
++ if(!rc) {
++ if(strcmp("read-data", cal_mode) == 0){
++ ctlr->cal_rule->mode = SPI_CAL_READ_DATA;
++ } else if(strcmp("read-pp", cal_mode) == 0) {
++ ctlr->cal_rule->mode = SPI_CAL_READ_PP;
++ return 0;
++ } else if(strcmp("read-sfdp", cal_mode) == 0){
++ ctlr->cal_rule->mode = SPI_CAL_READ_SFDP;
++ return 0;
++ }
++ } else
++ goto err;
++
++ ctlr->cal_rule->datalen = 0;
++ rc = of_property_read_u32(nc, "spi-cal-datalen", &value);
++ if(!rc && value > 0) {
++ ctlr->cal_rule->datalen = value;
++
++ ctlr->cal_rule->match_data = kzalloc(value * sizeof(u8), GFP_KERNEL);
++ rc = of_property_read_u8_array(nc, "spi-cal-data",
++ ctlr->cal_rule->match_data, value);
++ if(rc)
++ kfree(ctlr->cal_rule->match_data);
++ }
++
++ rc = of_property_read_u32(nc, "spi-cal-addrlen", &value);
++ if(!rc && value > 0) {
++ ctlr->cal_rule->addrlen = value;
++
++ ctlr->cal_rule->addr = kzalloc(value * sizeof(u32), GFP_KERNEL);
++ rc = of_property_read_u32_array(nc, "spi-cal-addr",
++ ctlr->cal_rule->addr, value);
++ if(rc)
++ kfree(ctlr->cal_rule->addr);
++ }
++ return 0;
++
++err:
++ alloc_cal_data(&ctlr->cal_target, &ctlr->cal_rule, false);
++ return 0;
++}
++
+ static void of_spi_parse_dt_cs_delay(struct device_node *nc,
+ struct spi_delay *delay, const char *prop)
+ {
+@@ -2364,6 +2497,10 @@ of_register_spi_device(struct spi_contro
+ if (rc)
+ goto err_out;
+
++ rc = of_spi_parse_cal_dt(ctlr, spi, nc);
++ if (rc)
++ goto err_out;
++
+ /* Store a pointer to the node in the device structure */
+ of_node_get(nc);
+
+--- a/include/linux/spi/spi.h
++++ b/include/linux/spi/spi.h
+@@ -330,6 +330,40 @@ struct spi_driver {
+ struct device_driver driver;
+ };
+
++enum {
++ SPI_CAL_READ_DATA = 0,
++ SPI_CAL_READ_PP = 1, /* only for SPI-NAND */
++ SPI_CAL_READ_SFDP = 2, /* only for SPI-NOR */
++};
++
++struct nand_addr {
++ unsigned int lun;
++ unsigned int plane;
++ unsigned int eraseblock;
++ unsigned int page;
++ unsigned int dataoffs;
++};
++
++/**
++ * Read calibration rule from device dts node.
++ * Once calibration result matches the rule, we regard is as success.
++ */
++struct spi_cal_rule {
++ int datalen;
++ u8 *match_data;
++ int addrlen;
++ u32 *addr;
++ int mode;
++};
++
++struct spi_cal_target {
++ u32 *cal_item;
++ int cal_min; /* min of cal_item */
++ int cal_max; /* max of cal_item */
++ int step; /* Increase/decrease cal_item */
++ struct list_head list;
++};
++
+ static inline struct spi_driver *to_spi_driver(struct device_driver *drv)
+ {
+ return drv ? container_of(drv, struct spi_driver, driver) : NULL;
+@@ -727,6 +761,11 @@ struct spi_controller {
+ void *dummy_rx;
+ void *dummy_tx;
+
++ /* For calibration */
++ int (*append_caldata)(struct spi_controller *ctlr);
++ struct list_head *cal_target;
++ struct spi_cal_rule *cal_rule;
++
+ int (*fw_translate_cs)(struct spi_controller *ctlr, unsigned cs);
+
+ /*
+@@ -1601,6 +1640,9 @@ spi_register_board_info(struct spi_board
+ { return 0; }
+ #endif
+
++extern int spi_do_calibration(struct spi_controller *ctlr,
++ struct spi_device *spi, int (*cal_read)(void *, u32 *, int, u8 *, int), void *drv_priv);
++
+ /*
+ * If you're hotplugging an adapter with devices (parport, USB, etc)
+ * use spi_new_device() to describe each device. You can also call
--- /dev/null
+From 06640a5da2973318c06e516da16a5b579622e7c5 Mon Sep 17 00:00:00 2001
+From: "SkyLake.Huang" <skylake.huang@mediatek.com>
+Date: Thu, 23 Jun 2022 18:37:55 +0800
+Subject: [PATCH 3/6] drivers: spi-mem: Add spi calibration hook
+
+Signed-off-by: SkyLake.Huang <skylake.huang@mediatek.com>
+---
+ drivers/spi/spi-mem.c | 8 ++++++++
+ include/linux/spi/spi-mem.h | 4 ++++
+ 2 files changed, 12 insertions(+)
+
+--- a/drivers/spi/spi-mem.c
++++ b/drivers/spi/spi-mem.c
+@@ -419,6 +419,14 @@ int spi_mem_exec_op(struct spi_mem *mem,
+ }
+ EXPORT_SYMBOL_GPL(spi_mem_exec_op);
+
++int spi_mem_do_calibration(struct spi_mem *mem,
++ int (*cal_read)(void *priv, u32 *addr, int addrlen, u8 *buf, int readlen),
++ void *priv)
++{
++ return spi_do_calibration(mem->spi->controller, mem->spi, cal_read, priv);
++}
++EXPORT_SYMBOL_GPL(spi_mem_do_calibration);
++
+ /**
+ * spi_mem_get_name() - Return the SPI mem device name to be used by the
+ * upper layer if necessary
+--- a/include/linux/spi/spi-mem.h
++++ b/include/linux/spi/spi-mem.h
+@@ -370,6 +370,10 @@ bool spi_mem_supports_op(struct spi_mem
+ int spi_mem_exec_op(struct spi_mem *mem,
+ const struct spi_mem_op *op);
+
++int spi_mem_do_calibration(struct spi_mem *mem,
++ int (*cal_read)(void *, u32 *, int, u8 *, int),
++ void *priv);
++
+ const char *spi_mem_get_name(struct spi_mem *mem);
+
+ struct spi_mem_dirmap_desc *
--- /dev/null
+From d278c7a0bf730318a7ccf8d0a8b434c813e23fd0 Mon Sep 17 00:00:00 2001
+From: "SkyLake.Huang" <skylake.huang@mediatek.com>
+Date: Thu, 23 Jun 2022 18:39:03 +0800
+Subject: [PATCH 4/6] drivers: spi-mt65xx: Add controller's calibration
+ paramter
+
+Signed-off-by: SkyLake.Huang <skylake.huang@mediatek.com>
+---
+ drivers/spi/spi-mt65xx.c | 16 ++++++++++++++++
+ 1 file changed, 16 insertions(+)
+
+--- a/drivers/spi/spi-mt65xx.c
++++ b/drivers/spi/spi-mt65xx.c
+@@ -834,6 +834,21 @@ static irqreturn_t mtk_spi_interrupt(int
+ return IRQ_HANDLED;
+ }
+
++static int mtk_spi_append_caldata(struct spi_controller *ctlr)
++{
++ struct spi_cal_target *cal_target = kmalloc(sizeof(*cal_target), GFP_KERNEL);
++ struct mtk_spi *mdata = spi_master_get_devdata(ctlr);
++
++ cal_target->cal_item = &mdata->get_tick_dly;
++ cal_target->cal_min = 0;
++ cal_target->cal_max = 7;
++ cal_target->step = 1;
++
++ list_add(&cal_target->list, ctlr->cal_target);
++
++ return 0;
++}
++
+ static int mtk_spi_mem_adjust_op_size(struct spi_mem *mem,
+ struct spi_mem_op *op)
+ {
+@@ -1124,6 +1139,7 @@ static int mtk_spi_probe(struct platform
+ master->setup = mtk_spi_setup;
+ master->set_cs_timing = mtk_spi_set_hw_cs_timing;
+ master->use_gpio_descriptors = true;
++ master->append_caldata = mtk_spi_append_caldata;
+
+ mdata = spi_master_get_devdata(master);
+ mdata->dev_comp = device_get_match_data(dev);
--- /dev/null
+From 7670ec4a14891a1a182b98a9c403ffbf6b49e4b1 Mon Sep 17 00:00:00 2001
+From: "SkyLake.Huang" <skylake.huang@mediatek.com>
+Date: Thu, 23 Jun 2022 18:39:56 +0800
+Subject: [PATCH 5/6] drivers: mtd: spinand: Add calibration support for
+ spinand
+
+Signed-off-by: SkyLake.Huang <skylake.huang@mediatek.com>
+---
+ drivers/mtd/nand/spi/core.c | 54 +++++++++++++++++++++++++++++++++++++
+ 1 file changed, 54 insertions(+)
+
+--- a/drivers/mtd/nand/spi/core.c
++++ b/drivers/mtd/nand/spi/core.c
+@@ -980,6 +980,56 @@ static int spinand_manufacturer_match(st
+ return -ENOTSUPP;
+ }
+
++int spinand_cal_read(void *priv, u32 *addr, int addrlen, u8 *buf, int readlen) {
++ struct spinand_device *spinand = (struct spinand_device *)priv;
++ struct device *dev = &spinand->spimem->spi->dev;
++ struct spi_mem_op op = SPINAND_PAGE_READ_FROM_CACHE_OP(false, 0, 1, buf, readlen);
++ struct nand_pos pos;
++ struct nand_page_io_req req;
++ u8 status;
++ int ret;
++
++ if(addrlen != sizeof(struct nand_addr)/sizeof(unsigned int)) {
++ dev_err(dev, "Must provide correct addr(length) for spinand calibration\n");
++ return -EINVAL;
++ }
++
++ ret = spinand_reset_op(spinand);
++ if (ret)
++ return ret;
++
++ /* We should store our golden data in first target because
++ * we can't switch target at this moment.
++ */
++ pos = (struct nand_pos){
++ .target = 0,
++ .lun = *addr,
++ .plane = *(addr+1),
++ .eraseblock = *(addr+2),
++ .page = *(addr+3),
++ };
++
++ req = (struct nand_page_io_req){
++ .pos = pos,
++ .dataoffs = *(addr+4),
++ .datalen = readlen,
++ .databuf.in = buf,
++ .mode = MTD_OPS_AUTO_OOB,
++ };
++
++ ret = spinand_load_page_op(spinand, &req);
++ if (ret)
++ return ret;
++
++ ret = spinand_wait(spinand, &status);
++ if (ret < 0)
++ return ret;
++
++ ret = spi_mem_exec_op(spinand->spimem, &op);
++
++ return 0;
++}
++
+ static int spinand_id_detect(struct spinand_device *spinand)
+ {
+ u8 *id = spinand->id.data;
+@@ -1230,6 +1280,10 @@ static int spinand_init(struct spinand_d
+ if (!spinand->scratchbuf)
+ return -ENOMEM;
+
++ ret = spi_mem_do_calibration(spinand->spimem, spinand_cal_read, spinand);
++ if (ret)
++ dev_err(dev, "Failed to calibrate SPI-NAND (err = %d)\n", ret);
++
+ ret = spinand_detect(spinand);
+ if (ret)
+ goto err_free_bufs;
--- /dev/null
+From f3fe3b15eca7908eaac57f9b8387a5dbc45ec5b2 Mon Sep 17 00:00:00 2001
+From: "SkyLake.Huang" <skylake.huang@mediatek.com>
+Date: Thu, 23 Jun 2022 18:40:59 +0800
+Subject: [PATCH 6/6] drivers: mtd: spi-nor: Add calibration support for
+ spi-nor
+
+Signed-off-by: SkyLake.Huang <skylake.huang@mediatek.com>
+---
+ drivers/mtd/nand/spi/core.c | 5 ++++-
+ drivers/mtd/spi-nor/core.c | 15 +++++++++++++++
+ 2 files changed, 19 insertions(+), 1 deletion(-)
+
+--- a/drivers/mtd/nand/spi/core.c
++++ b/drivers/mtd/nand/spi/core.c
+@@ -1021,7 +1021,10 @@ int spinand_cal_read(void *priv, u32 *ad
+ if (ret)
+ return ret;
+
+- ret = spinand_wait(spinand, &status);
++ ret = spinand_wait(spinand,
++ SPINAND_READ_INITIAL_DELAY_US,
++ SPINAND_READ_POLL_DELAY_US,
++ &status);
+ if (ret < 0)
+ return ret;
+
+--- a/drivers/mtd/spi-nor/core.c
++++ b/drivers/mtd/spi-nor/core.c
+@@ -3378,6 +3378,18 @@ static const struct flash_info *spi_nor_
+ return NULL;
+ }
+
++static int spi_nor_cal_read(void *priv, u32 *addr, int addrlen, u8 *buf, int readlen)
++{
++ struct spi_nor *nor = (struct spi_nor *)priv;
++
++ nor->reg_proto = SNOR_PROTO_1_1_1;
++ nor->read_proto = SNOR_PROTO_1_1_1;
++ nor->read_opcode = SPINOR_OP_READ;
++ nor->read_dummy = 0;
++
++ return nor->controller_ops->read(nor, *addr, readlen, buf);
++}
++
+ static const struct flash_info *spi_nor_get_flash_info(struct spi_nor *nor,
+ const char *name)
+ {
+@@ -3506,6 +3518,9 @@ int spi_nor_scan(struct spi_nor *nor, co
+ if (ret)
+ return ret;
+
++ if(nor->spimem)
++ spi_mem_do_calibration(nor->spimem, spi_nor_cal_read, nor);
++
+ info = spi_nor_get_flash_info(nor, name);
+ if (IS_ERR(info))
+ return PTR_ERR(info);
--- /dev/null
+From c22bc82183c2dea64919f975473ec518738baa3e Mon Sep 17 00:00:00 2001
+From: Daniel Golle <daniel@makrotopia.org>
+Date: Wed, 12 Jul 2023 13:38:35 +0100
+Subject: [PATCH] nvmem: add layout for Adtran devices
+
+Adtran stores unique factory data on GPT partitions on the eMMC.
+Using blk-nvmem the 'mfginfo' partition gets exposes as NVMEM provider.
+
+Add layout driver to parse mfginfo, mainly to provide MAC addresses to
+Ethernet and wireless interfaces.
+
+Variable names are converted to lower-case and '_' is replaced with '-'
+in order to comply with the device tree node naming convention.
+The main MAC address always ends on a 0 and up to 16 addresses are
+alocated for each device to use for various interfaces.
+
+Implement post-processing function for 'MFG_MAC' variable ('mfg-mac'
+node name in device tree) adding the nvmem cell index to the least
+significant digit of the MAC address.
+
+Signed-off-by: Daniel Golle <daniel@makrotopia.org>
+---
+ drivers/nvmem/layouts/Kconfig | 9 +++
+ drivers/nvmem/layouts/Makefile | 1 +
+ drivers/nvmem/layouts/adtran.c | 135 +++++++++++++++++++++++++++++++++
+ 3 files changed, 145 insertions(+)
+ create mode 100644 drivers/nvmem/layouts/adtran.c
+
+--- a/drivers/nvmem/layouts/Kconfig
++++ b/drivers/nvmem/layouts/Kconfig
+@@ -8,6 +8,15 @@ if NVMEM_LAYOUTS
+
+ menu "Layout Types"
+
++config NVMEM_LAYOUT_ADTRAN
++ tristate "Adtran mfginfo layout support"
++ select GENERIC_NET_UTILS
++ help
++ Say Y here if you want to support the layout used by Adtran for
++ mfginfo.
++
++ If unsure, say N.
++
+ config NVMEM_LAYOUT_SL28_VPD
+ tristate "Kontron sl28 VPD layout support"
+ select CRC8
+--- a/drivers/nvmem/layouts/Makefile
++++ b/drivers/nvmem/layouts/Makefile
+@@ -6,4 +6,5 @@
+ obj-$(CONFIG_NVMEM_LAYOUT_SL28_VPD) += sl28vpd.o
+ obj-$(CONFIG_NVMEM_LAYOUT_ONIE_TLV) += onie-tlv.o
+ obj-$(CONFIG_NVMEM_LAYOUT_U_BOOT_ENV) += u-boot-env.o
++obj-$(CONFIG_NVMEM_LAYOUT_ADTRAN) += adtran.o
+ obj-$(CONFIG_NVMEM_LAYOUT_ASCII_ENV) += ascii-env.o
+--- /dev/null
++++ b/drivers/nvmem/layouts/adtran.c
+@@ -0,0 +1,135 @@
++// SPDX-License-Identifier: GPL-2.0
++#include <linux/ctype.h>
++#include <linux/etherdevice.h>
++#include <linux/nvmem-consumer.h>
++#include <linux/nvmem-provider.h>
++#include <linux/of.h>
++#include <linux/platform_device.h>
++
++/*
++ * Adtran devices usually come with a main MAC address ending on 0 and
++ * hence may have up to 16 MAC addresses per device.
++ * The main MAC address is stored as variable MFG_MAC in ASCII format.
++ */
++static int adtran_mac_address_pp(void *priv, const char *id, int index,
++ unsigned int offset, void *buf,
++ size_t bytes)
++{
++ u8 mac[ETH_ALEN];
++
++ if (WARN_ON(bytes != 3 * ETH_ALEN - 1))
++ return -EINVAL;
++
++ if (!mac_pton(buf, mac))
++ return -EINVAL;
++
++ if (index)
++ eth_addr_add(mac, index);
++
++ ether_addr_copy(buf, mac);
++
++ return 0;
++}
++
++static int adtran_add_cells(struct nvmem_layout *layout)
++{
++ struct nvmem_device *nvmem = layout->nvmem;
++ struct nvmem_cell_info info;
++ struct device_node *layout_np;
++ char mfginfo[1024], *c, *t, *p;
++ int ret = -EINVAL;
++
++ ret = nvmem_device_read(nvmem, 0, sizeof(mfginfo), mfginfo);
++ if (ret < 0)
++ return ret;
++ else if (ret != sizeof(mfginfo))
++ return -EIO;
++
++ layout_np = of_nvmem_layout_get_container(nvmem);
++ if (!layout_np)
++ return -ENOENT;
++
++ c = mfginfo;
++ while (*c != 0xff) {
++ memset(&info, 0, sizeof(info));
++ if (*c == '#')
++ goto nextline;
++
++ t = strchr(c, '=');
++ if (!t)
++ goto nextline;
++
++ *t = '\0';
++ ++t;
++ info.offset = t - mfginfo;
++ /* process variable name: convert to lower-case, '_' -> '-' */
++ p = c;
++ do {
++ *p = tolower(*p);
++ if (*p == '_')
++ *p = '-';
++ } while (*++p);
++ info.name = c;
++ c = strchr(t, 0xa); /* find newline */
++ if (!c)
++ break;
++
++ info.bytes = c - t;
++ if (!strcmp(info.name, "mfg-mac")) {
++ info.raw_len = info.bytes;
++ info.bytes = ETH_ALEN;
++ info.read_post_process = adtran_mac_address_pp;
++ }
++
++ info.np = of_get_child_by_name(layout_np, info.name);
++ ret = nvmem_add_one_cell(nvmem, &info);
++ if (ret)
++ break;
++
++ ++c;
++ continue;
++
++nextline:
++ c = strchr(c, 0xa); /* find newline */
++ if (!c)
++ break;
++ ++c;
++ }
++
++ of_node_put(layout_np);
++
++ return ret;
++}
++
++static int adtran_probe(struct nvmem_layout *layout)
++{
++ layout->add_cells = adtran_add_cells;
++
++ return nvmem_layout_register(layout);
++}
++
++static void adtran_remove(struct nvmem_layout *layout)
++{
++ nvmem_layout_unregister(layout);
++}
++
++static const struct of_device_id adtran_of_match_table[] = {
++ { .compatible = "adtran,mfginfo" },
++ {},
++};
++MODULE_DEVICE_TABLE(of, adtran_of_match_table);
++
++static struct nvmem_layout_driver adtran_layout = {
++ .driver = {
++ .owner = THIS_MODULE,
++ .name = "adtran-layout",
++ .of_match_table = adtran_of_match_table,
++ },
++ .probe = adtran_probe,
++ .remove = adtran_remove,
++};
++module_nvmem_layout_driver(adtran_layout);
++
++MODULE_LICENSE("GPL");
++MODULE_AUTHOR("Daniel Golle <daniel@makrotopia.org>");
++MODULE_DESCRIPTION("NVMEM layout driver for Adtran mfginfo");
--- /dev/null
+--- a/drivers/net/phy/Kconfig
++++ b/drivers/net/phy/Kconfig
+@@ -418,6 +418,12 @@ config ROCKCHIP_PHY
+ help
+ Currently supports the integrated Ethernet PHY.
+
++config RTL8367S_GSW
++ tristate "rtl8367 Gigabit Switch support for mt7622"
++ depends on NET_VENDOR_MEDIATEK
++ help
++ This driver supports rtl8367s in mt7622
++
+ config SMSC_PHY
+ tristate "SMSC PHYs"
+ select CRC16
+--- a/drivers/net/phy/Makefile
++++ b/drivers/net/phy/Makefile
+@@ -103,6 +103,7 @@ obj-$(CONFIG_REALTEK_PHY) += realtek/
+ obj-y += rtl8261n/
+ obj-$(CONFIG_RENESAS_PHY) += uPD60620.o
+ obj-$(CONFIG_ROCKCHIP_PHY) += rockchip.o
++obj-$(CONFIG_RTL8367S_GSW) += rtk/
+ obj-$(CONFIG_SMSC_PHY) += smsc.o
+ obj-$(CONFIG_STE10XP) += ste10Xp.o
+ obj-$(CONFIG_TERANETICS_PHY) += teranetics.o
--- /dev/null
+From: qizhong cheng <qizhong.cheng@mediatek.com>
+Date: Mon, 27 Dec 2021 21:31:10 +0800
+Subject: [PATCH] PCI: mediatek: Assert PERST# for 100ms for power and clock to
+ stabilize
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Described in PCIe CEM specification sections 2.2 (PERST# Signal) and
+2.2.1 (Initial Power-Up (G3 to S0)). The deassertion of PERST# should
+be delayed 100ms (TPVPERL) for the power and clock to become stable.
+
+Link: https://lore.kernel.org/r/20211227133110.14500-1-qizhong.cheng@mediatek.com
+Signed-off-by: qizhong cheng <qizhong.cheng@mediatek.com>
+Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
+Acked-by: Pali Rohár <pali@kernel.org>
+---
+
+--- a/drivers/pci/controller/pcie-mediatek.c
++++ b/drivers/pci/controller/pcie-mediatek.c
+@@ -708,6 +708,13 @@ static int mtk_pcie_startup_port_v2(stru
+ */
+ msleep(100);
+
++ /*
++ * Described in PCIe CEM specification sections 2.2 (PERST# Signal) and
++ * 2.2.1 (Initial Power-Up (G3 to S0)). The deassertion of PERST# should
++ * be delayed 100ms (TPVPERL) for the power and clock to become stable.
++ */
++ msleep(100);
++
+ /* De-assert PHY, PE, PIPE, MAC and configuration reset */
+ val = readl(port->base + PCIE_RST_CTRL);
+ val |= PCIE_PHY_RSTB | PCIE_PERSTB | PCIE_PIPE_SRSTB |
--- /dev/null
+--- a/arch/arm64/boot/dts/mediatek/mt7622.dtsi
++++ b/arch/arm64/boot/dts/mediatek/mt7622.dtsi
+@@ -844,6 +844,12 @@
+ #address-cells = <0>;
+ #interrupt-cells = <1>;
+ };
++
++ slot0: pcie@0,0 {
++ reg = <0x0000 0 0 0 0>;
++ #address-cells = <3>;
++ #size-cells = <2>;
++ };
+ };
+
+ pcie1: pcie@1a145000 {
+@@ -882,6 +888,12 @@
+ #address-cells = <0>;
+ #interrupt-cells = <1>;
+ };
++
++ slot1: pcie@1,0 {
++ reg = <0x0800 0 0 0 0>;
++ #address-cells = <3>;
++ #size-cells = <2>;
++ };
+ };
+
+ sata: sata@1a200000 {
--- /dev/null
+From: Felix Fietkau <nbd@nbd.name>
+Date: Fri, 4 Sep 2020 18:33:27 +0200
+Subject: [PATCH] pcie-mediatek: fix clearing interrupt status
+
+Clearing the status needs to happen after running the handler, otherwise
+we will get an extra spurious interrupt after the cause has been cleared
+
+Signed-off-by: Felix Fietkau <nbd@nbd.name>
+---
+
+--- a/drivers/pci/controller/pcie-mediatek.c
++++ b/drivers/pci/controller/pcie-mediatek.c
+@@ -607,9 +607,9 @@ static void mtk_pcie_intr_handler(struct
+ if (status & INTX_MASK) {
+ for_each_set_bit_from(bit, &status, PCI_NUM_INTX + INTX_SHIFT) {
+ /* Clear the INTx */
+- writel(1 << bit, port->base + PCIE_INT_STATUS);
+ generic_handle_domain_irq(port->irq_domain,
+ bit - INTX_SHIFT);
++ writel(1 << bit, port->base + PCIE_INT_STATUS);
+ }
+ }
+
--- /dev/null
+--- a/drivers/pci/controller/pcie-mediatek-gen3.c
++++ b/drivers/pci/controller/pcie-mediatek-gen3.c
+@@ -375,7 +375,13 @@ static int mtk_pcie_startup_port(struct
+ msleep(100);
+
+ /* De-assert reset signals */
+- val &= ~(PCIE_MAC_RSTB | PCIE_PHY_RSTB | PCIE_BRG_RSTB | PCIE_PE_RSTB);
++ val &= ~(PCIE_MAC_RSTB | PCIE_PHY_RSTB | PCIE_BRG_RSTB);
++ writel_relaxed(val, pcie->base + PCIE_RST_CTRL_REG);
++
++ msleep(100);
++
++ /* De-assert PERST# signals */
++ val &= ~(PCIE_PE_RSTB);
+ writel_relaxed(val, pcie->base + PCIE_RST_CTRL_REG);
+
+ /* Check if the link is up or not */
--- /dev/null
+From 50cefacc6c001eea1d9b1c78ba27304566f304f1 Mon Sep 17 00:00:00 2001
+From: Daniel Golle <daniel@makrotopia.org>
+Date: Fri, 2 Jun 2023 13:06:26 +0800
+Subject: [PATCH] phy: mediatek: xsphy: support type switch by pericfg
+
+Patch from Sam Shih <sam.shih@mediatek.com> found in MediaTek SDK
+released under GPL.
+
+Get syscon and use it to set the PHY type.
+Extend support to PCIe and SGMII mode in addition to USB2 and USB3.
+
+Signed-off-by: Daniel Golle <daniel@makrotopia.org>
+---
+ drivers/phy/mediatek/phy-mtk-xsphy.c | 81 +++++++++++++++++++++++++++-
+ 1 file changed, 80 insertions(+), 1 deletion(-)
+
+--- a/drivers/phy/mediatek/phy-mtk-xsphy.c
++++ b/drivers/phy/mediatek/phy-mtk-xsphy.c
+@@ -11,10 +11,12 @@
+ #include <linux/clk.h>
+ #include <linux/delay.h>
+ #include <linux/iopoll.h>
++#include <linux/mfd/syscon.h>
+ #include <linux/module.h>
+ #include <linux/of_address.h>
+ #include <linux/phy/phy.h>
+ #include <linux/platform_device.h>
++#include <linux/regmap.h>
+
+ #include "phy-mtk-io.h"
+
+@@ -81,12 +83,22 @@
+ #define XSP_SR_COEF_DIVISOR 1000
+ #define XSP_FM_DET_CYCLE_CNT 1024
+
++/* PHY switch between pcie/usb3/sgmii */
++#define USB_PHY_SWITCH_CTRL 0x0
++#define RG_PHY_SW_TYPE GENMASK(3, 0)
++#define RG_PHY_SW_PCIE 0x0
++#define RG_PHY_SW_USB3 0x1
++#define RG_PHY_SW_SGMII 0x2
++
+ struct xsphy_instance {
+ struct phy *phy;
+ void __iomem *port_base;
+ struct clk *ref_clk; /* reference clock of anolog phy */
+ u32 index;
+ u32 type;
++ struct regmap *type_sw;
++ u32 type_sw_reg;
++ u32 type_sw_index;
+ /* only for HQA test */
+ int efuse_intr;
+ int efuse_tx_imp;
+@@ -259,6 +271,10 @@ static void phy_parse_property(struct mt
+ inst->efuse_intr, inst->efuse_tx_imp,
+ inst->efuse_rx_imp);
+ break;
++ case PHY_TYPE_PCIE:
++ case PHY_TYPE_SGMII:
++ /* nothing to do */
++ break;
+ default:
+ dev_err(xsphy->dev, "incompatible phy type\n");
+ return;
+@@ -305,6 +321,62 @@ static void u3_phy_props_set(struct mtk_
+ RG_XTP_LN0_RX_IMPSEL, inst->efuse_rx_imp);
+ }
+
++/* type switch for usb3/pcie/sgmii */
++static int phy_type_syscon_get(struct xsphy_instance *instance,
++ struct device_node *dn)
++{
++ struct of_phandle_args args;
++ int ret;
++
++ /* type switch function is optional */
++ if (!of_property_read_bool(dn, "mediatek,syscon-type"))
++ return 0;
++
++ ret = of_parse_phandle_with_fixed_args(dn, "mediatek,syscon-type",
++ 2, 0, &args);
++ if (ret)
++ return ret;
++
++ instance->type_sw_reg = args.args[0];
++ instance->type_sw_index = args.args[1] & 0x3; /* <=3 */
++ instance->type_sw = syscon_node_to_regmap(args.np);
++ of_node_put(args.np);
++ dev_info(&instance->phy->dev, "type_sw - reg %#x, index %d\n",
++ instance->type_sw_reg, instance->type_sw_index);
++
++ return PTR_ERR_OR_ZERO(instance->type_sw);
++}
++
++static int phy_type_set(struct xsphy_instance *instance)
++{
++ int type;
++ u32 offset;
++
++ if (!instance->type_sw)
++ return 0;
++
++ switch (instance->type) {
++ case PHY_TYPE_USB3:
++ type = RG_PHY_SW_USB3;
++ break;
++ case PHY_TYPE_PCIE:
++ type = RG_PHY_SW_PCIE;
++ break;
++ case PHY_TYPE_SGMII:
++ type = RG_PHY_SW_SGMII;
++ break;
++ case PHY_TYPE_USB2:
++ default:
++ return 0;
++ }
++
++ offset = instance->type_sw_index * BITS_PER_BYTE;
++ regmap_update_bits(instance->type_sw, instance->type_sw_reg,
++ RG_PHY_SW_TYPE << offset, type << offset);
++
++ return 0;
++}
++
+ static int mtk_phy_init(struct phy *phy)
+ {
+ struct xsphy_instance *inst = phy_get_drvdata(phy);
+@@ -325,6 +397,10 @@ static int mtk_phy_init(struct phy *phy)
+ case PHY_TYPE_USB3:
+ u3_phy_props_set(xsphy, inst);
+ break;
++ case PHY_TYPE_PCIE:
++ case PHY_TYPE_SGMII:
++ /* nothing to do, only used to set type */
++ break;
+ default:
+ dev_err(xsphy->dev, "incompatible phy type\n");
+ clk_disable_unprepare(inst->ref_clk);
+@@ -403,12 +479,15 @@ static struct phy *mtk_phy_xlate(struct
+
+ inst->type = args->args[0];
+ if (!(inst->type == PHY_TYPE_USB2 ||
+- inst->type == PHY_TYPE_USB3)) {
++ inst->type == PHY_TYPE_USB3 ||
++ inst->type == PHY_TYPE_PCIE ||
++ inst->type == PHY_TYPE_SGMII)) {
+ dev_err(dev, "unsupported phy type: %d\n", inst->type);
+ return ERR_PTR(-EINVAL);
+ }
+
+ phy_parse_property(xsphy, inst);
++ phy_type_set(inst);
+
+ return inst->phy;
+ }
+@@ -515,6 +594,10 @@ static int mtk_xsphy_probe(struct platfo
+ retval = PTR_ERR(inst->ref_clk);
+ goto put_child;
+ }
++
++ retval = phy_type_syscon_get(inst, child_np);
++ if (retval)
++ goto put_child;
+ }
+
+ provider = devm_of_phy_provider_register(dev, mtk_phy_xlate);
--- /dev/null
+From: Felix Fietkau <nbd@nbd.name>
+Date: Fri, 4 Sep 2020 18:42:42 +0200
+Subject: [PATCH] pci: pcie-mediatek: add support for coherent DMA
+
+It improves performance by eliminating the need for a cache flush for DMA on
+attached devices
+
+Signed-off-by: Felix Fietkau <nbd@nbd.name>
+---
+
+--- a/arch/arm64/boot/dts/mediatek/mt7622.dtsi
++++ b/arch/arm64/boot/dts/mediatek/mt7622.dtsi
+@@ -832,6 +832,9 @@
+ bus-range = <0x00 0xff>;
+ ranges = <0x82000000 0 0x20000000 0x0 0x20000000 0 0x8000000>;
+ status = "disabled";
++ dma-coherent;
++ mediatek,hifsys = <&hifsys>;
++ mediatek,cci-control = <&cci_control2>;
+
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 7>;
+@@ -876,6 +879,9 @@
+ bus-range = <0x00 0xff>;
+ ranges = <0x82000000 0 0x28000000 0x0 0x28000000 0 0x8000000>;
+ status = "disabled";
++ dma-coherent;
++ mediatek,hifsys = <&hifsys>;
++ mediatek,cci-control = <&cci_control2>;
+
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 7>;
+@@ -937,7 +943,7 @@
+ };
+
+ hifsys: clock-controller@1af00000 {
+- compatible = "mediatek,mt7622-hifsys";
++ compatible = "mediatek,mt7622-hifsys", "syscon";
+ reg = <0 0x1af00000 0 0x70>;
+ #clock-cells = <1>;
+ };
+--- a/drivers/pci/controller/pcie-mediatek.c
++++ b/drivers/pci/controller/pcie-mediatek.c
+@@ -20,6 +20,7 @@
+ #include <linux/of_address.h>
+ #include <linux/of_pci.h>
+ #include <linux/of_platform.h>
++#include <linux/of_address.h>
+ #include <linux/pci.h>
+ #include <linux/phy/phy.h>
+ #include <linux/platform_device.h>
+@@ -139,6 +140,11 @@
+ #define PCIE_LINK_STATUS_V2 0x804
+ #define PCIE_PORT_LINKUP_V2 BIT(10)
+
++/* DMA channel mapping */
++#define HIFSYS_DMA_AG_MAP 0x008
++#define HIFSYS_DMA_AG_MAP_PCIE0 BIT(0)
++#define HIFSYS_DMA_AG_MAP_PCIE1 BIT(1)
++
+ struct mtk_pcie_port;
+
+ /**
+@@ -1060,6 +1066,27 @@ static int mtk_pcie_setup(struct mtk_pci
+ struct mtk_pcie_port *port, *tmp;
+ int err, slot;
+
++ if (of_dma_is_coherent(node)) {
++ struct regmap *con;
++ u32 mask;
++
++ con = syscon_regmap_lookup_by_phandle(node,
++ "mediatek,cci-control");
++ /* enable CPU/bus coherency */
++ if (!IS_ERR(con))
++ regmap_write(con, 0, 3);
++
++ con = syscon_regmap_lookup_by_phandle(node,
++ "mediatek,hifsys");
++ if (IS_ERR(con)) {
++ dev_err(dev, "missing hifsys node\n");
++ return PTR_ERR(con);
++ }
++
++ mask = HIFSYS_DMA_AG_MAP_PCIE0 | HIFSYS_DMA_AG_MAP_PCIE1;
++ regmap_update_bits(con, HIFSYS_DMA_AG_MAP, mask, mask);
++ }
++
+ slot = of_get_pci_domain_nr(dev->of_node);
+ if (slot < 0) {
+ for_each_available_child_of_node(node, child) {
--- /dev/null
+From: Jip de Beer <gpk6x3591g0l@opayq.com>
+Date: Sun, 9 Jan 2022 13:14:04 +0100
+Subject: [PATCH] mediatek mt7622: fix 300mhz typo in dts
+
+The lowest frequency should be 300MHz, since that is the label
+assigned to the OPP in the mt7622.dtsi device tree, while there is one
+missing zero in the actual value.
+
+To be clear, the lowest frequency should be 300MHz instead of 30MHz.
+
+As mentioned @dangowrt on the OpenWrt forum there is no benefit in
+leaving 30MHz as the lowest frequency.
+
+Signed-off-by: Jip de Beer <gpk6x3591g0l@opayq.com>
+Signed-off-by: Fritz D. Ansel <fdansel@yandex.ru>
+---
+--- a/arch/arm64/boot/dts/mediatek/mt7622.dtsi
++++ b/arch/arm64/boot/dts/mediatek/mt7622.dtsi
+@@ -24,7 +24,7 @@
+ compatible = "operating-points-v2";
+ opp-shared;
+ opp-300000000 {
+- opp-hz = /bits/ 64 <30000000>;
++ opp-hz = /bits/ 64 <300000000>;
+ opp-microvolt = <950000>;
+ };
+
--- /dev/null
+--- a/arch/arm64/boot/dts/mediatek/mt7622.dtsi
++++ b/arch/arm64/boot/dts/mediatek/mt7622.dtsi
+@@ -23,11 +23,17 @@
+ cpu_opp_table: opp-table {
+ compatible = "operating-points-v2";
+ opp-shared;
+- opp-300000000 {
+- opp-hz = /bits/ 64 <300000000>;
+- opp-microvolt = <950000>;
+- };
+-
++ /* Due to the bug described at the link below, remove the 300 MHz clock to avoid a low
++ * voltage condition that can cause a hang when rebooting the RT3200/E8450.
++ *
++ * https://forum.openwrt.org/t/belkin-rt3200-linksys-e8450-wifi-ax-discussion/94302/1490
++ *
++ * opp-300000000 {
++ * opp-hz = /bits/ 64 <300000000>;
++ * opp-microvolt = <950000>;
++ * };
++ *
++ */
+ opp-437500000 {
+ opp-hz = /bits/ 64 <437500000>;
+ opp-microvolt = <1000000>;
--- /dev/null
+From a969b663c866129ed9eb217785a6574fbe826f1d Mon Sep 17 00:00:00 2001
+From: Daniel Golle <daniel@makrotopia.org>
+Date: Thu, 6 Apr 2023 23:36:50 +0100
+Subject: [PATCH] net: phy: mxl-gpy: don't use SGMII AN if using phylink
+
+MAC drivers using phylink expect SGMII in-band-status to be switched off
+when attached to a PHY. Make sure this is the case also for mxl-gpy which
+keeps SGMII in-band-status in case of SGMII interface mode is used.
+
+Signed-off-by: Daniel Golle <daniel@makrotopia.org>
+---
+ drivers/net/phy/mxl-gpy.c | 19 ++++++++++++++++---
+ 1 file changed, 16 insertions(+), 3 deletions(-)
+
+--- a/drivers/net/phy/mxl-gpy.c
++++ b/drivers/net/phy/mxl-gpy.c
+@@ -372,8 +372,11 @@ static bool gpy_2500basex_chk(struct phy
+
+ phydev->speed = SPEED_2500;
+ phydev->interface = PHY_INTERFACE_MODE_2500BASEX;
+- phy_modify_mmd(phydev, MDIO_MMD_VEND1, VSPEC1_SGMII_CTRL,
+- VSPEC1_SGMII_CTRL_ANEN, 0);
++
++ if (!phydev->phylink)
++ phy_modify_mmd(phydev, MDIO_MMD_VEND1, VSPEC1_SGMII_CTRL,
++ VSPEC1_SGMII_CTRL_ANEN, 0);
++
+ return true;
+ }
+
+@@ -424,6 +427,14 @@ static int gpy_config_aneg(struct phy_de
+ u32 adv;
+ int ret;
+
++ /* Disable SGMII auto-negotiation if using phylink */
++ if (phydev->phylink) {
++ ret = phy_modify_mmd(phydev, MDIO_MMD_VEND1, VSPEC1_SGMII_CTRL,
++ VSPEC1_SGMII_CTRL_ANEN, 0);
++ if (ret < 0)
++ return ret;
++ }
++
+ if (phydev->autoneg == AUTONEG_DISABLE) {
+ /* Configure half duplex with genphy_setup_forced,
+ * because genphy_c45_pma_setup_forced does not support.
+@@ -546,6 +557,8 @@ static int gpy_update_interface(struct p
+ switch (phydev->speed) {
+ case SPEED_2500:
+ phydev->interface = PHY_INTERFACE_MODE_2500BASEX;
++ if (phydev->phylink)
++ break;
+ ret = phy_modify_mmd(phydev, MDIO_MMD_VEND1, VSPEC1_SGMII_CTRL,
+ VSPEC1_SGMII_CTRL_ANEN, 0);
+ if (ret < 0) {
+@@ -559,7 +572,7 @@ static int gpy_update_interface(struct p
+ case SPEED_100:
+ case SPEED_10:
+ phydev->interface = PHY_INTERFACE_MODE_SGMII;
+- if (gpy_sgmii_aneg_en(phydev))
++ if (phydev->phylink || gpy_sgmii_aneg_en(phydev))
+ break;
+ /* Enable and restart SGMII ANEG for 10/100/1000Mbps link speed
+ * if ANEG is disabled (in 2500-BaseX mode).
--- /dev/null
+From 656f5fdeb6ee6fa95c28cab3b535e2e09ef59c57 Mon Sep 17 00:00:00 2001
+From: "SkyLake.Huang" <skylake.huang@mediatek.com>
+Date: Fri, 4 Oct 2024 18:24:05 +0800
+Subject: [PATCH 1/9] net: phy: mediatek: Re-organize MediaTek ethernet phy
+ drivers
+
+Re-organize MediaTek ethernet phy driver files and get ready to integrate
+some common functions (and add new 2.5G phy driver).
+mtk-ge.c: MT7530 Gphy on MT7621 & MT7531 Gphy
+mtk-ge-soc.c: Built-in Gphy on MT7981 & Built-in switch Gphy on MT7988
+(mtk-2p5ge.c: Planned for built-in 2.5G phy on MT7988
+ --> in another patchset)
+
+Signed-off-by: SkyLake.Huang <skylake.huang@mediatek.com>
+---
+ drivers/net/phy/Kconfig | 17 +-------------
+ drivers/net/phy/Makefile | 3 +--
+ drivers/net/phy/mediatek/Kconfig | 22 +++++++++++++++++++
+ drivers/net/phy/mediatek/Makefile | 3 +++
+ .../mtk-ge-soc.c} | 0
+ .../phy/{mediatek-ge.c => mediatek/mtk-ge.c} | 0
+ 6 files changed, 27 insertions(+), 18 deletions(-)
+ create mode 100644 drivers/net/phy/mediatek/Kconfig
+ create mode 100644 drivers/net/phy/mediatek/Makefile
+ rename drivers/net/phy/{mediatek-ge-soc.c => mediatek/mtk-ge-soc.c} (100%)
+ rename drivers/net/phy/{mediatek-ge.c => mediatek/mtk-ge.c} (100%)
+
+--- a/drivers/net/phy/Kconfig
++++ b/drivers/net/phy/Kconfig
+@@ -313,22 +313,7 @@ config MAXLINEAR_GPHY
+ Support for the Maxlinear GPY115, GPY211, GPY212, GPY215,
+ GPY241, GPY245 PHYs.
+
+-config MEDIATEK_GE_PHY
+- tristate "MediaTek Gigabit Ethernet PHYs"
+- help
+- Supports the MediaTek Gigabit Ethernet PHYs.
+-
+-config MEDIATEK_GE_SOC_PHY
+- tristate "MediaTek SoC Ethernet PHYs"
+- depends on (ARM64 && ARCH_MEDIATEK) || COMPILE_TEST
+- depends on NVMEM_MTK_EFUSE
+- help
+- Supports MediaTek SoC built-in Gigabit Ethernet PHYs.
+-
+- Include support for built-in Ethernet PHYs which are present in
+- the MT7981 and MT7988 SoCs. These PHYs need calibration data
+- present in the SoCs efuse and will dynamically calibrate VCM
+- (common-mode voltage) during startup.
++source "drivers/net/phy/mediatek/Kconfig"
+
+ config MICREL_PHY
+ tristate "Micrel PHYs"
+--- a/drivers/net/phy/Makefile
++++ b/drivers/net/phy/Makefile
+@@ -82,8 +82,7 @@ obj-$(CONFIG_MARVELL_PHY) += marvell.o
+ obj-$(CONFIG_MARVELL_88Q2XXX_PHY) += marvell-88q2xxx.o
+ obj-$(CONFIG_MARVELL_88X2222_PHY) += marvell-88x2222.o
+ obj-$(CONFIG_MAXLINEAR_GPHY) += mxl-gpy.o
+-obj-$(CONFIG_MEDIATEK_GE_PHY) += mediatek-ge.o
+-obj-$(CONFIG_MEDIATEK_GE_SOC_PHY) += mediatek-ge-soc.o
++obj-y += mediatek/
+ obj-$(CONFIG_MESON_GXL_PHY) += meson-gxl.o
+ obj-$(CONFIG_MICREL_KS8995MA) += spi_ks8995.o
+ obj-$(CONFIG_MICREL_PHY) += micrel.o
+--- /dev/null
++++ b/drivers/net/phy/mediatek/Kconfig
+@@ -0,0 +1,22 @@
++# SPDX-License-Identifier: GPL-2.0-only
++config MEDIATEK_GE_PHY
++ tristate "MediaTek Gigabit Ethernet PHYs"
++ help
++ Supports the MediaTek non-built-in Gigabit Ethernet PHYs.
++
++ Non-built-in Gigabit Ethernet PHYs include mt7530/mt7531.
++ You may find mt7530 inside mt7621. This driver shares some
++ common operations with MediaTek SoC built-in Gigabit
++ Ethernet PHYs.
++
++config MEDIATEK_GE_SOC_PHY
++ tristate "MediaTek SoC Ethernet PHYs"
++ depends on (ARM64 && ARCH_MEDIATEK) || COMPILE_TEST
++ select NVMEM_MTK_EFUSE
++ help
++ Supports MediaTek SoC built-in Gigabit Ethernet PHYs.
++
++ Include support for built-in Ethernet PHYs which are present in
++ the MT7981 and MT7988 SoCs. These PHYs need calibration data
++ present in the SoCs efuse and will dynamically calibrate VCM
++ (common-mode voltage) during startup.
+--- /dev/null
++++ b/drivers/net/phy/mediatek/Makefile
+@@ -0,0 +1,3 @@
++# SPDX-License-Identifier: GPL-2.0
++obj-$(CONFIG_MEDIATEK_GE_PHY) += mtk-ge.o
++obj-$(CONFIG_MEDIATEK_GE_SOC_PHY) += mtk-ge-soc.o
+--- a/drivers/net/phy/mediatek-ge-soc.c
++++ /dev/null
+@@ -1,1555 +0,0 @@
+-// SPDX-License-Identifier: GPL-2.0+
+-#include <linux/bitfield.h>
+-#include <linux/bitmap.h>
+-#include <linux/mfd/syscon.h>
+-#include <linux/module.h>
+-#include <linux/nvmem-consumer.h>
+-#include <linux/pinctrl/consumer.h>
+-#include <linux/phy.h>
+-#include <linux/regmap.h>
+-
+-#define MTK_GPHY_ID_MT7981 0x03a29461
+-#define MTK_GPHY_ID_MT7988 0x03a29481
+-
+-#define MTK_EXT_PAGE_ACCESS 0x1f
+-#define MTK_PHY_PAGE_STANDARD 0x0000
+-#define MTK_PHY_PAGE_EXTENDED_3 0x0003
+-
+-#define MTK_PHY_LPI_REG_14 0x14
+-#define MTK_PHY_LPI_WAKE_TIMER_1000_MASK GENMASK(8, 0)
+-
+-#define MTK_PHY_LPI_REG_1c 0x1c
+-#define MTK_PHY_SMI_DET_ON_THRESH_MASK GENMASK(13, 8)
+-
+-#define MTK_PHY_PAGE_EXTENDED_2A30 0x2a30
+-#define MTK_PHY_PAGE_EXTENDED_52B5 0x52b5
+-
+-#define ANALOG_INTERNAL_OPERATION_MAX_US 20
+-#define TXRESERVE_MIN 0
+-#define TXRESERVE_MAX 7
+-
+-#define MTK_PHY_ANARG_RG 0x10
+-#define MTK_PHY_TCLKOFFSET_MASK GENMASK(12, 8)
+-
+-/* Registers on MDIO_MMD_VEND1 */
+-#define MTK_PHY_TXVLD_DA_RG 0x12
+-#define MTK_PHY_DA_TX_I2MPB_A_GBE_MASK GENMASK(15, 10)
+-#define MTK_PHY_DA_TX_I2MPB_A_TBT_MASK GENMASK(5, 0)
+-
+-#define MTK_PHY_TX_I2MPB_TEST_MODE_A2 0x16
+-#define MTK_PHY_DA_TX_I2MPB_A_HBT_MASK GENMASK(15, 10)
+-#define MTK_PHY_DA_TX_I2MPB_A_TST_MASK GENMASK(5, 0)
+-
+-#define MTK_PHY_TX_I2MPB_TEST_MODE_B1 0x17
+-#define MTK_PHY_DA_TX_I2MPB_B_GBE_MASK GENMASK(13, 8)
+-#define MTK_PHY_DA_TX_I2MPB_B_TBT_MASK GENMASK(5, 0)
+-
+-#define MTK_PHY_TX_I2MPB_TEST_MODE_B2 0x18
+-#define MTK_PHY_DA_TX_I2MPB_B_HBT_MASK GENMASK(13, 8)
+-#define MTK_PHY_DA_TX_I2MPB_B_TST_MASK GENMASK(5, 0)
+-
+-#define MTK_PHY_TX_I2MPB_TEST_MODE_C1 0x19
+-#define MTK_PHY_DA_TX_I2MPB_C_GBE_MASK GENMASK(13, 8)
+-#define MTK_PHY_DA_TX_I2MPB_C_TBT_MASK GENMASK(5, 0)
+-
+-#define MTK_PHY_TX_I2MPB_TEST_MODE_C2 0x20
+-#define MTK_PHY_DA_TX_I2MPB_C_HBT_MASK GENMASK(13, 8)
+-#define MTK_PHY_DA_TX_I2MPB_C_TST_MASK GENMASK(5, 0)
+-
+-#define MTK_PHY_TX_I2MPB_TEST_MODE_D1 0x21
+-#define MTK_PHY_DA_TX_I2MPB_D_GBE_MASK GENMASK(13, 8)
+-#define MTK_PHY_DA_TX_I2MPB_D_TBT_MASK GENMASK(5, 0)
+-
+-#define MTK_PHY_TX_I2MPB_TEST_MODE_D2 0x22
+-#define MTK_PHY_DA_TX_I2MPB_D_HBT_MASK GENMASK(13, 8)
+-#define MTK_PHY_DA_TX_I2MPB_D_TST_MASK GENMASK(5, 0)
+-
+-#define MTK_PHY_RXADC_CTRL_RG7 0xc6
+-#define MTK_PHY_DA_AD_BUF_BIAS_LP_MASK GENMASK(9, 8)
+-
+-#define MTK_PHY_RXADC_CTRL_RG9 0xc8
+-#define MTK_PHY_DA_RX_PSBN_TBT_MASK GENMASK(14, 12)
+-#define MTK_PHY_DA_RX_PSBN_HBT_MASK GENMASK(10, 8)
+-#define MTK_PHY_DA_RX_PSBN_GBE_MASK GENMASK(6, 4)
+-#define MTK_PHY_DA_RX_PSBN_LP_MASK GENMASK(2, 0)
+-
+-#define MTK_PHY_LDO_OUTPUT_V 0xd7
+-
+-#define MTK_PHY_RG_ANA_CAL_RG0 0xdb
+-#define MTK_PHY_RG_CAL_CKINV BIT(12)
+-#define MTK_PHY_RG_ANA_CALEN BIT(8)
+-#define MTK_PHY_RG_ZCALEN_A BIT(0)
+-
+-#define MTK_PHY_RG_ANA_CAL_RG1 0xdc
+-#define MTK_PHY_RG_ZCALEN_B BIT(12)
+-#define MTK_PHY_RG_ZCALEN_C BIT(8)
+-#define MTK_PHY_RG_ZCALEN_D BIT(4)
+-#define MTK_PHY_RG_TXVOS_CALEN BIT(0)
+-
+-#define MTK_PHY_RG_ANA_CAL_RG5 0xe0
+-#define MTK_PHY_RG_REXT_TRIM_MASK GENMASK(13, 8)
+-
+-#define MTK_PHY_RG_TX_FILTER 0xfe
+-
+-#define MTK_PHY_RG_LPI_PCS_DSP_CTRL_REG120 0x120
+-#define MTK_PHY_LPI_SIG_EN_LO_THRESH1000_MASK GENMASK(12, 8)
+-#define MTK_PHY_LPI_SIG_EN_HI_THRESH1000_MASK GENMASK(4, 0)
+-
+-#define MTK_PHY_RG_LPI_PCS_DSP_CTRL_REG122 0x122
+-#define MTK_PHY_LPI_NORM_MSE_HI_THRESH1000_MASK GENMASK(7, 0)
+-
+-#define MTK_PHY_RG_TESTMUX_ADC_CTRL 0x144
+-#define MTK_PHY_RG_TXEN_DIG_MASK GENMASK(5, 5)
+-
+-#define MTK_PHY_RG_CR_TX_AMP_OFFSET_A_B 0x172
+-#define MTK_PHY_CR_TX_AMP_OFFSET_A_MASK GENMASK(13, 8)
+-#define MTK_PHY_CR_TX_AMP_OFFSET_B_MASK GENMASK(6, 0)
+-
+-#define MTK_PHY_RG_CR_TX_AMP_OFFSET_C_D 0x173
+-#define MTK_PHY_CR_TX_AMP_OFFSET_C_MASK GENMASK(13, 8)
+-#define MTK_PHY_CR_TX_AMP_OFFSET_D_MASK GENMASK(6, 0)
+-
+-#define MTK_PHY_RG_AD_CAL_COMP 0x17a
+-#define MTK_PHY_AD_CAL_COMP_OUT_SHIFT (8)
+-
+-#define MTK_PHY_RG_AD_CAL_CLK 0x17b
+-#define MTK_PHY_DA_CAL_CLK BIT(0)
+-
+-#define MTK_PHY_RG_AD_CALIN 0x17c
+-#define MTK_PHY_DA_CALIN_FLAG BIT(0)
+-
+-#define MTK_PHY_RG_DASN_DAC_IN0_A 0x17d
+-#define MTK_PHY_DASN_DAC_IN0_A_MASK GENMASK(9, 0)
+-
+-#define MTK_PHY_RG_DASN_DAC_IN0_B 0x17e
+-#define MTK_PHY_DASN_DAC_IN0_B_MASK GENMASK(9, 0)
+-
+-#define MTK_PHY_RG_DASN_DAC_IN0_C 0x17f
+-#define MTK_PHY_DASN_DAC_IN0_C_MASK GENMASK(9, 0)
+-
+-#define MTK_PHY_RG_DASN_DAC_IN0_D 0x180
+-#define MTK_PHY_DASN_DAC_IN0_D_MASK GENMASK(9, 0)
+-
+-#define MTK_PHY_RG_DASN_DAC_IN1_A 0x181
+-#define MTK_PHY_DASN_DAC_IN1_A_MASK GENMASK(9, 0)
+-
+-#define MTK_PHY_RG_DASN_DAC_IN1_B 0x182
+-#define MTK_PHY_DASN_DAC_IN1_B_MASK GENMASK(9, 0)
+-
+-#define MTK_PHY_RG_DASN_DAC_IN1_C 0x183
+-#define MTK_PHY_DASN_DAC_IN1_C_MASK GENMASK(9, 0)
+-
+-#define MTK_PHY_RG_DASN_DAC_IN1_D 0x184
+-#define MTK_PHY_DASN_DAC_IN1_D_MASK GENMASK(9, 0)
+-
+-#define MTK_PHY_RG_DEV1E_REG19b 0x19b
+-#define MTK_PHY_BYPASS_DSP_LPI_READY BIT(8)
+-
+-#define MTK_PHY_RG_LP_IIR2_K1_L 0x22a
+-#define MTK_PHY_RG_LP_IIR2_K1_U 0x22b
+-#define MTK_PHY_RG_LP_IIR2_K2_L 0x22c
+-#define MTK_PHY_RG_LP_IIR2_K2_U 0x22d
+-#define MTK_PHY_RG_LP_IIR2_K3_L 0x22e
+-#define MTK_PHY_RG_LP_IIR2_K3_U 0x22f
+-#define MTK_PHY_RG_LP_IIR2_K4_L 0x230
+-#define MTK_PHY_RG_LP_IIR2_K4_U 0x231
+-#define MTK_PHY_RG_LP_IIR2_K5_L 0x232
+-#define MTK_PHY_RG_LP_IIR2_K5_U 0x233
+-
+-#define MTK_PHY_RG_DEV1E_REG234 0x234
+-#define MTK_PHY_TR_OPEN_LOOP_EN_MASK GENMASK(0, 0)
+-#define MTK_PHY_LPF_X_AVERAGE_MASK GENMASK(7, 4)
+-#define MTK_PHY_TR_LP_IIR_EEE_EN BIT(12)
+-
+-#define MTK_PHY_RG_LPF_CNT_VAL 0x235
+-
+-#define MTK_PHY_RG_DEV1E_REG238 0x238
+-#define MTK_PHY_LPI_SLV_SEND_TX_TIMER_MASK GENMASK(8, 0)
+-#define MTK_PHY_LPI_SLV_SEND_TX_EN BIT(12)
+-
+-#define MTK_PHY_RG_DEV1E_REG239 0x239
+-#define MTK_PHY_LPI_SEND_LOC_TIMER_MASK GENMASK(8, 0)
+-#define MTK_PHY_LPI_TXPCS_LOC_RCV BIT(12)
+-
+-#define MTK_PHY_RG_DEV1E_REG27C 0x27c
+-#define MTK_PHY_VGASTATE_FFE_THR_ST1_MASK GENMASK(12, 8)
+-#define MTK_PHY_RG_DEV1E_REG27D 0x27d
+-#define MTK_PHY_VGASTATE_FFE_THR_ST2_MASK GENMASK(4, 0)
+-
+-#define MTK_PHY_RG_DEV1E_REG2C7 0x2c7
+-#define MTK_PHY_MAX_GAIN_MASK GENMASK(4, 0)
+-#define MTK_PHY_MIN_GAIN_MASK GENMASK(12, 8)
+-
+-#define MTK_PHY_RG_DEV1E_REG2D1 0x2d1
+-#define MTK_PHY_VCO_SLICER_THRESH_BITS_HIGH_EEE_MASK GENMASK(7, 0)
+-#define MTK_PHY_LPI_SKIP_SD_SLV_TR BIT(8)
+-#define MTK_PHY_LPI_TR_READY BIT(9)
+-#define MTK_PHY_LPI_VCO_EEE_STG0_EN BIT(10)
+-
+-#define MTK_PHY_RG_DEV1E_REG323 0x323
+-#define MTK_PHY_EEE_WAKE_MAS_INT_DC BIT(0)
+-#define MTK_PHY_EEE_WAKE_SLV_INT_DC BIT(4)
+-
+-#define MTK_PHY_RG_DEV1E_REG324 0x324
+-#define MTK_PHY_SMI_DETCNT_MAX_MASK GENMASK(5, 0)
+-#define MTK_PHY_SMI_DET_MAX_EN BIT(8)
+-
+-#define MTK_PHY_RG_DEV1E_REG326 0x326
+-#define MTK_PHY_LPI_MODE_SD_ON BIT(0)
+-#define MTK_PHY_RESET_RANDUPD_CNT BIT(1)
+-#define MTK_PHY_TREC_UPDATE_ENAB_CLR BIT(2)
+-#define MTK_PHY_LPI_QUIT_WAIT_DFE_SIG_DET_OFF BIT(4)
+-#define MTK_PHY_TR_READY_SKIP_AFE_WAKEUP BIT(5)
+-
+-#define MTK_PHY_LDO_PUMP_EN_PAIRAB 0x502
+-#define MTK_PHY_LDO_PUMP_EN_PAIRCD 0x503
+-
+-#define MTK_PHY_DA_TX_R50_PAIR_A 0x53d
+-#define MTK_PHY_DA_TX_R50_PAIR_B 0x53e
+-#define MTK_PHY_DA_TX_R50_PAIR_C 0x53f
+-#define MTK_PHY_DA_TX_R50_PAIR_D 0x540
+-
+-/* Registers on MDIO_MMD_VEND2 */
+-#define MTK_PHY_LED0_ON_CTRL 0x24
+-#define MTK_PHY_LED1_ON_CTRL 0x26
+-#define MTK_PHY_LED_ON_MASK GENMASK(6, 0)
+-#define MTK_PHY_LED_ON_LINK1000 BIT(0)
+-#define MTK_PHY_LED_ON_LINK100 BIT(1)
+-#define MTK_PHY_LED_ON_LINK10 BIT(2)
+-#define MTK_PHY_LED_ON_LINK (MTK_PHY_LED_ON_LINK10 |\
+- MTK_PHY_LED_ON_LINK100 |\
+- MTK_PHY_LED_ON_LINK1000)
+-#define MTK_PHY_LED_ON_LINKDOWN BIT(3)
+-#define MTK_PHY_LED_ON_FDX BIT(4) /* Full duplex */
+-#define MTK_PHY_LED_ON_HDX BIT(5) /* Half duplex */
+-#define MTK_PHY_LED_ON_FORCE_ON BIT(6)
+-#define MTK_PHY_LED_ON_POLARITY BIT(14)
+-#define MTK_PHY_LED_ON_ENABLE BIT(15)
+-
+-#define MTK_PHY_LED0_BLINK_CTRL 0x25
+-#define MTK_PHY_LED1_BLINK_CTRL 0x27
+-#define MTK_PHY_LED_BLINK_1000TX BIT(0)
+-#define MTK_PHY_LED_BLINK_1000RX BIT(1)
+-#define MTK_PHY_LED_BLINK_100TX BIT(2)
+-#define MTK_PHY_LED_BLINK_100RX BIT(3)
+-#define MTK_PHY_LED_BLINK_10TX BIT(4)
+-#define MTK_PHY_LED_BLINK_10RX BIT(5)
+-#define MTK_PHY_LED_BLINK_RX (MTK_PHY_LED_BLINK_10RX |\
+- MTK_PHY_LED_BLINK_100RX |\
+- MTK_PHY_LED_BLINK_1000RX)
+-#define MTK_PHY_LED_BLINK_TX (MTK_PHY_LED_BLINK_10TX |\
+- MTK_PHY_LED_BLINK_100TX |\
+- MTK_PHY_LED_BLINK_1000TX)
+-#define MTK_PHY_LED_BLINK_COLLISION BIT(6)
+-#define MTK_PHY_LED_BLINK_RX_CRC_ERR BIT(7)
+-#define MTK_PHY_LED_BLINK_RX_IDLE_ERR BIT(8)
+-#define MTK_PHY_LED_BLINK_FORCE_BLINK BIT(9)
+-
+-#define MTK_PHY_LED1_DEFAULT_POLARITIES BIT(1)
+-
+-#define MTK_PHY_RG_BG_RASEL 0x115
+-#define MTK_PHY_RG_BG_RASEL_MASK GENMASK(2, 0)
+-
+-/* 'boottrap' register reflecting the configuration of the 4 PHY LEDs */
+-#define RG_GPIO_MISC_TPBANK0 0x6f0
+-#define RG_GPIO_MISC_TPBANK0_BOOTMODE GENMASK(11, 8)
+-
+-/* These macro privides efuse parsing for internal phy. */
+-#define EFS_DA_TX_I2MPB_A(x) (((x) >> 0) & GENMASK(5, 0))
+-#define EFS_DA_TX_I2MPB_B(x) (((x) >> 6) & GENMASK(5, 0))
+-#define EFS_DA_TX_I2MPB_C(x) (((x) >> 12) & GENMASK(5, 0))
+-#define EFS_DA_TX_I2MPB_D(x) (((x) >> 18) & GENMASK(5, 0))
+-#define EFS_DA_TX_AMP_OFFSET_A(x) (((x) >> 24) & GENMASK(5, 0))
+-
+-#define EFS_DA_TX_AMP_OFFSET_B(x) (((x) >> 0) & GENMASK(5, 0))
+-#define EFS_DA_TX_AMP_OFFSET_C(x) (((x) >> 6) & GENMASK(5, 0))
+-#define EFS_DA_TX_AMP_OFFSET_D(x) (((x) >> 12) & GENMASK(5, 0))
+-#define EFS_DA_TX_R50_A(x) (((x) >> 18) & GENMASK(5, 0))
+-#define EFS_DA_TX_R50_B(x) (((x) >> 24) & GENMASK(5, 0))
+-
+-#define EFS_DA_TX_R50_C(x) (((x) >> 0) & GENMASK(5, 0))
+-#define EFS_DA_TX_R50_D(x) (((x) >> 6) & GENMASK(5, 0))
+-
+-#define EFS_RG_BG_RASEL(x) (((x) >> 4) & GENMASK(2, 0))
+-#define EFS_RG_REXT_TRIM(x) (((x) >> 7) & GENMASK(5, 0))
+-
+-enum {
+- NO_PAIR,
+- PAIR_A,
+- PAIR_B,
+- PAIR_C,
+- PAIR_D,
+-};
+-
+-enum calibration_mode {
+- EFUSE_K,
+- SW_K
+-};
+-
+-enum CAL_ITEM {
+- REXT,
+- TX_OFFSET,
+- TX_AMP,
+- TX_R50,
+- TX_VCM
+-};
+-
+-enum CAL_MODE {
+- EFUSE_M,
+- SW_M
+-};
+-
+-#define MTK_PHY_LED_STATE_FORCE_ON 0
+-#define MTK_PHY_LED_STATE_FORCE_BLINK 1
+-#define MTK_PHY_LED_STATE_NETDEV 2
+-
+-struct mtk_socphy_priv {
+- unsigned long led_state;
+-};
+-
+-struct mtk_socphy_shared {
+- u32 boottrap;
+- struct mtk_socphy_priv priv[4];
+-};
+-
+-static int mtk_socphy_read_page(struct phy_device *phydev)
+-{
+- return __phy_read(phydev, MTK_EXT_PAGE_ACCESS);
+-}
+-
+-static int mtk_socphy_write_page(struct phy_device *phydev, int page)
+-{
+- return __phy_write(phydev, MTK_EXT_PAGE_ACCESS, page);
+-}
+-
+-/* One calibration cycle consists of:
+- * 1.Set DA_CALIN_FLAG high to start calibration. Keep it high
+- * until AD_CAL_COMP is ready to output calibration result.
+- * 2.Wait until DA_CAL_CLK is available.
+- * 3.Fetch AD_CAL_COMP_OUT.
+- */
+-static int cal_cycle(struct phy_device *phydev, int devad,
+- u32 regnum, u16 mask, u16 cal_val)
+-{
+- int reg_val;
+- int ret;
+-
+- phy_modify_mmd(phydev, devad, regnum,
+- mask, cal_val);
+- phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_AD_CALIN,
+- MTK_PHY_DA_CALIN_FLAG);
+-
+- ret = phy_read_mmd_poll_timeout(phydev, MDIO_MMD_VEND1,
+- MTK_PHY_RG_AD_CAL_CLK, reg_val,
+- reg_val & MTK_PHY_DA_CAL_CLK, 500,
+- ANALOG_INTERNAL_OPERATION_MAX_US, false);
+- if (ret) {
+- phydev_err(phydev, "Calibration cycle timeout\n");
+- return ret;
+- }
+-
+- phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_AD_CALIN,
+- MTK_PHY_DA_CALIN_FLAG);
+- ret = phy_read_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_AD_CAL_COMP) >>
+- MTK_PHY_AD_CAL_COMP_OUT_SHIFT;
+- phydev_dbg(phydev, "cal_val: 0x%x, ret: %d\n", cal_val, ret);
+-
+- return ret;
+-}
+-
+-static int rext_fill_result(struct phy_device *phydev, u16 *buf)
+-{
+- phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG5,
+- MTK_PHY_RG_REXT_TRIM_MASK, buf[0] << 8);
+- phy_modify_mmd(phydev, MDIO_MMD_VEND2, MTK_PHY_RG_BG_RASEL,
+- MTK_PHY_RG_BG_RASEL_MASK, buf[1]);
+-
+- return 0;
+-}
+-
+-static int rext_cal_efuse(struct phy_device *phydev, u32 *buf)
+-{
+- u16 rext_cal_val[2];
+-
+- rext_cal_val[0] = EFS_RG_REXT_TRIM(buf[3]);
+- rext_cal_val[1] = EFS_RG_BG_RASEL(buf[3]);
+- rext_fill_result(phydev, rext_cal_val);
+-
+- return 0;
+-}
+-
+-static int tx_offset_fill_result(struct phy_device *phydev, u16 *buf)
+-{
+- phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_CR_TX_AMP_OFFSET_A_B,
+- MTK_PHY_CR_TX_AMP_OFFSET_A_MASK, buf[0] << 8);
+- phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_CR_TX_AMP_OFFSET_A_B,
+- MTK_PHY_CR_TX_AMP_OFFSET_B_MASK, buf[1]);
+- phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_CR_TX_AMP_OFFSET_C_D,
+- MTK_PHY_CR_TX_AMP_OFFSET_C_MASK, buf[2] << 8);
+- phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_CR_TX_AMP_OFFSET_C_D,
+- MTK_PHY_CR_TX_AMP_OFFSET_D_MASK, buf[3]);
+-
+- return 0;
+-}
+-
+-static int tx_offset_cal_efuse(struct phy_device *phydev, u32 *buf)
+-{
+- u16 tx_offset_cal_val[4];
+-
+- tx_offset_cal_val[0] = EFS_DA_TX_AMP_OFFSET_A(buf[0]);
+- tx_offset_cal_val[1] = EFS_DA_TX_AMP_OFFSET_B(buf[1]);
+- tx_offset_cal_val[2] = EFS_DA_TX_AMP_OFFSET_C(buf[1]);
+- tx_offset_cal_val[3] = EFS_DA_TX_AMP_OFFSET_D(buf[1]);
+-
+- tx_offset_fill_result(phydev, tx_offset_cal_val);
+-
+- return 0;
+-}
+-
+-static int tx_amp_fill_result(struct phy_device *phydev, u16 *buf)
+-{
+- int i;
+- int bias[16] = {};
+- const int vals_9461[16] = { 7, 1, 4, 7,
+- 7, 1, 4, 7,
+- 7, 1, 4, 7,
+- 7, 1, 4, 7 };
+- const int vals_9481[16] = { 10, 6, 6, 10,
+- 10, 6, 6, 10,
+- 10, 6, 6, 10,
+- 10, 6, 6, 10 };
+- switch (phydev->drv->phy_id) {
+- case MTK_GPHY_ID_MT7981:
+- /* We add some calibration to efuse values
+- * due to board level influence.
+- * GBE: +7, TBT: +1, HBT: +4, TST: +7
+- */
+- memcpy(bias, (const void *)vals_9461, sizeof(bias));
+- break;
+- case MTK_GPHY_ID_MT7988:
+- memcpy(bias, (const void *)vals_9481, sizeof(bias));
+- break;
+- }
+-
+- /* Prevent overflow */
+- for (i = 0; i < 12; i++) {
+- if (buf[i >> 2] + bias[i] > 63) {
+- buf[i >> 2] = 63;
+- bias[i] = 0;
+- }
+- }
+-
+- phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TXVLD_DA_RG,
+- MTK_PHY_DA_TX_I2MPB_A_GBE_MASK, (buf[0] + bias[0]) << 10);
+- phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TXVLD_DA_RG,
+- MTK_PHY_DA_TX_I2MPB_A_TBT_MASK, buf[0] + bias[1]);
+- phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_A2,
+- MTK_PHY_DA_TX_I2MPB_A_HBT_MASK, (buf[0] + bias[2]) << 10);
+- phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_A2,
+- MTK_PHY_DA_TX_I2MPB_A_TST_MASK, buf[0] + bias[3]);
+-
+- phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_B1,
+- MTK_PHY_DA_TX_I2MPB_B_GBE_MASK, (buf[1] + bias[4]) << 8);
+- phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_B1,
+- MTK_PHY_DA_TX_I2MPB_B_TBT_MASK, buf[1] + bias[5]);
+- phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_B2,
+- MTK_PHY_DA_TX_I2MPB_B_HBT_MASK, (buf[1] + bias[6]) << 8);
+- phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_B2,
+- MTK_PHY_DA_TX_I2MPB_B_TST_MASK, buf[1] + bias[7]);
+-
+- phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_C1,
+- MTK_PHY_DA_TX_I2MPB_C_GBE_MASK, (buf[2] + bias[8]) << 8);
+- phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_C1,
+- MTK_PHY_DA_TX_I2MPB_C_TBT_MASK, buf[2] + bias[9]);
+- phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_C2,
+- MTK_PHY_DA_TX_I2MPB_C_HBT_MASK, (buf[2] + bias[10]) << 8);
+- phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_C2,
+- MTK_PHY_DA_TX_I2MPB_C_TST_MASK, buf[2] + bias[11]);
+-
+- phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_D1,
+- MTK_PHY_DA_TX_I2MPB_D_GBE_MASK, (buf[3] + bias[12]) << 8);
+- phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_D1,
+- MTK_PHY_DA_TX_I2MPB_D_TBT_MASK, buf[3] + bias[13]);
+- phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_D2,
+- MTK_PHY_DA_TX_I2MPB_D_HBT_MASK, (buf[3] + bias[14]) << 8);
+- phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_D2,
+- MTK_PHY_DA_TX_I2MPB_D_TST_MASK, buf[3] + bias[15]);
+-
+- return 0;
+-}
+-
+-static int tx_amp_cal_efuse(struct phy_device *phydev, u32 *buf)
+-{
+- u16 tx_amp_cal_val[4];
+-
+- tx_amp_cal_val[0] = EFS_DA_TX_I2MPB_A(buf[0]);
+- tx_amp_cal_val[1] = EFS_DA_TX_I2MPB_B(buf[0]);
+- tx_amp_cal_val[2] = EFS_DA_TX_I2MPB_C(buf[0]);
+- tx_amp_cal_val[3] = EFS_DA_TX_I2MPB_D(buf[0]);
+- tx_amp_fill_result(phydev, tx_amp_cal_val);
+-
+- return 0;
+-}
+-
+-static int tx_r50_fill_result(struct phy_device *phydev, u16 tx_r50_cal_val,
+- u8 txg_calen_x)
+-{
+- int bias = 0;
+- u16 reg, val;
+-
+- if (phydev->drv->phy_id == MTK_GPHY_ID_MT7988)
+- bias = -1;
+-
+- val = clamp_val(bias + tx_r50_cal_val, 0, 63);
+-
+- switch (txg_calen_x) {
+- case PAIR_A:
+- reg = MTK_PHY_DA_TX_R50_PAIR_A;
+- break;
+- case PAIR_B:
+- reg = MTK_PHY_DA_TX_R50_PAIR_B;
+- break;
+- case PAIR_C:
+- reg = MTK_PHY_DA_TX_R50_PAIR_C;
+- break;
+- case PAIR_D:
+- reg = MTK_PHY_DA_TX_R50_PAIR_D;
+- break;
+- default:
+- return -EINVAL;
+- }
+-
+- phy_write_mmd(phydev, MDIO_MMD_VEND1, reg, val | val << 8);
+-
+- return 0;
+-}
+-
+-static int tx_r50_cal_efuse(struct phy_device *phydev, u32 *buf,
+- u8 txg_calen_x)
+-{
+- u16 tx_r50_cal_val;
+-
+- switch (txg_calen_x) {
+- case PAIR_A:
+- tx_r50_cal_val = EFS_DA_TX_R50_A(buf[1]);
+- break;
+- case PAIR_B:
+- tx_r50_cal_val = EFS_DA_TX_R50_B(buf[1]);
+- break;
+- case PAIR_C:
+- tx_r50_cal_val = EFS_DA_TX_R50_C(buf[2]);
+- break;
+- case PAIR_D:
+- tx_r50_cal_val = EFS_DA_TX_R50_D(buf[2]);
+- break;
+- default:
+- return -EINVAL;
+- }
+- tx_r50_fill_result(phydev, tx_r50_cal_val, txg_calen_x);
+-
+- return 0;
+-}
+-
+-static int tx_vcm_cal_sw(struct phy_device *phydev, u8 rg_txreserve_x)
+-{
+- u8 lower_idx, upper_idx, txreserve_val;
+- u8 lower_ret, upper_ret;
+- int ret;
+-
+- phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG0,
+- MTK_PHY_RG_ANA_CALEN);
+- phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG0,
+- MTK_PHY_RG_CAL_CKINV);
+- phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG1,
+- MTK_PHY_RG_TXVOS_CALEN);
+-
+- switch (rg_txreserve_x) {
+- case PAIR_A:
+- phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1,
+- MTK_PHY_RG_DASN_DAC_IN0_A,
+- MTK_PHY_DASN_DAC_IN0_A_MASK);
+- phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1,
+- MTK_PHY_RG_DASN_DAC_IN1_A,
+- MTK_PHY_DASN_DAC_IN1_A_MASK);
+- phy_set_bits_mmd(phydev, MDIO_MMD_VEND1,
+- MTK_PHY_RG_ANA_CAL_RG0,
+- MTK_PHY_RG_ZCALEN_A);
+- break;
+- case PAIR_B:
+- phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1,
+- MTK_PHY_RG_DASN_DAC_IN0_B,
+- MTK_PHY_DASN_DAC_IN0_B_MASK);
+- phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1,
+- MTK_PHY_RG_DASN_DAC_IN1_B,
+- MTK_PHY_DASN_DAC_IN1_B_MASK);
+- phy_set_bits_mmd(phydev, MDIO_MMD_VEND1,
+- MTK_PHY_RG_ANA_CAL_RG1,
+- MTK_PHY_RG_ZCALEN_B);
+- break;
+- case PAIR_C:
+- phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1,
+- MTK_PHY_RG_DASN_DAC_IN0_C,
+- MTK_PHY_DASN_DAC_IN0_C_MASK);
+- phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1,
+- MTK_PHY_RG_DASN_DAC_IN1_C,
+- MTK_PHY_DASN_DAC_IN1_C_MASK);
+- phy_set_bits_mmd(phydev, MDIO_MMD_VEND1,
+- MTK_PHY_RG_ANA_CAL_RG1,
+- MTK_PHY_RG_ZCALEN_C);
+- break;
+- case PAIR_D:
+- phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1,
+- MTK_PHY_RG_DASN_DAC_IN0_D,
+- MTK_PHY_DASN_DAC_IN0_D_MASK);
+- phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1,
+- MTK_PHY_RG_DASN_DAC_IN1_D,
+- MTK_PHY_DASN_DAC_IN1_D_MASK);
+- phy_set_bits_mmd(phydev, MDIO_MMD_VEND1,
+- MTK_PHY_RG_ANA_CAL_RG1,
+- MTK_PHY_RG_ZCALEN_D);
+- break;
+- default:
+- ret = -EINVAL;
+- goto restore;
+- }
+-
+- lower_idx = TXRESERVE_MIN;
+- upper_idx = TXRESERVE_MAX;
+-
+- phydev_dbg(phydev, "Start TX-VCM SW cal.\n");
+- while ((upper_idx - lower_idx) > 1) {
+- txreserve_val = DIV_ROUND_CLOSEST(lower_idx + upper_idx, 2);
+- ret = cal_cycle(phydev, MDIO_MMD_VEND1, MTK_PHY_RXADC_CTRL_RG9,
+- MTK_PHY_DA_RX_PSBN_TBT_MASK |
+- MTK_PHY_DA_RX_PSBN_HBT_MASK |
+- MTK_PHY_DA_RX_PSBN_GBE_MASK |
+- MTK_PHY_DA_RX_PSBN_LP_MASK,
+- txreserve_val << 12 | txreserve_val << 8 |
+- txreserve_val << 4 | txreserve_val);
+- if (ret == 1) {
+- upper_idx = txreserve_val;
+- upper_ret = ret;
+- } else if (ret == 0) {
+- lower_idx = txreserve_val;
+- lower_ret = ret;
+- } else {
+- goto restore;
+- }
+- }
+-
+- if (lower_idx == TXRESERVE_MIN) {
+- lower_ret = cal_cycle(phydev, MDIO_MMD_VEND1,
+- MTK_PHY_RXADC_CTRL_RG9,
+- MTK_PHY_DA_RX_PSBN_TBT_MASK |
+- MTK_PHY_DA_RX_PSBN_HBT_MASK |
+- MTK_PHY_DA_RX_PSBN_GBE_MASK |
+- MTK_PHY_DA_RX_PSBN_LP_MASK,
+- lower_idx << 12 | lower_idx << 8 |
+- lower_idx << 4 | lower_idx);
+- ret = lower_ret;
+- } else if (upper_idx == TXRESERVE_MAX) {
+- upper_ret = cal_cycle(phydev, MDIO_MMD_VEND1,
+- MTK_PHY_RXADC_CTRL_RG9,
+- MTK_PHY_DA_RX_PSBN_TBT_MASK |
+- MTK_PHY_DA_RX_PSBN_HBT_MASK |
+- MTK_PHY_DA_RX_PSBN_GBE_MASK |
+- MTK_PHY_DA_RX_PSBN_LP_MASK,
+- upper_idx << 12 | upper_idx << 8 |
+- upper_idx << 4 | upper_idx);
+- ret = upper_ret;
+- }
+- if (ret < 0)
+- goto restore;
+-
+- /* We calibrate TX-VCM in different logic. Check upper index and then
+- * lower index. If this calibration is valid, apply lower index's result.
+- */
+- ret = upper_ret - lower_ret;
+- if (ret == 1) {
+- ret = 0;
+- /* Make sure we use upper_idx in our calibration system */
+- cal_cycle(phydev, MDIO_MMD_VEND1, MTK_PHY_RXADC_CTRL_RG9,
+- MTK_PHY_DA_RX_PSBN_TBT_MASK |
+- MTK_PHY_DA_RX_PSBN_HBT_MASK |
+- MTK_PHY_DA_RX_PSBN_GBE_MASK |
+- MTK_PHY_DA_RX_PSBN_LP_MASK,
+- upper_idx << 12 | upper_idx << 8 |
+- upper_idx << 4 | upper_idx);
+- phydev_dbg(phydev, "TX-VCM SW cal result: 0x%x\n", upper_idx);
+- } else if (lower_idx == TXRESERVE_MIN && upper_ret == 1 &&
+- lower_ret == 1) {
+- ret = 0;
+- cal_cycle(phydev, MDIO_MMD_VEND1, MTK_PHY_RXADC_CTRL_RG9,
+- MTK_PHY_DA_RX_PSBN_TBT_MASK |
+- MTK_PHY_DA_RX_PSBN_HBT_MASK |
+- MTK_PHY_DA_RX_PSBN_GBE_MASK |
+- MTK_PHY_DA_RX_PSBN_LP_MASK,
+- lower_idx << 12 | lower_idx << 8 |
+- lower_idx << 4 | lower_idx);
+- phydev_warn(phydev, "TX-VCM SW cal result at low margin 0x%x\n",
+- lower_idx);
+- } else if (upper_idx == TXRESERVE_MAX && upper_ret == 0 &&
+- lower_ret == 0) {
+- ret = 0;
+- phydev_warn(phydev, "TX-VCM SW cal result at high margin 0x%x\n",
+- upper_idx);
+- } else {
+- ret = -EINVAL;
+- }
+-
+-restore:
+- phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG0,
+- MTK_PHY_RG_ANA_CALEN);
+- phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG1,
+- MTK_PHY_RG_TXVOS_CALEN);
+- phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG0,
+- MTK_PHY_RG_ZCALEN_A);
+- phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG1,
+- MTK_PHY_RG_ZCALEN_B | MTK_PHY_RG_ZCALEN_C |
+- MTK_PHY_RG_ZCALEN_D);
+-
+- return ret;
+-}
+-
+-static void mt798x_phy_common_finetune(struct phy_device *phydev)
+-{
+- phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_52B5);
+- /* SlvDSPreadyTime = 24, MasDSPreadyTime = 24 */
+- __phy_write(phydev, 0x11, 0xc71);
+- __phy_write(phydev, 0x12, 0xc);
+- __phy_write(phydev, 0x10, 0x8fae);
+-
+- /* EnabRandUpdTrig = 1 */
+- __phy_write(phydev, 0x11, 0x2f00);
+- __phy_write(phydev, 0x12, 0xe);
+- __phy_write(phydev, 0x10, 0x8fb0);
+-
+- /* NormMseLoThresh = 85 */
+- __phy_write(phydev, 0x11, 0x55a0);
+- __phy_write(phydev, 0x12, 0x0);
+- __phy_write(phydev, 0x10, 0x83aa);
+-
+- /* FfeUpdGainForce = 1(Enable), FfeUpdGainForceVal = 4 */
+- __phy_write(phydev, 0x11, 0x240);
+- __phy_write(phydev, 0x12, 0x0);
+- __phy_write(phydev, 0x10, 0x9680);
+-
+- /* TrFreeze = 0 (mt7988 default) */
+- __phy_write(phydev, 0x11, 0x0);
+- __phy_write(phydev, 0x12, 0x0);
+- __phy_write(phydev, 0x10, 0x9686);
+-
+- /* SSTrKp100 = 5 */
+- /* SSTrKf100 = 6 */
+- /* SSTrKp1000Mas = 5 */
+- /* SSTrKf1000Mas = 6 */
+- /* SSTrKp1000Slv = 5 */
+- /* SSTrKf1000Slv = 6 */
+- __phy_write(phydev, 0x11, 0xbaef);
+- __phy_write(phydev, 0x12, 0x2e);
+- __phy_write(phydev, 0x10, 0x968c);
+- phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0);
+-}
+-
+-static void mt7981_phy_finetune(struct phy_device *phydev)
+-{
+- u16 val[8] = { 0x01ce, 0x01c1,
+- 0x020f, 0x0202,
+- 0x03d0, 0x03c0,
+- 0x0013, 0x0005 };
+- int i, k;
+-
+- /* 100M eye finetune:
+- * Keep middle level of TX MLT3 shapper as default.
+- * Only change TX MLT3 overshoot level here.
+- */
+- for (k = 0, i = 1; i < 12; i++) {
+- if (i % 3 == 0)
+- continue;
+- phy_write_mmd(phydev, MDIO_MMD_VEND1, i, val[k++]);
+- }
+-
+- phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_52B5);
+- /* ResetSyncOffset = 6 */
+- __phy_write(phydev, 0x11, 0x600);
+- __phy_write(phydev, 0x12, 0x0);
+- __phy_write(phydev, 0x10, 0x8fc0);
+-
+- /* VgaDecRate = 1 */
+- __phy_write(phydev, 0x11, 0x4c2a);
+- __phy_write(phydev, 0x12, 0x3e);
+- __phy_write(phydev, 0x10, 0x8fa4);
+-
+- /* MrvlTrFix100Kp = 3, MrvlTrFix100Kf = 2,
+- * MrvlTrFix1000Kp = 3, MrvlTrFix1000Kf = 2
+- */
+- __phy_write(phydev, 0x11, 0xd10a);
+- __phy_write(phydev, 0x12, 0x34);
+- __phy_write(phydev, 0x10, 0x8f82);
+-
+- /* VcoSlicerThreshBitsHigh */
+- __phy_write(phydev, 0x11, 0x5555);
+- __phy_write(phydev, 0x12, 0x55);
+- __phy_write(phydev, 0x10, 0x8ec0);
+- phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0);
+-
+- /* TR_OPEN_LOOP_EN = 1, lpf_x_average = 9 */
+- phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG234,
+- MTK_PHY_TR_OPEN_LOOP_EN_MASK | MTK_PHY_LPF_X_AVERAGE_MASK,
+- BIT(0) | FIELD_PREP(MTK_PHY_LPF_X_AVERAGE_MASK, 0x9));
+-
+- /* rg_tr_lpf_cnt_val = 512 */
+- phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LPF_CNT_VAL, 0x200);
+-
+- /* IIR2 related */
+- phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K1_L, 0x82);
+- phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K1_U, 0x0);
+- phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K2_L, 0x103);
+- phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K2_U, 0x0);
+- phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K3_L, 0x82);
+- phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K3_U, 0x0);
+- phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K4_L, 0xd177);
+- phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K4_U, 0x3);
+- phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K5_L, 0x2c82);
+- phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K5_U, 0xe);
+-
+- /* FFE peaking */
+- phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG27C,
+- MTK_PHY_VGASTATE_FFE_THR_ST1_MASK, 0x1b << 8);
+- phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG27D,
+- MTK_PHY_VGASTATE_FFE_THR_ST2_MASK, 0x1e);
+-
+- /* Disable LDO pump */
+- phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_LDO_PUMP_EN_PAIRAB, 0x0);
+- phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_LDO_PUMP_EN_PAIRCD, 0x0);
+- /* Adjust LDO output voltage */
+- phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_LDO_OUTPUT_V, 0x2222);
+-}
+-
+-static void mt7988_phy_finetune(struct phy_device *phydev)
+-{
+- u16 val[12] = { 0x0187, 0x01cd, 0x01c8, 0x0182,
+- 0x020d, 0x0206, 0x0384, 0x03d0,
+- 0x03c6, 0x030a, 0x0011, 0x0005 };
+- int i;
+-
+- /* Set default MLT3 shaper first */
+- for (i = 0; i < 12; i++)
+- phy_write_mmd(phydev, MDIO_MMD_VEND1, i, val[i]);
+-
+- /* TCT finetune */
+- phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_TX_FILTER, 0x5);
+-
+- phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_52B5);
+- /* ResetSyncOffset = 5 */
+- __phy_write(phydev, 0x11, 0x500);
+- __phy_write(phydev, 0x12, 0x0);
+- __phy_write(phydev, 0x10, 0x8fc0);
+-
+- /* VgaDecRate is 1 at default on mt7988 */
+-
+- /* MrvlTrFix100Kp = 6, MrvlTrFix100Kf = 7,
+- * MrvlTrFix1000Kp = 6, MrvlTrFix1000Kf = 7
+- */
+- __phy_write(phydev, 0x11, 0xb90a);
+- __phy_write(phydev, 0x12, 0x6f);
+- __phy_write(phydev, 0x10, 0x8f82);
+-
+- /* RemAckCntLimitCtrl = 1 */
+- __phy_write(phydev, 0x11, 0xfbba);
+- __phy_write(phydev, 0x12, 0xc3);
+- __phy_write(phydev, 0x10, 0x87f8);
+-
+- phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0);
+-
+- /* TR_OPEN_LOOP_EN = 1, lpf_x_average = 10 */
+- phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG234,
+- MTK_PHY_TR_OPEN_LOOP_EN_MASK | MTK_PHY_LPF_X_AVERAGE_MASK,
+- BIT(0) | FIELD_PREP(MTK_PHY_LPF_X_AVERAGE_MASK, 0xa));
+-
+- /* rg_tr_lpf_cnt_val = 1023 */
+- phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LPF_CNT_VAL, 0x3ff);
+-}
+-
+-static void mt798x_phy_eee(struct phy_device *phydev)
+-{
+- phy_modify_mmd(phydev, MDIO_MMD_VEND1,
+- MTK_PHY_RG_LPI_PCS_DSP_CTRL_REG120,
+- MTK_PHY_LPI_SIG_EN_LO_THRESH1000_MASK |
+- MTK_PHY_LPI_SIG_EN_HI_THRESH1000_MASK,
+- FIELD_PREP(MTK_PHY_LPI_SIG_EN_LO_THRESH1000_MASK, 0x0) |
+- FIELD_PREP(MTK_PHY_LPI_SIG_EN_HI_THRESH1000_MASK, 0x14));
+-
+- phy_modify_mmd(phydev, MDIO_MMD_VEND1,
+- MTK_PHY_RG_LPI_PCS_DSP_CTRL_REG122,
+- MTK_PHY_LPI_NORM_MSE_HI_THRESH1000_MASK,
+- FIELD_PREP(MTK_PHY_LPI_NORM_MSE_HI_THRESH1000_MASK,
+- 0xff));
+-
+- phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1,
+- MTK_PHY_RG_TESTMUX_ADC_CTRL,
+- MTK_PHY_RG_TXEN_DIG_MASK);
+-
+- phy_set_bits_mmd(phydev, MDIO_MMD_VEND1,
+- MTK_PHY_RG_DEV1E_REG19b, MTK_PHY_BYPASS_DSP_LPI_READY);
+-
+- phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1,
+- MTK_PHY_RG_DEV1E_REG234, MTK_PHY_TR_LP_IIR_EEE_EN);
+-
+- phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG238,
+- MTK_PHY_LPI_SLV_SEND_TX_TIMER_MASK |
+- MTK_PHY_LPI_SLV_SEND_TX_EN,
+- FIELD_PREP(MTK_PHY_LPI_SLV_SEND_TX_TIMER_MASK, 0x120));
+-
+- /* Keep MTK_PHY_LPI_SEND_LOC_TIMER as 375 */
+- phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG239,
+- MTK_PHY_LPI_TXPCS_LOC_RCV);
+-
+- /* This also fixes some IoT issues, such as CH340 */
+- phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG2C7,
+- MTK_PHY_MAX_GAIN_MASK | MTK_PHY_MIN_GAIN_MASK,
+- FIELD_PREP(MTK_PHY_MAX_GAIN_MASK, 0x8) |
+- FIELD_PREP(MTK_PHY_MIN_GAIN_MASK, 0x13));
+-
+- phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG2D1,
+- MTK_PHY_VCO_SLICER_THRESH_BITS_HIGH_EEE_MASK,
+- FIELD_PREP(MTK_PHY_VCO_SLICER_THRESH_BITS_HIGH_EEE_MASK,
+- 0x33) |
+- MTK_PHY_LPI_SKIP_SD_SLV_TR | MTK_PHY_LPI_TR_READY |
+- MTK_PHY_LPI_VCO_EEE_STG0_EN);
+-
+- phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG323,
+- MTK_PHY_EEE_WAKE_MAS_INT_DC |
+- MTK_PHY_EEE_WAKE_SLV_INT_DC);
+-
+- phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG324,
+- MTK_PHY_SMI_DETCNT_MAX_MASK,
+- FIELD_PREP(MTK_PHY_SMI_DETCNT_MAX_MASK, 0x3f) |
+- MTK_PHY_SMI_DET_MAX_EN);
+-
+- phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG326,
+- MTK_PHY_LPI_MODE_SD_ON | MTK_PHY_RESET_RANDUPD_CNT |
+- MTK_PHY_TREC_UPDATE_ENAB_CLR |
+- MTK_PHY_LPI_QUIT_WAIT_DFE_SIG_DET_OFF |
+- MTK_PHY_TR_READY_SKIP_AFE_WAKEUP);
+-
+- phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_52B5);
+- /* Regsigdet_sel_1000 = 0 */
+- __phy_write(phydev, 0x11, 0xb);
+- __phy_write(phydev, 0x12, 0x0);
+- __phy_write(phydev, 0x10, 0x9690);
+-
+- /* REG_EEE_st2TrKf1000 = 2 */
+- __phy_write(phydev, 0x11, 0x114f);
+- __phy_write(phydev, 0x12, 0x2);
+- __phy_write(phydev, 0x10, 0x969a);
+-
+- /* RegEEE_slv_wake_tr_timer_tar = 6, RegEEE_slv_remtx_timer_tar = 20 */
+- __phy_write(phydev, 0x11, 0x3028);
+- __phy_write(phydev, 0x12, 0x0);
+- __phy_write(phydev, 0x10, 0x969e);
+-
+- /* RegEEE_slv_wake_int_timer_tar = 8 */
+- __phy_write(phydev, 0x11, 0x5010);
+- __phy_write(phydev, 0x12, 0x0);
+- __phy_write(phydev, 0x10, 0x96a0);
+-
+- /* RegEEE_trfreeze_timer2 = 586 */
+- __phy_write(phydev, 0x11, 0x24a);
+- __phy_write(phydev, 0x12, 0x0);
+- __phy_write(phydev, 0x10, 0x96a8);
+-
+- /* RegEEE100Stg1_tar = 16 */
+- __phy_write(phydev, 0x11, 0x3210);
+- __phy_write(phydev, 0x12, 0x0);
+- __phy_write(phydev, 0x10, 0x96b8);
+-
+- /* REGEEE_wake_slv_tr_wait_dfesigdet_en = 0 */
+- __phy_write(phydev, 0x11, 0x1463);
+- __phy_write(phydev, 0x12, 0x0);
+- __phy_write(phydev, 0x10, 0x96ca);
+-
+- /* DfeTailEnableVgaThresh1000 = 27 */
+- __phy_write(phydev, 0x11, 0x36);
+- __phy_write(phydev, 0x12, 0x0);
+- __phy_write(phydev, 0x10, 0x8f80);
+- phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0);
+-
+- phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_3);
+- __phy_modify(phydev, MTK_PHY_LPI_REG_14, MTK_PHY_LPI_WAKE_TIMER_1000_MASK,
+- FIELD_PREP(MTK_PHY_LPI_WAKE_TIMER_1000_MASK, 0x19c));
+-
+- __phy_modify(phydev, MTK_PHY_LPI_REG_1c, MTK_PHY_SMI_DET_ON_THRESH_MASK,
+- FIELD_PREP(MTK_PHY_SMI_DET_ON_THRESH_MASK, 0xc));
+- phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0);
+-
+- phy_modify_mmd(phydev, MDIO_MMD_VEND1,
+- MTK_PHY_RG_LPI_PCS_DSP_CTRL_REG122,
+- MTK_PHY_LPI_NORM_MSE_HI_THRESH1000_MASK,
+- FIELD_PREP(MTK_PHY_LPI_NORM_MSE_HI_THRESH1000_MASK, 0xff));
+-}
+-
+-static int cal_sw(struct phy_device *phydev, enum CAL_ITEM cal_item,
+- u8 start_pair, u8 end_pair)
+-{
+- u8 pair_n;
+- int ret;
+-
+- for (pair_n = start_pair; pair_n <= end_pair; pair_n++) {
+- /* TX_OFFSET & TX_AMP have no SW calibration. */
+- switch (cal_item) {
+- case TX_VCM:
+- ret = tx_vcm_cal_sw(phydev, pair_n);
+- break;
+- default:
+- return -EINVAL;
+- }
+- if (ret)
+- return ret;
+- }
+- return 0;
+-}
+-
+-static int cal_efuse(struct phy_device *phydev, enum CAL_ITEM cal_item,
+- u8 start_pair, u8 end_pair, u32 *buf)
+-{
+- u8 pair_n;
+- int ret;
+-
+- for (pair_n = start_pair; pair_n <= end_pair; pair_n++) {
+- /* TX_VCM has no efuse calibration. */
+- switch (cal_item) {
+- case REXT:
+- ret = rext_cal_efuse(phydev, buf);
+- break;
+- case TX_OFFSET:
+- ret = tx_offset_cal_efuse(phydev, buf);
+- break;
+- case TX_AMP:
+- ret = tx_amp_cal_efuse(phydev, buf);
+- break;
+- case TX_R50:
+- ret = tx_r50_cal_efuse(phydev, buf, pair_n);
+- break;
+- default:
+- return -EINVAL;
+- }
+- if (ret)
+- return ret;
+- }
+-
+- return 0;
+-}
+-
+-static int start_cal(struct phy_device *phydev, enum CAL_ITEM cal_item,
+- enum CAL_MODE cal_mode, u8 start_pair,
+- u8 end_pair, u32 *buf)
+-{
+- int ret;
+-
+- switch (cal_mode) {
+- case EFUSE_M:
+- ret = cal_efuse(phydev, cal_item, start_pair,
+- end_pair, buf);
+- break;
+- case SW_M:
+- ret = cal_sw(phydev, cal_item, start_pair, end_pair);
+- break;
+- default:
+- return -EINVAL;
+- }
+-
+- if (ret) {
+- phydev_err(phydev, "cal %d failed\n", cal_item);
+- return -EIO;
+- }
+-
+- return 0;
+-}
+-
+-static int mt798x_phy_calibration(struct phy_device *phydev)
+-{
+- int ret = 0;
+- u32 *buf;
+- size_t len;
+- struct nvmem_cell *cell;
+-
+- cell = nvmem_cell_get(&phydev->mdio.dev, "phy-cal-data");
+- if (IS_ERR(cell)) {
+- if (PTR_ERR(cell) == -EPROBE_DEFER)
+- return PTR_ERR(cell);
+- return 0;
+- }
+-
+- buf = (u32 *)nvmem_cell_read(cell, &len);
+- if (IS_ERR(buf))
+- return PTR_ERR(buf);
+- nvmem_cell_put(cell);
+-
+- if (!buf[0] || !buf[1] || !buf[2] || !buf[3] || len < 4 * sizeof(u32)) {
+- phydev_err(phydev, "invalid efuse data\n");
+- ret = -EINVAL;
+- goto out;
+- }
+-
+- ret = start_cal(phydev, REXT, EFUSE_M, NO_PAIR, NO_PAIR, buf);
+- if (ret)
+- goto out;
+- ret = start_cal(phydev, TX_OFFSET, EFUSE_M, NO_PAIR, NO_PAIR, buf);
+- if (ret)
+- goto out;
+- ret = start_cal(phydev, TX_AMP, EFUSE_M, NO_PAIR, NO_PAIR, buf);
+- if (ret)
+- goto out;
+- ret = start_cal(phydev, TX_R50, EFUSE_M, PAIR_A, PAIR_D, buf);
+- if (ret)
+- goto out;
+- ret = start_cal(phydev, TX_VCM, SW_M, PAIR_A, PAIR_A, buf);
+- if (ret)
+- goto out;
+-
+-out:
+- kfree(buf);
+- return ret;
+-}
+-
+-static int mt798x_phy_config_init(struct phy_device *phydev)
+-{
+- switch (phydev->drv->phy_id) {
+- case MTK_GPHY_ID_MT7981:
+- mt7981_phy_finetune(phydev);
+- break;
+- case MTK_GPHY_ID_MT7988:
+- mt7988_phy_finetune(phydev);
+- break;
+- }
+-
+- mt798x_phy_common_finetune(phydev);
+- mt798x_phy_eee(phydev);
+-
+- return mt798x_phy_calibration(phydev);
+-}
+-
+-static int mt798x_phy_hw_led_on_set(struct phy_device *phydev, u8 index,
+- bool on)
+-{
+- unsigned int bit_on = MTK_PHY_LED_STATE_FORCE_ON + (index ? 16 : 0);
+- struct mtk_socphy_priv *priv = phydev->priv;
+- bool changed;
+-
+- if (on)
+- changed = !test_and_set_bit(bit_on, &priv->led_state);
+- else
+- changed = !!test_and_clear_bit(bit_on, &priv->led_state);
+-
+- changed |= !!test_and_clear_bit(MTK_PHY_LED_STATE_NETDEV +
+- (index ? 16 : 0), &priv->led_state);
+- if (changed)
+- return phy_modify_mmd(phydev, MDIO_MMD_VEND2, index ?
+- MTK_PHY_LED1_ON_CTRL : MTK_PHY_LED0_ON_CTRL,
+- MTK_PHY_LED_ON_MASK,
+- on ? MTK_PHY_LED_ON_FORCE_ON : 0);
+- else
+- return 0;
+-}
+-
+-static int mt798x_phy_hw_led_blink_set(struct phy_device *phydev, u8 index,
+- bool blinking)
+-{
+- unsigned int bit_blink = MTK_PHY_LED_STATE_FORCE_BLINK + (index ? 16 : 0);
+- struct mtk_socphy_priv *priv = phydev->priv;
+- bool changed;
+-
+- if (blinking)
+- changed = !test_and_set_bit(bit_blink, &priv->led_state);
+- else
+- changed = !!test_and_clear_bit(bit_blink, &priv->led_state);
+-
+- changed |= !!test_bit(MTK_PHY_LED_STATE_NETDEV +
+- (index ? 16 : 0), &priv->led_state);
+- if (changed)
+- return phy_write_mmd(phydev, MDIO_MMD_VEND2, index ?
+- MTK_PHY_LED1_BLINK_CTRL : MTK_PHY_LED0_BLINK_CTRL,
+- blinking ? MTK_PHY_LED_BLINK_FORCE_BLINK : 0);
+- else
+- return 0;
+-}
+-
+-static int mt798x_phy_led_blink_set(struct phy_device *phydev, u8 index,
+- unsigned long *delay_on,
+- unsigned long *delay_off)
+-{
+- bool blinking = false;
+- int err = 0;
+-
+- if (index > 1)
+- return -EINVAL;
+-
+- if (delay_on && delay_off && (*delay_on > 0) && (*delay_off > 0)) {
+- blinking = true;
+- *delay_on = 50;
+- *delay_off = 50;
+- }
+-
+- err = mt798x_phy_hw_led_blink_set(phydev, index, blinking);
+- if (err)
+- return err;
+-
+- return mt798x_phy_hw_led_on_set(phydev, index, false);
+-}
+-
+-static int mt798x_phy_led_brightness_set(struct phy_device *phydev,
+- u8 index, enum led_brightness value)
+-{
+- int err;
+-
+- err = mt798x_phy_hw_led_blink_set(phydev, index, false);
+- if (err)
+- return err;
+-
+- return mt798x_phy_hw_led_on_set(phydev, index, (value != LED_OFF));
+-}
+-
+-static const unsigned long supported_triggers = (BIT(TRIGGER_NETDEV_FULL_DUPLEX) |
+- BIT(TRIGGER_NETDEV_HALF_DUPLEX) |
+- BIT(TRIGGER_NETDEV_LINK) |
+- BIT(TRIGGER_NETDEV_LINK_10) |
+- BIT(TRIGGER_NETDEV_LINK_100) |
+- BIT(TRIGGER_NETDEV_LINK_1000) |
+- BIT(TRIGGER_NETDEV_RX) |
+- BIT(TRIGGER_NETDEV_TX));
+-
+-static int mt798x_phy_led_hw_is_supported(struct phy_device *phydev, u8 index,
+- unsigned long rules)
+-{
+- if (index > 1)
+- return -EINVAL;
+-
+- /* All combinations of the supported triggers are allowed */
+- if (rules & ~supported_triggers)
+- return -EOPNOTSUPP;
+-
+- return 0;
+-};
+-
+-static int mt798x_phy_led_hw_control_get(struct phy_device *phydev, u8 index,
+- unsigned long *rules)
+-{
+- unsigned int bit_blink = MTK_PHY_LED_STATE_FORCE_BLINK + (index ? 16 : 0);
+- unsigned int bit_netdev = MTK_PHY_LED_STATE_NETDEV + (index ? 16 : 0);
+- unsigned int bit_on = MTK_PHY_LED_STATE_FORCE_ON + (index ? 16 : 0);
+- struct mtk_socphy_priv *priv = phydev->priv;
+- int on, blink;
+-
+- if (index > 1)
+- return -EINVAL;
+-
+- on = phy_read_mmd(phydev, MDIO_MMD_VEND2,
+- index ? MTK_PHY_LED1_ON_CTRL : MTK_PHY_LED0_ON_CTRL);
+-
+- if (on < 0)
+- return -EIO;
+-
+- blink = phy_read_mmd(phydev, MDIO_MMD_VEND2,
+- index ? MTK_PHY_LED1_BLINK_CTRL :
+- MTK_PHY_LED0_BLINK_CTRL);
+- if (blink < 0)
+- return -EIO;
+-
+- if ((on & (MTK_PHY_LED_ON_LINK | MTK_PHY_LED_ON_FDX | MTK_PHY_LED_ON_HDX |
+- MTK_PHY_LED_ON_LINKDOWN)) ||
+- (blink & (MTK_PHY_LED_BLINK_RX | MTK_PHY_LED_BLINK_TX)))
+- set_bit(bit_netdev, &priv->led_state);
+- else
+- clear_bit(bit_netdev, &priv->led_state);
+-
+- if (on & MTK_PHY_LED_ON_FORCE_ON)
+- set_bit(bit_on, &priv->led_state);
+- else
+- clear_bit(bit_on, &priv->led_state);
+-
+- if (blink & MTK_PHY_LED_BLINK_FORCE_BLINK)
+- set_bit(bit_blink, &priv->led_state);
+- else
+- clear_bit(bit_blink, &priv->led_state);
+-
+- if (!rules)
+- return 0;
+-
+- if (on & MTK_PHY_LED_ON_LINK)
+- *rules |= BIT(TRIGGER_NETDEV_LINK);
+-
+- if (on & MTK_PHY_LED_ON_LINK10)
+- *rules |= BIT(TRIGGER_NETDEV_LINK_10);
+-
+- if (on & MTK_PHY_LED_ON_LINK100)
+- *rules |= BIT(TRIGGER_NETDEV_LINK_100);
+-
+- if (on & MTK_PHY_LED_ON_LINK1000)
+- *rules |= BIT(TRIGGER_NETDEV_LINK_1000);
+-
+- if (on & MTK_PHY_LED_ON_FDX)
+- *rules |= BIT(TRIGGER_NETDEV_FULL_DUPLEX);
+-
+- if (on & MTK_PHY_LED_ON_HDX)
+- *rules |= BIT(TRIGGER_NETDEV_HALF_DUPLEX);
+-
+- if (blink & MTK_PHY_LED_BLINK_RX)
+- *rules |= BIT(TRIGGER_NETDEV_RX);
+-
+- if (blink & MTK_PHY_LED_BLINK_TX)
+- *rules |= BIT(TRIGGER_NETDEV_TX);
+-
+- return 0;
+-};
+-
+-static int mt798x_phy_led_hw_control_set(struct phy_device *phydev, u8 index,
+- unsigned long rules)
+-{
+- unsigned int bit_netdev = MTK_PHY_LED_STATE_NETDEV + (index ? 16 : 0);
+- struct mtk_socphy_priv *priv = phydev->priv;
+- u16 on = 0, blink = 0;
+- int ret;
+-
+- if (index > 1)
+- return -EINVAL;
+-
+- if (rules & BIT(TRIGGER_NETDEV_FULL_DUPLEX))
+- on |= MTK_PHY_LED_ON_FDX;
+-
+- if (rules & BIT(TRIGGER_NETDEV_HALF_DUPLEX))
+- on |= MTK_PHY_LED_ON_HDX;
+-
+- if (rules & (BIT(TRIGGER_NETDEV_LINK_10) | BIT(TRIGGER_NETDEV_LINK)))
+- on |= MTK_PHY_LED_ON_LINK10;
+-
+- if (rules & (BIT(TRIGGER_NETDEV_LINK_100) | BIT(TRIGGER_NETDEV_LINK)))
+- on |= MTK_PHY_LED_ON_LINK100;
+-
+- if (rules & (BIT(TRIGGER_NETDEV_LINK_1000) | BIT(TRIGGER_NETDEV_LINK)))
+- on |= MTK_PHY_LED_ON_LINK1000;
+-
+- if (rules & BIT(TRIGGER_NETDEV_RX)) {
+- blink |= (on & MTK_PHY_LED_ON_LINK) ?
+- (((on & MTK_PHY_LED_ON_LINK10) ? MTK_PHY_LED_BLINK_10RX : 0) |
+- ((on & MTK_PHY_LED_ON_LINK100) ? MTK_PHY_LED_BLINK_100RX : 0) |
+- ((on & MTK_PHY_LED_ON_LINK1000) ? MTK_PHY_LED_BLINK_1000RX : 0)) :
+- MTK_PHY_LED_BLINK_RX;
+- }
+-
+- if (rules & BIT(TRIGGER_NETDEV_TX)) {
+- blink |= (on & MTK_PHY_LED_ON_LINK) ?
+- (((on & MTK_PHY_LED_ON_LINK10) ? MTK_PHY_LED_BLINK_10TX : 0) |
+- ((on & MTK_PHY_LED_ON_LINK100) ? MTK_PHY_LED_BLINK_100TX : 0) |
+- ((on & MTK_PHY_LED_ON_LINK1000) ? MTK_PHY_LED_BLINK_1000TX : 0)) :
+- MTK_PHY_LED_BLINK_TX;
+- }
+-
+- if (blink || on)
+- set_bit(bit_netdev, &priv->led_state);
+- else
+- clear_bit(bit_netdev, &priv->led_state);
+-
+- ret = phy_modify_mmd(phydev, MDIO_MMD_VEND2, index ?
+- MTK_PHY_LED1_ON_CTRL :
+- MTK_PHY_LED0_ON_CTRL,
+- MTK_PHY_LED_ON_FDX |
+- MTK_PHY_LED_ON_HDX |
+- MTK_PHY_LED_ON_LINK,
+- on);
+-
+- if (ret)
+- return ret;
+-
+- return phy_write_mmd(phydev, MDIO_MMD_VEND2, index ?
+- MTK_PHY_LED1_BLINK_CTRL :
+- MTK_PHY_LED0_BLINK_CTRL, blink);
+-};
+-
+-static bool mt7988_phy_led_get_polarity(struct phy_device *phydev, int led_num)
+-{
+- struct mtk_socphy_shared *priv = phydev->shared->priv;
+- u32 polarities;
+-
+- if (led_num == 0)
+- polarities = ~(priv->boottrap);
+- else
+- polarities = MTK_PHY_LED1_DEFAULT_POLARITIES;
+-
+- if (polarities & BIT(phydev->mdio.addr))
+- return true;
+-
+- return false;
+-}
+-
+-static int mt7988_phy_fix_leds_polarities(struct phy_device *phydev)
+-{
+- struct pinctrl *pinctrl;
+- int index;
+-
+- /* Setup LED polarity according to bootstrap use of LED pins */
+- for (index = 0; index < 2; ++index)
+- phy_modify_mmd(phydev, MDIO_MMD_VEND2, index ?
+- MTK_PHY_LED1_ON_CTRL : MTK_PHY_LED0_ON_CTRL,
+- MTK_PHY_LED_ON_POLARITY,
+- mt7988_phy_led_get_polarity(phydev, index) ?
+- MTK_PHY_LED_ON_POLARITY : 0);
+-
+- /* Only now setup pinctrl to avoid bogus blinking */
+- pinctrl = devm_pinctrl_get_select(&phydev->mdio.dev, "gbe-led");
+- if (IS_ERR(pinctrl))
+- dev_err(&phydev->mdio.bus->dev, "Failed to setup PHY LED pinctrl\n");
+-
+- return 0;
+-}
+-
+-static int mt7988_phy_probe_shared(struct phy_device *phydev)
+-{
+- struct device_node *np = dev_of_node(&phydev->mdio.bus->dev);
+- struct mtk_socphy_shared *shared = phydev->shared->priv;
+- struct regmap *regmap;
+- u32 reg;
+- int ret;
+-
+- /* The LED0 of the 4 PHYs in MT7988 are wired to SoC pins LED_A, LED_B,
+- * LED_C and LED_D respectively. At the same time those pins are used to
+- * bootstrap configuration of the reference clock source (LED_A),
+- * DRAM DDRx16b x2/x1 (LED_B) and boot device (LED_C, LED_D).
+- * In practise this is done using a LED and a resistor pulling the pin
+- * either to GND or to VIO.
+- * The detected value at boot time is accessible at run-time using the
+- * TPBANK0 register located in the gpio base of the pinctrl, in order
+- * to read it here it needs to be referenced by a phandle called
+- * 'mediatek,pio' in the MDIO bus hosting the PHY.
+- * The 4 bits in TPBANK0 are kept as package shared data and are used to
+- * set LED polarity for each of the LED0.
+- */
+- regmap = syscon_regmap_lookup_by_phandle(np, "mediatek,pio");
+- if (IS_ERR(regmap))
+- return PTR_ERR(regmap);
+-
+- ret = regmap_read(regmap, RG_GPIO_MISC_TPBANK0, ®);
+- if (ret)
+- return ret;
+-
+- shared->boottrap = FIELD_GET(RG_GPIO_MISC_TPBANK0_BOOTMODE, reg);
+-
+- return 0;
+-}
+-
+-static void mt798x_phy_leds_state_init(struct phy_device *phydev)
+-{
+- int i;
+-
+- for (i = 0; i < 2; ++i)
+- mt798x_phy_led_hw_control_get(phydev, i, NULL);
+-}
+-
+-static int mt7988_phy_probe(struct phy_device *phydev)
+-{
+- struct mtk_socphy_shared *shared;
+- struct mtk_socphy_priv *priv;
+- int err;
+-
+- if (phydev->mdio.addr > 3)
+- return -EINVAL;
+-
+- err = devm_phy_package_join(&phydev->mdio.dev, phydev, 0,
+- sizeof(struct mtk_socphy_shared));
+- if (err)
+- return err;
+-
+- if (phy_package_probe_once(phydev)) {
+- err = mt7988_phy_probe_shared(phydev);
+- if (err)
+- return err;
+- }
+-
+- shared = phydev->shared->priv;
+- priv = &shared->priv[phydev->mdio.addr];
+-
+- phydev->priv = priv;
+-
+- mt798x_phy_leds_state_init(phydev);
+-
+- err = mt7988_phy_fix_leds_polarities(phydev);
+- if (err)
+- return err;
+-
+- /* Disable TX power saving at probing to:
+- * 1. Meet common mode compliance test criteria
+- * 2. Make sure that TX-VCM calibration works fine
+- */
+- phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RXADC_CTRL_RG7,
+- MTK_PHY_DA_AD_BUF_BIAS_LP_MASK, 0x3 << 8);
+-
+- return mt798x_phy_calibration(phydev);
+-}
+-
+-static int mt7981_phy_probe(struct phy_device *phydev)
+-{
+- struct mtk_socphy_priv *priv;
+-
+- priv = devm_kzalloc(&phydev->mdio.dev, sizeof(struct mtk_socphy_priv),
+- GFP_KERNEL);
+- if (!priv)
+- return -ENOMEM;
+-
+- phydev->priv = priv;
+-
+- mt798x_phy_leds_state_init(phydev);
+-
+- return mt798x_phy_calibration(phydev);
+-}
+-
+-static struct phy_driver mtk_socphy_driver[] = {
+- {
+- PHY_ID_MATCH_EXACT(MTK_GPHY_ID_MT7981),
+- .name = "MediaTek MT7981 PHY",
+- .config_init = mt798x_phy_config_init,
+- .config_intr = genphy_no_config_intr,
+- .handle_interrupt = genphy_handle_interrupt_no_ack,
+- .probe = mt7981_phy_probe,
+- .suspend = genphy_suspend,
+- .resume = genphy_resume,
+- .read_page = mtk_socphy_read_page,
+- .write_page = mtk_socphy_write_page,
+- .led_blink_set = mt798x_phy_led_blink_set,
+- .led_brightness_set = mt798x_phy_led_brightness_set,
+- .led_hw_is_supported = mt798x_phy_led_hw_is_supported,
+- .led_hw_control_set = mt798x_phy_led_hw_control_set,
+- .led_hw_control_get = mt798x_phy_led_hw_control_get,
+- },
+- {
+- PHY_ID_MATCH_EXACT(MTK_GPHY_ID_MT7988),
+- .name = "MediaTek MT7988 PHY",
+- .config_init = mt798x_phy_config_init,
+- .config_intr = genphy_no_config_intr,
+- .handle_interrupt = genphy_handle_interrupt_no_ack,
+- .probe = mt7988_phy_probe,
+- .suspend = genphy_suspend,
+- .resume = genphy_resume,
+- .read_page = mtk_socphy_read_page,
+- .write_page = mtk_socphy_write_page,
+- .led_blink_set = mt798x_phy_led_blink_set,
+- .led_brightness_set = mt798x_phy_led_brightness_set,
+- .led_hw_is_supported = mt798x_phy_led_hw_is_supported,
+- .led_hw_control_set = mt798x_phy_led_hw_control_set,
+- .led_hw_control_get = mt798x_phy_led_hw_control_get,
+- },
+-};
+-
+-module_phy_driver(mtk_socphy_driver);
+-
+-static struct mdio_device_id __maybe_unused mtk_socphy_tbl[] = {
+- { PHY_ID_MATCH_EXACT(MTK_GPHY_ID_MT7981) },
+- { PHY_ID_MATCH_EXACT(MTK_GPHY_ID_MT7988) },
+- { }
+-};
+-
+-MODULE_DESCRIPTION("MediaTek SoC Gigabit Ethernet PHY driver");
+-MODULE_AUTHOR("Daniel Golle <daniel@makrotopia.org>");
+-MODULE_AUTHOR("SkyLake Huang <SkyLake.Huang@mediatek.com>");
+-MODULE_LICENSE("GPL");
+-
+-MODULE_DEVICE_TABLE(mdio, mtk_socphy_tbl);
+--- a/drivers/net/phy/mediatek-ge.c
++++ /dev/null
+@@ -1,148 +0,0 @@
+-// SPDX-License-Identifier: GPL-2.0+
+-#include <linux/of.h>
+-#include <linux/bitfield.h>
+-#include <linux/module.h>
+-#include <linux/phy.h>
+-
+-#define MTK_EXT_PAGE_ACCESS 0x1f
+-#define MTK_PHY_PAGE_STANDARD 0x0000
+-#define MTK_PHY_PAGE_EXTENDED 0x0001
+-#define MTK_PHY_PAGE_EXTENDED_2 0x0002
+-#define MTK_PHY_PAGE_EXTENDED_3 0x0003
+-#define MTK_PHY_PAGE_EXTENDED_2A30 0x2a30
+-#define MTK_PHY_PAGE_EXTENDED_52B5 0x52b5
+-
+-static int mtk_gephy_read_page(struct phy_device *phydev)
+-{
+- return __phy_read(phydev, MTK_EXT_PAGE_ACCESS);
+-}
+-
+-static int mtk_gephy_write_page(struct phy_device *phydev, int page)
+-{
+- return __phy_write(phydev, MTK_EXT_PAGE_ACCESS, page);
+-}
+-
+-static void mtk_gephy_config_init(struct phy_device *phydev)
+-{
+- /* Disable EEE */
+- phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_EEE_ADV, 0);
+-
+- /* Enable HW auto downshift */
+- phy_modify_paged(phydev, MTK_PHY_PAGE_EXTENDED, 0x14, 0, BIT(4));
+-
+- /* Increase SlvDPSready time */
+- phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_52B5);
+- __phy_write(phydev, 0x10, 0xafae);
+- __phy_write(phydev, 0x12, 0x2f);
+- __phy_write(phydev, 0x10, 0x8fae);
+- phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0);
+-
+- /* Adjust 100_mse_threshold */
+- phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x123, 0xffff);
+-
+- /* Disable mcc */
+- phy_write_mmd(phydev, MDIO_MMD_VEND1, 0xa6, 0x300);
+-}
+-
+-static int mt7530_phy_config_init(struct phy_device *phydev)
+-{
+- mtk_gephy_config_init(phydev);
+-
+- /* Increase post_update_timer */
+- phy_write_paged(phydev, MTK_PHY_PAGE_EXTENDED_3, 0x11, 0x4b);
+-
+- return 0;
+-}
+-
+-static int mt7530_led_config_of(struct phy_device *phydev)
+-{
+- struct device_node *np = phydev->mdio.dev.of_node;
+- const __be32 *paddr;
+- int len;
+- int i;
+-
+- paddr = of_get_property(np, "mediatek,led-config", &len);
+- if (!paddr)
+- return 0;
+-
+- if (len < (2 * sizeof(*paddr)))
+- return -EINVAL;
+-
+- len /= sizeof(*paddr);
+-
+- phydev_warn(phydev, "Configure LED registers (num=%d)\n", len);
+- for (i = 0; i < len - 1; i += 2) {
+- u32 reg;
+- u32 val;
+-
+- reg = be32_to_cpup(paddr + i);
+- val = be32_to_cpup(paddr + i + 1);
+-
+- phy_write_mmd(phydev, MDIO_MMD_VEND2, reg, val);
+- }
+-
+- return 0;
+-}
+-
+-static int mt7531_phy_config_init(struct phy_device *phydev)
+-{
+- mtk_gephy_config_init(phydev);
+-
+- /* PHY link down power saving enable */
+- phy_set_bits(phydev, 0x17, BIT(4));
+- phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, 0xc6, 0x300);
+-
+- /* Set TX Pair delay selection */
+- phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x13, 0x404);
+- phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x14, 0x404);
+-
+- /* LED Config*/
+- mt7530_led_config_of(phydev);
+-
+- return 0;
+-}
+-
+-static struct phy_driver mtk_gephy_driver[] = {
+- {
+- PHY_ID_MATCH_EXACT(0x03a29412),
+- .name = "MediaTek MT7530 PHY",
+- .config_init = mt7530_phy_config_init,
+- /* Interrupts are handled by the switch, not the PHY
+- * itself.
+- */
+- .config_intr = genphy_no_config_intr,
+- .handle_interrupt = genphy_handle_interrupt_no_ack,
+- .suspend = genphy_suspend,
+- .resume = genphy_resume,
+- .read_page = mtk_gephy_read_page,
+- .write_page = mtk_gephy_write_page,
+- },
+- {
+- PHY_ID_MATCH_EXACT(0x03a29441),
+- .name = "MediaTek MT7531 PHY",
+- .config_init = mt7531_phy_config_init,
+- /* Interrupts are handled by the switch, not the PHY
+- * itself.
+- */
+- .config_intr = genphy_no_config_intr,
+- .handle_interrupt = genphy_handle_interrupt_no_ack,
+- .suspend = genphy_suspend,
+- .resume = genphy_resume,
+- .read_page = mtk_gephy_read_page,
+- .write_page = mtk_gephy_write_page,
+- },
+-};
+-
+-module_phy_driver(mtk_gephy_driver);
+-
+-static struct mdio_device_id __maybe_unused mtk_gephy_tbl[] = {
+- { PHY_ID_MATCH_EXACT(0x03a29441) },
+- { PHY_ID_MATCH_EXACT(0x03a29412) },
+- { }
+-};
+-
+-MODULE_DESCRIPTION("MediaTek Gigabit Ethernet PHY driver");
+-MODULE_AUTHOR("DENG, Qingfang <dqfext@gmail.com>");
+-MODULE_LICENSE("GPL");
+-
+-MODULE_DEVICE_TABLE(mdio, mtk_gephy_tbl);
+--- /dev/null
++++ b/drivers/net/phy/mediatek/mtk-ge-soc.c
+@@ -0,0 +1,1555 @@
++// SPDX-License-Identifier: GPL-2.0+
++#include <linux/bitfield.h>
++#include <linux/bitmap.h>
++#include <linux/mfd/syscon.h>
++#include <linux/module.h>
++#include <linux/nvmem-consumer.h>
++#include <linux/pinctrl/consumer.h>
++#include <linux/phy.h>
++#include <linux/regmap.h>
++
++#define MTK_GPHY_ID_MT7981 0x03a29461
++#define MTK_GPHY_ID_MT7988 0x03a29481
++
++#define MTK_EXT_PAGE_ACCESS 0x1f
++#define MTK_PHY_PAGE_STANDARD 0x0000
++#define MTK_PHY_PAGE_EXTENDED_3 0x0003
++
++#define MTK_PHY_LPI_REG_14 0x14
++#define MTK_PHY_LPI_WAKE_TIMER_1000_MASK GENMASK(8, 0)
++
++#define MTK_PHY_LPI_REG_1c 0x1c
++#define MTK_PHY_SMI_DET_ON_THRESH_MASK GENMASK(13, 8)
++
++#define MTK_PHY_PAGE_EXTENDED_2A30 0x2a30
++#define MTK_PHY_PAGE_EXTENDED_52B5 0x52b5
++
++#define ANALOG_INTERNAL_OPERATION_MAX_US 20
++#define TXRESERVE_MIN 0
++#define TXRESERVE_MAX 7
++
++#define MTK_PHY_ANARG_RG 0x10
++#define MTK_PHY_TCLKOFFSET_MASK GENMASK(12, 8)
++
++/* Registers on MDIO_MMD_VEND1 */
++#define MTK_PHY_TXVLD_DA_RG 0x12
++#define MTK_PHY_DA_TX_I2MPB_A_GBE_MASK GENMASK(15, 10)
++#define MTK_PHY_DA_TX_I2MPB_A_TBT_MASK GENMASK(5, 0)
++
++#define MTK_PHY_TX_I2MPB_TEST_MODE_A2 0x16
++#define MTK_PHY_DA_TX_I2MPB_A_HBT_MASK GENMASK(15, 10)
++#define MTK_PHY_DA_TX_I2MPB_A_TST_MASK GENMASK(5, 0)
++
++#define MTK_PHY_TX_I2MPB_TEST_MODE_B1 0x17
++#define MTK_PHY_DA_TX_I2MPB_B_GBE_MASK GENMASK(13, 8)
++#define MTK_PHY_DA_TX_I2MPB_B_TBT_MASK GENMASK(5, 0)
++
++#define MTK_PHY_TX_I2MPB_TEST_MODE_B2 0x18
++#define MTK_PHY_DA_TX_I2MPB_B_HBT_MASK GENMASK(13, 8)
++#define MTK_PHY_DA_TX_I2MPB_B_TST_MASK GENMASK(5, 0)
++
++#define MTK_PHY_TX_I2MPB_TEST_MODE_C1 0x19
++#define MTK_PHY_DA_TX_I2MPB_C_GBE_MASK GENMASK(13, 8)
++#define MTK_PHY_DA_TX_I2MPB_C_TBT_MASK GENMASK(5, 0)
++
++#define MTK_PHY_TX_I2MPB_TEST_MODE_C2 0x20
++#define MTK_PHY_DA_TX_I2MPB_C_HBT_MASK GENMASK(13, 8)
++#define MTK_PHY_DA_TX_I2MPB_C_TST_MASK GENMASK(5, 0)
++
++#define MTK_PHY_TX_I2MPB_TEST_MODE_D1 0x21
++#define MTK_PHY_DA_TX_I2MPB_D_GBE_MASK GENMASK(13, 8)
++#define MTK_PHY_DA_TX_I2MPB_D_TBT_MASK GENMASK(5, 0)
++
++#define MTK_PHY_TX_I2MPB_TEST_MODE_D2 0x22
++#define MTK_PHY_DA_TX_I2MPB_D_HBT_MASK GENMASK(13, 8)
++#define MTK_PHY_DA_TX_I2MPB_D_TST_MASK GENMASK(5, 0)
++
++#define MTK_PHY_RXADC_CTRL_RG7 0xc6
++#define MTK_PHY_DA_AD_BUF_BIAS_LP_MASK GENMASK(9, 8)
++
++#define MTK_PHY_RXADC_CTRL_RG9 0xc8
++#define MTK_PHY_DA_RX_PSBN_TBT_MASK GENMASK(14, 12)
++#define MTK_PHY_DA_RX_PSBN_HBT_MASK GENMASK(10, 8)
++#define MTK_PHY_DA_RX_PSBN_GBE_MASK GENMASK(6, 4)
++#define MTK_PHY_DA_RX_PSBN_LP_MASK GENMASK(2, 0)
++
++#define MTK_PHY_LDO_OUTPUT_V 0xd7
++
++#define MTK_PHY_RG_ANA_CAL_RG0 0xdb
++#define MTK_PHY_RG_CAL_CKINV BIT(12)
++#define MTK_PHY_RG_ANA_CALEN BIT(8)
++#define MTK_PHY_RG_ZCALEN_A BIT(0)
++
++#define MTK_PHY_RG_ANA_CAL_RG1 0xdc
++#define MTK_PHY_RG_ZCALEN_B BIT(12)
++#define MTK_PHY_RG_ZCALEN_C BIT(8)
++#define MTK_PHY_RG_ZCALEN_D BIT(4)
++#define MTK_PHY_RG_TXVOS_CALEN BIT(0)
++
++#define MTK_PHY_RG_ANA_CAL_RG5 0xe0
++#define MTK_PHY_RG_REXT_TRIM_MASK GENMASK(13, 8)
++
++#define MTK_PHY_RG_TX_FILTER 0xfe
++
++#define MTK_PHY_RG_LPI_PCS_DSP_CTRL_REG120 0x120
++#define MTK_PHY_LPI_SIG_EN_LO_THRESH1000_MASK GENMASK(12, 8)
++#define MTK_PHY_LPI_SIG_EN_HI_THRESH1000_MASK GENMASK(4, 0)
++
++#define MTK_PHY_RG_LPI_PCS_DSP_CTRL_REG122 0x122
++#define MTK_PHY_LPI_NORM_MSE_HI_THRESH1000_MASK GENMASK(7, 0)
++
++#define MTK_PHY_RG_TESTMUX_ADC_CTRL 0x144
++#define MTK_PHY_RG_TXEN_DIG_MASK GENMASK(5, 5)
++
++#define MTK_PHY_RG_CR_TX_AMP_OFFSET_A_B 0x172
++#define MTK_PHY_CR_TX_AMP_OFFSET_A_MASK GENMASK(13, 8)
++#define MTK_PHY_CR_TX_AMP_OFFSET_B_MASK GENMASK(6, 0)
++
++#define MTK_PHY_RG_CR_TX_AMP_OFFSET_C_D 0x173
++#define MTK_PHY_CR_TX_AMP_OFFSET_C_MASK GENMASK(13, 8)
++#define MTK_PHY_CR_TX_AMP_OFFSET_D_MASK GENMASK(6, 0)
++
++#define MTK_PHY_RG_AD_CAL_COMP 0x17a
++#define MTK_PHY_AD_CAL_COMP_OUT_SHIFT (8)
++
++#define MTK_PHY_RG_AD_CAL_CLK 0x17b
++#define MTK_PHY_DA_CAL_CLK BIT(0)
++
++#define MTK_PHY_RG_AD_CALIN 0x17c
++#define MTK_PHY_DA_CALIN_FLAG BIT(0)
++
++#define MTK_PHY_RG_DASN_DAC_IN0_A 0x17d
++#define MTK_PHY_DASN_DAC_IN0_A_MASK GENMASK(9, 0)
++
++#define MTK_PHY_RG_DASN_DAC_IN0_B 0x17e
++#define MTK_PHY_DASN_DAC_IN0_B_MASK GENMASK(9, 0)
++
++#define MTK_PHY_RG_DASN_DAC_IN0_C 0x17f
++#define MTK_PHY_DASN_DAC_IN0_C_MASK GENMASK(9, 0)
++
++#define MTK_PHY_RG_DASN_DAC_IN0_D 0x180
++#define MTK_PHY_DASN_DAC_IN0_D_MASK GENMASK(9, 0)
++
++#define MTK_PHY_RG_DASN_DAC_IN1_A 0x181
++#define MTK_PHY_DASN_DAC_IN1_A_MASK GENMASK(9, 0)
++
++#define MTK_PHY_RG_DASN_DAC_IN1_B 0x182
++#define MTK_PHY_DASN_DAC_IN1_B_MASK GENMASK(9, 0)
++
++#define MTK_PHY_RG_DASN_DAC_IN1_C 0x183
++#define MTK_PHY_DASN_DAC_IN1_C_MASK GENMASK(9, 0)
++
++#define MTK_PHY_RG_DASN_DAC_IN1_D 0x184
++#define MTK_PHY_DASN_DAC_IN1_D_MASK GENMASK(9, 0)
++
++#define MTK_PHY_RG_DEV1E_REG19b 0x19b
++#define MTK_PHY_BYPASS_DSP_LPI_READY BIT(8)
++
++#define MTK_PHY_RG_LP_IIR2_K1_L 0x22a
++#define MTK_PHY_RG_LP_IIR2_K1_U 0x22b
++#define MTK_PHY_RG_LP_IIR2_K2_L 0x22c
++#define MTK_PHY_RG_LP_IIR2_K2_U 0x22d
++#define MTK_PHY_RG_LP_IIR2_K3_L 0x22e
++#define MTK_PHY_RG_LP_IIR2_K3_U 0x22f
++#define MTK_PHY_RG_LP_IIR2_K4_L 0x230
++#define MTK_PHY_RG_LP_IIR2_K4_U 0x231
++#define MTK_PHY_RG_LP_IIR2_K5_L 0x232
++#define MTK_PHY_RG_LP_IIR2_K5_U 0x233
++
++#define MTK_PHY_RG_DEV1E_REG234 0x234
++#define MTK_PHY_TR_OPEN_LOOP_EN_MASK GENMASK(0, 0)
++#define MTK_PHY_LPF_X_AVERAGE_MASK GENMASK(7, 4)
++#define MTK_PHY_TR_LP_IIR_EEE_EN BIT(12)
++
++#define MTK_PHY_RG_LPF_CNT_VAL 0x235
++
++#define MTK_PHY_RG_DEV1E_REG238 0x238
++#define MTK_PHY_LPI_SLV_SEND_TX_TIMER_MASK GENMASK(8, 0)
++#define MTK_PHY_LPI_SLV_SEND_TX_EN BIT(12)
++
++#define MTK_PHY_RG_DEV1E_REG239 0x239
++#define MTK_PHY_LPI_SEND_LOC_TIMER_MASK GENMASK(8, 0)
++#define MTK_PHY_LPI_TXPCS_LOC_RCV BIT(12)
++
++#define MTK_PHY_RG_DEV1E_REG27C 0x27c
++#define MTK_PHY_VGASTATE_FFE_THR_ST1_MASK GENMASK(12, 8)
++#define MTK_PHY_RG_DEV1E_REG27D 0x27d
++#define MTK_PHY_VGASTATE_FFE_THR_ST2_MASK GENMASK(4, 0)
++
++#define MTK_PHY_RG_DEV1E_REG2C7 0x2c7
++#define MTK_PHY_MAX_GAIN_MASK GENMASK(4, 0)
++#define MTK_PHY_MIN_GAIN_MASK GENMASK(12, 8)
++
++#define MTK_PHY_RG_DEV1E_REG2D1 0x2d1
++#define MTK_PHY_VCO_SLICER_THRESH_BITS_HIGH_EEE_MASK GENMASK(7, 0)
++#define MTK_PHY_LPI_SKIP_SD_SLV_TR BIT(8)
++#define MTK_PHY_LPI_TR_READY BIT(9)
++#define MTK_PHY_LPI_VCO_EEE_STG0_EN BIT(10)
++
++#define MTK_PHY_RG_DEV1E_REG323 0x323
++#define MTK_PHY_EEE_WAKE_MAS_INT_DC BIT(0)
++#define MTK_PHY_EEE_WAKE_SLV_INT_DC BIT(4)
++
++#define MTK_PHY_RG_DEV1E_REG324 0x324
++#define MTK_PHY_SMI_DETCNT_MAX_MASK GENMASK(5, 0)
++#define MTK_PHY_SMI_DET_MAX_EN BIT(8)
++
++#define MTK_PHY_RG_DEV1E_REG326 0x326
++#define MTK_PHY_LPI_MODE_SD_ON BIT(0)
++#define MTK_PHY_RESET_RANDUPD_CNT BIT(1)
++#define MTK_PHY_TREC_UPDATE_ENAB_CLR BIT(2)
++#define MTK_PHY_LPI_QUIT_WAIT_DFE_SIG_DET_OFF BIT(4)
++#define MTK_PHY_TR_READY_SKIP_AFE_WAKEUP BIT(5)
++
++#define MTK_PHY_LDO_PUMP_EN_PAIRAB 0x502
++#define MTK_PHY_LDO_PUMP_EN_PAIRCD 0x503
++
++#define MTK_PHY_DA_TX_R50_PAIR_A 0x53d
++#define MTK_PHY_DA_TX_R50_PAIR_B 0x53e
++#define MTK_PHY_DA_TX_R50_PAIR_C 0x53f
++#define MTK_PHY_DA_TX_R50_PAIR_D 0x540
++
++/* Registers on MDIO_MMD_VEND2 */
++#define MTK_PHY_LED0_ON_CTRL 0x24
++#define MTK_PHY_LED1_ON_CTRL 0x26
++#define MTK_PHY_LED_ON_MASK GENMASK(6, 0)
++#define MTK_PHY_LED_ON_LINK1000 BIT(0)
++#define MTK_PHY_LED_ON_LINK100 BIT(1)
++#define MTK_PHY_LED_ON_LINK10 BIT(2)
++#define MTK_PHY_LED_ON_LINK (MTK_PHY_LED_ON_LINK10 |\
++ MTK_PHY_LED_ON_LINK100 |\
++ MTK_PHY_LED_ON_LINK1000)
++#define MTK_PHY_LED_ON_LINKDOWN BIT(3)
++#define MTK_PHY_LED_ON_FDX BIT(4) /* Full duplex */
++#define MTK_PHY_LED_ON_HDX BIT(5) /* Half duplex */
++#define MTK_PHY_LED_ON_FORCE_ON BIT(6)
++#define MTK_PHY_LED_ON_POLARITY BIT(14)
++#define MTK_PHY_LED_ON_ENABLE BIT(15)
++
++#define MTK_PHY_LED0_BLINK_CTRL 0x25
++#define MTK_PHY_LED1_BLINK_CTRL 0x27
++#define MTK_PHY_LED_BLINK_1000TX BIT(0)
++#define MTK_PHY_LED_BLINK_1000RX BIT(1)
++#define MTK_PHY_LED_BLINK_100TX BIT(2)
++#define MTK_PHY_LED_BLINK_100RX BIT(3)
++#define MTK_PHY_LED_BLINK_10TX BIT(4)
++#define MTK_PHY_LED_BLINK_10RX BIT(5)
++#define MTK_PHY_LED_BLINK_RX (MTK_PHY_LED_BLINK_10RX |\
++ MTK_PHY_LED_BLINK_100RX |\
++ MTK_PHY_LED_BLINK_1000RX)
++#define MTK_PHY_LED_BLINK_TX (MTK_PHY_LED_BLINK_10TX |\
++ MTK_PHY_LED_BLINK_100TX |\
++ MTK_PHY_LED_BLINK_1000TX)
++#define MTK_PHY_LED_BLINK_COLLISION BIT(6)
++#define MTK_PHY_LED_BLINK_RX_CRC_ERR BIT(7)
++#define MTK_PHY_LED_BLINK_RX_IDLE_ERR BIT(8)
++#define MTK_PHY_LED_BLINK_FORCE_BLINK BIT(9)
++
++#define MTK_PHY_LED1_DEFAULT_POLARITIES BIT(1)
++
++#define MTK_PHY_RG_BG_RASEL 0x115
++#define MTK_PHY_RG_BG_RASEL_MASK GENMASK(2, 0)
++
++/* 'boottrap' register reflecting the configuration of the 4 PHY LEDs */
++#define RG_GPIO_MISC_TPBANK0 0x6f0
++#define RG_GPIO_MISC_TPBANK0_BOOTMODE GENMASK(11, 8)
++
++/* These macro privides efuse parsing for internal phy. */
++#define EFS_DA_TX_I2MPB_A(x) (((x) >> 0) & GENMASK(5, 0))
++#define EFS_DA_TX_I2MPB_B(x) (((x) >> 6) & GENMASK(5, 0))
++#define EFS_DA_TX_I2MPB_C(x) (((x) >> 12) & GENMASK(5, 0))
++#define EFS_DA_TX_I2MPB_D(x) (((x) >> 18) & GENMASK(5, 0))
++#define EFS_DA_TX_AMP_OFFSET_A(x) (((x) >> 24) & GENMASK(5, 0))
++
++#define EFS_DA_TX_AMP_OFFSET_B(x) (((x) >> 0) & GENMASK(5, 0))
++#define EFS_DA_TX_AMP_OFFSET_C(x) (((x) >> 6) & GENMASK(5, 0))
++#define EFS_DA_TX_AMP_OFFSET_D(x) (((x) >> 12) & GENMASK(5, 0))
++#define EFS_DA_TX_R50_A(x) (((x) >> 18) & GENMASK(5, 0))
++#define EFS_DA_TX_R50_B(x) (((x) >> 24) & GENMASK(5, 0))
++
++#define EFS_DA_TX_R50_C(x) (((x) >> 0) & GENMASK(5, 0))
++#define EFS_DA_TX_R50_D(x) (((x) >> 6) & GENMASK(5, 0))
++
++#define EFS_RG_BG_RASEL(x) (((x) >> 4) & GENMASK(2, 0))
++#define EFS_RG_REXT_TRIM(x) (((x) >> 7) & GENMASK(5, 0))
++
++enum {
++ NO_PAIR,
++ PAIR_A,
++ PAIR_B,
++ PAIR_C,
++ PAIR_D,
++};
++
++enum calibration_mode {
++ EFUSE_K,
++ SW_K
++};
++
++enum CAL_ITEM {
++ REXT,
++ TX_OFFSET,
++ TX_AMP,
++ TX_R50,
++ TX_VCM
++};
++
++enum CAL_MODE {
++ EFUSE_M,
++ SW_M
++};
++
++#define MTK_PHY_LED_STATE_FORCE_ON 0
++#define MTK_PHY_LED_STATE_FORCE_BLINK 1
++#define MTK_PHY_LED_STATE_NETDEV 2
++
++struct mtk_socphy_priv {
++ unsigned long led_state;
++};
++
++struct mtk_socphy_shared {
++ u32 boottrap;
++ struct mtk_socphy_priv priv[4];
++};
++
++static int mtk_socphy_read_page(struct phy_device *phydev)
++{
++ return __phy_read(phydev, MTK_EXT_PAGE_ACCESS);
++}
++
++static int mtk_socphy_write_page(struct phy_device *phydev, int page)
++{
++ return __phy_write(phydev, MTK_EXT_PAGE_ACCESS, page);
++}
++
++/* One calibration cycle consists of:
++ * 1.Set DA_CALIN_FLAG high to start calibration. Keep it high
++ * until AD_CAL_COMP is ready to output calibration result.
++ * 2.Wait until DA_CAL_CLK is available.
++ * 3.Fetch AD_CAL_COMP_OUT.
++ */
++static int cal_cycle(struct phy_device *phydev, int devad,
++ u32 regnum, u16 mask, u16 cal_val)
++{
++ int reg_val;
++ int ret;
++
++ phy_modify_mmd(phydev, devad, regnum,
++ mask, cal_val);
++ phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_AD_CALIN,
++ MTK_PHY_DA_CALIN_FLAG);
++
++ ret = phy_read_mmd_poll_timeout(phydev, MDIO_MMD_VEND1,
++ MTK_PHY_RG_AD_CAL_CLK, reg_val,
++ reg_val & MTK_PHY_DA_CAL_CLK, 500,
++ ANALOG_INTERNAL_OPERATION_MAX_US, false);
++ if (ret) {
++ phydev_err(phydev, "Calibration cycle timeout\n");
++ return ret;
++ }
++
++ phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_AD_CALIN,
++ MTK_PHY_DA_CALIN_FLAG);
++ ret = phy_read_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_AD_CAL_COMP) >>
++ MTK_PHY_AD_CAL_COMP_OUT_SHIFT;
++ phydev_dbg(phydev, "cal_val: 0x%x, ret: %d\n", cal_val, ret);
++
++ return ret;
++}
++
++static int rext_fill_result(struct phy_device *phydev, u16 *buf)
++{
++ phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG5,
++ MTK_PHY_RG_REXT_TRIM_MASK, buf[0] << 8);
++ phy_modify_mmd(phydev, MDIO_MMD_VEND2, MTK_PHY_RG_BG_RASEL,
++ MTK_PHY_RG_BG_RASEL_MASK, buf[1]);
++
++ return 0;
++}
++
++static int rext_cal_efuse(struct phy_device *phydev, u32 *buf)
++{
++ u16 rext_cal_val[2];
++
++ rext_cal_val[0] = EFS_RG_REXT_TRIM(buf[3]);
++ rext_cal_val[1] = EFS_RG_BG_RASEL(buf[3]);
++ rext_fill_result(phydev, rext_cal_val);
++
++ return 0;
++}
++
++static int tx_offset_fill_result(struct phy_device *phydev, u16 *buf)
++{
++ phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_CR_TX_AMP_OFFSET_A_B,
++ MTK_PHY_CR_TX_AMP_OFFSET_A_MASK, buf[0] << 8);
++ phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_CR_TX_AMP_OFFSET_A_B,
++ MTK_PHY_CR_TX_AMP_OFFSET_B_MASK, buf[1]);
++ phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_CR_TX_AMP_OFFSET_C_D,
++ MTK_PHY_CR_TX_AMP_OFFSET_C_MASK, buf[2] << 8);
++ phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_CR_TX_AMP_OFFSET_C_D,
++ MTK_PHY_CR_TX_AMP_OFFSET_D_MASK, buf[3]);
++
++ return 0;
++}
++
++static int tx_offset_cal_efuse(struct phy_device *phydev, u32 *buf)
++{
++ u16 tx_offset_cal_val[4];
++
++ tx_offset_cal_val[0] = EFS_DA_TX_AMP_OFFSET_A(buf[0]);
++ tx_offset_cal_val[1] = EFS_DA_TX_AMP_OFFSET_B(buf[1]);
++ tx_offset_cal_val[2] = EFS_DA_TX_AMP_OFFSET_C(buf[1]);
++ tx_offset_cal_val[3] = EFS_DA_TX_AMP_OFFSET_D(buf[1]);
++
++ tx_offset_fill_result(phydev, tx_offset_cal_val);
++
++ return 0;
++}
++
++static int tx_amp_fill_result(struct phy_device *phydev, u16 *buf)
++{
++ int i;
++ int bias[16] = {};
++ const int vals_9461[16] = { 7, 1, 4, 7,
++ 7, 1, 4, 7,
++ 7, 1, 4, 7,
++ 7, 1, 4, 7 };
++ const int vals_9481[16] = { 10, 6, 6, 10,
++ 10, 6, 6, 10,
++ 10, 6, 6, 10,
++ 10, 6, 6, 10 };
++ switch (phydev->drv->phy_id) {
++ case MTK_GPHY_ID_MT7981:
++ /* We add some calibration to efuse values
++ * due to board level influence.
++ * GBE: +7, TBT: +1, HBT: +4, TST: +7
++ */
++ memcpy(bias, (const void *)vals_9461, sizeof(bias));
++ break;
++ case MTK_GPHY_ID_MT7988:
++ memcpy(bias, (const void *)vals_9481, sizeof(bias));
++ break;
++ }
++
++ /* Prevent overflow */
++ for (i = 0; i < 12; i++) {
++ if (buf[i >> 2] + bias[i] > 63) {
++ buf[i >> 2] = 63;
++ bias[i] = 0;
++ }
++ }
++
++ phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TXVLD_DA_RG,
++ MTK_PHY_DA_TX_I2MPB_A_GBE_MASK, (buf[0] + bias[0]) << 10);
++ phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TXVLD_DA_RG,
++ MTK_PHY_DA_TX_I2MPB_A_TBT_MASK, buf[0] + bias[1]);
++ phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_A2,
++ MTK_PHY_DA_TX_I2MPB_A_HBT_MASK, (buf[0] + bias[2]) << 10);
++ phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_A2,
++ MTK_PHY_DA_TX_I2MPB_A_TST_MASK, buf[0] + bias[3]);
++
++ phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_B1,
++ MTK_PHY_DA_TX_I2MPB_B_GBE_MASK, (buf[1] + bias[4]) << 8);
++ phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_B1,
++ MTK_PHY_DA_TX_I2MPB_B_TBT_MASK, buf[1] + bias[5]);
++ phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_B2,
++ MTK_PHY_DA_TX_I2MPB_B_HBT_MASK, (buf[1] + bias[6]) << 8);
++ phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_B2,
++ MTK_PHY_DA_TX_I2MPB_B_TST_MASK, buf[1] + bias[7]);
++
++ phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_C1,
++ MTK_PHY_DA_TX_I2MPB_C_GBE_MASK, (buf[2] + bias[8]) << 8);
++ phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_C1,
++ MTK_PHY_DA_TX_I2MPB_C_TBT_MASK, buf[2] + bias[9]);
++ phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_C2,
++ MTK_PHY_DA_TX_I2MPB_C_HBT_MASK, (buf[2] + bias[10]) << 8);
++ phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_C2,
++ MTK_PHY_DA_TX_I2MPB_C_TST_MASK, buf[2] + bias[11]);
++
++ phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_D1,
++ MTK_PHY_DA_TX_I2MPB_D_GBE_MASK, (buf[3] + bias[12]) << 8);
++ phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_D1,
++ MTK_PHY_DA_TX_I2MPB_D_TBT_MASK, buf[3] + bias[13]);
++ phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_D2,
++ MTK_PHY_DA_TX_I2MPB_D_HBT_MASK, (buf[3] + bias[14]) << 8);
++ phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_D2,
++ MTK_PHY_DA_TX_I2MPB_D_TST_MASK, buf[3] + bias[15]);
++
++ return 0;
++}
++
++static int tx_amp_cal_efuse(struct phy_device *phydev, u32 *buf)
++{
++ u16 tx_amp_cal_val[4];
++
++ tx_amp_cal_val[0] = EFS_DA_TX_I2MPB_A(buf[0]);
++ tx_amp_cal_val[1] = EFS_DA_TX_I2MPB_B(buf[0]);
++ tx_amp_cal_val[2] = EFS_DA_TX_I2MPB_C(buf[0]);
++ tx_amp_cal_val[3] = EFS_DA_TX_I2MPB_D(buf[0]);
++ tx_amp_fill_result(phydev, tx_amp_cal_val);
++
++ return 0;
++}
++
++static int tx_r50_fill_result(struct phy_device *phydev, u16 tx_r50_cal_val,
++ u8 txg_calen_x)
++{
++ int bias = 0;
++ u16 reg, val;
++
++ if (phydev->drv->phy_id == MTK_GPHY_ID_MT7988)
++ bias = -1;
++
++ val = clamp_val(bias + tx_r50_cal_val, 0, 63);
++
++ switch (txg_calen_x) {
++ case PAIR_A:
++ reg = MTK_PHY_DA_TX_R50_PAIR_A;
++ break;
++ case PAIR_B:
++ reg = MTK_PHY_DA_TX_R50_PAIR_B;
++ break;
++ case PAIR_C:
++ reg = MTK_PHY_DA_TX_R50_PAIR_C;
++ break;
++ case PAIR_D:
++ reg = MTK_PHY_DA_TX_R50_PAIR_D;
++ break;
++ default:
++ return -EINVAL;
++ }
++
++ phy_write_mmd(phydev, MDIO_MMD_VEND1, reg, val | val << 8);
++
++ return 0;
++}
++
++static int tx_r50_cal_efuse(struct phy_device *phydev, u32 *buf,
++ u8 txg_calen_x)
++{
++ u16 tx_r50_cal_val;
++
++ switch (txg_calen_x) {
++ case PAIR_A:
++ tx_r50_cal_val = EFS_DA_TX_R50_A(buf[1]);
++ break;
++ case PAIR_B:
++ tx_r50_cal_val = EFS_DA_TX_R50_B(buf[1]);
++ break;
++ case PAIR_C:
++ tx_r50_cal_val = EFS_DA_TX_R50_C(buf[2]);
++ break;
++ case PAIR_D:
++ tx_r50_cal_val = EFS_DA_TX_R50_D(buf[2]);
++ break;
++ default:
++ return -EINVAL;
++ }
++ tx_r50_fill_result(phydev, tx_r50_cal_val, txg_calen_x);
++
++ return 0;
++}
++
++static int tx_vcm_cal_sw(struct phy_device *phydev, u8 rg_txreserve_x)
++{
++ u8 lower_idx, upper_idx, txreserve_val;
++ u8 lower_ret, upper_ret;
++ int ret;
++
++ phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG0,
++ MTK_PHY_RG_ANA_CALEN);
++ phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG0,
++ MTK_PHY_RG_CAL_CKINV);
++ phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG1,
++ MTK_PHY_RG_TXVOS_CALEN);
++
++ switch (rg_txreserve_x) {
++ case PAIR_A:
++ phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1,
++ MTK_PHY_RG_DASN_DAC_IN0_A,
++ MTK_PHY_DASN_DAC_IN0_A_MASK);
++ phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1,
++ MTK_PHY_RG_DASN_DAC_IN1_A,
++ MTK_PHY_DASN_DAC_IN1_A_MASK);
++ phy_set_bits_mmd(phydev, MDIO_MMD_VEND1,
++ MTK_PHY_RG_ANA_CAL_RG0,
++ MTK_PHY_RG_ZCALEN_A);
++ break;
++ case PAIR_B:
++ phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1,
++ MTK_PHY_RG_DASN_DAC_IN0_B,
++ MTK_PHY_DASN_DAC_IN0_B_MASK);
++ phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1,
++ MTK_PHY_RG_DASN_DAC_IN1_B,
++ MTK_PHY_DASN_DAC_IN1_B_MASK);
++ phy_set_bits_mmd(phydev, MDIO_MMD_VEND1,
++ MTK_PHY_RG_ANA_CAL_RG1,
++ MTK_PHY_RG_ZCALEN_B);
++ break;
++ case PAIR_C:
++ phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1,
++ MTK_PHY_RG_DASN_DAC_IN0_C,
++ MTK_PHY_DASN_DAC_IN0_C_MASK);
++ phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1,
++ MTK_PHY_RG_DASN_DAC_IN1_C,
++ MTK_PHY_DASN_DAC_IN1_C_MASK);
++ phy_set_bits_mmd(phydev, MDIO_MMD_VEND1,
++ MTK_PHY_RG_ANA_CAL_RG1,
++ MTK_PHY_RG_ZCALEN_C);
++ break;
++ case PAIR_D:
++ phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1,
++ MTK_PHY_RG_DASN_DAC_IN0_D,
++ MTK_PHY_DASN_DAC_IN0_D_MASK);
++ phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1,
++ MTK_PHY_RG_DASN_DAC_IN1_D,
++ MTK_PHY_DASN_DAC_IN1_D_MASK);
++ phy_set_bits_mmd(phydev, MDIO_MMD_VEND1,
++ MTK_PHY_RG_ANA_CAL_RG1,
++ MTK_PHY_RG_ZCALEN_D);
++ break;
++ default:
++ ret = -EINVAL;
++ goto restore;
++ }
++
++ lower_idx = TXRESERVE_MIN;
++ upper_idx = TXRESERVE_MAX;
++
++ phydev_dbg(phydev, "Start TX-VCM SW cal.\n");
++ while ((upper_idx - lower_idx) > 1) {
++ txreserve_val = DIV_ROUND_CLOSEST(lower_idx + upper_idx, 2);
++ ret = cal_cycle(phydev, MDIO_MMD_VEND1, MTK_PHY_RXADC_CTRL_RG9,
++ MTK_PHY_DA_RX_PSBN_TBT_MASK |
++ MTK_PHY_DA_RX_PSBN_HBT_MASK |
++ MTK_PHY_DA_RX_PSBN_GBE_MASK |
++ MTK_PHY_DA_RX_PSBN_LP_MASK,
++ txreserve_val << 12 | txreserve_val << 8 |
++ txreserve_val << 4 | txreserve_val);
++ if (ret == 1) {
++ upper_idx = txreserve_val;
++ upper_ret = ret;
++ } else if (ret == 0) {
++ lower_idx = txreserve_val;
++ lower_ret = ret;
++ } else {
++ goto restore;
++ }
++ }
++
++ if (lower_idx == TXRESERVE_MIN) {
++ lower_ret = cal_cycle(phydev, MDIO_MMD_VEND1,
++ MTK_PHY_RXADC_CTRL_RG9,
++ MTK_PHY_DA_RX_PSBN_TBT_MASK |
++ MTK_PHY_DA_RX_PSBN_HBT_MASK |
++ MTK_PHY_DA_RX_PSBN_GBE_MASK |
++ MTK_PHY_DA_RX_PSBN_LP_MASK,
++ lower_idx << 12 | lower_idx << 8 |
++ lower_idx << 4 | lower_idx);
++ ret = lower_ret;
++ } else if (upper_idx == TXRESERVE_MAX) {
++ upper_ret = cal_cycle(phydev, MDIO_MMD_VEND1,
++ MTK_PHY_RXADC_CTRL_RG9,
++ MTK_PHY_DA_RX_PSBN_TBT_MASK |
++ MTK_PHY_DA_RX_PSBN_HBT_MASK |
++ MTK_PHY_DA_RX_PSBN_GBE_MASK |
++ MTK_PHY_DA_RX_PSBN_LP_MASK,
++ upper_idx << 12 | upper_idx << 8 |
++ upper_idx << 4 | upper_idx);
++ ret = upper_ret;
++ }
++ if (ret < 0)
++ goto restore;
++
++ /* We calibrate TX-VCM in different logic. Check upper index and then
++ * lower index. If this calibration is valid, apply lower index's result.
++ */
++ ret = upper_ret - lower_ret;
++ if (ret == 1) {
++ ret = 0;
++ /* Make sure we use upper_idx in our calibration system */
++ cal_cycle(phydev, MDIO_MMD_VEND1, MTK_PHY_RXADC_CTRL_RG9,
++ MTK_PHY_DA_RX_PSBN_TBT_MASK |
++ MTK_PHY_DA_RX_PSBN_HBT_MASK |
++ MTK_PHY_DA_RX_PSBN_GBE_MASK |
++ MTK_PHY_DA_RX_PSBN_LP_MASK,
++ upper_idx << 12 | upper_idx << 8 |
++ upper_idx << 4 | upper_idx);
++ phydev_dbg(phydev, "TX-VCM SW cal result: 0x%x\n", upper_idx);
++ } else if (lower_idx == TXRESERVE_MIN && upper_ret == 1 &&
++ lower_ret == 1) {
++ ret = 0;
++ cal_cycle(phydev, MDIO_MMD_VEND1, MTK_PHY_RXADC_CTRL_RG9,
++ MTK_PHY_DA_RX_PSBN_TBT_MASK |
++ MTK_PHY_DA_RX_PSBN_HBT_MASK |
++ MTK_PHY_DA_RX_PSBN_GBE_MASK |
++ MTK_PHY_DA_RX_PSBN_LP_MASK,
++ lower_idx << 12 | lower_idx << 8 |
++ lower_idx << 4 | lower_idx);
++ phydev_warn(phydev, "TX-VCM SW cal result at low margin 0x%x\n",
++ lower_idx);
++ } else if (upper_idx == TXRESERVE_MAX && upper_ret == 0 &&
++ lower_ret == 0) {
++ ret = 0;
++ phydev_warn(phydev, "TX-VCM SW cal result at high margin 0x%x\n",
++ upper_idx);
++ } else {
++ ret = -EINVAL;
++ }
++
++restore:
++ phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG0,
++ MTK_PHY_RG_ANA_CALEN);
++ phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG1,
++ MTK_PHY_RG_TXVOS_CALEN);
++ phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG0,
++ MTK_PHY_RG_ZCALEN_A);
++ phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG1,
++ MTK_PHY_RG_ZCALEN_B | MTK_PHY_RG_ZCALEN_C |
++ MTK_PHY_RG_ZCALEN_D);
++
++ return ret;
++}
++
++static void mt798x_phy_common_finetune(struct phy_device *phydev)
++{
++ phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_52B5);
++ /* SlvDSPreadyTime = 24, MasDSPreadyTime = 24 */
++ __phy_write(phydev, 0x11, 0xc71);
++ __phy_write(phydev, 0x12, 0xc);
++ __phy_write(phydev, 0x10, 0x8fae);
++
++ /* EnabRandUpdTrig = 1 */
++ __phy_write(phydev, 0x11, 0x2f00);
++ __phy_write(phydev, 0x12, 0xe);
++ __phy_write(phydev, 0x10, 0x8fb0);
++
++ /* NormMseLoThresh = 85 */
++ __phy_write(phydev, 0x11, 0x55a0);
++ __phy_write(phydev, 0x12, 0x0);
++ __phy_write(phydev, 0x10, 0x83aa);
++
++ /* FfeUpdGainForce = 1(Enable), FfeUpdGainForceVal = 4 */
++ __phy_write(phydev, 0x11, 0x240);
++ __phy_write(phydev, 0x12, 0x0);
++ __phy_write(phydev, 0x10, 0x9680);
++
++ /* TrFreeze = 0 (mt7988 default) */
++ __phy_write(phydev, 0x11, 0x0);
++ __phy_write(phydev, 0x12, 0x0);
++ __phy_write(phydev, 0x10, 0x9686);
++
++ /* SSTrKp100 = 5 */
++ /* SSTrKf100 = 6 */
++ /* SSTrKp1000Mas = 5 */
++ /* SSTrKf1000Mas = 6 */
++ /* SSTrKp1000Slv = 5 */
++ /* SSTrKf1000Slv = 6 */
++ __phy_write(phydev, 0x11, 0xbaef);
++ __phy_write(phydev, 0x12, 0x2e);
++ __phy_write(phydev, 0x10, 0x968c);
++ phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0);
++}
++
++static void mt7981_phy_finetune(struct phy_device *phydev)
++{
++ u16 val[8] = { 0x01ce, 0x01c1,
++ 0x020f, 0x0202,
++ 0x03d0, 0x03c0,
++ 0x0013, 0x0005 };
++ int i, k;
++
++ /* 100M eye finetune:
++ * Keep middle level of TX MLT3 shapper as default.
++ * Only change TX MLT3 overshoot level here.
++ */
++ for (k = 0, i = 1; i < 12; i++) {
++ if (i % 3 == 0)
++ continue;
++ phy_write_mmd(phydev, MDIO_MMD_VEND1, i, val[k++]);
++ }
++
++ phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_52B5);
++ /* ResetSyncOffset = 6 */
++ __phy_write(phydev, 0x11, 0x600);
++ __phy_write(phydev, 0x12, 0x0);
++ __phy_write(phydev, 0x10, 0x8fc0);
++
++ /* VgaDecRate = 1 */
++ __phy_write(phydev, 0x11, 0x4c2a);
++ __phy_write(phydev, 0x12, 0x3e);
++ __phy_write(phydev, 0x10, 0x8fa4);
++
++ /* MrvlTrFix100Kp = 3, MrvlTrFix100Kf = 2,
++ * MrvlTrFix1000Kp = 3, MrvlTrFix1000Kf = 2
++ */
++ __phy_write(phydev, 0x11, 0xd10a);
++ __phy_write(phydev, 0x12, 0x34);
++ __phy_write(phydev, 0x10, 0x8f82);
++
++ /* VcoSlicerThreshBitsHigh */
++ __phy_write(phydev, 0x11, 0x5555);
++ __phy_write(phydev, 0x12, 0x55);
++ __phy_write(phydev, 0x10, 0x8ec0);
++ phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0);
++
++ /* TR_OPEN_LOOP_EN = 1, lpf_x_average = 9 */
++ phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG234,
++ MTK_PHY_TR_OPEN_LOOP_EN_MASK | MTK_PHY_LPF_X_AVERAGE_MASK,
++ BIT(0) | FIELD_PREP(MTK_PHY_LPF_X_AVERAGE_MASK, 0x9));
++
++ /* rg_tr_lpf_cnt_val = 512 */
++ phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LPF_CNT_VAL, 0x200);
++
++ /* IIR2 related */
++ phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K1_L, 0x82);
++ phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K1_U, 0x0);
++ phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K2_L, 0x103);
++ phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K2_U, 0x0);
++ phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K3_L, 0x82);
++ phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K3_U, 0x0);
++ phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K4_L, 0xd177);
++ phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K4_U, 0x3);
++ phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K5_L, 0x2c82);
++ phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K5_U, 0xe);
++
++ /* FFE peaking */
++ phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG27C,
++ MTK_PHY_VGASTATE_FFE_THR_ST1_MASK, 0x1b << 8);
++ phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG27D,
++ MTK_PHY_VGASTATE_FFE_THR_ST2_MASK, 0x1e);
++
++ /* Disable LDO pump */
++ phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_LDO_PUMP_EN_PAIRAB, 0x0);
++ phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_LDO_PUMP_EN_PAIRCD, 0x0);
++ /* Adjust LDO output voltage */
++ phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_LDO_OUTPUT_V, 0x2222);
++}
++
++static void mt7988_phy_finetune(struct phy_device *phydev)
++{
++ u16 val[12] = { 0x0187, 0x01cd, 0x01c8, 0x0182,
++ 0x020d, 0x0206, 0x0384, 0x03d0,
++ 0x03c6, 0x030a, 0x0011, 0x0005 };
++ int i;
++
++ /* Set default MLT3 shaper first */
++ for (i = 0; i < 12; i++)
++ phy_write_mmd(phydev, MDIO_MMD_VEND1, i, val[i]);
++
++ /* TCT finetune */
++ phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_TX_FILTER, 0x5);
++
++ phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_52B5);
++ /* ResetSyncOffset = 5 */
++ __phy_write(phydev, 0x11, 0x500);
++ __phy_write(phydev, 0x12, 0x0);
++ __phy_write(phydev, 0x10, 0x8fc0);
++
++ /* VgaDecRate is 1 at default on mt7988 */
++
++ /* MrvlTrFix100Kp = 6, MrvlTrFix100Kf = 7,
++ * MrvlTrFix1000Kp = 6, MrvlTrFix1000Kf = 7
++ */
++ __phy_write(phydev, 0x11, 0xb90a);
++ __phy_write(phydev, 0x12, 0x6f);
++ __phy_write(phydev, 0x10, 0x8f82);
++
++ /* RemAckCntLimitCtrl = 1 */
++ __phy_write(phydev, 0x11, 0xfbba);
++ __phy_write(phydev, 0x12, 0xc3);
++ __phy_write(phydev, 0x10, 0x87f8);
++
++ phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0);
++
++ /* TR_OPEN_LOOP_EN = 1, lpf_x_average = 10 */
++ phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG234,
++ MTK_PHY_TR_OPEN_LOOP_EN_MASK | MTK_PHY_LPF_X_AVERAGE_MASK,
++ BIT(0) | FIELD_PREP(MTK_PHY_LPF_X_AVERAGE_MASK, 0xa));
++
++ /* rg_tr_lpf_cnt_val = 1023 */
++ phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LPF_CNT_VAL, 0x3ff);
++}
++
++static void mt798x_phy_eee(struct phy_device *phydev)
++{
++ phy_modify_mmd(phydev, MDIO_MMD_VEND1,
++ MTK_PHY_RG_LPI_PCS_DSP_CTRL_REG120,
++ MTK_PHY_LPI_SIG_EN_LO_THRESH1000_MASK |
++ MTK_PHY_LPI_SIG_EN_HI_THRESH1000_MASK,
++ FIELD_PREP(MTK_PHY_LPI_SIG_EN_LO_THRESH1000_MASK, 0x0) |
++ FIELD_PREP(MTK_PHY_LPI_SIG_EN_HI_THRESH1000_MASK, 0x14));
++
++ phy_modify_mmd(phydev, MDIO_MMD_VEND1,
++ MTK_PHY_RG_LPI_PCS_DSP_CTRL_REG122,
++ MTK_PHY_LPI_NORM_MSE_HI_THRESH1000_MASK,
++ FIELD_PREP(MTK_PHY_LPI_NORM_MSE_HI_THRESH1000_MASK,
++ 0xff));
++
++ phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1,
++ MTK_PHY_RG_TESTMUX_ADC_CTRL,
++ MTK_PHY_RG_TXEN_DIG_MASK);
++
++ phy_set_bits_mmd(phydev, MDIO_MMD_VEND1,
++ MTK_PHY_RG_DEV1E_REG19b, MTK_PHY_BYPASS_DSP_LPI_READY);
++
++ phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1,
++ MTK_PHY_RG_DEV1E_REG234, MTK_PHY_TR_LP_IIR_EEE_EN);
++
++ phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG238,
++ MTK_PHY_LPI_SLV_SEND_TX_TIMER_MASK |
++ MTK_PHY_LPI_SLV_SEND_TX_EN,
++ FIELD_PREP(MTK_PHY_LPI_SLV_SEND_TX_TIMER_MASK, 0x120));
++
++ /* Keep MTK_PHY_LPI_SEND_LOC_TIMER as 375 */
++ phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG239,
++ MTK_PHY_LPI_TXPCS_LOC_RCV);
++
++ /* This also fixes some IoT issues, such as CH340 */
++ phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG2C7,
++ MTK_PHY_MAX_GAIN_MASK | MTK_PHY_MIN_GAIN_MASK,
++ FIELD_PREP(MTK_PHY_MAX_GAIN_MASK, 0x8) |
++ FIELD_PREP(MTK_PHY_MIN_GAIN_MASK, 0x13));
++
++ phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG2D1,
++ MTK_PHY_VCO_SLICER_THRESH_BITS_HIGH_EEE_MASK,
++ FIELD_PREP(MTK_PHY_VCO_SLICER_THRESH_BITS_HIGH_EEE_MASK,
++ 0x33) |
++ MTK_PHY_LPI_SKIP_SD_SLV_TR | MTK_PHY_LPI_TR_READY |
++ MTK_PHY_LPI_VCO_EEE_STG0_EN);
++
++ phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG323,
++ MTK_PHY_EEE_WAKE_MAS_INT_DC |
++ MTK_PHY_EEE_WAKE_SLV_INT_DC);
++
++ phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG324,
++ MTK_PHY_SMI_DETCNT_MAX_MASK,
++ FIELD_PREP(MTK_PHY_SMI_DETCNT_MAX_MASK, 0x3f) |
++ MTK_PHY_SMI_DET_MAX_EN);
++
++ phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG326,
++ MTK_PHY_LPI_MODE_SD_ON | MTK_PHY_RESET_RANDUPD_CNT |
++ MTK_PHY_TREC_UPDATE_ENAB_CLR |
++ MTK_PHY_LPI_QUIT_WAIT_DFE_SIG_DET_OFF |
++ MTK_PHY_TR_READY_SKIP_AFE_WAKEUP);
++
++ phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_52B5);
++ /* Regsigdet_sel_1000 = 0 */
++ __phy_write(phydev, 0x11, 0xb);
++ __phy_write(phydev, 0x12, 0x0);
++ __phy_write(phydev, 0x10, 0x9690);
++
++ /* REG_EEE_st2TrKf1000 = 2 */
++ __phy_write(phydev, 0x11, 0x114f);
++ __phy_write(phydev, 0x12, 0x2);
++ __phy_write(phydev, 0x10, 0x969a);
++
++ /* RegEEE_slv_wake_tr_timer_tar = 6, RegEEE_slv_remtx_timer_tar = 20 */
++ __phy_write(phydev, 0x11, 0x3028);
++ __phy_write(phydev, 0x12, 0x0);
++ __phy_write(phydev, 0x10, 0x969e);
++
++ /* RegEEE_slv_wake_int_timer_tar = 8 */
++ __phy_write(phydev, 0x11, 0x5010);
++ __phy_write(phydev, 0x12, 0x0);
++ __phy_write(phydev, 0x10, 0x96a0);
++
++ /* RegEEE_trfreeze_timer2 = 586 */
++ __phy_write(phydev, 0x11, 0x24a);
++ __phy_write(phydev, 0x12, 0x0);
++ __phy_write(phydev, 0x10, 0x96a8);
++
++ /* RegEEE100Stg1_tar = 16 */
++ __phy_write(phydev, 0x11, 0x3210);
++ __phy_write(phydev, 0x12, 0x0);
++ __phy_write(phydev, 0x10, 0x96b8);
++
++ /* REGEEE_wake_slv_tr_wait_dfesigdet_en = 0 */
++ __phy_write(phydev, 0x11, 0x1463);
++ __phy_write(phydev, 0x12, 0x0);
++ __phy_write(phydev, 0x10, 0x96ca);
++
++ /* DfeTailEnableVgaThresh1000 = 27 */
++ __phy_write(phydev, 0x11, 0x36);
++ __phy_write(phydev, 0x12, 0x0);
++ __phy_write(phydev, 0x10, 0x8f80);
++ phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0);
++
++ phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_3);
++ __phy_modify(phydev, MTK_PHY_LPI_REG_14, MTK_PHY_LPI_WAKE_TIMER_1000_MASK,
++ FIELD_PREP(MTK_PHY_LPI_WAKE_TIMER_1000_MASK, 0x19c));
++
++ __phy_modify(phydev, MTK_PHY_LPI_REG_1c, MTK_PHY_SMI_DET_ON_THRESH_MASK,
++ FIELD_PREP(MTK_PHY_SMI_DET_ON_THRESH_MASK, 0xc));
++ phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0);
++
++ phy_modify_mmd(phydev, MDIO_MMD_VEND1,
++ MTK_PHY_RG_LPI_PCS_DSP_CTRL_REG122,
++ MTK_PHY_LPI_NORM_MSE_HI_THRESH1000_MASK,
++ FIELD_PREP(MTK_PHY_LPI_NORM_MSE_HI_THRESH1000_MASK, 0xff));
++}
++
++static int cal_sw(struct phy_device *phydev, enum CAL_ITEM cal_item,
++ u8 start_pair, u8 end_pair)
++{
++ u8 pair_n;
++ int ret;
++
++ for (pair_n = start_pair; pair_n <= end_pair; pair_n++) {
++ /* TX_OFFSET & TX_AMP have no SW calibration. */
++ switch (cal_item) {
++ case TX_VCM:
++ ret = tx_vcm_cal_sw(phydev, pair_n);
++ break;
++ default:
++ return -EINVAL;
++ }
++ if (ret)
++ return ret;
++ }
++ return 0;
++}
++
++static int cal_efuse(struct phy_device *phydev, enum CAL_ITEM cal_item,
++ u8 start_pair, u8 end_pair, u32 *buf)
++{
++ u8 pair_n;
++ int ret;
++
++ for (pair_n = start_pair; pair_n <= end_pair; pair_n++) {
++ /* TX_VCM has no efuse calibration. */
++ switch (cal_item) {
++ case REXT:
++ ret = rext_cal_efuse(phydev, buf);
++ break;
++ case TX_OFFSET:
++ ret = tx_offset_cal_efuse(phydev, buf);
++ break;
++ case TX_AMP:
++ ret = tx_amp_cal_efuse(phydev, buf);
++ break;
++ case TX_R50:
++ ret = tx_r50_cal_efuse(phydev, buf, pair_n);
++ break;
++ default:
++ return -EINVAL;
++ }
++ if (ret)
++ return ret;
++ }
++
++ return 0;
++}
++
++static int start_cal(struct phy_device *phydev, enum CAL_ITEM cal_item,
++ enum CAL_MODE cal_mode, u8 start_pair,
++ u8 end_pair, u32 *buf)
++{
++ int ret;
++
++ switch (cal_mode) {
++ case EFUSE_M:
++ ret = cal_efuse(phydev, cal_item, start_pair,
++ end_pair, buf);
++ break;
++ case SW_M:
++ ret = cal_sw(phydev, cal_item, start_pair, end_pair);
++ break;
++ default:
++ return -EINVAL;
++ }
++
++ if (ret) {
++ phydev_err(phydev, "cal %d failed\n", cal_item);
++ return -EIO;
++ }
++
++ return 0;
++}
++
++static int mt798x_phy_calibration(struct phy_device *phydev)
++{
++ int ret = 0;
++ u32 *buf;
++ size_t len;
++ struct nvmem_cell *cell;
++
++ cell = nvmem_cell_get(&phydev->mdio.dev, "phy-cal-data");
++ if (IS_ERR(cell)) {
++ if (PTR_ERR(cell) == -EPROBE_DEFER)
++ return PTR_ERR(cell);
++ return 0;
++ }
++
++ buf = (u32 *)nvmem_cell_read(cell, &len);
++ if (IS_ERR(buf))
++ return PTR_ERR(buf);
++ nvmem_cell_put(cell);
++
++ if (!buf[0] || !buf[1] || !buf[2] || !buf[3] || len < 4 * sizeof(u32)) {
++ phydev_err(phydev, "invalid efuse data\n");
++ ret = -EINVAL;
++ goto out;
++ }
++
++ ret = start_cal(phydev, REXT, EFUSE_M, NO_PAIR, NO_PAIR, buf);
++ if (ret)
++ goto out;
++ ret = start_cal(phydev, TX_OFFSET, EFUSE_M, NO_PAIR, NO_PAIR, buf);
++ if (ret)
++ goto out;
++ ret = start_cal(phydev, TX_AMP, EFUSE_M, NO_PAIR, NO_PAIR, buf);
++ if (ret)
++ goto out;
++ ret = start_cal(phydev, TX_R50, EFUSE_M, PAIR_A, PAIR_D, buf);
++ if (ret)
++ goto out;
++ ret = start_cal(phydev, TX_VCM, SW_M, PAIR_A, PAIR_A, buf);
++ if (ret)
++ goto out;
++
++out:
++ kfree(buf);
++ return ret;
++}
++
++static int mt798x_phy_config_init(struct phy_device *phydev)
++{
++ switch (phydev->drv->phy_id) {
++ case MTK_GPHY_ID_MT7981:
++ mt7981_phy_finetune(phydev);
++ break;
++ case MTK_GPHY_ID_MT7988:
++ mt7988_phy_finetune(phydev);
++ break;
++ }
++
++ mt798x_phy_common_finetune(phydev);
++ mt798x_phy_eee(phydev);
++
++ return mt798x_phy_calibration(phydev);
++}
++
++static int mt798x_phy_hw_led_on_set(struct phy_device *phydev, u8 index,
++ bool on)
++{
++ unsigned int bit_on = MTK_PHY_LED_STATE_FORCE_ON + (index ? 16 : 0);
++ struct mtk_socphy_priv *priv = phydev->priv;
++ bool changed;
++
++ if (on)
++ changed = !test_and_set_bit(bit_on, &priv->led_state);
++ else
++ changed = !!test_and_clear_bit(bit_on, &priv->led_state);
++
++ changed |= !!test_and_clear_bit(MTK_PHY_LED_STATE_NETDEV +
++ (index ? 16 : 0), &priv->led_state);
++ if (changed)
++ return phy_modify_mmd(phydev, MDIO_MMD_VEND2, index ?
++ MTK_PHY_LED1_ON_CTRL : MTK_PHY_LED0_ON_CTRL,
++ MTK_PHY_LED_ON_MASK,
++ on ? MTK_PHY_LED_ON_FORCE_ON : 0);
++ else
++ return 0;
++}
++
++static int mt798x_phy_hw_led_blink_set(struct phy_device *phydev, u8 index,
++ bool blinking)
++{
++ unsigned int bit_blink = MTK_PHY_LED_STATE_FORCE_BLINK + (index ? 16 : 0);
++ struct mtk_socphy_priv *priv = phydev->priv;
++ bool changed;
++
++ if (blinking)
++ changed = !test_and_set_bit(bit_blink, &priv->led_state);
++ else
++ changed = !!test_and_clear_bit(bit_blink, &priv->led_state);
++
++ changed |= !!test_bit(MTK_PHY_LED_STATE_NETDEV +
++ (index ? 16 : 0), &priv->led_state);
++ if (changed)
++ return phy_write_mmd(phydev, MDIO_MMD_VEND2, index ?
++ MTK_PHY_LED1_BLINK_CTRL : MTK_PHY_LED0_BLINK_CTRL,
++ blinking ? MTK_PHY_LED_BLINK_FORCE_BLINK : 0);
++ else
++ return 0;
++}
++
++static int mt798x_phy_led_blink_set(struct phy_device *phydev, u8 index,
++ unsigned long *delay_on,
++ unsigned long *delay_off)
++{
++ bool blinking = false;
++ int err = 0;
++
++ if (index > 1)
++ return -EINVAL;
++
++ if (delay_on && delay_off && (*delay_on > 0) && (*delay_off > 0)) {
++ blinking = true;
++ *delay_on = 50;
++ *delay_off = 50;
++ }
++
++ err = mt798x_phy_hw_led_blink_set(phydev, index, blinking);
++ if (err)
++ return err;
++
++ return mt798x_phy_hw_led_on_set(phydev, index, false);
++}
++
++static int mt798x_phy_led_brightness_set(struct phy_device *phydev,
++ u8 index, enum led_brightness value)
++{
++ int err;
++
++ err = mt798x_phy_hw_led_blink_set(phydev, index, false);
++ if (err)
++ return err;
++
++ return mt798x_phy_hw_led_on_set(phydev, index, (value != LED_OFF));
++}
++
++static const unsigned long supported_triggers = (BIT(TRIGGER_NETDEV_FULL_DUPLEX) |
++ BIT(TRIGGER_NETDEV_HALF_DUPLEX) |
++ BIT(TRIGGER_NETDEV_LINK) |
++ BIT(TRIGGER_NETDEV_LINK_10) |
++ BIT(TRIGGER_NETDEV_LINK_100) |
++ BIT(TRIGGER_NETDEV_LINK_1000) |
++ BIT(TRIGGER_NETDEV_RX) |
++ BIT(TRIGGER_NETDEV_TX));
++
++static int mt798x_phy_led_hw_is_supported(struct phy_device *phydev, u8 index,
++ unsigned long rules)
++{
++ if (index > 1)
++ return -EINVAL;
++
++ /* All combinations of the supported triggers are allowed */
++ if (rules & ~supported_triggers)
++ return -EOPNOTSUPP;
++
++ return 0;
++};
++
++static int mt798x_phy_led_hw_control_get(struct phy_device *phydev, u8 index,
++ unsigned long *rules)
++{
++ unsigned int bit_blink = MTK_PHY_LED_STATE_FORCE_BLINK + (index ? 16 : 0);
++ unsigned int bit_netdev = MTK_PHY_LED_STATE_NETDEV + (index ? 16 : 0);
++ unsigned int bit_on = MTK_PHY_LED_STATE_FORCE_ON + (index ? 16 : 0);
++ struct mtk_socphy_priv *priv = phydev->priv;
++ int on, blink;
++
++ if (index > 1)
++ return -EINVAL;
++
++ on = phy_read_mmd(phydev, MDIO_MMD_VEND2,
++ index ? MTK_PHY_LED1_ON_CTRL : MTK_PHY_LED0_ON_CTRL);
++
++ if (on < 0)
++ return -EIO;
++
++ blink = phy_read_mmd(phydev, MDIO_MMD_VEND2,
++ index ? MTK_PHY_LED1_BLINK_CTRL :
++ MTK_PHY_LED0_BLINK_CTRL);
++ if (blink < 0)
++ return -EIO;
++
++ if ((on & (MTK_PHY_LED_ON_LINK | MTK_PHY_LED_ON_FDX | MTK_PHY_LED_ON_HDX |
++ MTK_PHY_LED_ON_LINKDOWN)) ||
++ (blink & (MTK_PHY_LED_BLINK_RX | MTK_PHY_LED_BLINK_TX)))
++ set_bit(bit_netdev, &priv->led_state);
++ else
++ clear_bit(bit_netdev, &priv->led_state);
++
++ if (on & MTK_PHY_LED_ON_FORCE_ON)
++ set_bit(bit_on, &priv->led_state);
++ else
++ clear_bit(bit_on, &priv->led_state);
++
++ if (blink & MTK_PHY_LED_BLINK_FORCE_BLINK)
++ set_bit(bit_blink, &priv->led_state);
++ else
++ clear_bit(bit_blink, &priv->led_state);
++
++ if (!rules)
++ return 0;
++
++ if (on & MTK_PHY_LED_ON_LINK)
++ *rules |= BIT(TRIGGER_NETDEV_LINK);
++
++ if (on & MTK_PHY_LED_ON_LINK10)
++ *rules |= BIT(TRIGGER_NETDEV_LINK_10);
++
++ if (on & MTK_PHY_LED_ON_LINK100)
++ *rules |= BIT(TRIGGER_NETDEV_LINK_100);
++
++ if (on & MTK_PHY_LED_ON_LINK1000)
++ *rules |= BIT(TRIGGER_NETDEV_LINK_1000);
++
++ if (on & MTK_PHY_LED_ON_FDX)
++ *rules |= BIT(TRIGGER_NETDEV_FULL_DUPLEX);
++
++ if (on & MTK_PHY_LED_ON_HDX)
++ *rules |= BIT(TRIGGER_NETDEV_HALF_DUPLEX);
++
++ if (blink & MTK_PHY_LED_BLINK_RX)
++ *rules |= BIT(TRIGGER_NETDEV_RX);
++
++ if (blink & MTK_PHY_LED_BLINK_TX)
++ *rules |= BIT(TRIGGER_NETDEV_TX);
++
++ return 0;
++};
++
++static int mt798x_phy_led_hw_control_set(struct phy_device *phydev, u8 index,
++ unsigned long rules)
++{
++ unsigned int bit_netdev = MTK_PHY_LED_STATE_NETDEV + (index ? 16 : 0);
++ struct mtk_socphy_priv *priv = phydev->priv;
++ u16 on = 0, blink = 0;
++ int ret;
++
++ if (index > 1)
++ return -EINVAL;
++
++ if (rules & BIT(TRIGGER_NETDEV_FULL_DUPLEX))
++ on |= MTK_PHY_LED_ON_FDX;
++
++ if (rules & BIT(TRIGGER_NETDEV_HALF_DUPLEX))
++ on |= MTK_PHY_LED_ON_HDX;
++
++ if (rules & (BIT(TRIGGER_NETDEV_LINK_10) | BIT(TRIGGER_NETDEV_LINK)))
++ on |= MTK_PHY_LED_ON_LINK10;
++
++ if (rules & (BIT(TRIGGER_NETDEV_LINK_100) | BIT(TRIGGER_NETDEV_LINK)))
++ on |= MTK_PHY_LED_ON_LINK100;
++
++ if (rules & (BIT(TRIGGER_NETDEV_LINK_1000) | BIT(TRIGGER_NETDEV_LINK)))
++ on |= MTK_PHY_LED_ON_LINK1000;
++
++ if (rules & BIT(TRIGGER_NETDEV_RX)) {
++ blink |= (on & MTK_PHY_LED_ON_LINK) ?
++ (((on & MTK_PHY_LED_ON_LINK10) ? MTK_PHY_LED_BLINK_10RX : 0) |
++ ((on & MTK_PHY_LED_ON_LINK100) ? MTK_PHY_LED_BLINK_100RX : 0) |
++ ((on & MTK_PHY_LED_ON_LINK1000) ? MTK_PHY_LED_BLINK_1000RX : 0)) :
++ MTK_PHY_LED_BLINK_RX;
++ }
++
++ if (rules & BIT(TRIGGER_NETDEV_TX)) {
++ blink |= (on & MTK_PHY_LED_ON_LINK) ?
++ (((on & MTK_PHY_LED_ON_LINK10) ? MTK_PHY_LED_BLINK_10TX : 0) |
++ ((on & MTK_PHY_LED_ON_LINK100) ? MTK_PHY_LED_BLINK_100TX : 0) |
++ ((on & MTK_PHY_LED_ON_LINK1000) ? MTK_PHY_LED_BLINK_1000TX : 0)) :
++ MTK_PHY_LED_BLINK_TX;
++ }
++
++ if (blink || on)
++ set_bit(bit_netdev, &priv->led_state);
++ else
++ clear_bit(bit_netdev, &priv->led_state);
++
++ ret = phy_modify_mmd(phydev, MDIO_MMD_VEND2, index ?
++ MTK_PHY_LED1_ON_CTRL :
++ MTK_PHY_LED0_ON_CTRL,
++ MTK_PHY_LED_ON_FDX |
++ MTK_PHY_LED_ON_HDX |
++ MTK_PHY_LED_ON_LINK,
++ on);
++
++ if (ret)
++ return ret;
++
++ return phy_write_mmd(phydev, MDIO_MMD_VEND2, index ?
++ MTK_PHY_LED1_BLINK_CTRL :
++ MTK_PHY_LED0_BLINK_CTRL, blink);
++};
++
++static bool mt7988_phy_led_get_polarity(struct phy_device *phydev, int led_num)
++{
++ struct mtk_socphy_shared *priv = phydev->shared->priv;
++ u32 polarities;
++
++ if (led_num == 0)
++ polarities = ~(priv->boottrap);
++ else
++ polarities = MTK_PHY_LED1_DEFAULT_POLARITIES;
++
++ if (polarities & BIT(phydev->mdio.addr))
++ return true;
++
++ return false;
++}
++
++static int mt7988_phy_fix_leds_polarities(struct phy_device *phydev)
++{
++ struct pinctrl *pinctrl;
++ int index;
++
++ /* Setup LED polarity according to bootstrap use of LED pins */
++ for (index = 0; index < 2; ++index)
++ phy_modify_mmd(phydev, MDIO_MMD_VEND2, index ?
++ MTK_PHY_LED1_ON_CTRL : MTK_PHY_LED0_ON_CTRL,
++ MTK_PHY_LED_ON_POLARITY,
++ mt7988_phy_led_get_polarity(phydev, index) ?
++ MTK_PHY_LED_ON_POLARITY : 0);
++
++ /* Only now setup pinctrl to avoid bogus blinking */
++ pinctrl = devm_pinctrl_get_select(&phydev->mdio.dev, "gbe-led");
++ if (IS_ERR(pinctrl))
++ dev_err(&phydev->mdio.bus->dev, "Failed to setup PHY LED pinctrl\n");
++
++ return 0;
++}
++
++static int mt7988_phy_probe_shared(struct phy_device *phydev)
++{
++ struct device_node *np = dev_of_node(&phydev->mdio.bus->dev);
++ struct mtk_socphy_shared *shared = phydev->shared->priv;
++ struct regmap *regmap;
++ u32 reg;
++ int ret;
++
++ /* The LED0 of the 4 PHYs in MT7988 are wired to SoC pins LED_A, LED_B,
++ * LED_C and LED_D respectively. At the same time those pins are used to
++ * bootstrap configuration of the reference clock source (LED_A),
++ * DRAM DDRx16b x2/x1 (LED_B) and boot device (LED_C, LED_D).
++ * In practise this is done using a LED and a resistor pulling the pin
++ * either to GND or to VIO.
++ * The detected value at boot time is accessible at run-time using the
++ * TPBANK0 register located in the gpio base of the pinctrl, in order
++ * to read it here it needs to be referenced by a phandle called
++ * 'mediatek,pio' in the MDIO bus hosting the PHY.
++ * The 4 bits in TPBANK0 are kept as package shared data and are used to
++ * set LED polarity for each of the LED0.
++ */
++ regmap = syscon_regmap_lookup_by_phandle(np, "mediatek,pio");
++ if (IS_ERR(regmap))
++ return PTR_ERR(regmap);
++
++ ret = regmap_read(regmap, RG_GPIO_MISC_TPBANK0, ®);
++ if (ret)
++ return ret;
++
++ shared->boottrap = FIELD_GET(RG_GPIO_MISC_TPBANK0_BOOTMODE, reg);
++
++ return 0;
++}
++
++static void mt798x_phy_leds_state_init(struct phy_device *phydev)
++{
++ int i;
++
++ for (i = 0; i < 2; ++i)
++ mt798x_phy_led_hw_control_get(phydev, i, NULL);
++}
++
++static int mt7988_phy_probe(struct phy_device *phydev)
++{
++ struct mtk_socphy_shared *shared;
++ struct mtk_socphy_priv *priv;
++ int err;
++
++ if (phydev->mdio.addr > 3)
++ return -EINVAL;
++
++ err = devm_phy_package_join(&phydev->mdio.dev, phydev, 0,
++ sizeof(struct mtk_socphy_shared));
++ if (err)
++ return err;
++
++ if (phy_package_probe_once(phydev)) {
++ err = mt7988_phy_probe_shared(phydev);
++ if (err)
++ return err;
++ }
++
++ shared = phydev->shared->priv;
++ priv = &shared->priv[phydev->mdio.addr];
++
++ phydev->priv = priv;
++
++ mt798x_phy_leds_state_init(phydev);
++
++ err = mt7988_phy_fix_leds_polarities(phydev);
++ if (err)
++ return err;
++
++ /* Disable TX power saving at probing to:
++ * 1. Meet common mode compliance test criteria
++ * 2. Make sure that TX-VCM calibration works fine
++ */
++ phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RXADC_CTRL_RG7,
++ MTK_PHY_DA_AD_BUF_BIAS_LP_MASK, 0x3 << 8);
++
++ return mt798x_phy_calibration(phydev);
++}
++
++static int mt7981_phy_probe(struct phy_device *phydev)
++{
++ struct mtk_socphy_priv *priv;
++
++ priv = devm_kzalloc(&phydev->mdio.dev, sizeof(struct mtk_socphy_priv),
++ GFP_KERNEL);
++ if (!priv)
++ return -ENOMEM;
++
++ phydev->priv = priv;
++
++ mt798x_phy_leds_state_init(phydev);
++
++ return mt798x_phy_calibration(phydev);
++}
++
++static struct phy_driver mtk_socphy_driver[] = {
++ {
++ PHY_ID_MATCH_EXACT(MTK_GPHY_ID_MT7981),
++ .name = "MediaTek MT7981 PHY",
++ .config_init = mt798x_phy_config_init,
++ .config_intr = genphy_no_config_intr,
++ .handle_interrupt = genphy_handle_interrupt_no_ack,
++ .probe = mt7981_phy_probe,
++ .suspend = genphy_suspend,
++ .resume = genphy_resume,
++ .read_page = mtk_socphy_read_page,
++ .write_page = mtk_socphy_write_page,
++ .led_blink_set = mt798x_phy_led_blink_set,
++ .led_brightness_set = mt798x_phy_led_brightness_set,
++ .led_hw_is_supported = mt798x_phy_led_hw_is_supported,
++ .led_hw_control_set = mt798x_phy_led_hw_control_set,
++ .led_hw_control_get = mt798x_phy_led_hw_control_get,
++ },
++ {
++ PHY_ID_MATCH_EXACT(MTK_GPHY_ID_MT7988),
++ .name = "MediaTek MT7988 PHY",
++ .config_init = mt798x_phy_config_init,
++ .config_intr = genphy_no_config_intr,
++ .handle_interrupt = genphy_handle_interrupt_no_ack,
++ .probe = mt7988_phy_probe,
++ .suspend = genphy_suspend,
++ .resume = genphy_resume,
++ .read_page = mtk_socphy_read_page,
++ .write_page = mtk_socphy_write_page,
++ .led_blink_set = mt798x_phy_led_blink_set,
++ .led_brightness_set = mt798x_phy_led_brightness_set,
++ .led_hw_is_supported = mt798x_phy_led_hw_is_supported,
++ .led_hw_control_set = mt798x_phy_led_hw_control_set,
++ .led_hw_control_get = mt798x_phy_led_hw_control_get,
++ },
++};
++
++module_phy_driver(mtk_socphy_driver);
++
++static struct mdio_device_id __maybe_unused mtk_socphy_tbl[] = {
++ { PHY_ID_MATCH_EXACT(MTK_GPHY_ID_MT7981) },
++ { PHY_ID_MATCH_EXACT(MTK_GPHY_ID_MT7988) },
++ { }
++};
++
++MODULE_DESCRIPTION("MediaTek SoC Gigabit Ethernet PHY driver");
++MODULE_AUTHOR("Daniel Golle <daniel@makrotopia.org>");
++MODULE_AUTHOR("SkyLake Huang <SkyLake.Huang@mediatek.com>");
++MODULE_LICENSE("GPL");
++
++MODULE_DEVICE_TABLE(mdio, mtk_socphy_tbl);
+--- /dev/null
++++ b/drivers/net/phy/mediatek/mtk-ge.c
+@@ -0,0 +1,148 @@
++// SPDX-License-Identifier: GPL-2.0+
++#include <linux/of.h>
++#include <linux/bitfield.h>
++#include <linux/module.h>
++#include <linux/phy.h>
++
++#define MTK_EXT_PAGE_ACCESS 0x1f
++#define MTK_PHY_PAGE_STANDARD 0x0000
++#define MTK_PHY_PAGE_EXTENDED 0x0001
++#define MTK_PHY_PAGE_EXTENDED_2 0x0002
++#define MTK_PHY_PAGE_EXTENDED_3 0x0003
++#define MTK_PHY_PAGE_EXTENDED_2A30 0x2a30
++#define MTK_PHY_PAGE_EXTENDED_52B5 0x52b5
++
++static int mtk_gephy_read_page(struct phy_device *phydev)
++{
++ return __phy_read(phydev, MTK_EXT_PAGE_ACCESS);
++}
++
++static int mtk_gephy_write_page(struct phy_device *phydev, int page)
++{
++ return __phy_write(phydev, MTK_EXT_PAGE_ACCESS, page);
++}
++
++static void mtk_gephy_config_init(struct phy_device *phydev)
++{
++ /* Disable EEE */
++ phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_EEE_ADV, 0);
++
++ /* Enable HW auto downshift */
++ phy_modify_paged(phydev, MTK_PHY_PAGE_EXTENDED, 0x14, 0, BIT(4));
++
++ /* Increase SlvDPSready time */
++ phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_52B5);
++ __phy_write(phydev, 0x10, 0xafae);
++ __phy_write(phydev, 0x12, 0x2f);
++ __phy_write(phydev, 0x10, 0x8fae);
++ phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0);
++
++ /* Adjust 100_mse_threshold */
++ phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x123, 0xffff);
++
++ /* Disable mcc */
++ phy_write_mmd(phydev, MDIO_MMD_VEND1, 0xa6, 0x300);
++}
++
++static int mt7530_phy_config_init(struct phy_device *phydev)
++{
++ mtk_gephy_config_init(phydev);
++
++ /* Increase post_update_timer */
++ phy_write_paged(phydev, MTK_PHY_PAGE_EXTENDED_3, 0x11, 0x4b);
++
++ return 0;
++}
++
++static int mt7530_led_config_of(struct phy_device *phydev)
++{
++ struct device_node *np = phydev->mdio.dev.of_node;
++ const __be32 *paddr;
++ int len;
++ int i;
++
++ paddr = of_get_property(np, "mediatek,led-config", &len);
++ if (!paddr)
++ return 0;
++
++ if (len < (2 * sizeof(*paddr)))
++ return -EINVAL;
++
++ len /= sizeof(*paddr);
++
++ phydev_warn(phydev, "Configure LED registers (num=%d)\n", len);
++ for (i = 0; i < len - 1; i += 2) {
++ u32 reg;
++ u32 val;
++
++ reg = be32_to_cpup(paddr + i);
++ val = be32_to_cpup(paddr + i + 1);
++
++ phy_write_mmd(phydev, MDIO_MMD_VEND2, reg, val);
++ }
++
++ return 0;
++}
++
++static int mt7531_phy_config_init(struct phy_device *phydev)
++{
++ mtk_gephy_config_init(phydev);
++
++ /* PHY link down power saving enable */
++ phy_set_bits(phydev, 0x17, BIT(4));
++ phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, 0xc6, 0x300);
++
++ /* Set TX Pair delay selection */
++ phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x13, 0x404);
++ phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x14, 0x404);
++
++ /* LED Config*/
++ mt7530_led_config_of(phydev);
++
++ return 0;
++}
++
++static struct phy_driver mtk_gephy_driver[] = {
++ {
++ PHY_ID_MATCH_EXACT(0x03a29412),
++ .name = "MediaTek MT7530 PHY",
++ .config_init = mt7530_phy_config_init,
++ /* Interrupts are handled by the switch, not the PHY
++ * itself.
++ */
++ .config_intr = genphy_no_config_intr,
++ .handle_interrupt = genphy_handle_interrupt_no_ack,
++ .suspend = genphy_suspend,
++ .resume = genphy_resume,
++ .read_page = mtk_gephy_read_page,
++ .write_page = mtk_gephy_write_page,
++ },
++ {
++ PHY_ID_MATCH_EXACT(0x03a29441),
++ .name = "MediaTek MT7531 PHY",
++ .config_init = mt7531_phy_config_init,
++ /* Interrupts are handled by the switch, not the PHY
++ * itself.
++ */
++ .config_intr = genphy_no_config_intr,
++ .handle_interrupt = genphy_handle_interrupt_no_ack,
++ .suspend = genphy_suspend,
++ .resume = genphy_resume,
++ .read_page = mtk_gephy_read_page,
++ .write_page = mtk_gephy_write_page,
++ },
++};
++
++module_phy_driver(mtk_gephy_driver);
++
++static struct mdio_device_id __maybe_unused mtk_gephy_tbl[] = {
++ { PHY_ID_MATCH_EXACT(0x03a29441) },
++ { PHY_ID_MATCH_EXACT(0x03a29412) },
++ { }
++};
++
++MODULE_DESCRIPTION("MediaTek Gigabit Ethernet PHY driver");
++MODULE_AUTHOR("DENG, Qingfang <dqfext@gmail.com>");
++MODULE_LICENSE("GPL");
++
++MODULE_DEVICE_TABLE(mdio, mtk_gephy_tbl);
--- /dev/null
+From 61bcabdb69418215ea05bdc48cb88459d757f505 Mon Sep 17 00:00:00 2001
+From: "SkyLake.Huang" <skylake.huang@mediatek.com>
+Date: Fri, 4 Oct 2024 18:24:06 +0800
+Subject: [PATCH 2/9] net: phy: mediatek: Fix spelling errors and rearrange
+ variables
+
+This patch fixes spelling errors which comes from mediatek-ge-soc.c and
+rearrange variables with reverse Xmas tree order.
+
+Signed-off-by: SkyLake.Huang <skylake.huang@mediatek.com>
+---
+ drivers/net/phy/mediatek/mtk-ge-soc.c | 19 ++++++++++---------
+ 1 file changed, 10 insertions(+), 9 deletions(-)
+
+--- a/drivers/net/phy/mediatek/mtk-ge-soc.c
++++ b/drivers/net/phy/mediatek/mtk-ge-soc.c
+@@ -408,16 +408,17 @@ static int tx_offset_cal_efuse(struct ph
+
+ static int tx_amp_fill_result(struct phy_device *phydev, u16 *buf)
+ {
+- int i;
+- int bias[16] = {};
+- const int vals_9461[16] = { 7, 1, 4, 7,
+- 7, 1, 4, 7,
+- 7, 1, 4, 7,
+- 7, 1, 4, 7 };
+ const int vals_9481[16] = { 10, 6, 6, 10,
+ 10, 6, 6, 10,
+ 10, 6, 6, 10,
+ 10, 6, 6, 10 };
++ const int vals_9461[16] = { 7, 1, 4, 7,
++ 7, 1, 4, 7,
++ 7, 1, 4, 7,
++ 7, 1, 4, 7 };
++ int bias[16] = {};
++ int i;
++
+ switch (phydev->drv->phy_id) {
+ case MTK_GPHY_ID_MT7981:
+ /* We add some calibration to efuse values
+@@ -1069,10 +1070,10 @@ static int start_cal(struct phy_device *
+
+ static int mt798x_phy_calibration(struct phy_device *phydev)
+ {
++ struct nvmem_cell *cell;
+ int ret = 0;
+- u32 *buf;
+ size_t len;
+- struct nvmem_cell *cell;
++ u32 *buf;
+
+ cell = nvmem_cell_get(&phydev->mdio.dev, "phy-cal-data");
+ if (IS_ERR(cell)) {
+@@ -1415,7 +1416,7 @@ static int mt7988_phy_probe_shared(struc
+ * LED_C and LED_D respectively. At the same time those pins are used to
+ * bootstrap configuration of the reference clock source (LED_A),
+ * DRAM DDRx16b x2/x1 (LED_B) and boot device (LED_C, LED_D).
+- * In practise this is done using a LED and a resistor pulling the pin
++ * In practice this is done using a LED and a resistor pulling the pin
+ * either to GND or to VIO.
+ * The detected value at boot time is accessible at run-time using the
+ * TPBANK0 register located in the gpio base of the pinctrl, in order
--- /dev/null
+From 16bbd4ecb67ec1899ad8aa1eb1219a6d576cbaaf Mon Sep 17 00:00:00 2001
+From: "SkyLake.Huang" <skylake.huang@mediatek.com>
+Date: Fri, 4 Oct 2024 18:24:07 +0800
+Subject: [PATCH 3/9] net: phy: mediatek: Move LED helper functions into mtk
+ phy lib
+
+This patch creates mtk-phy-lib.c & mtk-phy.h and integrates mtk-ge-soc.c's
+LED helper functions so that we can use those helper functions in other
+MTK's ethernet phy driver.
+
+Signed-off-by: SkyLake.Huang <skylake.huang@mediatek.com>
+---
+ drivers/net/phy/mediatek/Kconfig | 5 +
+ drivers/net/phy/mediatek/Makefile | 1 +
+ drivers/net/phy/mediatek/mtk-ge-soc.c | 262 +++----------------------
+ drivers/net/phy/mediatek/mtk-phy-lib.c | 251 +++++++++++++++++++++++
+ drivers/net/phy/mediatek/mtk.h | 82 ++++++++
+ 5 files changed, 366 insertions(+), 235 deletions(-)
+ create mode 100644 drivers/net/phy/mediatek/mtk-phy-lib.c
+ create mode 100644 drivers/net/phy/mediatek/mtk.h
+
+--- a/drivers/net/phy/mediatek/Kconfig
++++ b/drivers/net/phy/mediatek/Kconfig
+@@ -1,6 +1,10 @@
+ # SPDX-License-Identifier: GPL-2.0-only
++config MTK_NET_PHYLIB
++ tristate
++
+ config MEDIATEK_GE_PHY
+ tristate "MediaTek Gigabit Ethernet PHYs"
++ select MTK_NET_PHYLIB
+ help
+ Supports the MediaTek non-built-in Gigabit Ethernet PHYs.
+
+@@ -13,6 +17,7 @@ config MEDIATEK_GE_SOC_PHY
+ tristate "MediaTek SoC Ethernet PHYs"
+ depends on (ARM64 && ARCH_MEDIATEK) || COMPILE_TEST
+ select NVMEM_MTK_EFUSE
++ select MTK_NET_PHYLIB
+ help
+ Supports MediaTek SoC built-in Gigabit Ethernet PHYs.
+
+--- a/drivers/net/phy/mediatek/Makefile
++++ b/drivers/net/phy/mediatek/Makefile
+@@ -1,3 +1,4 @@
+ # SPDX-License-Identifier: GPL-2.0
++obj-$(CONFIG_MTK_NET_PHYLIB) += mtk-phy-lib.o
+ obj-$(CONFIG_MEDIATEK_GE_PHY) += mtk-ge.o
+ obj-$(CONFIG_MEDIATEK_GE_SOC_PHY) += mtk-ge-soc.o
+--- a/drivers/net/phy/mediatek/mtk-ge-soc.c
++++ b/drivers/net/phy/mediatek/mtk-ge-soc.c
+@@ -8,6 +8,8 @@
+ #include <linux/phy.h>
+ #include <linux/regmap.h>
+
++#include "mtk.h"
++
+ #define MTK_GPHY_ID_MT7981 0x03a29461
+ #define MTK_GPHY_ID_MT7988 0x03a29481
+
+@@ -210,41 +212,6 @@
+ #define MTK_PHY_DA_TX_R50_PAIR_D 0x540
+
+ /* Registers on MDIO_MMD_VEND2 */
+-#define MTK_PHY_LED0_ON_CTRL 0x24
+-#define MTK_PHY_LED1_ON_CTRL 0x26
+-#define MTK_PHY_LED_ON_MASK GENMASK(6, 0)
+-#define MTK_PHY_LED_ON_LINK1000 BIT(0)
+-#define MTK_PHY_LED_ON_LINK100 BIT(1)
+-#define MTK_PHY_LED_ON_LINK10 BIT(2)
+-#define MTK_PHY_LED_ON_LINK (MTK_PHY_LED_ON_LINK10 |\
+- MTK_PHY_LED_ON_LINK100 |\
+- MTK_PHY_LED_ON_LINK1000)
+-#define MTK_PHY_LED_ON_LINKDOWN BIT(3)
+-#define MTK_PHY_LED_ON_FDX BIT(4) /* Full duplex */
+-#define MTK_PHY_LED_ON_HDX BIT(5) /* Half duplex */
+-#define MTK_PHY_LED_ON_FORCE_ON BIT(6)
+-#define MTK_PHY_LED_ON_POLARITY BIT(14)
+-#define MTK_PHY_LED_ON_ENABLE BIT(15)
+-
+-#define MTK_PHY_LED0_BLINK_CTRL 0x25
+-#define MTK_PHY_LED1_BLINK_CTRL 0x27
+-#define MTK_PHY_LED_BLINK_1000TX BIT(0)
+-#define MTK_PHY_LED_BLINK_1000RX BIT(1)
+-#define MTK_PHY_LED_BLINK_100TX BIT(2)
+-#define MTK_PHY_LED_BLINK_100RX BIT(3)
+-#define MTK_PHY_LED_BLINK_10TX BIT(4)
+-#define MTK_PHY_LED_BLINK_10RX BIT(5)
+-#define MTK_PHY_LED_BLINK_RX (MTK_PHY_LED_BLINK_10RX |\
+- MTK_PHY_LED_BLINK_100RX |\
+- MTK_PHY_LED_BLINK_1000RX)
+-#define MTK_PHY_LED_BLINK_TX (MTK_PHY_LED_BLINK_10TX |\
+- MTK_PHY_LED_BLINK_100TX |\
+- MTK_PHY_LED_BLINK_1000TX)
+-#define MTK_PHY_LED_BLINK_COLLISION BIT(6)
+-#define MTK_PHY_LED_BLINK_RX_CRC_ERR BIT(7)
+-#define MTK_PHY_LED_BLINK_RX_IDLE_ERR BIT(8)
+-#define MTK_PHY_LED_BLINK_FORCE_BLINK BIT(9)
+-
+ #define MTK_PHY_LED1_DEFAULT_POLARITIES BIT(1)
+
+ #define MTK_PHY_RG_BG_RASEL 0x115
+@@ -299,10 +266,6 @@ enum CAL_MODE {
+ SW_M
+ };
+
+-#define MTK_PHY_LED_STATE_FORCE_ON 0
+-#define MTK_PHY_LED_STATE_FORCE_BLINK 1
+-#define MTK_PHY_LED_STATE_NETDEV 2
+-
+ struct mtk_socphy_priv {
+ unsigned long led_state;
+ };
+@@ -1131,84 +1094,39 @@ static int mt798x_phy_config_init(struct
+ return mt798x_phy_calibration(phydev);
+ }
+
+-static int mt798x_phy_hw_led_on_set(struct phy_device *phydev, u8 index,
+- bool on)
+-{
+- unsigned int bit_on = MTK_PHY_LED_STATE_FORCE_ON + (index ? 16 : 0);
+- struct mtk_socphy_priv *priv = phydev->priv;
+- bool changed;
+-
+- if (on)
+- changed = !test_and_set_bit(bit_on, &priv->led_state);
+- else
+- changed = !!test_and_clear_bit(bit_on, &priv->led_state);
+-
+- changed |= !!test_and_clear_bit(MTK_PHY_LED_STATE_NETDEV +
+- (index ? 16 : 0), &priv->led_state);
+- if (changed)
+- return phy_modify_mmd(phydev, MDIO_MMD_VEND2, index ?
+- MTK_PHY_LED1_ON_CTRL : MTK_PHY_LED0_ON_CTRL,
+- MTK_PHY_LED_ON_MASK,
+- on ? MTK_PHY_LED_ON_FORCE_ON : 0);
+- else
+- return 0;
+-}
+-
+-static int mt798x_phy_hw_led_blink_set(struct phy_device *phydev, u8 index,
+- bool blinking)
+-{
+- unsigned int bit_blink = MTK_PHY_LED_STATE_FORCE_BLINK + (index ? 16 : 0);
+- struct mtk_socphy_priv *priv = phydev->priv;
+- bool changed;
+-
+- if (blinking)
+- changed = !test_and_set_bit(bit_blink, &priv->led_state);
+- else
+- changed = !!test_and_clear_bit(bit_blink, &priv->led_state);
+-
+- changed |= !!test_bit(MTK_PHY_LED_STATE_NETDEV +
+- (index ? 16 : 0), &priv->led_state);
+- if (changed)
+- return phy_write_mmd(phydev, MDIO_MMD_VEND2, index ?
+- MTK_PHY_LED1_BLINK_CTRL : MTK_PHY_LED0_BLINK_CTRL,
+- blinking ? MTK_PHY_LED_BLINK_FORCE_BLINK : 0);
+- else
+- return 0;
+-}
+-
+ static int mt798x_phy_led_blink_set(struct phy_device *phydev, u8 index,
+ unsigned long *delay_on,
+ unsigned long *delay_off)
+ {
++ struct mtk_socphy_priv *priv = phydev->priv;
+ bool blinking = false;
+ int err = 0;
+
+- if (index > 1)
+- return -EINVAL;
+-
+- if (delay_on && delay_off && (*delay_on > 0) && (*delay_off > 0)) {
+- blinking = true;
+- *delay_on = 50;
+- *delay_off = 50;
+- }
++ err = mtk_phy_led_num_dly_cfg(index, delay_on, delay_off, &blinking);
++ if (err < 0)
++ return err;
+
+- err = mt798x_phy_hw_led_blink_set(phydev, index, blinking);
++ err = mtk_phy_hw_led_blink_set(phydev, index, &priv->led_state,
++ blinking);
+ if (err)
+ return err;
+
+- return mt798x_phy_hw_led_on_set(phydev, index, false);
++ return mtk_phy_hw_led_on_set(phydev, index, &priv->led_state,
++ MTK_GPHY_LED_ON_MASK, false);
+ }
+
+ static int mt798x_phy_led_brightness_set(struct phy_device *phydev,
+ u8 index, enum led_brightness value)
+ {
++ struct mtk_socphy_priv *priv = phydev->priv;
+ int err;
+
+- err = mt798x_phy_hw_led_blink_set(phydev, index, false);
++ err = mtk_phy_hw_led_blink_set(phydev, index, &priv->led_state, false);
+ if (err)
+ return err;
+
+- return mt798x_phy_hw_led_on_set(phydev, index, (value != LED_OFF));
++ return mtk_phy_hw_led_on_set(phydev, index, &priv->led_state,
++ MTK_GPHY_LED_ON_MASK, (value != LED_OFF));
+ }
+
+ static const unsigned long supported_triggers = (BIT(TRIGGER_NETDEV_FULL_DUPLEX) |
+@@ -1223,148 +1141,30 @@ static const unsigned long supported_tri
+ static int mt798x_phy_led_hw_is_supported(struct phy_device *phydev, u8 index,
+ unsigned long rules)
+ {
+- if (index > 1)
+- return -EINVAL;
+-
+- /* All combinations of the supported triggers are allowed */
+- if (rules & ~supported_triggers)
+- return -EOPNOTSUPP;
+-
+- return 0;
+-};
++ return mtk_phy_led_hw_is_supported(phydev, index, rules,
++ supported_triggers);
++}
+
+ static int mt798x_phy_led_hw_control_get(struct phy_device *phydev, u8 index,
+ unsigned long *rules)
+ {
+- unsigned int bit_blink = MTK_PHY_LED_STATE_FORCE_BLINK + (index ? 16 : 0);
+- unsigned int bit_netdev = MTK_PHY_LED_STATE_NETDEV + (index ? 16 : 0);
+- unsigned int bit_on = MTK_PHY_LED_STATE_FORCE_ON + (index ? 16 : 0);
+ struct mtk_socphy_priv *priv = phydev->priv;
+- int on, blink;
+-
+- if (index > 1)
+- return -EINVAL;
+-
+- on = phy_read_mmd(phydev, MDIO_MMD_VEND2,
+- index ? MTK_PHY_LED1_ON_CTRL : MTK_PHY_LED0_ON_CTRL);
+-
+- if (on < 0)
+- return -EIO;
+-
+- blink = phy_read_mmd(phydev, MDIO_MMD_VEND2,
+- index ? MTK_PHY_LED1_BLINK_CTRL :
+- MTK_PHY_LED0_BLINK_CTRL);
+- if (blink < 0)
+- return -EIO;
+-
+- if ((on & (MTK_PHY_LED_ON_LINK | MTK_PHY_LED_ON_FDX | MTK_PHY_LED_ON_HDX |
+- MTK_PHY_LED_ON_LINKDOWN)) ||
+- (blink & (MTK_PHY_LED_BLINK_RX | MTK_PHY_LED_BLINK_TX)))
+- set_bit(bit_netdev, &priv->led_state);
+- else
+- clear_bit(bit_netdev, &priv->led_state);
+-
+- if (on & MTK_PHY_LED_ON_FORCE_ON)
+- set_bit(bit_on, &priv->led_state);
+- else
+- clear_bit(bit_on, &priv->led_state);
+-
+- if (blink & MTK_PHY_LED_BLINK_FORCE_BLINK)
+- set_bit(bit_blink, &priv->led_state);
+- else
+- clear_bit(bit_blink, &priv->led_state);
+-
+- if (!rules)
+- return 0;
+-
+- if (on & MTK_PHY_LED_ON_LINK)
+- *rules |= BIT(TRIGGER_NETDEV_LINK);
+
+- if (on & MTK_PHY_LED_ON_LINK10)
+- *rules |= BIT(TRIGGER_NETDEV_LINK_10);
+-
+- if (on & MTK_PHY_LED_ON_LINK100)
+- *rules |= BIT(TRIGGER_NETDEV_LINK_100);
+-
+- if (on & MTK_PHY_LED_ON_LINK1000)
+- *rules |= BIT(TRIGGER_NETDEV_LINK_1000);
+-
+- if (on & MTK_PHY_LED_ON_FDX)
+- *rules |= BIT(TRIGGER_NETDEV_FULL_DUPLEX);
+-
+- if (on & MTK_PHY_LED_ON_HDX)
+- *rules |= BIT(TRIGGER_NETDEV_HALF_DUPLEX);
+-
+- if (blink & MTK_PHY_LED_BLINK_RX)
+- *rules |= BIT(TRIGGER_NETDEV_RX);
+-
+- if (blink & MTK_PHY_LED_BLINK_TX)
+- *rules |= BIT(TRIGGER_NETDEV_TX);
+-
+- return 0;
++ return mtk_phy_led_hw_ctrl_get(phydev, index, rules, &priv->led_state,
++ MTK_GPHY_LED_ON_SET,
++ MTK_GPHY_LED_RX_BLINK_SET,
++ MTK_GPHY_LED_TX_BLINK_SET);
+ };
+
+ static int mt798x_phy_led_hw_control_set(struct phy_device *phydev, u8 index,
+ unsigned long rules)
+ {
+- unsigned int bit_netdev = MTK_PHY_LED_STATE_NETDEV + (index ? 16 : 0);
+ struct mtk_socphy_priv *priv = phydev->priv;
+- u16 on = 0, blink = 0;
+- int ret;
+
+- if (index > 1)
+- return -EINVAL;
+-
+- if (rules & BIT(TRIGGER_NETDEV_FULL_DUPLEX))
+- on |= MTK_PHY_LED_ON_FDX;
+-
+- if (rules & BIT(TRIGGER_NETDEV_HALF_DUPLEX))
+- on |= MTK_PHY_LED_ON_HDX;
+-
+- if (rules & (BIT(TRIGGER_NETDEV_LINK_10) | BIT(TRIGGER_NETDEV_LINK)))
+- on |= MTK_PHY_LED_ON_LINK10;
+-
+- if (rules & (BIT(TRIGGER_NETDEV_LINK_100) | BIT(TRIGGER_NETDEV_LINK)))
+- on |= MTK_PHY_LED_ON_LINK100;
+-
+- if (rules & (BIT(TRIGGER_NETDEV_LINK_1000) | BIT(TRIGGER_NETDEV_LINK)))
+- on |= MTK_PHY_LED_ON_LINK1000;
+-
+- if (rules & BIT(TRIGGER_NETDEV_RX)) {
+- blink |= (on & MTK_PHY_LED_ON_LINK) ?
+- (((on & MTK_PHY_LED_ON_LINK10) ? MTK_PHY_LED_BLINK_10RX : 0) |
+- ((on & MTK_PHY_LED_ON_LINK100) ? MTK_PHY_LED_BLINK_100RX : 0) |
+- ((on & MTK_PHY_LED_ON_LINK1000) ? MTK_PHY_LED_BLINK_1000RX : 0)) :
+- MTK_PHY_LED_BLINK_RX;
+- }
+-
+- if (rules & BIT(TRIGGER_NETDEV_TX)) {
+- blink |= (on & MTK_PHY_LED_ON_LINK) ?
+- (((on & MTK_PHY_LED_ON_LINK10) ? MTK_PHY_LED_BLINK_10TX : 0) |
+- ((on & MTK_PHY_LED_ON_LINK100) ? MTK_PHY_LED_BLINK_100TX : 0) |
+- ((on & MTK_PHY_LED_ON_LINK1000) ? MTK_PHY_LED_BLINK_1000TX : 0)) :
+- MTK_PHY_LED_BLINK_TX;
+- }
+-
+- if (blink || on)
+- set_bit(bit_netdev, &priv->led_state);
+- else
+- clear_bit(bit_netdev, &priv->led_state);
+-
+- ret = phy_modify_mmd(phydev, MDIO_MMD_VEND2, index ?
+- MTK_PHY_LED1_ON_CTRL :
+- MTK_PHY_LED0_ON_CTRL,
+- MTK_PHY_LED_ON_FDX |
+- MTK_PHY_LED_ON_HDX |
+- MTK_PHY_LED_ON_LINK,
+- on);
+-
+- if (ret)
+- return ret;
+-
+- return phy_write_mmd(phydev, MDIO_MMD_VEND2, index ?
+- MTK_PHY_LED1_BLINK_CTRL :
+- MTK_PHY_LED0_BLINK_CTRL, blink);
++ return mtk_phy_led_hw_ctrl_set(phydev, index, rules, &priv->led_state,
++ MTK_GPHY_LED_ON_SET,
++ MTK_GPHY_LED_RX_BLINK_SET,
++ MTK_GPHY_LED_TX_BLINK_SET);
+ };
+
+ static bool mt7988_phy_led_get_polarity(struct phy_device *phydev, int led_num)
+@@ -1438,14 +1238,6 @@ static int mt7988_phy_probe_shared(struc
+ return 0;
+ }
+
+-static void mt798x_phy_leds_state_init(struct phy_device *phydev)
+-{
+- int i;
+-
+- for (i = 0; i < 2; ++i)
+- mt798x_phy_led_hw_control_get(phydev, i, NULL);
+-}
+-
+ static int mt7988_phy_probe(struct phy_device *phydev)
+ {
+ struct mtk_socphy_shared *shared;
+@@ -1471,7 +1263,7 @@ static int mt7988_phy_probe(struct phy_d
+
+ phydev->priv = priv;
+
+- mt798x_phy_leds_state_init(phydev);
++ mtk_phy_leds_state_init(phydev);
+
+ err = mt7988_phy_fix_leds_polarities(phydev);
+ if (err)
+@@ -1498,7 +1290,7 @@ static int mt7981_phy_probe(struct phy_d
+
+ phydev->priv = priv;
+
+- mt798x_phy_leds_state_init(phydev);
++ mtk_phy_leds_state_init(phydev);
+
+ return mt798x_phy_calibration(phydev);
+ }
+--- /dev/null
++++ b/drivers/net/phy/mediatek/mtk-phy-lib.c
+@@ -0,0 +1,251 @@
++// SPDX-License-Identifier: GPL-2.0
++#include <linux/phy.h>
++#include <linux/module.h>
++
++#include <linux/netdevice.h>
++
++#include "mtk.h"
++
++int mtk_phy_led_hw_is_supported(struct phy_device *phydev, u8 index,
++ unsigned long rules,
++ unsigned long supported_triggers)
++{
++ if (index > 1)
++ return -EINVAL;
++
++ /* All combinations of the supported triggers are allowed */
++ if (rules & ~supported_triggers)
++ return -EOPNOTSUPP;
++
++ return 0;
++}
++EXPORT_SYMBOL_GPL(mtk_phy_led_hw_is_supported);
++
++int mtk_phy_led_hw_ctrl_get(struct phy_device *phydev, u8 index,
++ unsigned long *rules, unsigned long *led_state,
++ u16 on_set, u16 rx_blink_set, u16 tx_blink_set)
++{
++ unsigned int bit_blink = MTK_PHY_LED_STATE_FORCE_BLINK +
++ (index ? 16 : 0);
++ unsigned int bit_netdev = MTK_PHY_LED_STATE_NETDEV + (index ? 16 : 0);
++ unsigned int bit_on = MTK_PHY_LED_STATE_FORCE_ON + (index ? 16 : 0);
++ int on, blink;
++
++ if (index > 1)
++ return -EINVAL;
++
++ on = phy_read_mmd(phydev, MDIO_MMD_VEND2,
++ index ? MTK_PHY_LED1_ON_CTRL : MTK_PHY_LED0_ON_CTRL);
++
++ if (on < 0)
++ return -EIO;
++
++ blink = phy_read_mmd(phydev, MDIO_MMD_VEND2,
++ index ? MTK_PHY_LED1_BLINK_CTRL :
++ MTK_PHY_LED0_BLINK_CTRL);
++ if (blink < 0)
++ return -EIO;
++
++ if ((on & (on_set | MTK_PHY_LED_ON_FDX |
++ MTK_PHY_LED_ON_HDX | MTK_PHY_LED_ON_LINKDOWN)) ||
++ (blink & (rx_blink_set | tx_blink_set)))
++ set_bit(bit_netdev, led_state);
++ else
++ clear_bit(bit_netdev, led_state);
++
++ if (on & MTK_PHY_LED_ON_FORCE_ON)
++ set_bit(bit_on, led_state);
++ else
++ clear_bit(bit_on, led_state);
++
++ if (blink & MTK_PHY_LED_BLINK_FORCE_BLINK)
++ set_bit(bit_blink, led_state);
++ else
++ clear_bit(bit_blink, led_state);
++
++ if (!rules)
++ return 0;
++
++ if (on & on_set)
++ *rules |= BIT(TRIGGER_NETDEV_LINK);
++
++ if (on & MTK_PHY_LED_ON_LINK10)
++ *rules |= BIT(TRIGGER_NETDEV_LINK_10);
++
++ if (on & MTK_PHY_LED_ON_LINK100)
++ *rules |= BIT(TRIGGER_NETDEV_LINK_100);
++
++ if (on & MTK_PHY_LED_ON_LINK1000)
++ *rules |= BIT(TRIGGER_NETDEV_LINK_1000);
++
++ if (on & MTK_PHY_LED_ON_LINK2500)
++ *rules |= BIT(TRIGGER_NETDEV_LINK_2500);
++
++ if (on & MTK_PHY_LED_ON_FDX)
++ *rules |= BIT(TRIGGER_NETDEV_FULL_DUPLEX);
++
++ if (on & MTK_PHY_LED_ON_HDX)
++ *rules |= BIT(TRIGGER_NETDEV_HALF_DUPLEX);
++
++ if (blink & rx_blink_set)
++ *rules |= BIT(TRIGGER_NETDEV_RX);
++
++ if (blink & tx_blink_set)
++ *rules |= BIT(TRIGGER_NETDEV_TX);
++
++ return 0;
++}
++EXPORT_SYMBOL_GPL(mtk_phy_led_hw_ctrl_get);
++
++int mtk_phy_led_hw_ctrl_set(struct phy_device *phydev, u8 index,
++ unsigned long rules, unsigned long *led_state,
++ u16 on_set, u16 rx_blink_set, u16 tx_blink_set)
++{
++ unsigned int bit_netdev = MTK_PHY_LED_STATE_NETDEV + (index ? 16 : 0);
++ u16 on = 0, blink = 0;
++ int ret;
++
++ if (index > 1)
++ return -EINVAL;
++
++ if (rules & BIT(TRIGGER_NETDEV_FULL_DUPLEX))
++ on |= MTK_PHY_LED_ON_FDX;
++
++ if (rules & BIT(TRIGGER_NETDEV_HALF_DUPLEX))
++ on |= MTK_PHY_LED_ON_HDX;
++
++ if (rules & (BIT(TRIGGER_NETDEV_LINK_10) | BIT(TRIGGER_NETDEV_LINK)))
++ on |= MTK_PHY_LED_ON_LINK10;
++
++ if (rules & (BIT(TRIGGER_NETDEV_LINK_100) | BIT(TRIGGER_NETDEV_LINK)))
++ on |= MTK_PHY_LED_ON_LINK100;
++
++ if (rules & (BIT(TRIGGER_NETDEV_LINK_1000) | BIT(TRIGGER_NETDEV_LINK)))
++ on |= MTK_PHY_LED_ON_LINK1000;
++
++ if (rules & (BIT(TRIGGER_NETDEV_LINK_2500) | BIT(TRIGGER_NETDEV_LINK)))
++ on |= MTK_PHY_LED_ON_LINK2500;
++
++ if (rules & BIT(TRIGGER_NETDEV_RX)) {
++ blink |= (on & on_set) ?
++ (((on & MTK_PHY_LED_ON_LINK10) ?
++ MTK_PHY_LED_BLINK_10RX : 0) |
++ ((on & MTK_PHY_LED_ON_LINK100) ?
++ MTK_PHY_LED_BLINK_100RX : 0) |
++ ((on & MTK_PHY_LED_ON_LINK1000) ?
++ MTK_PHY_LED_BLINK_1000RX : 0) |
++ ((on & MTK_PHY_LED_ON_LINK2500) ?
++ MTK_PHY_LED_BLINK_2500RX : 0)) :
++ rx_blink_set;
++ }
++
++ if (rules & BIT(TRIGGER_NETDEV_TX)) {
++ blink |= (on & on_set) ?
++ (((on & MTK_PHY_LED_ON_LINK10) ?
++ MTK_PHY_LED_BLINK_10TX : 0) |
++ ((on & MTK_PHY_LED_ON_LINK100) ?
++ MTK_PHY_LED_BLINK_100TX : 0) |
++ ((on & MTK_PHY_LED_ON_LINK1000) ?
++ MTK_PHY_LED_BLINK_1000TX : 0) |
++ ((on & MTK_PHY_LED_ON_LINK2500) ?
++ MTK_PHY_LED_BLINK_2500TX : 0)) :
++ tx_blink_set;
++ }
++
++ if (blink || on)
++ set_bit(bit_netdev, led_state);
++ else
++ clear_bit(bit_netdev, led_state);
++
++ ret = phy_modify_mmd(phydev, MDIO_MMD_VEND2, index ?
++ MTK_PHY_LED1_ON_CTRL : MTK_PHY_LED0_ON_CTRL,
++ MTK_PHY_LED_ON_FDX | MTK_PHY_LED_ON_HDX | on_set,
++ on);
++
++ if (ret)
++ return ret;
++
++ return phy_write_mmd(phydev, MDIO_MMD_VEND2, index ?
++ MTK_PHY_LED1_BLINK_CTRL :
++ MTK_PHY_LED0_BLINK_CTRL, blink);
++}
++EXPORT_SYMBOL_GPL(mtk_phy_led_hw_ctrl_set);
++
++int mtk_phy_led_num_dly_cfg(u8 index, unsigned long *delay_on,
++ unsigned long *delay_off, bool *blinking)
++{
++ if (index > 1)
++ return -EINVAL;
++
++ if (delay_on && delay_off && (*delay_on > 0) && (*delay_off > 0)) {
++ *blinking = true;
++ *delay_on = 50;
++ *delay_off = 50;
++ }
++
++ return 0;
++}
++EXPORT_SYMBOL_GPL(mtk_phy_led_num_dly_cfg);
++
++int mtk_phy_hw_led_on_set(struct phy_device *phydev, u8 index,
++ unsigned long *led_state, u16 led_on_mask, bool on)
++{
++ unsigned int bit_on = MTK_PHY_LED_STATE_FORCE_ON + (index ? 16 : 0);
++ bool changed;
++
++ if (on)
++ changed = !test_and_set_bit(bit_on, led_state);
++ else
++ changed = !!test_and_clear_bit(bit_on, led_state);
++
++ changed |= !!test_and_clear_bit(MTK_PHY_LED_STATE_NETDEV +
++ (index ? 16 : 0), led_state);
++ if (changed)
++ return phy_modify_mmd(phydev, MDIO_MMD_VEND2, index ?
++ MTK_PHY_LED1_ON_CTRL :
++ MTK_PHY_LED0_ON_CTRL,
++ led_on_mask,
++ on ? MTK_PHY_LED_ON_FORCE_ON : 0);
++ else
++ return 0;
++}
++EXPORT_SYMBOL_GPL(mtk_phy_hw_led_on_set);
++
++int mtk_phy_hw_led_blink_set(struct phy_device *phydev, u8 index,
++ unsigned long *led_state, bool blinking)
++{
++ unsigned int bit_blink = MTK_PHY_LED_STATE_FORCE_BLINK +
++ (index ? 16 : 0);
++ bool changed;
++
++ if (blinking)
++ changed = !test_and_set_bit(bit_blink, led_state);
++ else
++ changed = !!test_and_clear_bit(bit_blink, led_state);
++
++ changed |= !!test_bit(MTK_PHY_LED_STATE_NETDEV +
++ (index ? 16 : 0), led_state);
++ if (changed)
++ return phy_write_mmd(phydev, MDIO_MMD_VEND2, index ?
++ MTK_PHY_LED1_BLINK_CTRL :
++ MTK_PHY_LED0_BLINK_CTRL,
++ blinking ?
++ MTK_PHY_LED_BLINK_FORCE_BLINK : 0);
++ else
++ return 0;
++}
++EXPORT_SYMBOL_GPL(mtk_phy_hw_led_blink_set);
++
++void mtk_phy_leds_state_init(struct phy_device *phydev)
++{
++ int i;
++
++ for (i = 0; i < 2; ++i)
++ phydev->drv->led_hw_control_get(phydev, i, NULL);
++}
++EXPORT_SYMBOL_GPL(mtk_phy_leds_state_init);
++
++MODULE_DESCRIPTION("MediaTek Ethernet PHY driver common");
++MODULE_AUTHOR("Sky Huang <SkyLake.Huang@mediatek.com>");
++MODULE_AUTHOR("Daniel Golle <daniel@makrotopia.org>");
++MODULE_LICENSE("GPL");
+--- /dev/null
++++ b/drivers/net/phy/mediatek/mtk.h
+@@ -0,0 +1,82 @@
++/* SPDX-License-Identifier: GPL-2.0
++ *
++ * Common definition for Mediatek Ethernet PHYs
++ * Author: SkyLake Huang <SkyLake.Huang@mediatek.com>
++ * Copyright (c) 2024 MediaTek Inc.
++ */
++
++#ifndef _MTK_EPHY_H_
++#define _MTK_EPHY_H_
++
++#define MTK_EXT_PAGE_ACCESS 0x1f
++
++/* Registers on MDIO_MMD_VEND2 */
++#define MTK_PHY_LED0_ON_CTRL 0x24
++#define MTK_PHY_LED1_ON_CTRL 0x26
++#define MTK_GPHY_LED_ON_MASK GENMASK(6, 0)
++#define MTK_2P5GPHY_LED_ON_MASK GENMASK(7, 0)
++#define MTK_PHY_LED_ON_LINK1000 BIT(0)
++#define MTK_PHY_LED_ON_LINK100 BIT(1)
++#define MTK_PHY_LED_ON_LINK10 BIT(2)
++#define MTK_PHY_LED_ON_LINKDOWN BIT(3)
++#define MTK_PHY_LED_ON_FDX BIT(4) /* Full duplex */
++#define MTK_PHY_LED_ON_HDX BIT(5) /* Half duplex */
++#define MTK_PHY_LED_ON_FORCE_ON BIT(6)
++#define MTK_PHY_LED_ON_LINK2500 BIT(7)
++#define MTK_PHY_LED_ON_POLARITY BIT(14)
++#define MTK_PHY_LED_ON_ENABLE BIT(15)
++
++#define MTK_PHY_LED0_BLINK_CTRL 0x25
++#define MTK_PHY_LED1_BLINK_CTRL 0x27
++#define MTK_PHY_LED_BLINK_1000TX BIT(0)
++#define MTK_PHY_LED_BLINK_1000RX BIT(1)
++#define MTK_PHY_LED_BLINK_100TX BIT(2)
++#define MTK_PHY_LED_BLINK_100RX BIT(3)
++#define MTK_PHY_LED_BLINK_10TX BIT(4)
++#define MTK_PHY_LED_BLINK_10RX BIT(5)
++#define MTK_PHY_LED_BLINK_COLLISION BIT(6)
++#define MTK_PHY_LED_BLINK_RX_CRC_ERR BIT(7)
++#define MTK_PHY_LED_BLINK_RX_IDLE_ERR BIT(8)
++#define MTK_PHY_LED_BLINK_FORCE_BLINK BIT(9)
++#define MTK_PHY_LED_BLINK_2500TX BIT(10)
++#define MTK_PHY_LED_BLINK_2500RX BIT(11)
++
++#define MTK_GPHY_LED_ON_SET (MTK_PHY_LED_ON_LINK1000 | \
++ MTK_PHY_LED_ON_LINK100 | \
++ MTK_PHY_LED_ON_LINK10)
++#define MTK_GPHY_LED_RX_BLINK_SET (MTK_PHY_LED_BLINK_1000RX | \
++ MTK_PHY_LED_BLINK_100RX | \
++ MTK_PHY_LED_BLINK_10RX)
++#define MTK_GPHY_LED_TX_BLINK_SET (MTK_PHY_LED_BLINK_1000RX | \
++ MTK_PHY_LED_BLINK_100RX | \
++ MTK_PHY_LED_BLINK_10RX)
++
++#define MTK_2P5GPHY_LED_ON_SET (MTK_PHY_LED_ON_LINK2500 | \
++ MTK_GPHY_LED_ON_SET)
++#define MTK_2P5GPHY_LED_RX_BLINK_SET (MTK_PHY_LED_BLINK_2500RX | \
++ MTK_GPHY_LED_RX_BLINK_SET)
++#define MTK_2P5GPHY_LED_TX_BLINK_SET (MTK_PHY_LED_BLINK_2500RX | \
++ MTK_GPHY_LED_TX_BLINK_SET)
++
++#define MTK_PHY_LED_STATE_FORCE_ON 0
++#define MTK_PHY_LED_STATE_FORCE_BLINK 1
++#define MTK_PHY_LED_STATE_NETDEV 2
++
++int mtk_phy_led_hw_is_supported(struct phy_device *phydev, u8 index,
++ unsigned long rules,
++ unsigned long supported_triggers);
++int mtk_phy_led_hw_ctrl_set(struct phy_device *phydev, u8 index,
++ unsigned long rules, unsigned long *led_state,
++ u16 on_set, u16 rx_blink_set, u16 tx_blink_set);
++int mtk_phy_led_hw_ctrl_get(struct phy_device *phydev, u8 index,
++ unsigned long *rules, unsigned long *led_state,
++ u16 on_set, u16 rx_blink_set, u16 tx_blink_set);
++int mtk_phy_led_num_dly_cfg(u8 index, unsigned long *delay_on,
++ unsigned long *delay_off, bool *blinking);
++int mtk_phy_hw_led_on_set(struct phy_device *phydev, u8 index,
++ unsigned long *led_state, u16 led_on_mask, bool on);
++int mtk_phy_hw_led_blink_set(struct phy_device *phydev, u8 index,
++ unsigned long *led_state, bool blinking);
++void mtk_phy_leds_state_init(struct phy_device *phydev);
++
++#endif /* _MTK_EPHY_H_ */
--- /dev/null
+From 2b118202583eb05a1799d435d2dce974dc3f5b16 Mon Sep 17 00:00:00 2001
+From: "SkyLake.Huang" <skylake.huang@mediatek.com>
+Date: Fri, 4 Oct 2024 18:24:08 +0800
+Subject: [PATCH 4/9] net: phy: mediatek: Improve readability of
+ mtk-phy-lib.c's mtk_phy_led_hw_ctrl_set()
+
+This patch removes parens around TRIGGER_NETDEV_RX/TRIGGER_NETDEV_TX in
+mtk_phy_led_hw_ctrl_set(), which improves readability.
+
+Signed-off-by: SkyLake.Huang <skylake.huang@mediatek.com>
+---
+ drivers/net/phy/mediatek/mtk-phy-lib.c | 44 ++++++++++++++------------
+ 1 file changed, 24 insertions(+), 20 deletions(-)
+
+--- a/drivers/net/phy/mediatek/mtk-phy-lib.c
++++ b/drivers/net/phy/mediatek/mtk-phy-lib.c
+@@ -127,29 +127,33 @@ int mtk_phy_led_hw_ctrl_set(struct phy_d
+ on |= MTK_PHY_LED_ON_LINK2500;
+
+ if (rules & BIT(TRIGGER_NETDEV_RX)) {
+- blink |= (on & on_set) ?
+- (((on & MTK_PHY_LED_ON_LINK10) ?
+- MTK_PHY_LED_BLINK_10RX : 0) |
+- ((on & MTK_PHY_LED_ON_LINK100) ?
+- MTK_PHY_LED_BLINK_100RX : 0) |
+- ((on & MTK_PHY_LED_ON_LINK1000) ?
+- MTK_PHY_LED_BLINK_1000RX : 0) |
+- ((on & MTK_PHY_LED_ON_LINK2500) ?
+- MTK_PHY_LED_BLINK_2500RX : 0)) :
+- rx_blink_set;
++ if (on & on_set) {
++ if (on & MTK_PHY_LED_ON_LINK10)
++ blink |= MTK_PHY_LED_BLINK_10RX;
++ if (on & MTK_PHY_LED_ON_LINK100)
++ blink |= MTK_PHY_LED_BLINK_100RX;
++ if (on & MTK_PHY_LED_ON_LINK1000)
++ blink |= MTK_PHY_LED_BLINK_1000RX;
++ if (on & MTK_PHY_LED_ON_LINK2500)
++ blink |= MTK_PHY_LED_BLINK_2500RX;
++ } else {
++ blink |= rx_blink_set;
++ }
+ }
+
+ if (rules & BIT(TRIGGER_NETDEV_TX)) {
+- blink |= (on & on_set) ?
+- (((on & MTK_PHY_LED_ON_LINK10) ?
+- MTK_PHY_LED_BLINK_10TX : 0) |
+- ((on & MTK_PHY_LED_ON_LINK100) ?
+- MTK_PHY_LED_BLINK_100TX : 0) |
+- ((on & MTK_PHY_LED_ON_LINK1000) ?
+- MTK_PHY_LED_BLINK_1000TX : 0) |
+- ((on & MTK_PHY_LED_ON_LINK2500) ?
+- MTK_PHY_LED_BLINK_2500TX : 0)) :
+- tx_blink_set;
++ if (on & on_set) {
++ if (on & MTK_PHY_LED_ON_LINK10)
++ blink |= MTK_PHY_LED_BLINK_10TX;
++ if (on & MTK_PHY_LED_ON_LINK100)
++ blink |= MTK_PHY_LED_BLINK_100TX;
++ if (on & MTK_PHY_LED_ON_LINK1000)
++ blink |= MTK_PHY_LED_BLINK_1000TX;
++ if (on & MTK_PHY_LED_ON_LINK2500)
++ blink |= MTK_PHY_LED_BLINK_2500TX;
++ } else {
++ blink |= tx_blink_set;
++ }
+ }
+
+ if (blink || on)
--- /dev/null
+From 59e7082cb8c8e89bceb44cc60df156d818c8da96 Mon Sep 17 00:00:00 2001
+From: "SkyLake.Huang" <skylake.huang@mediatek.com>
+Date: Fri, 4 Oct 2024 18:24:09 +0800
+Subject: [PATCH 5/9] net: phy: mediatek: Integrate read/write page helper
+ functions
+
+This patch integrates read/write page helper functions as MTK phy lib.
+They are basically the same in mtk-ge.c & mtk-ge-soc.c.
+
+Signed-off-by: SkyLake.Huang <skylake.huang@mediatek.com>
+---
+ drivers/net/phy/mediatek/mtk-ge-soc.c | 18 ++++--------------
+ drivers/net/phy/mediatek/mtk-ge.c | 20 ++++++--------------
+ drivers/net/phy/mediatek/mtk-phy-lib.c | 12 ++++++++++++
+ drivers/net/phy/mediatek/mtk.h | 3 +++
+ 4 files changed, 25 insertions(+), 28 deletions(-)
+
+--- a/drivers/net/phy/mediatek/mtk-ge-soc.c
++++ b/drivers/net/phy/mediatek/mtk-ge-soc.c
+@@ -275,16 +275,6 @@ struct mtk_socphy_shared {
+ struct mtk_socphy_priv priv[4];
+ };
+
+-static int mtk_socphy_read_page(struct phy_device *phydev)
+-{
+- return __phy_read(phydev, MTK_EXT_PAGE_ACCESS);
+-}
+-
+-static int mtk_socphy_write_page(struct phy_device *phydev, int page)
+-{
+- return __phy_write(phydev, MTK_EXT_PAGE_ACCESS, page);
+-}
+-
+ /* One calibration cycle consists of:
+ * 1.Set DA_CALIN_FLAG high to start calibration. Keep it high
+ * until AD_CAL_COMP is ready to output calibration result.
+@@ -1305,8 +1295,8 @@ static struct phy_driver mtk_socphy_driv
+ .probe = mt7981_phy_probe,
+ .suspend = genphy_suspend,
+ .resume = genphy_resume,
+- .read_page = mtk_socphy_read_page,
+- .write_page = mtk_socphy_write_page,
++ .read_page = mtk_phy_read_page,
++ .write_page = mtk_phy_write_page,
+ .led_blink_set = mt798x_phy_led_blink_set,
+ .led_brightness_set = mt798x_phy_led_brightness_set,
+ .led_hw_is_supported = mt798x_phy_led_hw_is_supported,
+@@ -1322,8 +1312,8 @@ static struct phy_driver mtk_socphy_driv
+ .probe = mt7988_phy_probe,
+ .suspend = genphy_suspend,
+ .resume = genphy_resume,
+- .read_page = mtk_socphy_read_page,
+- .write_page = mtk_socphy_write_page,
++ .read_page = mtk_phy_read_page,
++ .write_page = mtk_phy_write_page,
+ .led_blink_set = mt798x_phy_led_blink_set,
+ .led_brightness_set = mt798x_phy_led_brightness_set,
+ .led_hw_is_supported = mt798x_phy_led_hw_is_supported,
+--- a/drivers/net/phy/mediatek/mtk-ge.c
++++ b/drivers/net/phy/mediatek/mtk-ge.c
+@@ -4,6 +4,8 @@
+ #include <linux/module.h>
+ #include <linux/phy.h>
+
++#include "mtk.h"
++
+ #define MTK_EXT_PAGE_ACCESS 0x1f
+ #define MTK_PHY_PAGE_STANDARD 0x0000
+ #define MTK_PHY_PAGE_EXTENDED 0x0001
+@@ -12,16 +14,6 @@
+ #define MTK_PHY_PAGE_EXTENDED_2A30 0x2a30
+ #define MTK_PHY_PAGE_EXTENDED_52B5 0x52b5
+
+-static int mtk_gephy_read_page(struct phy_device *phydev)
+-{
+- return __phy_read(phydev, MTK_EXT_PAGE_ACCESS);
+-}
+-
+-static int mtk_gephy_write_page(struct phy_device *phydev, int page)
+-{
+- return __phy_write(phydev, MTK_EXT_PAGE_ACCESS, page);
+-}
+-
+ static void mtk_gephy_config_init(struct phy_device *phydev)
+ {
+ /* Disable EEE */
+@@ -114,8 +106,8 @@ static struct phy_driver mtk_gephy_drive
+ .handle_interrupt = genphy_handle_interrupt_no_ack,
+ .suspend = genphy_suspend,
+ .resume = genphy_resume,
+- .read_page = mtk_gephy_read_page,
+- .write_page = mtk_gephy_write_page,
++ .read_page = mtk_phy_read_page,
++ .write_page = mtk_phy_write_page,
+ },
+ {
+ PHY_ID_MATCH_EXACT(0x03a29441),
+@@ -128,8 +120,8 @@ static struct phy_driver mtk_gephy_drive
+ .handle_interrupt = genphy_handle_interrupt_no_ack,
+ .suspend = genphy_suspend,
+ .resume = genphy_resume,
+- .read_page = mtk_gephy_read_page,
+- .write_page = mtk_gephy_write_page,
++ .read_page = mtk_phy_read_page,
++ .write_page = mtk_phy_write_page,
+ },
+ };
+
+--- a/drivers/net/phy/mediatek/mtk-phy-lib.c
++++ b/drivers/net/phy/mediatek/mtk-phy-lib.c
+@@ -6,6 +6,18 @@
+
+ #include "mtk.h"
+
++int mtk_phy_read_page(struct phy_device *phydev)
++{
++ return __phy_read(phydev, MTK_EXT_PAGE_ACCESS);
++}
++EXPORT_SYMBOL_GPL(mtk_phy_read_page);
++
++int mtk_phy_write_page(struct phy_device *phydev, int page)
++{
++ return __phy_write(phydev, MTK_EXT_PAGE_ACCESS, page);
++}
++EXPORT_SYMBOL_GPL(mtk_phy_write_page);
++
+ int mtk_phy_led_hw_is_supported(struct phy_device *phydev, u8 index,
+ unsigned long rules,
+ unsigned long supported_triggers)
+--- a/drivers/net/phy/mediatek/mtk.h
++++ b/drivers/net/phy/mediatek/mtk.h
+@@ -62,6 +62,9 @@
+ #define MTK_PHY_LED_STATE_FORCE_BLINK 1
+ #define MTK_PHY_LED_STATE_NETDEV 2
+
++int mtk_phy_read_page(struct phy_device *phydev);
++int mtk_phy_write_page(struct phy_device *phydev, int page);
++
+ int mtk_phy_led_hw_is_supported(struct phy_device *phydev, u8 index,
+ unsigned long rules,
+ unsigned long supported_triggers);
--- /dev/null
+From 5b605457b93d0979ab623ef2aa6eb456c46e511c Mon Sep 17 00:00:00 2001
+From: "SkyLake.Huang" <skylake.huang@mediatek.com>
+Date: Fri, 4 Oct 2024 18:24:10 +0800
+Subject: [PATCH 6/9] net: phy: mediatek: Hook LED helper functions in mtk-ge.c
+
+We have mtk-phy-lib.c now so that we can use LED helper functions in
+mtk-ge.c(mt7531 part). It also means that mt7531/mt7981/mt7988's
+Giga ethernet phys share almost the same HW LED controller design.
+Also, add probe function for mt7531 so that it can initialize LED state.
+
+Signed-off-by: SkyLake.Huang <skylake.huang@mediatek.com>
+---
+ drivers/net/phy/mediatek/mtk-ge.c | 100 ++++++++++++++++++++++++++++++
+ 1 file changed, 100 insertions(+)
+
+--- a/drivers/net/phy/mediatek/mtk-ge.c
++++ b/drivers/net/phy/mediatek/mtk-ge.c
+@@ -14,6 +14,10 @@
+ #define MTK_PHY_PAGE_EXTENDED_2A30 0x2a30
+ #define MTK_PHY_PAGE_EXTENDED_52B5 0x52b5
+
++struct mtk_gephy_priv {
++ unsigned long led_state;
++};
++
+ static void mtk_gephy_config_init(struct phy_device *phydev)
+ {
+ /* Disable EEE */
+@@ -94,6 +98,96 @@ static int mt7531_phy_config_init(struct
+ return 0;
+ }
+
++static int mt7531_phy_probe(struct phy_device *phydev)
++{
++ struct mtk_gephy_priv *priv;
++
++ priv = devm_kzalloc(&phydev->mdio.dev, sizeof(struct mtk_gephy_priv),
++ GFP_KERNEL);
++ if (!priv)
++ return -ENOMEM;
++
++ phydev->priv = priv;
++
++ mtk_phy_leds_state_init(phydev);
++
++ return 0;
++}
++
++static int mt753x_phy_led_blink_set(struct phy_device *phydev, u8 index,
++ unsigned long *delay_on,
++ unsigned long *delay_off)
++{
++ struct mtk_gephy_priv *priv = phydev->priv;
++ bool blinking = false;
++ int err = 0;
++
++ err = mtk_phy_led_num_dly_cfg(index, delay_on, delay_off, &blinking);
++ if (err < 0)
++ return err;
++
++ err = mtk_phy_hw_led_blink_set(phydev, index, &priv->led_state,
++ blinking);
++ if (err)
++ return err;
++
++ return mtk_phy_hw_led_on_set(phydev, index, &priv->led_state,
++ MTK_GPHY_LED_ON_MASK, false);
++}
++
++static int mt753x_phy_led_brightness_set(struct phy_device *phydev,
++ u8 index, enum led_brightness value)
++{
++ struct mtk_gephy_priv *priv = phydev->priv;
++ int err;
++
++ err = mtk_phy_hw_led_blink_set(phydev, index, &priv->led_state, false);
++ if (err)
++ return err;
++
++ return mtk_phy_hw_led_on_set(phydev, index, &priv->led_state,
++ MTK_GPHY_LED_ON_MASK, (value != LED_OFF));
++}
++
++static const unsigned long supported_triggers =
++ BIT(TRIGGER_NETDEV_FULL_DUPLEX) |
++ BIT(TRIGGER_NETDEV_HALF_DUPLEX) |
++ BIT(TRIGGER_NETDEV_LINK) |
++ BIT(TRIGGER_NETDEV_LINK_10) |
++ BIT(TRIGGER_NETDEV_LINK_100) |
++ BIT(TRIGGER_NETDEV_LINK_1000) |
++ BIT(TRIGGER_NETDEV_RX) |
++ BIT(TRIGGER_NETDEV_TX);
++
++static int mt753x_phy_led_hw_is_supported(struct phy_device *phydev, u8 index,
++ unsigned long rules)
++{
++ return mtk_phy_led_hw_is_supported(phydev, index, rules,
++ supported_triggers);
++}
++
++static int mt753x_phy_led_hw_control_get(struct phy_device *phydev, u8 index,
++ unsigned long *rules)
++{
++ struct mtk_gephy_priv *priv = phydev->priv;
++
++ return mtk_phy_led_hw_ctrl_get(phydev, index, rules, &priv->led_state,
++ MTK_GPHY_LED_ON_SET,
++ MTK_GPHY_LED_RX_BLINK_SET,
++ MTK_GPHY_LED_TX_BLINK_SET);
++};
++
++static int mt753x_phy_led_hw_control_set(struct phy_device *phydev, u8 index,
++ unsigned long rules)
++{
++ struct mtk_gephy_priv *priv = phydev->priv;
++
++ return mtk_phy_led_hw_ctrl_set(phydev, index, rules, &priv->led_state,
++ MTK_GPHY_LED_ON_SET,
++ MTK_GPHY_LED_RX_BLINK_SET,
++ MTK_GPHY_LED_TX_BLINK_SET);
++};
++
+ static struct phy_driver mtk_gephy_driver[] = {
+ {
+ PHY_ID_MATCH_EXACT(0x03a29412),
+@@ -112,6 +206,7 @@ static struct phy_driver mtk_gephy_drive
+ {
+ PHY_ID_MATCH_EXACT(0x03a29441),
+ .name = "MediaTek MT7531 PHY",
++ .probe = mt7531_phy_probe,
+ .config_init = mt7531_phy_config_init,
+ /* Interrupts are handled by the switch, not the PHY
+ * itself.
+@@ -122,6 +217,11 @@ static struct phy_driver mtk_gephy_drive
+ .resume = genphy_resume,
+ .read_page = mtk_phy_read_page,
+ .write_page = mtk_phy_write_page,
++ .led_blink_set = mt753x_phy_led_blink_set,
++ .led_brightness_set = mt753x_phy_led_brightness_set,
++ .led_hw_is_supported = mt753x_phy_led_hw_is_supported,
++ .led_hw_control_set = mt753x_phy_led_hw_control_set,
++ .led_hw_control_get = mt753x_phy_led_hw_control_get,
+ },
+ };
+
--- /dev/null
+From c5ff7bece642dbba601be89e70f78ff037ca084f Mon Sep 17 00:00:00 2001
+From: "SkyLake.Huang" <skylake.huang@mediatek.com>
+Date: Fri, 4 Oct 2024 18:24:11 +0800
+Subject: [PATCH 7/9] net: phy: mediatek: add MT7530 & MT7531's PHY ID macros
+
+This patch adds MT7530 & MT7531's PHY ID macros in mtk-ge.c so that
+it follows the same rule of mtk-ge-soc.c.
+
+Signed-off-by: SkyLake.Huang <skylake.huang@mediatek.com>
+---
+ drivers/net/phy/mediatek/mtk-ge.c | 11 +++++++----
+ 1 file changed, 7 insertions(+), 4 deletions(-)
+
+--- a/drivers/net/phy/mediatek/mtk-ge.c
++++ b/drivers/net/phy/mediatek/mtk-ge.c
+@@ -6,6 +6,9 @@
+
+ #include "mtk.h"
+
++#define MTK_GPHY_ID_MT7530 0x03a29412
++#define MTK_GPHY_ID_MT7531 0x03a29441
++
+ #define MTK_EXT_PAGE_ACCESS 0x1f
+ #define MTK_PHY_PAGE_STANDARD 0x0000
+ #define MTK_PHY_PAGE_EXTENDED 0x0001
+@@ -190,7 +193,7 @@ static int mt753x_phy_led_hw_control_set
+
+ static struct phy_driver mtk_gephy_driver[] = {
+ {
+- PHY_ID_MATCH_EXACT(0x03a29412),
++ PHY_ID_MATCH_EXACT(MTK_GPHY_ID_MT7530),
+ .name = "MediaTek MT7530 PHY",
+ .config_init = mt7530_phy_config_init,
+ /* Interrupts are handled by the switch, not the PHY
+@@ -204,7 +207,7 @@ static struct phy_driver mtk_gephy_drive
+ .write_page = mtk_phy_write_page,
+ },
+ {
+- PHY_ID_MATCH_EXACT(0x03a29441),
++ PHY_ID_MATCH_EXACT(MTK_GPHY_ID_MT7531),
+ .name = "MediaTek MT7531 PHY",
+ .probe = mt7531_phy_probe,
+ .config_init = mt7531_phy_config_init,
+@@ -228,8 +231,8 @@ static struct phy_driver mtk_gephy_drive
+ module_phy_driver(mtk_gephy_driver);
+
+ static struct mdio_device_id __maybe_unused mtk_gephy_tbl[] = {
+- { PHY_ID_MATCH_EXACT(0x03a29441) },
+- { PHY_ID_MATCH_EXACT(0x03a29412) },
++ { PHY_ID_MATCH_EXACT(MTK_GPHY_ID_MT7530) },
++ { PHY_ID_MATCH_EXACT(MTK_GPHY_ID_MT7531) },
+ { }
+ };
+
--- /dev/null
+From dbe70a9353b5095a90af61a051486484765ada6f Mon Sep 17 00:00:00 2001
+From: "SkyLake.Huang" <skylake.huang@mediatek.com>
+Date: Fri, 4 Oct 2024 18:24:12 +0800
+Subject: [PATCH 8/9] net: phy: mediatek: Change mtk-ge-soc.c line wrapping
+
+This patch shrinks mtk-ge-soc.c line wrapping to 80 characters.
+
+Signed-off-by: SkyLake.Huang <skylake.huang@mediatek.com>
+---
+ drivers/net/phy/mediatek/mtk-ge-soc.c | 67 +++++++++++++++++----------
+ 1 file changed, 42 insertions(+), 25 deletions(-)
+
+--- a/drivers/net/phy/mediatek/mtk-ge-soc.c
++++ b/drivers/net/phy/mediatek/mtk-ge-soc.c
+@@ -295,7 +295,8 @@ static int cal_cycle(struct phy_device *
+ ret = phy_read_mmd_poll_timeout(phydev, MDIO_MMD_VEND1,
+ MTK_PHY_RG_AD_CAL_CLK, reg_val,
+ reg_val & MTK_PHY_DA_CAL_CLK, 500,
+- ANALOG_INTERNAL_OPERATION_MAX_US, false);
++ ANALOG_INTERNAL_OPERATION_MAX_US,
++ false);
+ if (ret) {
+ phydev_err(phydev, "Calibration cycle timeout\n");
+ return ret;
+@@ -304,7 +305,7 @@ static int cal_cycle(struct phy_device *
+ phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_AD_CALIN,
+ MTK_PHY_DA_CALIN_FLAG);
+ ret = phy_read_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_AD_CAL_COMP) >>
+- MTK_PHY_AD_CAL_COMP_OUT_SHIFT;
++ MTK_PHY_AD_CAL_COMP_OUT_SHIFT;
+ phydev_dbg(phydev, "cal_val: 0x%x, ret: %d\n", cal_val, ret);
+
+ return ret;
+@@ -394,38 +395,46 @@ static int tx_amp_fill_result(struct phy
+ }
+
+ phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TXVLD_DA_RG,
+- MTK_PHY_DA_TX_I2MPB_A_GBE_MASK, (buf[0] + bias[0]) << 10);
++ MTK_PHY_DA_TX_I2MPB_A_GBE_MASK,
++ (buf[0] + bias[0]) << 10);
+ phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TXVLD_DA_RG,
+ MTK_PHY_DA_TX_I2MPB_A_TBT_MASK, buf[0] + bias[1]);
+ phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_A2,
+- MTK_PHY_DA_TX_I2MPB_A_HBT_MASK, (buf[0] + bias[2]) << 10);
++ MTK_PHY_DA_TX_I2MPB_A_HBT_MASK,
++ (buf[0] + bias[2]) << 10);
+ phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_A2,
+ MTK_PHY_DA_TX_I2MPB_A_TST_MASK, buf[0] + bias[3]);
+
+ phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_B1,
+- MTK_PHY_DA_TX_I2MPB_B_GBE_MASK, (buf[1] + bias[4]) << 8);
++ MTK_PHY_DA_TX_I2MPB_B_GBE_MASK,
++ (buf[1] + bias[4]) << 8);
+ phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_B1,
+ MTK_PHY_DA_TX_I2MPB_B_TBT_MASK, buf[1] + bias[5]);
+ phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_B2,
+- MTK_PHY_DA_TX_I2MPB_B_HBT_MASK, (buf[1] + bias[6]) << 8);
++ MTK_PHY_DA_TX_I2MPB_B_HBT_MASK,
++ (buf[1] + bias[6]) << 8);
+ phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_B2,
+ MTK_PHY_DA_TX_I2MPB_B_TST_MASK, buf[1] + bias[7]);
+
+ phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_C1,
+- MTK_PHY_DA_TX_I2MPB_C_GBE_MASK, (buf[2] + bias[8]) << 8);
++ MTK_PHY_DA_TX_I2MPB_C_GBE_MASK,
++ (buf[2] + bias[8]) << 8);
+ phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_C1,
+ MTK_PHY_DA_TX_I2MPB_C_TBT_MASK, buf[2] + bias[9]);
+ phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_C2,
+- MTK_PHY_DA_TX_I2MPB_C_HBT_MASK, (buf[2] + bias[10]) << 8);
++ MTK_PHY_DA_TX_I2MPB_C_HBT_MASK,
++ (buf[2] + bias[10]) << 8);
+ phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_C2,
+ MTK_PHY_DA_TX_I2MPB_C_TST_MASK, buf[2] + bias[11]);
+
+ phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_D1,
+- MTK_PHY_DA_TX_I2MPB_D_GBE_MASK, (buf[3] + bias[12]) << 8);
++ MTK_PHY_DA_TX_I2MPB_D_GBE_MASK,
++ (buf[3] + bias[12]) << 8);
+ phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_D1,
+ MTK_PHY_DA_TX_I2MPB_D_TBT_MASK, buf[3] + bias[13]);
+ phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_D2,
+- MTK_PHY_DA_TX_I2MPB_D_HBT_MASK, (buf[3] + bias[14]) << 8);
++ MTK_PHY_DA_TX_I2MPB_D_HBT_MASK,
++ (buf[3] + bias[14]) << 8);
+ phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_D2,
+ MTK_PHY_DA_TX_I2MPB_D_TST_MASK, buf[3] + bias[15]);
+
+@@ -616,7 +625,8 @@ static int tx_vcm_cal_sw(struct phy_devi
+ goto restore;
+
+ /* We calibrate TX-VCM in different logic. Check upper index and then
+- * lower index. If this calibration is valid, apply lower index's result.
++ * lower index. If this calibration is valid, apply lower index's
++ * result.
+ */
+ ret = upper_ret - lower_ret;
+ if (ret == 1) {
+@@ -645,7 +655,8 @@ static int tx_vcm_cal_sw(struct phy_devi
+ } else if (upper_idx == TXRESERVE_MAX && upper_ret == 0 &&
+ lower_ret == 0) {
+ ret = 0;
+- phydev_warn(phydev, "TX-VCM SW cal result at high margin 0x%x\n",
++ phydev_warn(phydev,
++ "TX-VCM SW cal result at high margin 0x%x\n",
+ upper_idx);
+ } else {
+ ret = -EINVAL;
+@@ -749,7 +760,8 @@ static void mt7981_phy_finetune(struct p
+
+ /* TR_OPEN_LOOP_EN = 1, lpf_x_average = 9 */
+ phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG234,
+- MTK_PHY_TR_OPEN_LOOP_EN_MASK | MTK_PHY_LPF_X_AVERAGE_MASK,
++ MTK_PHY_TR_OPEN_LOOP_EN_MASK |
++ MTK_PHY_LPF_X_AVERAGE_MASK,
+ BIT(0) | FIELD_PREP(MTK_PHY_LPF_X_AVERAGE_MASK, 0x9));
+
+ /* rg_tr_lpf_cnt_val = 512 */
+@@ -818,7 +830,8 @@ static void mt7988_phy_finetune(struct p
+
+ /* TR_OPEN_LOOP_EN = 1, lpf_x_average = 10 */
+ phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG234,
+- MTK_PHY_TR_OPEN_LOOP_EN_MASK | MTK_PHY_LPF_X_AVERAGE_MASK,
++ MTK_PHY_TR_OPEN_LOOP_EN_MASK |
++ MTK_PHY_LPF_X_AVERAGE_MASK,
+ BIT(0) | FIELD_PREP(MTK_PHY_LPF_X_AVERAGE_MASK, 0xa));
+
+ /* rg_tr_lpf_cnt_val = 1023 */
+@@ -930,7 +943,8 @@ static void mt798x_phy_eee(struct phy_de
+ phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0);
+
+ phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_3);
+- __phy_modify(phydev, MTK_PHY_LPI_REG_14, MTK_PHY_LPI_WAKE_TIMER_1000_MASK,
++ __phy_modify(phydev, MTK_PHY_LPI_REG_14,
++ MTK_PHY_LPI_WAKE_TIMER_1000_MASK,
+ FIELD_PREP(MTK_PHY_LPI_WAKE_TIMER_1000_MASK, 0x19c));
+
+ __phy_modify(phydev, MTK_PHY_LPI_REG_1c, MTK_PHY_SMI_DET_ON_THRESH_MASK,
+@@ -940,7 +954,8 @@ static void mt798x_phy_eee(struct phy_de
+ phy_modify_mmd(phydev, MDIO_MMD_VEND1,
+ MTK_PHY_RG_LPI_PCS_DSP_CTRL_REG122,
+ MTK_PHY_LPI_NORM_MSE_HI_THRESH1000_MASK,
+- FIELD_PREP(MTK_PHY_LPI_NORM_MSE_HI_THRESH1000_MASK, 0xff));
++ FIELD_PREP(MTK_PHY_LPI_NORM_MSE_HI_THRESH1000_MASK,
++ 0xff));
+ }
+
+ static int cal_sw(struct phy_device *phydev, enum CAL_ITEM cal_item,
+@@ -1119,14 +1134,15 @@ static int mt798x_phy_led_brightness_set
+ MTK_GPHY_LED_ON_MASK, (value != LED_OFF));
+ }
+
+-static const unsigned long supported_triggers = (BIT(TRIGGER_NETDEV_FULL_DUPLEX) |
+- BIT(TRIGGER_NETDEV_HALF_DUPLEX) |
+- BIT(TRIGGER_NETDEV_LINK) |
+- BIT(TRIGGER_NETDEV_LINK_10) |
+- BIT(TRIGGER_NETDEV_LINK_100) |
+- BIT(TRIGGER_NETDEV_LINK_1000) |
+- BIT(TRIGGER_NETDEV_RX) |
+- BIT(TRIGGER_NETDEV_TX));
++static const unsigned long supported_triggers =
++ (BIT(TRIGGER_NETDEV_FULL_DUPLEX) |
++ BIT(TRIGGER_NETDEV_HALF_DUPLEX) |
++ BIT(TRIGGER_NETDEV_LINK) |
++ BIT(TRIGGER_NETDEV_LINK_10) |
++ BIT(TRIGGER_NETDEV_LINK_100) |
++ BIT(TRIGGER_NETDEV_LINK_1000) |
++ BIT(TRIGGER_NETDEV_RX) |
++ BIT(TRIGGER_NETDEV_TX));
+
+ static int mt798x_phy_led_hw_is_supported(struct phy_device *phydev, u8 index,
+ unsigned long rules)
+@@ -1189,7 +1205,8 @@ static int mt7988_phy_fix_leds_polaritie
+ /* Only now setup pinctrl to avoid bogus blinking */
+ pinctrl = devm_pinctrl_get_select(&phydev->mdio.dev, "gbe-led");
+ if (IS_ERR(pinctrl))
+- dev_err(&phydev->mdio.bus->dev, "Failed to setup PHY LED pinctrl\n");
++ dev_err(&phydev->mdio.bus->dev,
++ "Failed to setup PHY LED pinctrl\n");
+
+ return 0;
+ }
--- /dev/null
+From ca024bc7267a8c0439325d352f9b8818ba0f2cf0 Mon Sep 17 00:00:00 2001
+From: "SkyLake.Huang" <skylake.huang@mediatek.com>
+Date: Fri, 4 Oct 2024 18:24:13 +0800
+Subject: [PATCH 9/9] net: phy: mediatek: Add token ring access helper
+ functions in mtk-phy-lib
+
+This patch adds TR(token ring) manipulations and adds correct
+macro names for those magic numbers. TR is a way to access
+proprietary registers on page 52b5. Use these helper functions
+so we can see which fields we're going to modify/set/clear.
+
+This patch doesn't really change registers' settings but just
+enhances readability and maintainability.
+
+Signed-off-by: SkyLake.Huang <skylake.huang@mediatek.com>
+---
+ drivers/net/phy/mediatek/mtk-ge-soc.c | 297 ++++++++++++++++---------
+ drivers/net/phy/mediatek/mtk-ge.c | 82 +++++--
+ drivers/net/phy/mediatek/mtk-phy-lib.c | 91 ++++++++
+ drivers/net/phy/mediatek/mtk.h | 13 ++
+ 4 files changed, 358 insertions(+), 125 deletions(-)
+
+--- a/drivers/net/phy/mediatek/mtk-ge-soc.c
++++ b/drivers/net/phy/mediatek/mtk-ge-soc.c
+@@ -24,7 +24,108 @@
+ #define MTK_PHY_SMI_DET_ON_THRESH_MASK GENMASK(13, 8)
+
+ #define MTK_PHY_PAGE_EXTENDED_2A30 0x2a30
+-#define MTK_PHY_PAGE_EXTENDED_52B5 0x52b5
++
++/* Registers on Token Ring debug nodes */
++/* ch_addr = 0x0, node_addr = 0x7, data_addr = 0x15 */
++/* NormMseLoThresh */
++#define NORMAL_MSE_LO_THRESH_MASK GENMASK(15, 8)
++
++/* ch_addr = 0x0, node_addr = 0xf, data_addr = 0x3c */
++/* RemAckCntLimitCtrl */
++#define REMOTE_ACK_COUNT_LIMIT_CTRL_MASK GENMASK(2, 1)
++
++/* ch_addr = 0x1, node_addr = 0xd, data_addr = 0x20 */
++/* VcoSlicerThreshBitsHigh */
++#define VCO_SLICER_THRESH_HIGH_MASK GENMASK(23, 0)
++
++/* ch_addr = 0x1, node_addr = 0xf, data_addr = 0x0 */
++/* DfeTailEnableVgaThresh1000 */
++#define DFE_TAIL_EANBLE_VGA_TRHESH_1000 GENMASK(5, 1)
++
++/* ch_addr = 0x1, node_addr = 0xf, data_addr = 0x1 */
++/* MrvlTrFix100Kp */
++#define MRVL_TR_FIX_100KP_MASK GENMASK(22, 20)
++/* MrvlTrFix100Kf */
++#define MRVL_TR_FIX_100KF_MASK GENMASK(19, 17)
++/* MrvlTrFix1000Kp */
++#define MRVL_TR_FIX_1000KP_MASK GENMASK(16, 14)
++/* MrvlTrFix1000Kf */
++#define MRVL_TR_FIX_1000KF_MASK GENMASK(13, 11)
++
++/* ch_addr = 0x1, node_addr = 0xf, data_addr = 0x12 */
++/* VgaDecRate */
++#define VGA_DECIMATION_RATE_MASK GENMASK(8, 5)
++
++/* ch_addr = 0x1, node_addr = 0xf, data_addr = 0x17 */
++/* SlvDSPreadyTime */
++#define SLAVE_DSP_READY_TIME_MASK GENMASK(22, 15)
++/* MasDSPreadyTime */
++#define MASTER_DSP_READY_TIME_MASK GENMASK(14, 7)
++
++/* ch_addr = 0x1, node_addr = 0xf, data_addr = 0x18 */
++/* EnabRandUpdTrig */
++#define ENABLE_RANDOM_UPDOWN_COUNTER_TRIGGER BIT(8)
++
++/* ch_addr = 0x1, node_addr = 0xf, data_addr = 0x20 */
++/* ResetSyncOffset */
++#define RESET_SYNC_OFFSET_MASK GENMASK(11, 8)
++
++/* ch_addr = 0x2, node_addr = 0xd, data_addr = 0x0 */
++/* FfeUpdGainForceVal */
++#define FFE_UPDATE_GAIN_FORCE_VAL_MASK GENMASK(9, 7)
++/* FfeUpdGainForce */
++#define FFE_UPDATE_GAIN_FORCE BIT(6)
++
++/* ch_addr = 0x2, node_addr = 0xd, data_addr = 0x3 */
++/* TrFreeze */
++#define TR_FREEZE_MASK GENMASK(11, 0)
++
++/* ch_addr = 0x2, node_addr = 0xd, data_addr = 0x6 */
++/* SS: Steady-state, KP: Proportional Gain */
++/* SSTrKp100 */
++#define SS_TR_KP100_MASK GENMASK(21, 19)
++/* SSTrKf100 */
++#define SS_TR_KF100_MASK GENMASK(18, 16)
++/* SSTrKp1000Mas */
++#define SS_TR_KP1000_MASTER_MASK GENMASK(15, 13)
++/* SSTrKf1000Mas */
++#define SS_TR_KF1000_MASTER_MASK GENMASK(12, 10)
++/* SSTrKp1000Slv */
++#define SS_TR_KP1000_SLAVE_MASK GENMASK(9, 7)
++/* SSTrKf1000Slv */
++#define SS_TR_KF1000_SLAVE_MASK GENMASK(6, 4)
++
++/* ch_addr = 0x2, node_addr = 0xd, data_addr = 0x8 */
++/* clear this bit if wanna select from AFE */
++/* Regsigdet_sel_1000 */
++#define EEE1000_SELECT_SIGNAL_DETECTION_FROM_DFE BIT(4)
++
++/* ch_addr = 0x2, node_addr = 0xd, data_addr = 0xd */
++/* RegEEE_st2TrKf1000 */
++#define EEE1000_STAGE2_TR_KF_MASK GENMASK(13, 11)
++
++/* ch_addr = 0x2, node_addr = 0xd, data_addr = 0xf */
++/* RegEEE_slv_waketr_timer_tar */
++#define SLAVE_WAKETR_TIMER_MASK GENMASK(20, 11)
++/* RegEEE_slv_remtx_timer_tar */
++#define SLAVE_REMTX_TIMER_MASK GENMASK(10, 1)
++
++/* ch_addr = 0x2, node_addr = 0xd, data_addr = 0x10 */
++/* RegEEE_slv_wake_int_timer_tar */
++#define SLAVE_WAKEINT_TIMER_MASK GENMASK(10, 1)
++
++/* ch_addr = 0x2, node_addr = 0xd, data_addr = 0x14 */
++/* RegEEE_trfreeze_timer2 */
++#define TR_FREEZE_TIMER2_MASK GENMASK(9, 0)
++
++/* ch_addr = 0x2, node_addr = 0xd, data_addr = 0x1c */
++/* RegEEE100Stg1_tar */
++#define EEE100_LPSYNC_STAGE1_UPDATE_TIMER_MASK GENMASK(8, 0)
++
++/* ch_addr = 0x2, node_addr = 0xd, data_addr = 0x25 */
++/* REGEEE_wake_slv_tr_wait_dfesigdet_en */
++#define WAKE_SLAVE_TR_WAIT_DFE_DETECTION_EN BIT(11)
++
+
+ #define ANALOG_INTERNAL_OPERATION_MAX_US 20
+ #define TXRESERVE_MIN 0
+@@ -679,40 +780,36 @@ restore:
+ static void mt798x_phy_common_finetune(struct phy_device *phydev)
+ {
+ phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_52B5);
+- /* SlvDSPreadyTime = 24, MasDSPreadyTime = 24 */
+- __phy_write(phydev, 0x11, 0xc71);
+- __phy_write(phydev, 0x12, 0xc);
+- __phy_write(phydev, 0x10, 0x8fae);
+-
+- /* EnabRandUpdTrig = 1 */
+- __phy_write(phydev, 0x11, 0x2f00);
+- __phy_write(phydev, 0x12, 0xe);
+- __phy_write(phydev, 0x10, 0x8fb0);
+-
+- /* NormMseLoThresh = 85 */
+- __phy_write(phydev, 0x11, 0x55a0);
+- __phy_write(phydev, 0x12, 0x0);
+- __phy_write(phydev, 0x10, 0x83aa);
+-
+- /* FfeUpdGainForce = 1(Enable), FfeUpdGainForceVal = 4 */
+- __phy_write(phydev, 0x11, 0x240);
+- __phy_write(phydev, 0x12, 0x0);
+- __phy_write(phydev, 0x10, 0x9680);
+-
+- /* TrFreeze = 0 (mt7988 default) */
+- __phy_write(phydev, 0x11, 0x0);
+- __phy_write(phydev, 0x12, 0x0);
+- __phy_write(phydev, 0x10, 0x9686);
+-
+- /* SSTrKp100 = 5 */
+- /* SSTrKf100 = 6 */
+- /* SSTrKp1000Mas = 5 */
+- /* SSTrKf1000Mas = 6 */
+- /* SSTrKp1000Slv = 5 */
+- /* SSTrKf1000Slv = 6 */
+- __phy_write(phydev, 0x11, 0xbaef);
+- __phy_write(phydev, 0x12, 0x2e);
+- __phy_write(phydev, 0x10, 0x968c);
++ __mtk_tr_modify(phydev, 0x1, 0xf, 0x17,
++ SLAVE_DSP_READY_TIME_MASK | MASTER_DSP_READY_TIME_MASK,
++ FIELD_PREP(SLAVE_DSP_READY_TIME_MASK, 0x18) |
++ FIELD_PREP(MASTER_DSP_READY_TIME_MASK, 0x18));
++
++ __mtk_tr_set_bits(phydev, 0x1, 0xf, 0x18,
++ ENABLE_RANDOM_UPDOWN_COUNTER_TRIGGER);
++
++ __mtk_tr_modify(phydev, 0x0, 0x7, 0x15,
++ NORMAL_MSE_LO_THRESH_MASK,
++ FIELD_PREP(NORMAL_MSE_LO_THRESH_MASK, 0x55));
++
++ __mtk_tr_modify(phydev, 0x2, 0xd, 0x0,
++ FFE_UPDATE_GAIN_FORCE_VAL_MASK,
++ FIELD_PREP(FFE_UPDATE_GAIN_FORCE_VAL_MASK, 0x4) |
++ FFE_UPDATE_GAIN_FORCE);
++
++ __mtk_tr_clr_bits(phydev, 0x2, 0xd, 0x3, TR_FREEZE_MASK);
++
++ __mtk_tr_modify(phydev, 0x2, 0xd, 0x6,
++ SS_TR_KP100_MASK | SS_TR_KF100_MASK |
++ SS_TR_KP1000_MASTER_MASK | SS_TR_KF1000_MASTER_MASK |
++ SS_TR_KP1000_SLAVE_MASK | SS_TR_KF1000_SLAVE_MASK,
++ FIELD_PREP(SS_TR_KP100_MASK, 0x5) |
++ FIELD_PREP(SS_TR_KF100_MASK, 0x6) |
++ FIELD_PREP(SS_TR_KP1000_MASTER_MASK, 0x5) |
++ FIELD_PREP(SS_TR_KF1000_MASTER_MASK, 0x6) |
++ FIELD_PREP(SS_TR_KP1000_SLAVE_MASK, 0x5) |
++ FIELD_PREP(SS_TR_KF1000_SLAVE_MASK, 0x6));
++
+ phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0);
+ }
+
+@@ -735,27 +832,29 @@ static void mt7981_phy_finetune(struct p
+ }
+
+ phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_52B5);
+- /* ResetSyncOffset = 6 */
+- __phy_write(phydev, 0x11, 0x600);
+- __phy_write(phydev, 0x12, 0x0);
+- __phy_write(phydev, 0x10, 0x8fc0);
+-
+- /* VgaDecRate = 1 */
+- __phy_write(phydev, 0x11, 0x4c2a);
+- __phy_write(phydev, 0x12, 0x3e);
+- __phy_write(phydev, 0x10, 0x8fa4);
++ __mtk_tr_modify(phydev, 0x1, 0xf, 0x20,
++ RESET_SYNC_OFFSET_MASK,
++ FIELD_PREP(RESET_SYNC_OFFSET_MASK, 0x6));
++
++ __mtk_tr_modify(phydev, 0x1, 0xf, 0x12,
++ VGA_DECIMATION_RATE_MASK,
++ FIELD_PREP(VGA_DECIMATION_RATE_MASK, 0x1));
+
+ /* MrvlTrFix100Kp = 3, MrvlTrFix100Kf = 2,
+ * MrvlTrFix1000Kp = 3, MrvlTrFix1000Kf = 2
+ */
+- __phy_write(phydev, 0x11, 0xd10a);
+- __phy_write(phydev, 0x12, 0x34);
+- __phy_write(phydev, 0x10, 0x8f82);
++ __mtk_tr_modify(phydev, 0x1, 0xf, 0x1,
++ MRVL_TR_FIX_100KP_MASK | MRVL_TR_FIX_100KF_MASK |
++ MRVL_TR_FIX_1000KP_MASK | MRVL_TR_FIX_1000KF_MASK,
++ FIELD_PREP(MRVL_TR_FIX_100KP_MASK, 0x3) |
++ FIELD_PREP(MRVL_TR_FIX_100KF_MASK, 0x2) |
++ FIELD_PREP(MRVL_TR_FIX_1000KP_MASK, 0x3) |
++ FIELD_PREP(MRVL_TR_FIX_1000KF_MASK, 0x2));
+
+ /* VcoSlicerThreshBitsHigh */
+- __phy_write(phydev, 0x11, 0x5555);
+- __phy_write(phydev, 0x12, 0x55);
+- __phy_write(phydev, 0x10, 0x8ec0);
++ __mtk_tr_modify(phydev, 0x1, 0xd, 0x20,
++ VCO_SLICER_THRESH_HIGH_MASK,
++ FIELD_PREP(VCO_SLICER_THRESH_HIGH_MASK, 0x555555));
+ phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0);
+
+ /* TR_OPEN_LOOP_EN = 1, lpf_x_average = 9 */
+@@ -807,25 +906,23 @@ static void mt7988_phy_finetune(struct p
+ phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_TX_FILTER, 0x5);
+
+ phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_52B5);
+- /* ResetSyncOffset = 5 */
+- __phy_write(phydev, 0x11, 0x500);
+- __phy_write(phydev, 0x12, 0x0);
+- __phy_write(phydev, 0x10, 0x8fc0);
++ __mtk_tr_modify(phydev, 0x1, 0xf, 0x20,
++ RESET_SYNC_OFFSET_MASK,
++ FIELD_PREP(RESET_SYNC_OFFSET_MASK, 0x5));
+
+ /* VgaDecRate is 1 at default on mt7988 */
+
+- /* MrvlTrFix100Kp = 6, MrvlTrFix100Kf = 7,
+- * MrvlTrFix1000Kp = 6, MrvlTrFix1000Kf = 7
+- */
+- __phy_write(phydev, 0x11, 0xb90a);
+- __phy_write(phydev, 0x12, 0x6f);
+- __phy_write(phydev, 0x10, 0x8f82);
+-
+- /* RemAckCntLimitCtrl = 1 */
+- __phy_write(phydev, 0x11, 0xfbba);
+- __phy_write(phydev, 0x12, 0xc3);
+- __phy_write(phydev, 0x10, 0x87f8);
+-
++ __mtk_tr_modify(phydev, 0x1, 0xf, 0x1,
++ MRVL_TR_FIX_100KP_MASK | MRVL_TR_FIX_100KF_MASK |
++ MRVL_TR_FIX_1000KP_MASK | MRVL_TR_FIX_1000KF_MASK,
++ FIELD_PREP(MRVL_TR_FIX_100KP_MASK, 0x6) |
++ FIELD_PREP(MRVL_TR_FIX_100KF_MASK, 0x7) |
++ FIELD_PREP(MRVL_TR_FIX_1000KP_MASK, 0x6) |
++ FIELD_PREP(MRVL_TR_FIX_1000KF_MASK, 0x7));
++
++ __mtk_tr_modify(phydev, 0x0, 0xf, 0x3c,
++ REMOTE_ACK_COUNT_LIMIT_CTRL_MASK,
++ FIELD_PREP(REMOTE_ACK_COUNT_LIMIT_CTRL_MASK, 0x1));
+ phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0);
+
+ /* TR_OPEN_LOOP_EN = 1, lpf_x_average = 10 */
+@@ -901,45 +998,37 @@ static void mt798x_phy_eee(struct phy_de
+ MTK_PHY_TR_READY_SKIP_AFE_WAKEUP);
+
+ phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_52B5);
+- /* Regsigdet_sel_1000 = 0 */
+- __phy_write(phydev, 0x11, 0xb);
+- __phy_write(phydev, 0x12, 0x0);
+- __phy_write(phydev, 0x10, 0x9690);
+-
+- /* REG_EEE_st2TrKf1000 = 2 */
+- __phy_write(phydev, 0x11, 0x114f);
+- __phy_write(phydev, 0x12, 0x2);
+- __phy_write(phydev, 0x10, 0x969a);
+-
+- /* RegEEE_slv_wake_tr_timer_tar = 6, RegEEE_slv_remtx_timer_tar = 20 */
+- __phy_write(phydev, 0x11, 0x3028);
+- __phy_write(phydev, 0x12, 0x0);
+- __phy_write(phydev, 0x10, 0x969e);
+-
+- /* RegEEE_slv_wake_int_timer_tar = 8 */
+- __phy_write(phydev, 0x11, 0x5010);
+- __phy_write(phydev, 0x12, 0x0);
+- __phy_write(phydev, 0x10, 0x96a0);
+-
+- /* RegEEE_trfreeze_timer2 = 586 */
+- __phy_write(phydev, 0x11, 0x24a);
+- __phy_write(phydev, 0x12, 0x0);
+- __phy_write(phydev, 0x10, 0x96a8);
+-
+- /* RegEEE100Stg1_tar = 16 */
+- __phy_write(phydev, 0x11, 0x3210);
+- __phy_write(phydev, 0x12, 0x0);
+- __phy_write(phydev, 0x10, 0x96b8);
+-
+- /* REGEEE_wake_slv_tr_wait_dfesigdet_en = 0 */
+- __phy_write(phydev, 0x11, 0x1463);
+- __phy_write(phydev, 0x12, 0x0);
+- __phy_write(phydev, 0x10, 0x96ca);
+-
+- /* DfeTailEnableVgaThresh1000 = 27 */
+- __phy_write(phydev, 0x11, 0x36);
+- __phy_write(phydev, 0x12, 0x0);
+- __phy_write(phydev, 0x10, 0x8f80);
++ __mtk_tr_clr_bits(phydev, 0x2, 0xd, 0x8,
++ EEE1000_SELECT_SIGNAL_DETECTION_FROM_DFE);
++
++ __mtk_tr_modify(phydev, 0x2, 0xd, 0xd,
++ EEE1000_STAGE2_TR_KF_MASK,
++ FIELD_PREP(EEE1000_STAGE2_TR_KF_MASK, 0x2));
++
++ __mtk_tr_modify(phydev, 0x2, 0xd, 0xf,
++ SLAVE_WAKETR_TIMER_MASK | SLAVE_REMTX_TIMER_MASK,
++ FIELD_PREP(SLAVE_WAKETR_TIMER_MASK, 0x6) |
++ FIELD_PREP(SLAVE_REMTX_TIMER_MASK, 0x14));
++
++ __mtk_tr_modify(phydev, 0x2, 0xd, 0x10,
++ SLAVE_WAKEINT_TIMER_MASK,
++ FIELD_PREP(SLAVE_WAKEINT_TIMER_MASK, 0x8));
++
++ __mtk_tr_modify(phydev, 0x2, 0xd, 0x14,
++ TR_FREEZE_TIMER2_MASK,
++ FIELD_PREP(TR_FREEZE_TIMER2_MASK, 0x24a));
++
++ __mtk_tr_modify(phydev, 0x2, 0xd, 0x1c,
++ EEE100_LPSYNC_STAGE1_UPDATE_TIMER_MASK,
++ FIELD_PREP(EEE100_LPSYNC_STAGE1_UPDATE_TIMER_MASK,
++ 0x10));
++
++ __mtk_tr_clr_bits(phydev, 0x2, 0xd, 0x25,
++ WAKE_SLAVE_TR_WAIT_DFE_DETECTION_EN);
++
++ __mtk_tr_modify(phydev, 0x1, 0xf, 0x0,
++ DFE_TAIL_EANBLE_VGA_TRHESH_1000,
++ FIELD_PREP(DFE_TAIL_EANBLE_VGA_TRHESH_1000, 0x1b));
+ phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0);
+
+ phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_3);
+--- a/drivers/net/phy/mediatek/mtk-ge.c
++++ b/drivers/net/phy/mediatek/mtk-ge.c
+@@ -9,13 +9,35 @@
+ #define MTK_GPHY_ID_MT7530 0x03a29412
+ #define MTK_GPHY_ID_MT7531 0x03a29441
+
+-#define MTK_EXT_PAGE_ACCESS 0x1f
+-#define MTK_PHY_PAGE_STANDARD 0x0000
+-#define MTK_PHY_PAGE_EXTENDED 0x0001
+-#define MTK_PHY_PAGE_EXTENDED_2 0x0002
+-#define MTK_PHY_PAGE_EXTENDED_3 0x0003
+-#define MTK_PHY_PAGE_EXTENDED_2A30 0x2a30
+-#define MTK_PHY_PAGE_EXTENDED_52B5 0x52b5
++#define MTK_PHY_PAGE_EXTENDED_1 0x0001
++#define MTK_PHY_AUX_CTRL_AND_STATUS 0x14
++#define MTK_PHY_ENABLE_DOWNSHIFT BIT(4)
++
++#define MTK_PHY_PAGE_EXTENDED_2 0x0002
++#define MTK_PHY_PAGE_EXTENDED_3 0x0003
++#define MTK_PHY_RG_LPI_PCS_DSP_CTRL_REG11 0x11
++
++#define MTK_PHY_PAGE_EXTENDED_2A30 0x2a30
++
++/* Registers on Token Ring debug nodes */
++/* ch_addr = 0x1, node_addr = 0xf, data_addr = 0x17 */
++#define SLAVE_DSP_READY_TIME_MASK GENMASK(22, 15)
++
++/* Registers on MDIO_MMD_VEND1 */
++#define MTK_PHY_GBE_MODE_TX_DELAY_SEL 0x13
++#define MTK_PHY_TEST_MODE_TX_DELAY_SEL 0x14
++#define MTK_TX_DELAY_PAIR_B_MASK GENMASK(10, 8)
++#define MTK_TX_DELAY_PAIR_D_MASK GENMASK(2, 0)
++
++#define MTK_PHY_MCC_CTRL_AND_TX_POWER_CTRL 0xa6
++#define MTK_MCC_NEARECHO_OFFSET_MASK GENMASK(15, 8)
++
++#define MTK_PHY_RXADC_CTRL_RG7 0xc6
++#define MTK_PHY_DA_AD_BUF_BIAS_LP_MASK GENMASK(9, 8)
++
++#define MTK_PHY_RG_LPI_PCS_DSP_CTRL_REG123 0x123
++#define MTK_PHY_LPI_NORM_MSE_LO_THRESH100_MASK GENMASK(15, 8)
++#define MTK_PHY_LPI_NORM_MSE_HI_THRESH100_MASK GENMASK(7, 0)
+
+ struct mtk_gephy_priv {
+ unsigned long led_state;
+@@ -27,20 +49,29 @@ static void mtk_gephy_config_init(struct
+ phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_EEE_ADV, 0);
+
+ /* Enable HW auto downshift */
+- phy_modify_paged(phydev, MTK_PHY_PAGE_EXTENDED, 0x14, 0, BIT(4));
++ phy_modify_paged(phydev, MTK_PHY_PAGE_EXTENDED_1,
++ MTK_PHY_AUX_CTRL_AND_STATUS,
++ 0, MTK_PHY_ENABLE_DOWNSHIFT);
+
+ /* Increase SlvDPSready time */
+- phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_52B5);
+- __phy_write(phydev, 0x10, 0xafae);
+- __phy_write(phydev, 0x12, 0x2f);
+- __phy_write(phydev, 0x10, 0x8fae);
+- phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0);
++ mtk_tr_modify(phydev, 0x1, 0xf, 0x17, SLAVE_DSP_READY_TIME_MASK,
++ FIELD_PREP(SLAVE_DSP_READY_TIME_MASK, 0x5e));
+
+ /* Adjust 100_mse_threshold */
+- phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x123, 0xffff);
+-
+- /* Disable mcc */
+- phy_write_mmd(phydev, MDIO_MMD_VEND1, 0xa6, 0x300);
++ phy_modify_mmd(phydev, MDIO_MMD_VEND1,
++ MTK_PHY_RG_LPI_PCS_DSP_CTRL_REG123,
++ MTK_PHY_LPI_NORM_MSE_LO_THRESH100_MASK |
++ MTK_PHY_LPI_NORM_MSE_HI_THRESH100_MASK,
++ FIELD_PREP(MTK_PHY_LPI_NORM_MSE_LO_THRESH100_MASK,
++ 0xff) |
++ FIELD_PREP(MTK_PHY_LPI_NORM_MSE_HI_THRESH100_MASK,
++ 0xff));
++
++ /* If echo time is narrower than 0x3, it will be regarded as noise */
++ phy_modify_mmd(phydev, MDIO_MMD_VEND1,
++ MTK_PHY_MCC_CTRL_AND_TX_POWER_CTRL,
++ MTK_MCC_NEARECHO_OFFSET_MASK,
++ FIELD_PREP(MTK_MCC_NEARECHO_OFFSET_MASK, 0x3));
+ }
+
+ static int mt7530_phy_config_init(struct phy_device *phydev)
+@@ -48,7 +79,8 @@ static int mt7530_phy_config_init(struct
+ mtk_gephy_config_init(phydev);
+
+ /* Increase post_update_timer */
+- phy_write_paged(phydev, MTK_PHY_PAGE_EXTENDED_3, 0x11, 0x4b);
++ phy_write_paged(phydev, MTK_PHY_PAGE_EXTENDED_3,
++ MTK_PHY_RG_LPI_PCS_DSP_CTRL_REG11, 0x4b);
+
+ return 0;
+ }
+@@ -89,11 +121,19 @@ static int mt7531_phy_config_init(struct
+
+ /* PHY link down power saving enable */
+ phy_set_bits(phydev, 0x17, BIT(4));
+- phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, 0xc6, 0x300);
++ phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RXADC_CTRL_RG7,
++ MTK_PHY_DA_AD_BUF_BIAS_LP_MASK,
++ FIELD_PREP(MTK_PHY_DA_AD_BUF_BIAS_LP_MASK, 0x3));
+
+ /* Set TX Pair delay selection */
+- phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x13, 0x404);
+- phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x14, 0x404);
++ phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_GBE_MODE_TX_DELAY_SEL,
++ MTK_TX_DELAY_PAIR_B_MASK | MTK_TX_DELAY_PAIR_D_MASK,
++ FIELD_PREP(MTK_TX_DELAY_PAIR_B_MASK, 0x4) |
++ FIELD_PREP(MTK_TX_DELAY_PAIR_D_MASK, 0x4));
++ phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TEST_MODE_TX_DELAY_SEL,
++ MTK_TX_DELAY_PAIR_B_MASK | MTK_TX_DELAY_PAIR_D_MASK,
++ FIELD_PREP(MTK_TX_DELAY_PAIR_B_MASK, 0x4) |
++ FIELD_PREP(MTK_TX_DELAY_PAIR_D_MASK, 0x4));
+
+ /* LED Config*/
+ mt7530_led_config_of(phydev);
+--- a/drivers/net/phy/mediatek/mtk-phy-lib.c
++++ b/drivers/net/phy/mediatek/mtk-phy-lib.c
+@@ -6,6 +6,97 @@
+
+ #include "mtk.h"
+
++/* Difference between functions with mtk_tr* and __mtk_tr* prefixes is
++ * mtk_tr* functions: wrapped by page switching operations
++ * __mtk_tr* functions: no page switching operations
++ */
++
++static void __mtk_tr_access(struct phy_device *phydev, bool read, u8 ch_addr,
++ u8 node_addr, u8 data_addr)
++{
++ u16 tr_cmd = BIT(15); /* bit 14 & 0 are reserved */
++
++ if (read)
++ tr_cmd |= BIT(13);
++
++ tr_cmd |= (((ch_addr & 0x3) << 11) |
++ ((node_addr & 0xf) << 7) |
++ ((data_addr & 0x3f) << 1));
++ dev_dbg(&phydev->mdio.dev, "tr_cmd: 0x%x\n", tr_cmd);
++ __phy_write(phydev, 0x10, tr_cmd);
++}
++
++static void __mtk_tr_read(struct phy_device *phydev, u8 ch_addr, u8 node_addr,
++ u8 data_addr, u16 *tr_high, u16 *tr_low)
++{
++ __mtk_tr_access(phydev, true, ch_addr, node_addr, data_addr);
++ *tr_low = __phy_read(phydev, 0x11);
++ *tr_high = __phy_read(phydev, 0x12);
++ dev_dbg(&phydev->mdio.dev, "tr_high read: 0x%x, tr_low read: 0x%x\n",
++ *tr_high, *tr_low);
++}
++
++u32 mtk_tr_read(struct phy_device *phydev, u8 ch_addr, u8 node_addr,
++ u8 data_addr)
++{
++ u16 tr_high;
++ u16 tr_low;
++
++ phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_52B5);
++ __mtk_tr_read(phydev, ch_addr, node_addr, data_addr, &tr_high, &tr_low);
++ phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0);
++
++ return (tr_high << 16) | tr_low;
++}
++EXPORT_SYMBOL_GPL(mtk_tr_read);
++
++static void __mtk_tr_write(struct phy_device *phydev, u8 ch_addr, u8 node_addr,
++ u8 data_addr, u32 tr_data)
++{
++ __phy_write(phydev, 0x11, tr_data & 0xffff);
++ __phy_write(phydev, 0x12, tr_data >> 16);
++ dev_dbg(&phydev->mdio.dev, "tr_high write: 0x%x, tr_low write: 0x%x\n",
++ tr_data >> 16, tr_data & 0xffff);
++ __mtk_tr_access(phydev, false, ch_addr, node_addr, data_addr);
++}
++
++void __mtk_tr_modify(struct phy_device *phydev, u8 ch_addr, u8 node_addr,
++ u8 data_addr, u32 mask, u32 set)
++{
++ u32 tr_data;
++ u16 tr_high;
++ u16 tr_low;
++
++ __mtk_tr_read(phydev, ch_addr, node_addr, data_addr, &tr_high, &tr_low);
++ tr_data = (tr_high << 16) | tr_low;
++ tr_data = (tr_data & ~mask) | set;
++ __mtk_tr_write(phydev, ch_addr, node_addr, data_addr, tr_data);
++}
++EXPORT_SYMBOL_GPL(__mtk_tr_modify);
++
++void mtk_tr_modify(struct phy_device *phydev, u8 ch_addr, u8 node_addr,
++ u8 data_addr, u32 mask, u32 set)
++{
++ phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_52B5);
++ __mtk_tr_modify(phydev, ch_addr, node_addr, data_addr, mask, set);
++ phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0);
++}
++EXPORT_SYMBOL_GPL(mtk_tr_modify);
++
++void __mtk_tr_set_bits(struct phy_device *phydev, u8 ch_addr, u8 node_addr,
++ u8 data_addr, u32 set)
++{
++ __mtk_tr_modify(phydev, ch_addr, node_addr, data_addr, 0, set);
++}
++EXPORT_SYMBOL_GPL(__mtk_tr_set_bits);
++
++void __mtk_tr_clr_bits(struct phy_device *phydev, u8 ch_addr, u8 node_addr,
++ u8 data_addr, u32 clr)
++{
++ __mtk_tr_modify(phydev, ch_addr, node_addr, data_addr, clr, 0);
++}
++EXPORT_SYMBOL_GPL(__mtk_tr_clr_bits);
++
+ int mtk_phy_read_page(struct phy_device *phydev)
+ {
+ return __phy_read(phydev, MTK_EXT_PAGE_ACCESS);
+--- a/drivers/net/phy/mediatek/mtk.h
++++ b/drivers/net/phy/mediatek/mtk.h
+@@ -9,6 +9,8 @@
+ #define _MTK_EPHY_H_
+
+ #define MTK_EXT_PAGE_ACCESS 0x1f
++#define MTK_PHY_PAGE_STANDARD 0x0000
++#define MTK_PHY_PAGE_EXTENDED_52B5 0x52b5
+
+ /* Registers on MDIO_MMD_VEND2 */
+ #define MTK_PHY_LED0_ON_CTRL 0x24
+@@ -62,6 +64,17 @@
+ #define MTK_PHY_LED_STATE_FORCE_BLINK 1
+ #define MTK_PHY_LED_STATE_NETDEV 2
+
++u32 mtk_tr_read(struct phy_device *phydev, u8 ch_addr, u8 node_addr,
++ u8 data_addr);
++void __mtk_tr_modify(struct phy_device *phydev, u8 ch_addr, u8 node_addr,
++ u8 data_addr, u32 mask, u32 set);
++void mtk_tr_modify(struct phy_device *phydev, u8 ch_addr, u8 node_addr,
++ u8 data_addr, u32 mask, u32 set);
++void __mtk_tr_set_bits(struct phy_device *phydev, u8 ch_addr, u8 node_addr,
++ u8 data_addr, u32 set);
++void __mtk_tr_clr_bits(struct phy_device *phydev, u8 ch_addr, u8 node_addr,
++ u8 data_addr, u32 clr);
++
+ int mtk_phy_read_page(struct phy_device *phydev);
+ int mtk_phy_write_page(struct phy_device *phydev, int page);
+
--- /dev/null
+From 69ca89165e39e6b6f4c79e6b4c03559e0fac7051 Mon Sep 17 00:00:00 2001
+From: "SkyLake.Huang" <skylake.huang@mediatek.com>
+Date: Mon, 1 Jul 2024 18:54:15 +0800
+Subject: [PATCH 11/13] net: phy: add driver for built-in 2.5G ethernet PHY on
+ MT7988
+
+Add support for internal 2.5Gphy on MT7988. This driver will load
+necessary firmware, add appropriate time delay and figure out LED.
+Also, certain control registers will be set to fix link-up issues.
+
+Signed-off-by: SkyLake.Huang <skylake.huang@mediatek.com>
+---
+ drivers/net/phy/mediatek/Kconfig | 11 +
+ drivers/net/phy/mediatek/Makefile | 1 +
+ drivers/net/phy/mediatek/mtk-2p5ge.c | 432 +++++++++++++++++++++++++++
+ 4 files changed, 445 insertions(+)
+ create mode 100644 drivers/net/phy/mediatek/mtk-2p5ge.c
+
+--- a/drivers/net/phy/mediatek/Kconfig
++++ b/drivers/net/phy/mediatek/Kconfig
+@@ -25,3 +25,14 @@ config MEDIATEK_GE_SOC_PHY
+ the MT7981 and MT7988 SoCs. These PHYs need calibration data
+ present in the SoCs efuse and will dynamically calibrate VCM
+ (common-mode voltage) during startup.
++
++config MEDIATEK_2P5GE_PHY
++ tristate "MediaTek 2.5Gb Ethernet PHYs"
++ depends on (ARM64 && ARCH_MEDIATEK) || COMPILE_TEST
++ select MTK_NET_PHYLIB
++ help
++ Supports MediaTek SoC built-in 2.5Gb Ethernet PHYs.
++
++ This will load necessary firmware and add appropriate time delay.
++ Accelerate this procedure through internal pbus instead of MDIO
++ bus. Certain link-up issues will also be fixed here.
+--- a/drivers/net/phy/mediatek/Makefile
++++ b/drivers/net/phy/mediatek/Makefile
+@@ -2,3 +2,4 @@
+ obj-$(CONFIG_MTK_NET_PHYLIB) += mtk-phy-lib.o
+ obj-$(CONFIG_MEDIATEK_GE_PHY) += mtk-ge.o
+ obj-$(CONFIG_MEDIATEK_GE_SOC_PHY) += mtk-ge-soc.o
++obj-$(CONFIG_MEDIATEK_2P5GE_PHY) += mtk-2p5ge.o
+--- /dev/null
++++ b/drivers/net/phy/mediatek/mtk-2p5ge.c
+@@ -0,0 +1,436 @@
++// SPDX-License-Identifier: GPL-2.0+
++#include <linux/bitfield.h>
++#include <linux/firmware.h>
++#include <linux/module.h>
++#include <linux/nvmem-consumer.h>
++#include <linux/of_address.h>
++#include <linux/of_platform.h>
++#include <linux/pinctrl/consumer.h>
++#include <linux/phy.h>
++#include <linux/pm_domain.h>
++#include <linux/pm_runtime.h>
++
++#include "mtk.h"
++
++#define MTK_2P5GPHY_ID_MT7988 (0x00339c11)
++
++#define MTK_PHY_PAGE_EXTENDED_1 0x0001
++#define MTK_PHY_AUX_CTRL_AND_STATUS 0x14
++#define MTK_PHY_ENABLE_DOWNSHIFT BIT(4)
++
++#define MT7988_2P5GE_PMB_FW "mediatek/mt7988/i2p5ge-phy-pmb.bin"
++#define MT7988_2P5GE_PMB_FW_SIZE (0x20000)
++#define MT7988_2P5GE_PMB_FW_BASE (0x0f100000)
++#define MT7988_2P5GE_PMB_FW_LEN (0x20000)
++#define MT7988_2P5GE_MD32_EN_CFG_BASE (0x0f0f0018)
++#define MT7988_2P5GE_MD32_EN_CFG_LEN (0x20)
++#define MD32_EN BIT(0)
++
++#define BASE100T_STATUS_EXTEND (0x10)
++#define BASE1000T_STATUS_EXTEND (0x11)
++#define EXTEND_CTRL_AND_STATUS (0x16)
++
++#define PHY_AUX_CTRL_STATUS (0x1d)
++#define PHY_AUX_DPX_MASK GENMASK(5, 5)
++#define PHY_AUX_SPEED_MASK GENMASK(4, 2)
++
++#define MTK_PHY_LPI_PCS_DSP_CTRL (0x121)
++#define MTK_PHY_LPI_SIG_EN_LO_THRESH100_MASK GENMASK(12, 8)
++
++/* Registers on Token Ring debug nodes */
++/* ch_addr = 0x0, node_addr = 0xf, data_addr = 0x3c */
++#define AUTO_NP_10XEN BIT(6)
++
++struct mtk_i2p5ge_phy_priv {
++ bool fw_loaded;
++ unsigned long led_state;
++};
++
++enum {
++ PHY_AUX_SPD_10 = 0,
++ PHY_AUX_SPD_100,
++ PHY_AUX_SPD_1000,
++ PHY_AUX_SPD_2500,
++};
++
++static int mt798x_2p5ge_phy_load_fw(struct phy_device *phydev)
++{
++ struct mtk_i2p5ge_phy_priv *priv = phydev->priv;
++ void __iomem *md32_en_cfg_base, *pmb_addr;
++ struct device *dev = &phydev->mdio.dev;
++ const struct firmware *fw;
++ int ret, i;
++ u16 reg;
++
++ if (priv->fw_loaded)
++ return 0;
++
++ pmb_addr = ioremap(MT7988_2P5GE_PMB_FW_BASE, MT7988_2P5GE_PMB_FW_LEN);
++ if (!pmb_addr)
++ return -ENOMEM;
++ md32_en_cfg_base = ioremap(MT7988_2P5GE_MD32_EN_CFG_BASE,
++ MT7988_2P5GE_MD32_EN_CFG_LEN);
++ if (!md32_en_cfg_base) {
++ ret = -ENOMEM;
++ goto free_pmb;
++ }
++
++ ret = request_firmware(&fw, MT7988_2P5GE_PMB_FW, dev);
++ if (ret) {
++ dev_err(dev, "failed to load firmware: %s, ret: %d\n",
++ MT7988_2P5GE_PMB_FW, ret);
++ goto free;
++ }
++
++ if (fw->size != MT7988_2P5GE_PMB_FW_SIZE) {
++ dev_err(dev, "Firmware size 0x%zx != 0x%x\n",
++ fw->size, MT7988_2P5GE_PMB_FW_SIZE);
++ ret = -EINVAL;
++ goto release_fw;
++ }
++
++ reg = readw(md32_en_cfg_base);
++ if (reg & MD32_EN) {
++ phy_set_bits(phydev, MII_BMCR, BMCR_RESET);
++ usleep_range(10000, 11000);
++ }
++ phy_set_bits(phydev, MII_BMCR, BMCR_PDOWN);
++
++ /* Write magic number to safely stall MCU */
++ phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x800e, 0x1100);
++ phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x800f, 0x00df);
++
++ for (i = 0; i < MT7988_2P5GE_PMB_FW_SIZE - 1; i += 4)
++ writel(*((uint32_t *)(fw->data + i)), pmb_addr + i);
++ dev_info(dev, "Firmware date code: %x/%x/%x, version: %x.%x\n",
++ be16_to_cpu(*((__be16 *)(fw->data +
++ MT7988_2P5GE_PMB_FW_SIZE - 8))),
++ *(fw->data + MT7988_2P5GE_PMB_FW_SIZE - 6),
++ *(fw->data + MT7988_2P5GE_PMB_FW_SIZE - 5),
++ *(fw->data + MT7988_2P5GE_PMB_FW_SIZE - 2),
++ *(fw->data + MT7988_2P5GE_PMB_FW_SIZE - 1));
++
++ writew(reg & ~MD32_EN, md32_en_cfg_base);
++ writew(reg | MD32_EN, md32_en_cfg_base);
++ phy_set_bits(phydev, MII_BMCR, BMCR_RESET);
++ /* We need a delay here to stabilize initialization of MCU */
++ usleep_range(7000, 8000);
++ dev_info(dev, "Firmware loading/trigger ok.\n");
++
++ priv->fw_loaded = true;
++
++release_fw:
++ release_firmware(fw);
++free:
++ iounmap(md32_en_cfg_base);
++free_pmb:
++ iounmap(pmb_addr);
++
++ return ret;
++}
++
++static int mt798x_2p5ge_phy_config_init(struct phy_device *phydev)
++{
++ struct pinctrl *pinctrl;
++ int ret;
++
++ /* Check if PHY interface type is compatible */
++ if (phydev->interface != PHY_INTERFACE_MODE_INTERNAL)
++ return -ENODEV;
++
++ ret = mt798x_2p5ge_phy_load_fw(phydev);
++ if (ret < 0)
++ return ret;
++
++ /* Setup LED */
++ phy_set_bits_mmd(phydev, MDIO_MMD_VEND2, MTK_PHY_LED0_ON_CTRL,
++ MTK_PHY_LED_ON_POLARITY | MTK_PHY_LED_ON_LINK10 |
++ MTK_PHY_LED_ON_LINK100 | MTK_PHY_LED_ON_LINK1000 |
++ MTK_PHY_LED_ON_LINK2500);
++ phy_set_bits_mmd(phydev, MDIO_MMD_VEND2, MTK_PHY_LED1_ON_CTRL,
++ MTK_PHY_LED_ON_FDX | MTK_PHY_LED_ON_HDX);
++
++ /* Switch pinctrl after setting polarity to avoid bogus blinking */
++ pinctrl = devm_pinctrl_get_select(&phydev->mdio.dev, "i2p5gbe-led");
++ if (IS_ERR(pinctrl))
++ dev_err(&phydev->mdio.dev, "Fail to set LED pins!\n");
++
++ phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_LPI_PCS_DSP_CTRL,
++ MTK_PHY_LPI_SIG_EN_LO_THRESH100_MASK, 0);
++
++ /* Enable 16-bit next page exchange bit if 1000-BT isn't advertising */
++ mtk_tr_modify(phydev, 0x0, 0xf, 0x3c, AUTO_NP_10XEN,
++ FIELD_PREP(AUTO_NP_10XEN, 0x1));
++
++ /* Enable HW auto downshift */
++ phy_modify_paged(phydev, MTK_PHY_PAGE_EXTENDED_1,
++ MTK_PHY_AUX_CTRL_AND_STATUS,
++ 0, MTK_PHY_ENABLE_DOWNSHIFT);
++
++ return 0;
++}
++
++static int mt798x_2p5ge_phy_config_aneg(struct phy_device *phydev)
++{
++ bool changed = false;
++ u32 adv;
++ int ret;
++
++ /* In fact, if we disable autoneg, we can't link up correctly:
++ * 2.5G/1G: Need AN to exchange master/slave information.
++ * 100M/10M: Without AN, link starts at half duplex (According to
++ * IEEE 802.3-2018), which this phy doesn't support.
++ */
++ if (phydev->autoneg == AUTONEG_DISABLE)
++ return -EOPNOTSUPP;
++
++ ret = genphy_c45_an_config_aneg(phydev);
++ if (ret < 0)
++ return ret;
++ if (ret > 0)
++ changed = true;
++
++ /* Clause 45 doesn't define 1000BaseT support. Use Clause 22 instead in
++ * our design.
++ */
++ adv = linkmode_adv_to_mii_ctrl1000_t(phydev->advertising);
++ ret = phy_modify_changed(phydev, MII_CTRL1000, ADVERTISE_1000FULL, adv);
++ if (ret < 0)
++ return ret;
++ if (ret > 0)
++ changed = true;
++
++ return genphy_c45_check_and_restart_aneg(phydev, changed);
++}
++
++static int mt798x_2p5ge_phy_get_features(struct phy_device *phydev)
++{
++ int ret;
++
++ ret = genphy_c45_pma_read_abilities(phydev);
++ if (ret)
++ return ret;
++
++ /* This phy can't handle collision, and neither can (XFI)MAC it's
++ * connected to. Although it can do HDX handshake, it doesn't support
++ * CSMA/CD that HDX requires.
++ */
++ linkmode_clear_bit(ETHTOOL_LINK_MODE_100baseT_Half_BIT,
++ phydev->supported);
++
++ return 0;
++}
++
++static int mt798x_2p5ge_phy_read_status(struct phy_device *phydev)
++{
++ int ret;
++
++ /* When MDIO_STAT1_LSTATUS is raised genphy_c45_read_link(), this phy
++ * actually hasn't finished AN. So use CL22's link update function
++ * instead.
++ */
++ ret = genphy_update_link(phydev);
++ if (ret)
++ return ret;
++
++ phydev->speed = SPEED_UNKNOWN;
++ phydev->duplex = DUPLEX_UNKNOWN;
++ phydev->pause = 0;
++ phydev->asym_pause = 0;
++
++ /* We'll read link speed through vendor specific registers down below.
++ * So remove phy_resolve_aneg_linkmode (AN on) & genphy_c45_read_pma
++ * (AN off).
++ */
++ if (phydev->autoneg == AUTONEG_ENABLE && phydev->autoneg_complete) {
++ ret = genphy_c45_read_lpa(phydev);
++ if (ret < 0)
++ return ret;
++
++ /* Clause 45 doesn't define 1000BaseT support. Read the link
++ * partner's 1G advertisement via Clause 22.
++ */
++ ret = phy_read(phydev, MII_STAT1000);
++ if (ret < 0)
++ return ret;
++ mii_stat1000_mod_linkmode_lpa_t(phydev->lp_advertising, ret);
++ } else if (phydev->autoneg == AUTONEG_DISABLE) {
++ linkmode_zero(phydev->lp_advertising);
++ }
++
++ if (phydev->link) {
++ ret = phy_read(phydev, PHY_AUX_CTRL_STATUS);
++ if (ret < 0)
++ return ret;
++
++ switch (FIELD_GET(PHY_AUX_SPEED_MASK, ret)) {
++ case PHY_AUX_SPD_10:
++ phydev->speed = SPEED_10;
++ break;
++ case PHY_AUX_SPD_100:
++ phydev->speed = SPEED_100;
++ break;
++ case PHY_AUX_SPD_1000:
++ phydev->speed = SPEED_1000;
++ break;
++ case PHY_AUX_SPD_2500:
++ phydev->speed = SPEED_2500;
++ break;
++ }
++
++ phydev->duplex = DUPLEX_FULL;
++ /* FIXME:
++ * The current firmware always enables rate adaptation mode.
++ */
++ phydev->rate_matching = RATE_MATCH_PAUSE;
++ }
++
++ return 0;
++}
++
++static int mt798x_2p5ge_phy_get_rate_matching(struct phy_device *phydev,
++ phy_interface_t iface)
++{
++ return RATE_MATCH_PAUSE;
++}
++
++static const unsigned long supported_triggers =
++ BIT(TRIGGER_NETDEV_FULL_DUPLEX) |
++ BIT(TRIGGER_NETDEV_LINK) |
++ BIT(TRIGGER_NETDEV_LINK_10) |
++ BIT(TRIGGER_NETDEV_LINK_100) |
++ BIT(TRIGGER_NETDEV_LINK_1000) |
++ BIT(TRIGGER_NETDEV_LINK_2500) |
++ BIT(TRIGGER_NETDEV_RX) |
++ BIT(TRIGGER_NETDEV_TX);
++
++static int mt798x_2p5ge_phy_led_blink_set(struct phy_device *phydev, u8 index,
++ unsigned long *delay_on,
++ unsigned long *delay_off)
++{
++ struct mtk_i2p5ge_phy_priv *priv = phydev->priv;
++ bool blinking = false;
++ int err = 0;
++
++ err = mtk_phy_led_num_dly_cfg(index, delay_on, delay_off, &blinking);
++ if (err < 0)
++ return err;
++
++ err = mtk_phy_hw_led_blink_set(phydev, index, &priv->led_state,
++ blinking);
++ if (err)
++ return err;
++
++ return mtk_phy_hw_led_on_set(phydev, index, &priv->led_state,
++ MTK_2P5GPHY_LED_ON_MASK, false);
++}
++
++static int mt798x_2p5ge_phy_led_brightness_set(struct phy_device *phydev,
++ u8 index,
++ enum led_brightness value)
++{
++ struct mtk_i2p5ge_phy_priv *priv = phydev->priv;
++ int err;
++
++ err = mtk_phy_hw_led_blink_set(phydev, index, &priv->led_state, false);
++ if (err)
++ return err;
++
++ return mtk_phy_hw_led_on_set(phydev, index, &priv->led_state,
++ MTK_2P5GPHY_LED_ON_MASK,
++ (value != LED_OFF));
++}
++
++static int mt798x_2p5ge_phy_led_hw_is_supported(struct phy_device *phydev,
++ u8 index, unsigned long rules)
++{
++ return mtk_phy_led_hw_is_supported(phydev, index, rules,
++ supported_triggers);
++}
++
++static int mt798x_2p5ge_phy_led_hw_control_get(struct phy_device *phydev,
++ u8 index, unsigned long *rules)
++{
++ struct mtk_i2p5ge_phy_priv *priv = phydev->priv;
++
++ return mtk_phy_led_hw_ctrl_get(phydev, index, rules, &priv->led_state,
++ MTK_2P5GPHY_LED_ON_SET,
++ MTK_2P5GPHY_LED_RX_BLINK_SET,
++ MTK_2P5GPHY_LED_TX_BLINK_SET);
++};
++
++static int mt798x_2p5ge_phy_led_hw_control_set(struct phy_device *phydev,
++ u8 index, unsigned long rules)
++{
++ struct mtk_i2p5ge_phy_priv *priv = phydev->priv;
++
++ return mtk_phy_led_hw_ctrl_set(phydev, index, rules, &priv->led_state,
++ MTK_2P5GPHY_LED_ON_SET,
++ MTK_2P5GPHY_LED_RX_BLINK_SET,
++ MTK_2P5GPHY_LED_TX_BLINK_SET);
++};
++
++static int mt798x_2p5ge_phy_probe(struct phy_device *phydev)
++{
++ struct mtk_i2p5ge_phy_priv *priv;
++
++ priv = devm_kzalloc(&phydev->mdio.dev,
++ sizeof(struct mtk_i2p5ge_phy_priv), GFP_KERNEL);
++ if (!priv)
++ return -ENOMEM;
++
++ switch (phydev->drv->phy_id) {
++ case MTK_2P5GPHY_ID_MT7988:
++ /* The original hardware only sets MDIO_DEVS_PMAPMD */
++ phydev->c45_ids.mmds_present |= MDIO_DEVS_PCS |
++ MDIO_DEVS_AN |
++ MDIO_DEVS_VEND1 |
++ MDIO_DEVS_VEND2;
++ break;
++ default:
++ return -EINVAL;
++ }
++
++ priv->fw_loaded = false;
++ phydev->priv = priv;
++
++ mtk_phy_leds_state_init(phydev);
++
++ return 0;
++}
++
++static struct phy_driver mtk_2p5gephy_driver[] = {
++ {
++ PHY_ID_MATCH_MODEL(MTK_2P5GPHY_ID_MT7988),
++ .name = "MediaTek MT7988 2.5GbE PHY",
++ .probe = mt798x_2p5ge_phy_probe,
++ .config_init = mt798x_2p5ge_phy_config_init,
++ .config_aneg = mt798x_2p5ge_phy_config_aneg,
++ .get_features = mt798x_2p5ge_phy_get_features,
++ .read_status = mt798x_2p5ge_phy_read_status,
++ .get_rate_matching = mt798x_2p5ge_phy_get_rate_matching,
++ .suspend = genphy_suspend,
++ .resume = genphy_resume,
++ .read_page = mtk_phy_read_page,
++ .write_page = mtk_phy_write_page,
++ .led_blink_set = mt798x_2p5ge_phy_led_blink_set,
++ .led_brightness_set = mt798x_2p5ge_phy_led_brightness_set,
++ .led_hw_is_supported = mt798x_2p5ge_phy_led_hw_is_supported,
++ .led_hw_control_get = mt798x_2p5ge_phy_led_hw_control_get,
++ .led_hw_control_set = mt798x_2p5ge_phy_led_hw_control_set,
++ },
++};
++
++module_phy_driver(mtk_2p5gephy_driver);
++
++static struct mdio_device_id __maybe_unused mtk_2p5ge_phy_tbl[] = {
++ { PHY_ID_MATCH_VENDOR(0x00339c00) },
++ { }
++};
++
++MODULE_DESCRIPTION("MediaTek 2.5Gb Ethernet PHY driver");
++MODULE_AUTHOR("SkyLake Huang <SkyLake.Huang@mediatek.com>");
++MODULE_LICENSE("GPL");
++
++MODULE_DEVICE_TABLE(mdio, mtk_2p5ge_phy_tbl);
++MODULE_FIRMWARE(MT7988_2P5GE_PMB_FW);
--- /dev/null
+From 5314e73cb941b47e6866b49b3b78c25e32d62df8 Mon Sep 17 00:00:00 2001
+From: Robert Marko <robert.marko@sartura.hr>
+Date: Sat, 23 Mar 2024 20:21:14 +0100
+Subject: [PATCH] net: phy: add Airoha EN8801SC PHY
+
+Airoha EN8801SC Gigabit PHY is used on Edgecore EAP111, so include a
+modified version of MTK SDK driver.
+
+Signed-off-by: Robert Marko <robert.marko@sartura.hr>
+---
+ drivers/net/phy/Kconfig | 5 +++++
+ drivers/net/phy/Makefile | 1 +
+ 2 files changed, 6 insertions(+)
+
+--- a/drivers/net/phy/Kconfig
++++ b/drivers/net/phy/Kconfig
+@@ -142,6 +142,11 @@ endif # RTL8366_SMI
+
+ comment "MII PHY device drivers"
+
++config AIROHA_EN8801SC_PHY
++ tristate "Airoha EN8801SC Gigabit PHY"
++ help
++ Currently supports the Airoha EN8801SC PHY.
++
+ config AIR_EN8811H_PHY
+ tristate "Airoha EN8811H 2.5 Gigabit PHY"
+ help
+--- a/drivers/net/phy/Makefile
++++ b/drivers/net/phy/Makefile
+@@ -49,6 +49,7 @@ obj-y += $(sfp-obj-y) $(sfp-obj-m)
+
+ obj-$(CONFIG_ADIN_PHY) += adin.o
+ obj-$(CONFIG_ADIN1100_PHY) += adin1100.o
++obj-$(CONFIG_AIROHA_EN8801SC_PHY) += en8801sc.o
+ obj-$(CONFIG_AIR_EN8811H_PHY) += air_en8811h.o
+ obj-$(CONFIG_AMD_PHY) += amd.o
+ obj-$(CONFIG_AQUANTIA_PHY) += aquantia/
--- /dev/null
+--- a/drivers/net/pcs/pcs-mtk-usxgmii.c
++++ b/drivers/net/pcs/pcs-mtk-usxgmii.c
+@@ -52,6 +52,12 @@
+ #define USXGMII_LPA GENMASK(15, 0)
+ #define USXGMII_LPA_LATCH BIT(31)
+
++/* Register to control PCS polarity */
++#define RG_PHY_TOP_CTRL0 0x82C
++#define USXGMII_PN_SWAP_MASK GENMASK(1, 0)
++#define USXGMII_PN_SWAP_RX BIT(1)
++#define USXGMII_PN_SWAP_TX BIT(0)
++
+ /* Register to read PCS link status */
+ #define RG_PCS_RX_STATUS0 0x904
+ #define RG_PCS_RX_STATUS_UPDATE BIT(16)
+@@ -74,6 +80,7 @@ struct mtk_usxgmii_pcs {
+ struct clk *clk;
+ struct reset_control *reset;
+ phy_interface_t interface;
++ unsigned int polarity;
+ unsigned int neg_mode;
+ struct list_head node;
+ };
+@@ -155,6 +162,10 @@ static int mtk_usxgmii_pcs_config(struct
+
+ mtk_usxgmii_reset(mpcs);
+
++ /* Configure the interface polarity */
++ mtk_m32(mpcs, RG_PHY_TOP_CTRL0,
++ USXGMII_PN_SWAP_MASK, mpcs->polarity);
++
+ /* Setup USXGMII AN ctrl */
+ mtk_m32(mpcs, RG_PCS_AN_CTRL0,
+ USXGMII_AN_SYNC_CNT | USXGMII_AN_ENABLE,
+@@ -332,6 +343,7 @@ static const struct phylink_pcs_ops mtk_
+ static int mtk_usxgmii_probe(struct platform_device *pdev)
+ {
+ struct device *dev = &pdev->dev;
++ struct device_node *np = dev->of_node;
+ struct mtk_usxgmii_pcs *mpcs;
+
+ mpcs = devm_kzalloc(dev, sizeof(*mpcs), GFP_KERNEL);
+@@ -342,6 +354,13 @@ static int mtk_usxgmii_probe(struct plat
+ if (IS_ERR(mpcs->base))
+ return PTR_ERR(mpcs->base);
+
++ if (of_property_read_bool(np->parent, "mediatek,pnswap"))
++ mpcs->polarity = USXGMII_PN_SWAP_TX | USXGMII_PN_SWAP_RX;
++ else if (of_property_read_bool(np, "mediatek,pnswap-tx"))
++ mpcs->polarity = USXGMII_PN_SWAP_TX;
++ else if (of_property_read_bool(np, "mediatek,pnswap-rx"))
++ mpcs->polarity = USXGMII_PN_SWAP_RX;
++
+ mpcs->dev = dev;
+ mpcs->pcs.ops = &mtk_usxgmii_pcs_ops;
+ mpcs->pcs.poll = true;
--- /dev/null
+From: Christian Marangi <ansuelsmth@gmail.com>
+To: Christian Marangi <ansuelsmth@gmail.com>,
+ Lee Jones <lee@kernel.org>, Rob Herring <robh@kernel.org>,
+ Krzysztof Kozlowski <krzk+dt@kernel.org>,
+ Conor Dooley <conor+dt@kernel.org>,
+ Andrew Lunn <andrew+netdev@lunn.ch>,
+ "David S. Miller" <davem@davemloft.net>,
+ Eric Dumazet <edumazet@google.com>,
+ Jakub Kicinski <kuba@kernel.org>, Paolo Abeni <pabeni@redhat.com>,
+ Vladimir Oltean <olteanv@gmail.com>,
+ Srinivas Kandagatla <srinivas.kandagatla@linaro.org>,
+ Heiner Kallweit <hkallweit1@gmail.com>,
+ Russell King <linux@armlinux.org.uk>,
+ Matthias Brugger <matthias.bgg@gmail.com>,
+ AngeloGioacchino Del Regno
+ <angelogioacchino.delregno@collabora.com>,
+ linux-arm-kernel@lists.infradead.org,
+ linux-mediatek@lists.infradead.org, netdev@vger.kernel.org,
+ devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
+ upstream@airoha.com
+Subject: [net-next PATCH v11 0/9] net: dsa: Add Airoha AN8855 support
+Date: Mon, 9 Dec 2024 14:44:17 +0100 [thread overview]
+Message-ID: <20241209134459.27110-1-ansuelsmth@gmail.com> (raw)
+
+This small series add the initial support for the Airoha AN8855 Switch.
+
+It's a 5 port Gigabit Switch with SGMII/HSGMII upstream port.
+
+This is starting to get in the wild and there are already some router
+having this switch chip.
+
+It's conceptually similar to mediatek switch but register and bits
+are different. And there is that massive Hell that is the PCS
+configuration.
+Saddly for that part we have absolutely NO documentation currently.
+
+There is this special thing where PHY needs to be calibrated with values
+from the switch efuse. (the thing have a whole cpu timer and MCU)
+
+Changes v11:
+- Address reviews from Christophe (spell mistake + dev_err_probe)
+- Fix kconfig dependency for MFD driver (depends on MDIO_DEVICE instead of MDIO)
+ (indirectly fix link error for mdio APIs)
+- Fix copy-paste error for MFD driver of_table
+- Fix compilation error for PHY (move NVMEM to .config)
+- Drop unneeded NVMEM node from MDIO example schema (from Andrew)
+- Adapt MFD example schema to MDIO reg property restrictions
+Changes v10:
+- Entire rework to MFD + split to MDIO, EFUSE, SWITCH separate drivers
+- Drop EEE OPs (while Russell finish RFC for EEE changes)
+- Use new pcs_inpand OPs
+- Drop AN restart function and move to pcs_config
+- Enable assisted_learning and disable CPU learn (preparation for fdb_isolation)
+- Move EFUSE read in Internal PHY driver to .config to handle EPROBE_DEFER
+ (needed now that NVMEM driver is register externally instead of internally to switch
+ node)
+Changes v9:
+- Error out on using 5G speed as currently not supported
+- Add missing MAC_2500FD in phylink mac_capabilities
+- Add comment and improve if condition for an8855_phylink_mac_config
+Changes v8:
+- Add port Fast Age support
+- Add support for Port Isolation
+- Use correct register for Learning Disable
+- Add support for Ageing Time OP
+- Set default PVID to 0 by default
+- Add mdb OPs
+- Add port change MTU
+- Fix support for Upper VLAN
+Changes v7:
+- Fix devm_dsa_register_switch wrong export symbol
+Changes v6:
+- Drop standard MIB and handle with ethtool OPs (as requested by Jakub)
+- Cosmetic: use bool instead of 0 or 1
+Changes v5:
+- Add devm_dsa_register_switch() patch
+- Add Reviewed-by tag for DT patch
+Changes v4:
+- Set regmap readable_table static (mute compilation warning)
+- Add support for port_bridge flags (LEARNING, FLOOD)
+- Reset fdb struct in fdb_dump
+- Drop support_asym_pause in port_enable
+- Add define for get_phy_flags
+- Fix bug for port not inititially part of a bridge
+ (in an8855_setup the port matrix was always cleared but
+ the CPU port was never initially added)
+- Disable learning and flood for user port by default
+- Set CPU port to flood and learning by default
+- Correctly AND force duplex and flow control in an8855_phylink_mac_link_up
+- Drop RGMII from pcs_config
+- Check ret in "Disable AN if not in autoneg"
+- Use devm_mutex_init
+- Fix typo for AN8855_PORT_CHECK_MODE
+- Better define AN8855_STP_LISTENING = AN8855_STP_BLOCKING
+- Fix typo in AN8855_PHY_EN_DOWN_SHIFT
+- Use paged helper for PHY
+- Skip calibration in config_init if priv not defined
+Changes v3:
+- Out of RFC
+- Switch PHY code to select_page API
+- Better describe masks and bits in PHY driver for ADC register
+- Drop raw values and use define for mii read/write
+- Switch to absolute PHY address
+- Replace raw values with mask and bits for pcs_config
+- Fix typo for ext-surge property name
+- Drop support for relocating Switch base PHY address on the bus
+Changes v2:
+- Drop mutex guard patch
+- Drop guard usage in DSA driver
+- Use __mdiobus_write/read
+- Check return condition and return errors for mii read/write
+- Fix wrong logic for EEE
+- Fix link_down (don't force link down with autoneg)
+- Fix forcing speed on sgmii autoneg
+- Better document link speed for sgmii reg
+- Use standard define for sgmii reg
+- Imlement nvmem support to expose switch EFUSE
+- Rework PHY calibration with the use of NVMEM producer/consumer
+- Update DT with new NVMEM property
+- Move aneg validation for 2500-basex in pcs_config
+- Move r50Ohm table and function to PHY driver
+
+Christian Marangi (9):
+ dt-bindings: nvmem: Document support for Airoha AN8855 Switch EFUSE
+ dt-bindings: net: Document support for Airoha AN8855 Switch Virtual
+ MDIO
+ dt-bindings: net: dsa: Document support for Airoha AN8855 DSA Switch
+ dt-bindings: mfd: Document support for Airoha AN8855 Switch SoC
+ mfd: an8855: Add support for Airoha AN8855 Switch MFD
+ net: mdio: Add Airoha AN8855 Switch MDIO Passtrough
+ nvmem: an8855: Add support for Airoha AN8855 Switch EFUSE
+ net: dsa: Add Airoha AN8855 5-Port Gigabit DSA Switch driver
+ net: phy: Add Airoha AN8855 Internal Switch Gigabit PHY
+
+ .../bindings/mfd/airoha,an8855-mfd.yaml | 178 ++
+ .../bindings/net/airoha,an8855-mdio.yaml | 56 +
+ .../net/dsa/airoha,an8855-switch.yaml | 105 +
+ .../bindings/nvmem/airoha,an8855-efuse.yaml | 123 +
+ MAINTAINERS | 17 +
+ drivers/mfd/Kconfig | 10 +
+ drivers/mfd/Makefile | 1 +
+ drivers/mfd/airoha-an8855.c | 278 ++
+ drivers/net/dsa/Kconfig | 9 +
+ drivers/net/dsa/Makefile | 1 +
+ drivers/net/dsa/an8855.c | 2310 +++++++++++++++++
+ drivers/net/dsa/an8855.h | 783 ++++++
+ drivers/net/mdio/Kconfig | 9 +
+ drivers/net/mdio/Makefile | 1 +
+ drivers/net/mdio/mdio-an8855.c | 113 +
+ drivers/net/phy/Kconfig | 5 +
+ drivers/net/phy/Makefile | 1 +
+ drivers/net/phy/air_an8855.c | 267 ++
+ drivers/nvmem/Kconfig | 11 +
+ drivers/nvmem/Makefile | 2 +
+ drivers/nvmem/an8855-efuse.c | 63 +
+ include/linux/mfd/airoha-an8855-mfd.h | 41 +
+ 22 files changed, 4384 insertions(+)
+ create mode 100644 Documentation/devicetree/bindings/mfd/airoha,an8855-mfd.yaml
+ create mode 100644 Documentation/devicetree/bindings/net/airoha,an8855-mdio.yaml
+ create mode 100644 Documentation/devicetree/bindings/net/dsa/airoha,an8855-switch.yaml
+ create mode 100644 Documentation/devicetree/bindings/nvmem/airoha,an8855-efuse.yaml
+ create mode 100644 drivers/mfd/airoha-an8855.c
+ create mode 100644 drivers/net/dsa/an8855.c
+ create mode 100644 drivers/net/dsa/an8855.h
+ create mode 100644 drivers/net/mdio/mdio-an8855.c
+ create mode 100644 drivers/net/phy/air_an8855.c
+ create mode 100644 drivers/nvmem/an8855-efuse.c
+ create mode 100644 include/linux/mfd/airoha-an8855-mfd.h
+
+--- a/drivers/mfd/Kconfig
++++ b/drivers/mfd/Kconfig
+@@ -41,6 +41,16 @@ config MFD_ALTERA_SYSMGR
+ using regmap_mmio accesses for ARM32 parts and SMC calls to
+ EL3 for ARM64 parts.
+
++config MFD_AIROHA_AN8855
++ tristate "Airoha AN8855 Switch MFD"
++ select MFD_CORE
++ select MDIO_DEVICE
++ depends on NETDEVICES && OF
++ help
++ Support for the Airoha AN8855 Switch MFD. This is a SoC Switch
++ that provides various peripherals. Currently it provides a
++ DSA switch and a NVMEM provider.
++
+ config MFD_ACT8945A
+ tristate "Active-semi ACT8945A"
+ select MFD_CORE
+--- a/drivers/mfd/Makefile
++++ b/drivers/mfd/Makefile
+@@ -7,6 +7,7 @@
+ obj-$(CONFIG_MFD_88PM860X) += 88pm860x.o
+ obj-$(CONFIG_MFD_88PM800) += 88pm800.o 88pm80x.o
+ obj-$(CONFIG_MFD_88PM805) += 88pm805.o 88pm80x.o
++obj-$(CONFIG_MFD_AIROHA_AN8855) += airoha-an8855.o
+ obj-$(CONFIG_MFD_ACT8945A) += act8945a.o
+ obj-$(CONFIG_MFD_SM501) += sm501.o
+ obj-$(CONFIG_ARCH_BCM2835) += bcm2835-pm.o
+--- a/drivers/net/dsa/Kconfig
++++ b/drivers/net/dsa/Kconfig
+@@ -24,6 +24,15 @@ config NET_DSA_LOOP
+ This enables support for a fake mock-up switch chip which
+ exercises the DSA APIs.
+
++config NET_DSA_AN8855
++ tristate "Airoha AN8855 Ethernet switch support"
++ depends on MFD_AIROHA_AN8855
++ depends on NET_DSA
++ select NET_DSA_TAG_MTK
++ help
++ This enables support for the Airoha AN8855 Ethernet switch
++ chip.
++
+ source "drivers/net/dsa/hirschmann/Kconfig"
+
+ config NET_DSA_LANTIQ_GSWIP
+--- a/drivers/net/dsa/Makefile
++++ b/drivers/net/dsa/Makefile
+@@ -5,6 +5,7 @@ obj-$(CONFIG_NET_DSA_LOOP) += dsa_loop.o
+ ifdef CONFIG_NET_DSA_LOOP
+ obj-$(CONFIG_FIXED_PHY) += dsa_loop_bdinfo.o
+ endif
++obj-$(CONFIG_NET_DSA_AN8855) += an8855.o
+ obj-$(CONFIG_NET_DSA_LANTIQ_GSWIP) += lantiq_gswip.o
+ obj-$(CONFIG_NET_DSA_MT7530) += mt7530.o
+ obj-$(CONFIG_NET_DSA_MT7530_MDIO) += mt7530-mdio.o
+--- a/drivers/net/mdio/Kconfig
++++ b/drivers/net/mdio/Kconfig
+@@ -61,6 +61,15 @@ config MDIO_XGENE
+ This module provides a driver for the MDIO busses found in the
+ APM X-Gene SoC's.
+
++config MDIO_AN8855
++ tristate "Airoha AN8855 Switch MDIO bus controller"
++ depends on MFD_AIROHA_AN8855
++ depends on OF_MDIO
++ help
++ This module provides a driver for the Airoha AN8855 Switch
++ that requires a MDIO passtrough as switch address is shared
++ with the internal PHYs and requires additional page handling.
++
+ config MDIO_ASPEED
+ tristate "ASPEED MDIO bus controller"
+ depends on ARCH_ASPEED || COMPILE_TEST
+--- a/drivers/net/mdio/Makefile
++++ b/drivers/net/mdio/Makefile
+@@ -5,6 +5,7 @@ obj-$(CONFIG_ACPI_MDIO) += acpi_mdio.o
+ obj-$(CONFIG_FWNODE_MDIO) += fwnode_mdio.o
+ obj-$(CONFIG_OF_MDIO) += of_mdio.o
+
++obj-$(CONFIG_MDIO_AN8855) += mdio-an8855.o
+ obj-$(CONFIG_MDIO_ASPEED) += mdio-aspeed.o
+ obj-$(CONFIG_MDIO_BCM_IPROC) += mdio-bcm-iproc.o
+ obj-$(CONFIG_MDIO_BCM_UNIMAC) += mdio-bcm-unimac.o
+--- a/drivers/net/phy/Kconfig
++++ b/drivers/net/phy/Kconfig
+@@ -147,6 +147,11 @@ config AIROHA_EN8801SC_PHY
+ help
+ Currently supports the Airoha EN8801SC PHY.
+
++config AIR_AN8855_PHY
++ tristate "Airoha AN8855 Internal Gigabit PHY"
++ help
++ Currently supports the internal Airoha AN8855 Switch PHY.
++
+ config AIR_EN8811H_PHY
+ tristate "Airoha EN8811H 2.5 Gigabit PHY"
+ help
+--- a/drivers/net/phy/Makefile
++++ b/drivers/net/phy/Makefile
+@@ -50,6 +50,7 @@ obj-y += $(sfp-obj-y) $(sfp-obj-m)
+ obj-$(CONFIG_ADIN_PHY) += adin.o
+ obj-$(CONFIG_ADIN1100_PHY) += adin1100.o
+ obj-$(CONFIG_AIROHA_EN8801SC_PHY) += en8801sc.o
++obj-$(CONFIG_AIR_AN8855_PHY) += air_an8855.o
+ obj-$(CONFIG_AIR_EN8811H_PHY) += air_en8811h.o
+ obj-$(CONFIG_AMD_PHY) += amd.o
+ obj-$(CONFIG_AQUANTIA_PHY) += aquantia/
+--- a/drivers/nvmem/Kconfig
++++ b/drivers/nvmem/Kconfig
+@@ -29,6 +29,17 @@ source "drivers/nvmem/layouts/Kconfig"
+
+ # Devices
+
++config NVMEM_AN8855_EFUSE
++ tristate "Airoha AN8855 eFuse support"
++ depends on MFD_AIROHA_AN8855 || COMPILE_TEST
++ help
++ Say y here to enable support for reading eFuses on Airoha AN8855
++ Switch. These are e.g. used to store factory programmed
++ calibration data required for the PHY.
++
++ This driver can also be built as a module. If so, the module will
++ be called nvmem-an8855-efuse.
++
+ config NVMEM_APPLE_EFUSES
+ tristate "Apple eFuse support"
+ depends on ARCH_APPLE || COMPILE_TEST
+--- a/drivers/nvmem/Makefile
++++ b/drivers/nvmem/Makefile
+@@ -10,6 +10,8 @@ nvmem_layouts-y := layouts.o
+ obj-y += layouts/
+
+ # Devices
++obj-$(CONFIG_NVMEM_AN8855_EFUSE) += nvmem-an8855-efuse.o
++nvmem-an8855-efuse-y := an8855-efuse.o
+ obj-$(CONFIG_NVMEM_APPLE_EFUSES) += nvmem-apple-efuses.o
+ nvmem-apple-efuses-y := apple-efuses.o
+ obj-$(CONFIG_NVMEM_BCM_OCOTP) += nvmem-bcm-ocotp.o
--- /dev/null
+From 5e5401d6612ef599ad45785b941eebda7effc90f Mon Sep 17 00:00:00 2001\r
+From: "Russell King (Oracle)" <rmk+kernel@armlinux.org.uk>\r
+Date: Thu, 4 Jan 2024 09:47:36 +0000\r
+Subject: [PATCH] net: phylink: move phylink_pcs_neg_mode() into phylink.c\r
+\r
+Move phylink_pcs_neg_mode() from the header file into the .c file since\r
+nothing should be using it.\r
+\r
+Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>\r
+Reviewed-by: Andrew Lunn <andrew@lunn.ch>\r
+Signed-off-by: David S. Miller <davem@davemloft.net>\r
+---\r
+ drivers/net/phy/phylink.c | 66 +++++++++++++++++++++++++++++++++++++++\r
+ include/linux/phylink.h | 66 ---------------------------------------\r
+ 2 files changed, 66 insertions(+), 66 deletions(-)\r
+\r
+--- a/drivers/net/phy/phylink.c
++++ b/drivers/net/phy/phylink.c
+@@ -1150,6 +1150,72 @@ static void phylink_pcs_an_restart(struc
+ pl->pcs->ops->pcs_an_restart(pl->pcs);
+ }
+
++/**
++ * phylink_pcs_neg_mode() - helper to determine PCS inband mode
++ * @mode: one of %MLO_AN_FIXED, %MLO_AN_PHY, %MLO_AN_INBAND.
++ * @interface: interface mode to be used
++ * @advertising: adertisement ethtool link mode mask
++ *
++ * Determines the negotiation mode to be used by the PCS, and returns
++ * one of:
++ *
++ * - %PHYLINK_PCS_NEG_NONE: interface mode does not support inband
++ * - %PHYLINK_PCS_NEG_OUTBAND: an out of band mode (e.g. reading the PHY)
++ * will be used.
++ * - %PHYLINK_PCS_NEG_INBAND_DISABLED: inband mode selected but autoneg
++ * disabled
++ * - %PHYLINK_PCS_NEG_INBAND_ENABLED: inband mode selected and autoneg enabled
++ *
++ * Note: this is for cases where the PCS itself is involved in negotiation
++ * (e.g. Clause 37, SGMII and similar) not Clause 73.
++ */
++static unsigned int phylink_pcs_neg_mode(unsigned int mode,
++ phy_interface_t interface,
++ const unsigned long *advertising)
++{
++ unsigned int neg_mode;
++
++ switch (interface) {
++ case PHY_INTERFACE_MODE_SGMII:
++ case PHY_INTERFACE_MODE_QSGMII:
++ case PHY_INTERFACE_MODE_QUSGMII:
++ case PHY_INTERFACE_MODE_USXGMII:
++ /* These protocols are designed for use with a PHY which
++ * communicates its negotiation result back to the MAC via
++ * inband communication. Note: there exist PHYs that run
++ * with SGMII but do not send the inband data.
++ */
++ if (!phylink_autoneg_inband(mode))
++ neg_mode = PHYLINK_PCS_NEG_OUTBAND;
++ else
++ neg_mode = PHYLINK_PCS_NEG_INBAND_ENABLED;
++ break;
++
++ case PHY_INTERFACE_MODE_1000BASEX:
++ case PHY_INTERFACE_MODE_2500BASEX:
++ /* 1000base-X is designed for use media-side for Fibre
++ * connections, and thus the Autoneg bit needs to be
++ * taken into account. We also do this for 2500base-X
++ * as well, but drivers may not support this, so may
++ * need to override this.
++ */
++ if (!phylink_autoneg_inband(mode))
++ neg_mode = PHYLINK_PCS_NEG_OUTBAND;
++ else if (linkmode_test_bit(ETHTOOL_LINK_MODE_Autoneg_BIT,
++ advertising))
++ neg_mode = PHYLINK_PCS_NEG_INBAND_ENABLED;
++ else
++ neg_mode = PHYLINK_PCS_NEG_INBAND_DISABLED;
++ break;
++
++ default:
++ neg_mode = PHYLINK_PCS_NEG_NONE;
++ break;
++ }
++
++ return neg_mode;
++}
++
+ static void phylink_major_config(struct phylink *pl, bool restart,
+ const struct phylink_link_state *state)
+ {
+--- a/include/linux/phylink.h
++++ b/include/linux/phylink.h
+@@ -99,72 +99,6 @@ static inline bool phylink_autoneg_inban
+ }
+
+ /**
+- * phylink_pcs_neg_mode() - helper to determine PCS inband mode
+- * @mode: one of %MLO_AN_FIXED, %MLO_AN_PHY, %MLO_AN_INBAND.
+- * @interface: interface mode to be used
+- * @advertising: adertisement ethtool link mode mask
+- *
+- * Determines the negotiation mode to be used by the PCS, and returns
+- * one of:
+- *
+- * - %PHYLINK_PCS_NEG_NONE: interface mode does not support inband
+- * - %PHYLINK_PCS_NEG_OUTBAND: an out of band mode (e.g. reading the PHY)
+- * will be used.
+- * - %PHYLINK_PCS_NEG_INBAND_DISABLED: inband mode selected but autoneg
+- * disabled
+- * - %PHYLINK_PCS_NEG_INBAND_ENABLED: inband mode selected and autoneg enabled
+- *
+- * Note: this is for cases where the PCS itself is involved in negotiation
+- * (e.g. Clause 37, SGMII and similar) not Clause 73.
+- */
+-static inline unsigned int phylink_pcs_neg_mode(unsigned int mode,
+- phy_interface_t interface,
+- const unsigned long *advertising)
+-{
+- unsigned int neg_mode;
+-
+- switch (interface) {
+- case PHY_INTERFACE_MODE_SGMII:
+- case PHY_INTERFACE_MODE_QSGMII:
+- case PHY_INTERFACE_MODE_QUSGMII:
+- case PHY_INTERFACE_MODE_USXGMII:
+- /* These protocols are designed for use with a PHY which
+- * communicates its negotiation result back to the MAC via
+- * inband communication. Note: there exist PHYs that run
+- * with SGMII but do not send the inband data.
+- */
+- if (!phylink_autoneg_inband(mode))
+- neg_mode = PHYLINK_PCS_NEG_OUTBAND;
+- else
+- neg_mode = PHYLINK_PCS_NEG_INBAND_ENABLED;
+- break;
+-
+- case PHY_INTERFACE_MODE_1000BASEX:
+- case PHY_INTERFACE_MODE_2500BASEX:
+- /* 1000base-X is designed for use media-side for Fibre
+- * connections, and thus the Autoneg bit needs to be
+- * taken into account. We also do this for 2500base-X
+- * as well, but drivers may not support this, so may
+- * need to override this.
+- */
+- if (!phylink_autoneg_inband(mode))
+- neg_mode = PHYLINK_PCS_NEG_OUTBAND;
+- else if (linkmode_test_bit(ETHTOOL_LINK_MODE_Autoneg_BIT,
+- advertising))
+- neg_mode = PHYLINK_PCS_NEG_INBAND_ENABLED;
+- else
+- neg_mode = PHYLINK_PCS_NEG_INBAND_DISABLED;
+- break;
+-
+- default:
+- neg_mode = PHYLINK_PCS_NEG_NONE;
+- break;
+- }
+-
+- return neg_mode;
+-}
+-
+-/**
+ * struct phylink_link_state - link state structure
+ * @advertising: ethtool bitmask containing advertised link modes
+ * @lp_advertising: ethtool bitmask containing link partner advertised link
--- /dev/null
+From: "Russell King (Oracle)" <linux@armlinux.org.uk>
+To: Andrew Lunn <andrew@lunn.ch>, Heiner Kallweit <hkallweit1@gmail.com>
+Cc: Alexander Couzens <lynxis@fe80.eu>,
+ Andrew Lunn <andrew+netdev@lunn.ch>,
+ AngeloGioacchino Del Regno
+ <angelogioacchino.delregno@collabora.com>,
+ Broadcom internal kernel review list
+ <bcm-kernel-feedback-list@broadcom.com>,
+ Daniel Golle <daniel@makrotopia.org>,
+ "David S. Miller" <davem@davemloft.net>,
+ Eric Dumazet <edumazet@google.com>,
+ Florian Fainelli <florian.fainelli@broadcom.com>,
+ Ioana Ciornei <ioana.ciornei@nxp.com>,
+ Jakub Kicinski <kuba@kernel.org>,
+ Jose Abreu <Jose.Abreu@synopsys.com>,
+ linux-arm-kernel@lists.infradead.org,
+ linux-mediatek@lists.infradead.org,
+ Marcin Wojtas <marcin.s.wojtas@gmail.com>,
+ Matthias Brugger <matthias.bgg@gmail.com>,
+ netdev@vger.kernel.org, Paolo Abeni <pabeni@redhat.com>
+Subject: [PATCH RFC net-next 00/16] net: add negotiation of in-band capabilities
+Date: Tue, 26 Nov 2024 09:23:48 +0000 [thread overview]
+Message-ID: <Z0WTpE8wkpjMiv_J@shell.armlinux.org.uk> (raw)
+
+Hi,
+
+Yes, this is one patch over the limit of 15 for netdev - but I think it's
+important to include the last patch to head off review comments like "why
+don't you remove phylink_phy_no_inband() in this series?"
+
+Phylink's handling of in-band has been deficient for a long time, and
+people keep hitting problems with it. Notably, situations with the way-
+to-late standardized 2500Base-X and whether that should or should not
+have in-band enabled. We have also been carrying a hack in the form of
+phylink_phy_no_inband() for a PHY that has been used on a SFP module,
+but has no in-band capabilities, not even for SGMII.
+
+When phylink is trying to operate in in-band mode, this series will look
+at the capabilities of the MAC-side PCS and PHY, and work out whether
+in-band can or should be used, programming the PHY as appropriate. This
+includes in-band bypass mode at the PHY.
+
+We don't... yet... support that on the MAC side PCS, because that
+requires yet more complexity.
+
+Patch 1 passes struct phylink and struct phylink_pcs into
+phylink_pcs_neg_mode() so we can look at more state in this function in
+a future patch.
+
+Patch 2 splits "cur_link_an_mode" (the MLO_AN_* mode) into two separate
+purposes - a requested and an active mode. The active mode is the one
+we will be using for the MAC, which becomes dependent on the result of
+in-band negotiation.
+
+Patch 3 adds debug to phylink_major_config() so we can see what is going
+on with the requested and active AN modes.
+
+Patch 4 adds to phylib a method to get the in-band capabilities of the
+PHY from phylib. Patches 5 and 6 add implementations for BCM84881 and
+some Marvell PHYs found on SFPs.
+
+Patch 7 adds to phylib a method to configure the PHY in-band signalling,
+and patch 8 implements it for those Marvell PHYs that support the method
+in patch 4.
+
+Patch 9 does the same as patch 4 but for the MAC-side PCS, with patches
+10 through 14 adding support to several PCS.
+
+Patch 15 adds the code to phylink_pcs_neg_mode() which looks at the
+capabilities, and works out whether to use in-band or out-band mode for
+driving the link between the MAC PCS and PHY.
+
+Patch 16 removes the phylink_phy_no_inband() hack now that we are
+publishing the in-band capabilities from the BCM84881 PHY driver.
+
+ drivers/net/ethernet/marvell/mvneta.c | 27 +-
+ drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c | 25 +-
+ drivers/net/pcs/pcs-lynx.c | 22 ++
+ drivers/net/pcs/pcs-mtk-lynxi.c | 16 ++
+ drivers/net/pcs/pcs-xpcs.c | 28 ++
+ drivers/net/phy/bcm84881.c | 10 +
+ drivers/net/phy/marvell.c | 48 ++++
+ drivers/net/phy/phy.c | 52 ++++
+ drivers/net/phy/phylink.c | 352 +++++++++++++++++++-----
+ include/linux/phy.h | 34 +++
+ include/linux/phylink.h | 17 ++
+ 11 files changed, 539 insertions(+), 92 deletions(-)
+
+--- a/drivers/net/phy/phylink.c
++++ b/drivers/net/phy/phylink.c
+@@ -56,7 +56,8 @@ struct phylink {
+ struct phy_device *phydev;
+ phy_interface_t link_interface; /* PHY_INTERFACE_xxx */
+ u8 cfg_link_an_mode; /* MLO_AN_xxx */
+- u8 cur_link_an_mode;
++ u8 req_link_an_mode; /* Requested MLO_AN_xxx mode */
++ u8 act_link_an_mode; /* Active MLO_AN_xxx mode */
+ u8 link_port; /* The current non-phy ethtool port */
+ __ETHTOOL_DECLARE_LINK_MODE_MASK(supported);
+
+@@ -74,6 +75,7 @@ struct phylink {
+
+ struct mutex state_mutex;
+ struct phylink_link_state phy_state;
++ unsigned int phy_ib_mode;
+ struct work_struct resolve;
+ unsigned int pcs_neg_mode;
+ unsigned int pcs_state;
+@@ -175,6 +177,24 @@ static const char *phylink_an_mode_str(u
+ return mode < ARRAY_SIZE(modestr) ? modestr[mode] : "unknown";
+ }
+
++static const char *phylink_pcs_mode_str(unsigned int mode)
++{
++ if (!mode)
++ return "none";
++
++ if (mode & PHYLINK_PCS_NEG_OUTBAND)
++ return "outband";
++
++ if (mode & PHYLINK_PCS_NEG_INBAND) {
++ if (mode & PHYLINK_PCS_NEG_ENABLED)
++ return "inband,an-enabled";
++ else
++ return "inband,an-disabled";
++ }
++
++ return "unknown";
++}
++
+ static unsigned int phylink_interface_signal_rate(phy_interface_t interface)
+ {
+ switch (interface) {
+@@ -1053,6 +1073,15 @@ static void phylink_resolve_an_pause(str
+ }
+ }
+
++static unsigned int phylink_pcs_inband_caps(struct phylink_pcs *pcs,
++ phy_interface_t interface)
++{
++ if (pcs && pcs->ops->pcs_inband_caps)
++ return pcs->ops->pcs_inband_caps(pcs, interface);
++
++ return 0;
++}
++
+ static void phylink_pcs_pre_config(struct phylink_pcs *pcs,
+ phy_interface_t interface)
+ {
+@@ -1106,6 +1135,24 @@ static void phylink_pcs_link_up(struct p
+ pcs->ops->pcs_link_up(pcs, neg_mode, interface, speed, duplex);
+ }
+
++/* Query inband for a specific interface mode, asking the MAC for the
++ * PCS which will be used to handle the interface mode.
++ */
++static unsigned int phylink_inband_caps(struct phylink *pl,
++ phy_interface_t interface)
++{
++ struct phylink_pcs *pcs;
++
++ if (!pl->mac_ops->mac_select_pcs)
++ return 0;
++
++ pcs = pl->mac_ops->mac_select_pcs(pl->config, interface);
++ if (!pcs)
++ return 0;
++
++ return phylink_pcs_inband_caps(pcs, interface);
++}
++
+ static void phylink_pcs_poll_stop(struct phylink *pl)
+ {
+ if (pl->cfg_link_an_mode == MLO_AN_INBAND)
+@@ -1132,13 +1179,13 @@ static void phylink_mac_config(struct ph
+
+ phylink_dbg(pl,
+ "%s: mode=%s/%s/%s adv=%*pb pause=%02x\n",
+- __func__, phylink_an_mode_str(pl->cur_link_an_mode),
++ __func__, phylink_an_mode_str(pl->act_link_an_mode),
+ phy_modes(st.interface),
+ phy_rate_matching_to_str(st.rate_matching),
+ __ETHTOOL_LINK_MODE_MASK_NBITS, st.advertising,
+ st.pause);
+
+- pl->mac_ops->mac_config(pl->config, pl->cur_link_an_mode, &st);
++ pl->mac_ops->mac_config(pl->config, pl->act_link_an_mode, &st);
+ }
+
+ static void phylink_pcs_an_restart(struct phylink *pl)
+@@ -1146,13 +1193,14 @@ static void phylink_pcs_an_restart(struc
+ if (pl->pcs && linkmode_test_bit(ETHTOOL_LINK_MODE_Autoneg_BIT,
+ pl->link_config.advertising) &&
+ phy_interface_mode_is_8023z(pl->link_config.interface) &&
+- phylink_autoneg_inband(pl->cur_link_an_mode))
++ phylink_autoneg_inband(pl->act_link_an_mode))
+ pl->pcs->ops->pcs_an_restart(pl->pcs);
+ }
+
+ /**
+ * phylink_pcs_neg_mode() - helper to determine PCS inband mode
+- * @mode: one of %MLO_AN_FIXED, %MLO_AN_PHY, %MLO_AN_INBAND.
++ * @pl: a pointer to a &struct phylink returned from phylink_create()
++ * @pcs: a pointer to &struct phylink_pcs
+ * @interface: interface mode to be used
+ * @advertising: adertisement ethtool link mode mask
+ *
+@@ -1169,11 +1217,21 @@ static void phylink_pcs_an_restart(struc
+ * Note: this is for cases where the PCS itself is involved in negotiation
+ * (e.g. Clause 37, SGMII and similar) not Clause 73.
+ */
+-static unsigned int phylink_pcs_neg_mode(unsigned int mode,
+- phy_interface_t interface,
+- const unsigned long *advertising)
++static void phylink_pcs_neg_mode(struct phylink *pl, struct phylink_pcs *pcs,
++ phy_interface_t interface,
++ const unsigned long *advertising)
+ {
+- unsigned int neg_mode;
++ unsigned int pcs_ib_caps = 0;
++ unsigned int phy_ib_caps = 0;
++ unsigned int neg_mode, mode;
++ enum {
++ INBAND_CISCO_SGMII,
++ INBAND_BASEX,
++ } type;
++
++ mode = pl->req_link_an_mode;
++
++ pl->phy_ib_mode = 0;
+
+ switch (interface) {
+ case PHY_INTERFACE_MODE_SGMII:
+@@ -1185,10 +1243,7 @@ static unsigned int phylink_pcs_neg_mode
+ * inband communication. Note: there exist PHYs that run
+ * with SGMII but do not send the inband data.
+ */
+- if (!phylink_autoneg_inband(mode))
+- neg_mode = PHYLINK_PCS_NEG_OUTBAND;
+- else
+- neg_mode = PHYLINK_PCS_NEG_INBAND_ENABLED;
++ type = INBAND_CISCO_SGMII;
+ break;
+
+ case PHY_INTERFACE_MODE_1000BASEX:
+@@ -1199,21 +1254,143 @@ static unsigned int phylink_pcs_neg_mode
+ * as well, but drivers may not support this, so may
+ * need to override this.
+ */
+- if (!phylink_autoneg_inband(mode))
++ type = INBAND_BASEX;
++ break;
++
++ default:
++ pl->pcs_neg_mode = PHYLINK_PCS_NEG_NONE;
++ pl->act_link_an_mode = mode;
++ return;
++ }
++
++ if (pcs)
++ pcs_ib_caps = phylink_pcs_inband_caps(pcs, interface);
++
++ if (pl->phydev)
++ phy_ib_caps = phy_inband_caps(pl->phydev, interface);
++
++ phylink_dbg(pl, "interface %s inband modes: pcs=%02x phy=%02x\n",
++ phy_modes(interface), pcs_ib_caps, phy_ib_caps);
++
++ if (!phylink_autoneg_inband(mode)) {
++ bool pcs_ib_only = false;
++ bool phy_ib_only = false;
++
++ if (pcs_ib_caps && pcs_ib_caps != LINK_INBAND_DISABLE) {
++ /* PCS supports reporting in-band capabilities, and
++ * supports more than disable mode.
++ */
++ if (pcs_ib_caps & LINK_INBAND_DISABLE)
++ neg_mode = PHYLINK_PCS_NEG_OUTBAND;
++ else if (pcs_ib_caps & LINK_INBAND_ENABLE)
++ pcs_ib_only = true;
++ }
++
++ if (phy_ib_caps && phy_ib_caps != LINK_INBAND_DISABLE) {
++ /* PHY supports in-band capabilities, and supports
++ * more than disable mode.
++ */
++ if (phy_ib_caps & LINK_INBAND_DISABLE)
++ pl->phy_ib_mode = LINK_INBAND_DISABLE;
++ else if (phy_ib_caps & LINK_INBAND_BYPASS)
++ pl->phy_ib_mode = LINK_INBAND_BYPASS;
++ else if (phy_ib_caps & LINK_INBAND_ENABLE)
++ phy_ib_only = true;
++ }
++
++ /* If either the PCS or PHY requires inband to be enabled,
++ * this is an invalid configuration. Provide a diagnostic
++ * message for this case, but don't try to force the issue.
++ */
++ if (pcs_ib_only || phy_ib_only)
++ phylink_warn(pl,
++ "firmware wants %s mode, but %s%s%s requires inband\n",
++ phylink_an_mode_str(mode),
++ pcs_ib_only ? "PCS" : "",
++ pcs_ib_only && phy_ib_only ? " and " : "",
++ phy_ib_only ? "PHY" : "");
++
++ neg_mode = PHYLINK_PCS_NEG_OUTBAND;
++ } else if (type == INBAND_CISCO_SGMII || pl->phydev) {
++ /* For SGMII modes which are designed to be used with PHYs, or
++ * Base-X with a PHY, we try to use in-band mode where-ever
++ * possible. However, there are some PHYs e.g. BCM84881 which
++ * do not support in-band.
++ */
++ const unsigned int inband_ok = LINK_INBAND_ENABLE |
++ LINK_INBAND_BYPASS;
++ const unsigned int outband_ok = LINK_INBAND_DISABLE |
++ LINK_INBAND_BYPASS;
++ /* PCS PHY
++ * D E D E
++ * 0 0 0 0 no information inband enabled
++ * 1 0 0 0 pcs doesn't support outband
++ * 0 1 0 0 pcs required inband enabled
++ * 1 1 0 0 pcs optional inband enabled
++ * 0 0 1 0 phy doesn't support outband
++ * 1 0 1 0 pcs+phy doesn't support outband
++ * 0 1 1 0 pcs required, phy doesn't support, invalid
++ * 1 1 1 0 pcs optional, phy doesn't support, outband
++ * 0 0 0 1 phy required inband enabled
++ * 1 0 0 1 pcs doesn't support, phy required, invalid
++ * 0 1 0 1 pcs+phy required inband enabled
++ * 1 1 0 1 pcs optional, phy required inband enabled
++ * 0 0 1 1 phy optional inband enabled
++ * 1 0 1 1 pcs doesn't support, phy optional, outband
++ * 0 1 1 1 pcs required, phy optional inband enabled
++ * 1 1 1 1 pcs+phy optional inband enabled
++ */
++ if ((!pcs_ib_caps || pcs_ib_caps & inband_ok) &&
++ (!phy_ib_caps || phy_ib_caps & inband_ok)) {
++ /* In-band supported or unknown at both ends. Enable
++ * in-band mode with or without bypass at the PHY.
++ */
++ if (phy_ib_caps & LINK_INBAND_ENABLE)
++ pl->phy_ib_mode = LINK_INBAND_ENABLE;
++ else if (phy_ib_caps & LINK_INBAND_BYPASS)
++ pl->phy_ib_mode = LINK_INBAND_BYPASS;
++
++ neg_mode = PHYLINK_PCS_NEG_INBAND_ENABLED;
++ } else if ((!pcs_ib_caps || pcs_ib_caps & outband_ok) &&
++ (!phy_ib_caps || phy_ib_caps & outband_ok)) {
++ /* Either in-band not supported at at least one end.
++ * In-band bypass at the other end is possible.
++ */
++ if (phy_ib_caps & LINK_INBAND_DISABLE)
++ pl->phy_ib_mode = LINK_INBAND_DISABLE;
++ else if (phy_ib_caps & LINK_INBAND_BYPASS)
++ pl->phy_ib_mode = LINK_INBAND_BYPASS;
++
+ neg_mode = PHYLINK_PCS_NEG_OUTBAND;
++ if (pl->phydev)
++ mode = MLO_AN_PHY;
++ } else {
++ /* invalid */
++ phylink_warn(pl, "%s: incompatible in-band capabilities, trying in-band",
++ phy_modes(interface));
++ neg_mode = PHYLINK_PCS_NEG_INBAND_ENABLED;
++ }
++ } else {
++ /* For Base-X without a PHY */
++ if (pcs_ib_caps == LINK_INBAND_DISABLE)
++ /* If the PCS doesn't support inband, then inband must
++ * be disabled.
++ */
++ neg_mode = PHYLINK_PCS_NEG_INBAND_DISABLED;
++ else if (pcs_ib_caps == LINK_INBAND_ENABLE)
++ /* If the PCS requires inband, then inband must always
++ * be enabled.
++ */
++ neg_mode = PHYLINK_PCS_NEG_INBAND_ENABLED;
+ else if (linkmode_test_bit(ETHTOOL_LINK_MODE_Autoneg_BIT,
+ advertising))
+ neg_mode = PHYLINK_PCS_NEG_INBAND_ENABLED;
+ else
+ neg_mode = PHYLINK_PCS_NEG_INBAND_DISABLED;
+- break;
+-
+- default:
+- neg_mode = PHYLINK_PCS_NEG_NONE;
+- break;
+ }
+
+- return neg_mode;
++ pl->pcs_neg_mode = neg_mode;
++ pl->act_link_an_mode = mode;
+ }
+
+ static void phylink_major_config(struct phylink *pl, bool restart,
+@@ -1225,11 +1402,9 @@ static void phylink_major_config(struct
+ unsigned int neg_mode;
+ int err;
+
+- phylink_dbg(pl, "major config %s\n", phy_modes(state->interface));
+-
+- pl->pcs_neg_mode = phylink_pcs_neg_mode(pl->cur_link_an_mode,
+- state->interface,
+- state->advertising);
++ phylink_dbg(pl, "major config, requested %s/%s\n",
++ phylink_an_mode_str(pl->req_link_an_mode),
++ phy_modes(state->interface));
+
+ if (pl->using_mac_select_pcs) {
+ pcs = pl->mac_ops->mac_select_pcs(pl->config, state->interface);
+@@ -1243,10 +1418,17 @@ static void phylink_major_config(struct
+ pcs_changed = pcs && pl->pcs != pcs;
+ }
+
++ phylink_pcs_neg_mode(pl, pcs, state->interface, state->advertising);
++
++ phylink_dbg(pl, "major config, active %s/%s/%s\n",
++ phylink_an_mode_str(pl->act_link_an_mode),
++ phylink_pcs_mode_str(pl->pcs_neg_mode),
++ phy_modes(state->interface));
++
+ phylink_pcs_poll_stop(pl);
+
+ if (pl->mac_ops->mac_prepare) {
+- err = pl->mac_ops->mac_prepare(pl->config, pl->cur_link_an_mode,
++ err = pl->mac_ops->mac_prepare(pl->config, pl->act_link_an_mode,
+ state->interface);
+ if (err < 0) {
+ phylink_err(pl, "mac_prepare failed: %pe\n",
+@@ -1280,7 +1462,7 @@ static void phylink_major_config(struct
+ if (pl->pcs_state == PCS_STATE_STARTING || pcs_changed)
+ phylink_pcs_enable(pl->pcs);
+
+- neg_mode = pl->cur_link_an_mode;
++ neg_mode = pl->act_link_an_mode;
+ if (pl->pcs && pl->pcs->neg_mode)
+ neg_mode = pl->pcs_neg_mode;
+
+@@ -1296,13 +1478,20 @@ static void phylink_major_config(struct
+ phylink_pcs_an_restart(pl);
+
+ if (pl->mac_ops->mac_finish) {
+- err = pl->mac_ops->mac_finish(pl->config, pl->cur_link_an_mode,
++ err = pl->mac_ops->mac_finish(pl->config, pl->act_link_an_mode,
+ state->interface);
+ if (err < 0)
+ phylink_err(pl, "mac_finish failed: %pe\n",
+ ERR_PTR(err));
+ }
+
++ if (pl->phydev && pl->phy_ib_mode) {
++ err = phy_config_inband(pl->phydev, pl->phy_ib_mode);
++ if (err < 0)
++ phylink_err(pl, "phy_config_inband: %pe\n",
++ ERR_PTR(err));
++ }
++
+ if (pl->sfp_bus) {
+ rate_kbd = phylink_interface_signal_rate(state->interface);
+ if (rate_kbd)
+@@ -1327,17 +1516,16 @@ static int phylink_change_inband_advert(
+ return 0;
+
+ phylink_dbg(pl, "%s: mode=%s/%s adv=%*pb pause=%02x\n", __func__,
+- phylink_an_mode_str(pl->cur_link_an_mode),
++ phylink_an_mode_str(pl->req_link_an_mode),
+ phy_modes(pl->link_config.interface),
+ __ETHTOOL_LINK_MODE_MASK_NBITS, pl->link_config.advertising,
+ pl->link_config.pause);
+
+ /* Recompute the PCS neg mode */
+- pl->pcs_neg_mode = phylink_pcs_neg_mode(pl->cur_link_an_mode,
+- pl->link_config.interface,
+- pl->link_config.advertising);
++ phylink_pcs_neg_mode(pl, pl->pcs, pl->link_config.interface,
++ pl->link_config.advertising);
+
+- neg_mode = pl->cur_link_an_mode;
++ neg_mode = pl->act_link_an_mode;
+ if (pl->pcs->neg_mode)
+ neg_mode = pl->pcs_neg_mode;
+
+@@ -1402,7 +1590,7 @@ static void phylink_mac_initial_config(s
+ {
+ struct phylink_link_state link_state;
+
+- switch (pl->cur_link_an_mode) {
++ switch (pl->req_link_an_mode) {
+ case MLO_AN_PHY:
+ link_state = pl->phy_state;
+ break;
+@@ -1476,14 +1664,14 @@ static void phylink_link_up(struct phyli
+
+ pl->cur_interface = link_state.interface;
+
+- neg_mode = pl->cur_link_an_mode;
++ neg_mode = pl->act_link_an_mode;
+ if (pl->pcs && pl->pcs->neg_mode)
+ neg_mode = pl->pcs_neg_mode;
+
+ phylink_pcs_link_up(pl->pcs, neg_mode, pl->cur_interface, speed,
+ duplex);
+
+- pl->mac_ops->mac_link_up(pl->config, pl->phydev, pl->cur_link_an_mode,
++ pl->mac_ops->mac_link_up(pl->config, pl->phydev, pl->act_link_an_mode,
+ pl->cur_interface, speed, duplex,
+ !!(link_state.pause & MLO_PAUSE_TX), rx_pause);
+
+@@ -1503,7 +1691,7 @@ static void phylink_link_down(struct phy
+
+ if (ndev)
+ netif_carrier_off(ndev);
+- pl->mac_ops->mac_link_down(pl->config, pl->cur_link_an_mode,
++ pl->mac_ops->mac_link_down(pl->config, pl->act_link_an_mode,
+ pl->cur_interface);
+ phylink_info(pl, "Link is Down\n");
+ }
+@@ -1530,7 +1718,7 @@ static void phylink_resolve(struct work_
+ link_state.link = false;
+ retrigger = true;
+ } else {
+- switch (pl->cur_link_an_mode) {
++ switch (pl->act_link_an_mode) {
+ case MLO_AN_PHY:
+ link_state = pl->phy_state;
+ phylink_apply_manual_flow(pl, &link_state);
+@@ -1773,7 +1961,7 @@ struct phylink *phylink_create(struct ph
+ }
+ }
+
+- pl->cur_link_an_mode = pl->cfg_link_an_mode;
++ pl->req_link_an_mode = pl->cfg_link_an_mode;
+
+ ret = phylink_register_sfp(pl, fwnode);
+ if (ret < 0) {
+@@ -2236,7 +2424,7 @@ void phylink_start(struct phylink *pl)
+ ASSERT_RTNL();
+
+ phylink_info(pl, "configuring for %s/%s link mode\n",
+- phylink_an_mode_str(pl->cur_link_an_mode),
++ phylink_an_mode_str(pl->req_link_an_mode),
+ phy_modes(pl->link_config.interface));
+
+ /* Always set the carrier off */
+@@ -2495,7 +2683,7 @@ int phylink_ethtool_ksettings_get(struct
+
+ linkmode_copy(kset->link_modes.supported, pl->supported);
+
+- switch (pl->cur_link_an_mode) {
++ switch (pl->act_link_an_mode) {
+ case MLO_AN_FIXED:
+ /* We are using fixed settings. Report these as the
+ * current link settings - and note that these also
+@@ -2526,6 +2714,26 @@ int phylink_ethtool_ksettings_get(struct
+ }
+ EXPORT_SYMBOL_GPL(phylink_ethtool_ksettings_get);
+
++static bool phylink_validate_pcs_inband_autoneg(struct phylink *pl,
++ phy_interface_t interface,
++ unsigned long *adv)
++{
++ unsigned int inband = phylink_inband_caps(pl, interface);
++ unsigned int mask;
++
++ /* If the PCS doesn't implement inband support, be permissive. */
++ if (!inband)
++ return true;
++
++ if (linkmode_test_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, adv))
++ mask = LINK_INBAND_ENABLE;
++ else
++ mask = LINK_INBAND_DISABLE;
++
++ /* Check whether the PCS implements the required mode */
++ return !!(inband & mask);
++}
++
+ /**
+ * phylink_ethtool_ksettings_set() - set the link settings
+ * @pl: a pointer to a &struct phylink returned from phylink_create()
+@@ -2587,7 +2795,7 @@ int phylink_ethtool_ksettings_set(struct
+ /* If we have a fixed link, refuse to change link parameters.
+ * If the link parameters match, accept them but do nothing.
+ */
+- if (pl->cur_link_an_mode == MLO_AN_FIXED) {
++ if (pl->req_link_an_mode == MLO_AN_FIXED) {
+ if (s->speed != pl->link_config.speed ||
+ s->duplex != pl->link_config.duplex)
+ return -EINVAL;
+@@ -2603,7 +2811,7 @@ int phylink_ethtool_ksettings_set(struct
+ * is our default case) but do not allow the advertisement to
+ * be changed. If the advertisement matches, simply return.
+ */
+- if (pl->cur_link_an_mode == MLO_AN_FIXED) {
++ if (pl->req_link_an_mode == MLO_AN_FIXED) {
+ if (!linkmode_equal(config.advertising,
+ pl->link_config.advertising))
+ return -EINVAL;
+@@ -2643,7 +2851,7 @@ int phylink_ethtool_ksettings_set(struct
+ linkmode_copy(support, pl->supported);
+ if (phylink_validate(pl, support, &config)) {
+ phylink_err(pl, "validation of %s/%s with support %*pb failed\n",
+- phylink_an_mode_str(pl->cur_link_an_mode),
++ phylink_an_mode_str(pl->req_link_an_mode),
+ phy_modes(config.interface),
+ __ETHTOOL_LINK_MODE_MASK_NBITS, support);
+ return -EINVAL;
+@@ -2661,6 +2869,13 @@ int phylink_ethtool_ksettings_set(struct
+ phylink_is_empty_linkmode(config.advertising))
+ return -EINVAL;
+
++ /* Validate the autonegotiation state. We don't have a PHY in this
++ * situation, so the PCS is the media-facing entity.
++ */
++ if (!phylink_validate_pcs_inband_autoneg(pl, config.interface,
++ config.advertising))
++ return -EINVAL;
++
+ mutex_lock(&pl->state_mutex);
+ pl->link_config.speed = config.speed;
+ pl->link_config.duplex = config.duplex;
+@@ -2743,7 +2958,7 @@ int phylink_ethtool_set_pauseparam(struc
+
+ ASSERT_RTNL();
+
+- if (pl->cur_link_an_mode == MLO_AN_FIXED)
++ if (pl->req_link_an_mode == MLO_AN_FIXED)
+ return -EOPNOTSUPP;
+
+ if (!phylink_test(pl->supported, Pause) &&
+@@ -3007,7 +3222,7 @@ static int phylink_mii_read(struct phyli
+ struct phylink_link_state state;
+ int val = 0xffff;
+
+- switch (pl->cur_link_an_mode) {
++ switch (pl->act_link_an_mode) {
+ case MLO_AN_FIXED:
+ if (phy_id == 0) {
+ phylink_get_fixed_state(pl, &state);
+@@ -3032,7 +3247,7 @@ static int phylink_mii_read(struct phyli
+ static int phylink_mii_write(struct phylink *pl, unsigned int phy_id,
+ unsigned int reg, unsigned int val)
+ {
+- switch (pl->cur_link_an_mode) {
++ switch (pl->act_link_an_mode) {
+ case MLO_AN_FIXED:
+ break;
+
+@@ -3202,10 +3417,11 @@ static phy_interface_t phylink_choose_sf
+ return interface;
+ }
+
+-static void phylink_sfp_set_config(struct phylink *pl, u8 mode,
++static void phylink_sfp_set_config(struct phylink *pl,
+ unsigned long *supported,
+ struct phylink_link_state *state)
+ {
++ u8 mode = MLO_AN_INBAND;
+ bool changed = false;
+
+ phylink_dbg(pl, "requesting link mode %s/%s with support %*pb\n",
+@@ -3222,9 +3438,9 @@ static void phylink_sfp_set_config(struc
+ changed = true;
+ }
+
+- if (pl->cur_link_an_mode != mode ||
++ if (pl->req_link_an_mode != mode ||
+ pl->link_config.interface != state->interface) {
+- pl->cur_link_an_mode = mode;
++ pl->req_link_an_mode = mode;
+ pl->link_config.interface = state->interface;
+
+ changed = true;
+@@ -3239,8 +3455,7 @@ static void phylink_sfp_set_config(struc
+ phylink_mac_initial_config(pl, false);
+ }
+
+-static int phylink_sfp_config_phy(struct phylink *pl, u8 mode,
+- struct phy_device *phy)
++static int phylink_sfp_config_phy(struct phylink *pl, struct phy_device *phy)
+ {
+ __ETHTOOL_DECLARE_LINK_MODE_MASK(support1);
+ __ETHTOOL_DECLARE_LINK_MODE_MASK(support);
+@@ -3279,8 +3494,7 @@ static int phylink_sfp_config_phy(struct
+ ret = phylink_validate(pl, support1, &config);
+ if (ret) {
+ phylink_err(pl,
+- "validation of %s/%s with support %*pb failed: %pe\n",
+- phylink_an_mode_str(mode),
++ "validation of %s with support %*pb failed: %pe\n",
+ phy_modes(config.interface),
+ __ETHTOOL_LINK_MODE_MASK_NBITS, support,
+ ERR_PTR(ret));
+@@ -3289,7 +3503,7 @@ static int phylink_sfp_config_phy(struct
+
+ pl->link_port = pl->sfp_port;
+
+- phylink_sfp_set_config(pl, mode, support, &config);
++ phylink_sfp_set_config(pl, support, &config);
+
+ return 0;
+ }
+@@ -3345,6 +3559,12 @@ static int phylink_sfp_config_optical(st
+ phylink_dbg(pl, "optical SFP: chosen %s interface\n",
+ phy_modes(interface));
+
++ if (!phylink_validate_pcs_inband_autoneg(pl, interface,
++ config.advertising)) {
++ phylink_err(pl, "autoneg setting not compatible with PCS");
++ return -EINVAL;
++ }
++
+ config.interface = interface;
+
+ /* Ignore errors if we're expecting a PHY to attach later */
+@@ -3358,7 +3578,7 @@ static int phylink_sfp_config_optical(st
+
+ pl->link_port = pl->sfp_port;
+
+- phylink_sfp_set_config(pl, MLO_AN_INBAND, pl->sfp_support, &config);
++ phylink_sfp_set_config(pl, pl->sfp_support, &config);
+
+ return 0;
+ }
+@@ -3429,20 +3649,10 @@ static void phylink_sfp_link_up(void *up
+ phylink_enable_and_run_resolve(pl, PHYLINK_DISABLE_LINK);
+ }
+
+-/* The Broadcom BCM84881 in the Methode DM7052 is unable to provide a SGMII
+- * or 802.3z control word, so inband will not work.
+- */
+-static bool phylink_phy_no_inband(struct phy_device *phy)
+-{
+- return phy->is_c45 && phy_id_compare(phy->c45_ids.device_ids[1],
+- 0xae025150, 0xfffffff0);
+-}
+-
+ static int phylink_sfp_connect_phy(void *upstream, struct phy_device *phy)
+ {
+ struct phylink *pl = upstream;
+ phy_interface_t interface;
+- u8 mode;
+ int ret;
+
+ /*
+@@ -3454,17 +3664,12 @@ static int phylink_sfp_connect_phy(void
+ */
+ phy_support_asym_pause(phy);
+
+- if (phylink_phy_no_inband(phy))
+- mode = MLO_AN_PHY;
+- else
+- mode = MLO_AN_INBAND;
+-
+ /* Set the PHY's host supported interfaces */
+ phy_interface_and(phy->host_interfaces, phylink_sfp_interfaces,
+ pl->config->supported_interfaces);
+
+ /* Do the initial configuration */
+- ret = phylink_sfp_config_phy(pl, mode, phy);
++ ret = phylink_sfp_config_phy(pl, phy);
+ if (ret < 0)
+ return ret;
+
+--- a/drivers/net/phy/phy.c
++++ b/drivers/net/phy/phy.c
+@@ -973,6 +973,58 @@ static int phy_check_link_status(struct
+ }
+
+ /**
++ * phy_inband_caps - query which in-band signalling modes are supported
++ * @phydev: a pointer to a &struct phy_device
++ * @interface: the interface mode for the PHY
++ *
++ * Returns zero if it is unknown what in-band signalling is supported by the
++ * PHY (e.g. because the PHY driver doesn't implement the method.) Otherwise,
++ * returns a bit mask of the LINK_INBAND_* values from
++ * &enum link_inband_signalling to describe which inband modes are supported
++ * by the PHY for this interface mode.
++ */
++unsigned int phy_inband_caps(struct phy_device *phydev,
++ phy_interface_t interface)
++{
++ if (phydev->drv && phydev->drv->inband_caps)
++ return phydev->drv->inband_caps(phydev, interface);
++
++ return 0;
++}
++EXPORT_SYMBOL_GPL(phy_inband_caps);
++
++/**
++ * phy_config_inband - configure the desired PHY in-band mode
++ * @phydev: the phy_device struct
++ * @modes: in-band modes to configure
++ *
++ * Description: disables, enables or enables-with-bypass in-band signalling
++ * between the PHY and host system.
++ *
++ * Returns: zero on success, or negative errno value.
++ */
++int phy_config_inband(struct phy_device *phydev, unsigned int modes)
++{
++ int err;
++
++ if (!!(modes & LINK_INBAND_DISABLE) +
++ !!(modes & LINK_INBAND_ENABLE) +
++ !!(modes & LINK_INBAND_BYPASS) != 1)
++ return -EINVAL;
++
++ mutex_lock(&phydev->lock);
++ if (!phydev->drv)
++ err = -EIO;
++ else if (!phydev->drv->config_inband)
++ err = -EOPNOTSUPP;
++ else
++ err = phydev->drv->config_inband(phydev, modes);
++ mutex_unlock(&phydev->lock);
++
++ return err;
++}
++
++/**
+ * _phy_start_aneg - start auto-negotiation for this PHY device
+ * @phydev: the phy_device struct
+ *
+--- a/include/linux/phy.h
++++ b/include/linux/phy.h
+@@ -800,6 +800,24 @@ struct phy_tdr_config {
+ #define PHY_PAIR_ALL -1
+
+ /**
++ * enum link_inband_signalling - in-band signalling modes that are supported
++ *
++ * @LINK_INBAND_DISABLE: in-band signalling can be disabled
++ * @LINK_INBAND_ENABLE: in-band signalling can be enabled without bypass
++ * @LINK_INBAND_BYPASS: in-band signalling can be enabled with bypass
++ *
++ * The possible and required bits can only be used if the valid bit is set.
++ * If possible is clear, that means inband signalling can not be used.
++ * Required is only valid when possible is set, and means that inband
++ * signalling must be used.
++ */
++enum link_inband_signalling {
++ LINK_INBAND_DISABLE = BIT(0),
++ LINK_INBAND_ENABLE = BIT(1),
++ LINK_INBAND_BYPASS = BIT(2),
++};
++
++/**
+ * struct phy_plca_cfg - Configuration of the PLCA (Physical Layer Collision
+ * Avoidance) Reconciliation Sublayer.
+ *
+@@ -939,6 +957,19 @@ struct phy_driver {
+ int (*get_features)(struct phy_device *phydev);
+
+ /**
++ * @inband_caps: query whether in-band is supported for the given PHY
++ * interface mode. Returns a bitmask of bits defined by enum
++ * link_inband_signalling.
++ */
++ unsigned int (*inband_caps)(struct phy_device *phydev,
++ phy_interface_t interface);
++
++ /**
++ * @config_inband: configure in-band mode for the PHY
++ */
++ int (*config_inband)(struct phy_device *phydev, unsigned int modes);
++
++ /**
+ * @get_rate_matching: Get the supported type of rate matching for a
+ * particular phy interface. This is used by phy consumers to determine
+ * whether to advertise lower-speed modes for that interface. It is
+@@ -1774,6 +1805,9 @@ void phy_stop(struct phy_device *phydev)
+ int phy_config_aneg(struct phy_device *phydev);
+ int phy_start_aneg(struct phy_device *phydev);
+ int phy_aneg_done(struct phy_device *phydev);
++unsigned int phy_inband_caps(struct phy_device *phydev,
++ phy_interface_t interface);
++int phy_config_inband(struct phy_device *phydev, unsigned int modes);
+ int phy_speed_down(struct phy_device *phydev, bool sync);
+ int phy_speed_up(struct phy_device *phydev);
+ bool phy_check_valid(int speed, int duplex, unsigned long *features);
+--- a/drivers/net/phy/bcm84881.c
++++ b/drivers/net/phy/bcm84881.c
+@@ -223,11 +223,21 @@ static int bcm84881_read_status(struct p
+ return genphy_c45_read_mdix(phydev);
+ }
+
++/* The Broadcom BCM84881 in the Methode DM7052 is unable to provide a SGMII
++ * or 802.3z control word, so inband will not work.
++ */
++static unsigned int bcm84881_inband_caps(struct phy_device *phydev,
++ phy_interface_t interface)
++{
++ return LINK_INBAND_DISABLE;
++}
++
+ static struct phy_driver bcm84881_drivers[] = {
+ {
+ .phy_id = 0xae025150,
+ .phy_id_mask = 0xfffffff0,
+ .name = "Broadcom BCM84881",
++ .inband_caps = bcm84881_inband_caps,
+ .config_init = bcm84881_config_init,
+ .probe = bcm84881_probe,
+ .get_features = bcm84881_get_features,
+--- a/drivers/net/phy/marvell.c
++++ b/drivers/net/phy/marvell.c
+@@ -673,6 +673,48 @@ static int marvell_config_aneg_fiber(str
+ return genphy_check_and_restart_aneg(phydev, changed);
+ }
+
++static unsigned int m88e1111_inband_caps(struct phy_device *phydev,
++ phy_interface_t interface)
++{
++ /* In 1000base-X and SGMII modes, the inband mode can be changed
++ * through the Fibre page BMCR ANENABLE bit.
++ */
++ if (interface == PHY_INTERFACE_MODE_1000BASEX ||
++ interface == PHY_INTERFACE_MODE_SGMII)
++ return LINK_INBAND_DISABLE | LINK_INBAND_ENABLE |
++ LINK_INBAND_BYPASS;
++
++ return 0;
++}
++
++static int m88e1111_config_inband(struct phy_device *phydev, unsigned int modes)
++{
++ u16 extsr, bmcr;
++ int err;
++
++ if (phydev->interface != PHY_INTERFACE_MODE_1000BASEX &&
++ phydev->interface != PHY_INTERFACE_MODE_SGMII)
++ return -EINVAL;
++
++ if (modes == LINK_INBAND_BYPASS)
++ extsr = MII_M1111_HWCFG_SERIAL_AN_BYPASS;
++ else
++ extsr = 0;
++
++ if (modes == LINK_INBAND_DISABLE)
++ bmcr = 0;
++ else
++ bmcr = BMCR_ANENABLE;
++
++ err = phy_modify(phydev, MII_M1111_PHY_EXT_SR,
++ MII_M1111_HWCFG_SERIAL_AN_BYPASS, extsr);
++ if (err < 0)
++ return extsr;
++
++ return phy_modify_paged(phydev, MII_MARVELL_FIBER_PAGE, MII_BMCR,
++ BMCR_ANENABLE, bmcr);
++}
++
+ static int m88e1111_config_aneg(struct phy_device *phydev)
+ {
+ int extsr = phy_read(phydev, MII_M1111_PHY_EXT_SR);
+@@ -3292,6 +3334,8 @@ static struct phy_driver marvell_drivers
+ .name = "Marvell 88E1112",
+ /* PHY_GBIT_FEATURES */
+ .probe = marvell_probe,
++ .inband_caps = m88e1111_inband_caps,
++ .config_inband = m88e1111_config_inband,
+ .config_init = m88e1112_config_init,
+ .config_aneg = marvell_config_aneg,
+ .config_intr = marvell_config_intr,
+@@ -3312,6 +3356,8 @@ static struct phy_driver marvell_drivers
+ .name = "Marvell 88E1111",
+ /* PHY_GBIT_FEATURES */
+ .probe = marvell_probe,
++ .inband_caps = m88e1111_inband_caps,
++ .config_inband = m88e1111_config_inband,
+ .config_init = m88e1111gbe_config_init,
+ .config_aneg = m88e1111_config_aneg,
+ .read_status = marvell_read_status,
+@@ -3333,6 +3379,8 @@ static struct phy_driver marvell_drivers
+ .name = "Marvell 88E1111 (Finisar)",
+ /* PHY_GBIT_FEATURES */
+ .probe = marvell_probe,
++ .inband_caps = m88e1111_inband_caps,
++ .config_inband = m88e1111_config_inband,
+ .config_init = m88e1111gbe_config_init,
+ .config_aneg = m88e1111_config_aneg,
+ .read_status = marvell_read_status,
+--- a/include/linux/phylink.h
++++ b/include/linux/phylink.h
+@@ -432,6 +432,7 @@ struct phylink_pcs {
+ /**
+ * struct phylink_pcs_ops - MAC PCS operations structure.
+ * @pcs_validate: validate the link configuration.
++ * @pcs_inband_caps: query inband support for interface mode.
+ * @pcs_enable: enable the PCS.
+ * @pcs_disable: disable the PCS.
+ * @pcs_pre_config: pre-mac_config method (for errata)
+@@ -445,6 +446,8 @@ struct phylink_pcs {
+ struct phylink_pcs_ops {
+ int (*pcs_validate)(struct phylink_pcs *pcs, unsigned long *supported,
+ const struct phylink_link_state *state);
++ unsigned int (*pcs_inband_caps)(struct phylink_pcs *pcs,
++ phy_interface_t interface);
+ int (*pcs_enable)(struct phylink_pcs *pcs);
+ void (*pcs_disable)(struct phylink_pcs *pcs);
+ void (*pcs_pre_config)(struct phylink_pcs *pcs,
+@@ -481,6 +484,20 @@ int pcs_validate(struct phylink_pcs *pcs
+ const struct phylink_link_state *state);
+
+ /**
++ * pcs_inband_caps - query PCS in-band capabilities for interface mode.
++ * @pcs: a pointer to a &struct phylink_pcs.
++ * @interface: interface mode to be queried
++ *
++ * Returns zero if it is unknown what in-band signalling is supported by the
++ * PHY (e.g. because the PHY driver doesn't implement the method.) Otherwise,
++ * returns a bit mask of the LINK_INBAND_* values from
++ * &enum link_inband_signalling to describe which inband modes are supported
++ * for this interface mode.
++ */
++unsigned int pcs_inband_caps(struct phylink_pcs *pcs,
++ phy_interface_t interface);
++
++/**
+ * pcs_enable() - enable the PCS.
+ * @pcs: a pointer to a &struct phylink_pcs.
+ */
+--- a/drivers/net/ethernet/marvell/mvneta.c
++++ b/drivers/net/ethernet/marvell/mvneta.c
+@@ -3959,20 +3959,27 @@ static struct mvneta_port *mvneta_pcs_to
+ return container_of(pcs, struct mvneta_port, phylink_pcs);
+ }
+
+-static int mvneta_pcs_validate(struct phylink_pcs *pcs,
+- unsigned long *supported,
+- const struct phylink_link_state *state)
++static unsigned int mvneta_pcs_inband_caps(struct phylink_pcs *pcs,
++ phy_interface_t interface)
+ {
+- /* We only support QSGMII, SGMII, 802.3z and RGMII modes.
+- * When in 802.3z mode, we must have AN enabled:
++ /* When operating in an 802.3z mode, we must have AN enabled:
+ * "Bit 2 Field InBandAnEn In-band Auto-Negotiation enable. ...
+ * When <PortType> = 1 (1000BASE-X) this field must be set to 1."
++ * Therefore, inband is "required".
+ */
+- if (phy_interface_mode_is_8023z(state->interface) &&
+- !phylink_test(state->advertising, Autoneg))
+- return -EINVAL;
++ if (phy_interface_mode_is_8023z(interface))
++ return LINK_INBAND_ENABLE;
+
+- return 0;
++ /* QSGMII, SGMII and RGMII can be configured to use inband
++ * signalling of the AN result. Indicate these as "possible".
++ */
++ if (interface == PHY_INTERFACE_MODE_SGMII ||
++ interface == PHY_INTERFACE_MODE_QSGMII ||
++ phy_interface_mode_is_rgmii(interface))
++ return LINK_INBAND_DISABLE | LINK_INBAND_ENABLE;
++
++ /* For any other modes, indicate that inband is not supported. */
++ return LINK_INBAND_DISABLE;
+ }
+
+ static void mvneta_pcs_get_state(struct phylink_pcs *pcs,
+@@ -4070,7 +4077,7 @@ static void mvneta_pcs_an_restart(struct
+ }
+
+ static const struct phylink_pcs_ops mvneta_phylink_pcs_ops = {
+- .pcs_validate = mvneta_pcs_validate,
++ .pcs_inband_caps = mvneta_pcs_inband_caps,
+ .pcs_get_state = mvneta_pcs_get_state,
+ .pcs_config = mvneta_pcs_config,
+ .pcs_an_restart = mvneta_pcs_an_restart,
+--- a/drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c
++++ b/drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c
+@@ -6214,19 +6214,26 @@ static const struct phylink_pcs_ops mvpp
+ .pcs_config = mvpp2_xlg_pcs_config,
+ };
+
+-static int mvpp2_gmac_pcs_validate(struct phylink_pcs *pcs,
+- unsigned long *supported,
+- const struct phylink_link_state *state)
++static unsigned int mvpp2_gmac_pcs_inband_caps(struct phylink_pcs *pcs,
++ phy_interface_t interface)
+ {
+- /* When in 802.3z mode, we must have AN enabled:
++ /* When operating in an 802.3z mode, we must have AN enabled:
+ * Bit 2 Field InBandAnEn In-band Auto-Negotiation enable. ...
+ * When <PortType> = 1 (1000BASE-X) this field must be set to 1.
++ * Therefore, inband is "required".
+ */
+- if (phy_interface_mode_is_8023z(state->interface) &&
+- !phylink_test(state->advertising, Autoneg))
+- return -EINVAL;
++ if (phy_interface_mode_is_8023z(interface))
++ return LINK_INBAND_ENABLE;
+
+- return 0;
++ /* SGMII and RGMII can be configured to use inband signalling of the
++ * AN result. Indicate these as "possible".
++ */
++ if (interface == PHY_INTERFACE_MODE_SGMII ||
++ phy_interface_mode_is_rgmii(interface))
++ return LINK_INBAND_DISABLE | LINK_INBAND_ENABLE;
++
++ /* For any other modes, indicate that inband is not supported. */
++ return LINK_INBAND_DISABLE;
+ }
+
+ static void mvpp2_gmac_pcs_get_state(struct phylink_pcs *pcs,
+@@ -6333,7 +6340,7 @@ static void mvpp2_gmac_pcs_an_restart(st
+ }
+
+ static const struct phylink_pcs_ops mvpp2_phylink_gmac_pcs_ops = {
+- .pcs_validate = mvpp2_gmac_pcs_validate,
++ .pcs_inband_caps = mvpp2_gmac_pcs_inband_caps,
+ .pcs_get_state = mvpp2_gmac_pcs_get_state,
+ .pcs_config = mvpp2_gmac_pcs_config,
+ .pcs_an_restart = mvpp2_gmac_pcs_an_restart,
+--- a/drivers/net/pcs/pcs-lynx.c
++++ b/drivers/net/pcs/pcs-lynx.c
+@@ -35,6 +35,27 @@ enum sgmii_speed {
+ #define phylink_pcs_to_lynx(pl_pcs) container_of((pl_pcs), struct lynx_pcs, pcs)
+ #define lynx_to_phylink_pcs(lynx) (&(lynx)->pcs)
+
++static unsigned int lynx_pcs_inband_caps(struct phylink_pcs *pcs,
++ phy_interface_t interface)
++{
++ switch (interface) {
++ case PHY_INTERFACE_MODE_1000BASEX:
++ case PHY_INTERFACE_MODE_SGMII:
++ case PHY_INTERFACE_MODE_QSGMII:
++ return LINK_INBAND_DISABLE | LINK_INBAND_ENABLE;
++
++ case PHY_INTERFACE_MODE_10GBASER:
++ case PHY_INTERFACE_MODE_2500BASEX:
++ return LINK_INBAND_DISABLE;
++
++ case PHY_INTERFACE_MODE_USXGMII:
++ return LINK_INBAND_ENABLE;
++
++ default:
++ return 0;
++ }
++}
++
+ static void lynx_pcs_get_state_usxgmii(struct mdio_device *pcs,
+ struct phylink_link_state *state)
+ {
+@@ -307,6 +328,7 @@ static void lynx_pcs_link_up(struct phyl
+ }
+
+ static const struct phylink_pcs_ops lynx_pcs_phylink_ops = {
++ .pcs_inband_caps = lynx_pcs_inband_caps,
+ .pcs_get_state = lynx_pcs_get_state,
+ .pcs_config = lynx_pcs_config,
+ .pcs_an_restart = lynx_pcs_an_restart,
+--- a/drivers/net/pcs/pcs-mtk-lynxi.c
++++ b/drivers/net/pcs/pcs-mtk-lynxi.c
+@@ -110,6 +110,21 @@ static struct mtk_pcs_lynxi *pcs_to_mtk_
+ return container_of(pcs, struct mtk_pcs_lynxi, pcs);
+ }
+
++static unsigned int mtk_pcs_lynxi_inband_caps(struct phylink_pcs *pcs,
++ phy_interface_t interface)
++{
++ switch (interface) {
++ case PHY_INTERFACE_MODE_1000BASEX:
++ case PHY_INTERFACE_MODE_2500BASEX:
++ case PHY_INTERFACE_MODE_SGMII:
++ case PHY_INTERFACE_MODE_QSGMII:
++ return LINK_INBAND_DISABLE | LINK_INBAND_ENABLE;
++
++ default:
++ return 0;
++ }
++}
++
+ static void mtk_pcs_lynxi_get_state(struct phylink_pcs *pcs,
+ struct phylink_link_state *state)
+ {
+@@ -302,6 +317,7 @@ static void mtk_pcs_lynxi_disable(struct
+ }
+
+ static const struct phylink_pcs_ops mtk_pcs_lynxi_ops = {
++ .pcs_inband_caps = mtk_pcs_lynxi_inband_caps,
+ .pcs_get_state = mtk_pcs_lynxi_get_state,
+ .pcs_config = mtk_pcs_lynxi_config,
+ .pcs_an_restart = mtk_pcs_lynxi_restart_an,
+--- a/drivers/net/pcs/pcs-xpcs.c
++++ b/drivers/net/pcs/pcs-xpcs.c
+@@ -628,6 +628,33 @@ static int xpcs_validate(struct phylink_
+ return 0;
+ }
+
++static unsigned int xpcs_inband_caps(struct phylink_pcs *pcs,
++ phy_interface_t interface)
++{
++ struct dw_xpcs *xpcs = phylink_pcs_to_xpcs(pcs);
++ const struct dw_xpcs_compat *compat;
++
++ compat = xpcs_find_compat(xpcs, interface);
++ if (!compat)
++ return 0;
++
++ switch (compat->an_mode) {
++ case DW_AN_C73:
++ return LINK_INBAND_ENABLE;
++
++ case DW_AN_C37_SGMII:
++ case DW_AN_C37_1000BASEX:
++ return LINK_INBAND_DISABLE | LINK_INBAND_ENABLE;
++
++ case DW_10GBASER:
++ case DW_2500BASEX:
++ return LINK_INBAND_DISABLE;
++
++ default:
++ return 0;
++ }
++}
++
+ void xpcs_get_interfaces(struct dw_xpcs *xpcs, unsigned long *interfaces)
+ {
+ int i, j;
+@@ -1331,6 +1358,7 @@ static const struct xpcs_id xpcs_id_list
+
+ static const struct phylink_pcs_ops xpcs_phylink_ops = {
+ .pcs_validate = xpcs_validate,
++ .pcs_inband_caps = xpcs_inband_caps,
+ .pcs_config = xpcs_config,
+ .pcs_get_state = xpcs_get_state,
+ .pcs_an_restart = xpcs_an_restart,
--- /dev/null
+From eb58bf4afd708eb3c64c7b9b2c5fbfacdcdee3e5 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>
+Date: Wed, 14 Feb 2024 15:04:54 +0100
+Subject: [PATCH] pwm: mediatek: add support for MT7988
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+MT7988 uses new registers layout just like MT7981 but it supports 8 PWM
+interfaces.
+
+Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
+Reviewed-by: Daniel Golle <daniel@makrotopia.org>
+Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
+Link: https://lore.kernel.org/r/20240214140454.6438-2-zajec5@gmail.com
+Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
+---
+ drivers/pwm/pwm-mediatek.c | 8 ++++++++
+ 1 file changed, 8 insertions(+)
+
+--- a/drivers/pwm/pwm-mediatek.c
++++ b/drivers/pwm/pwm-mediatek.c
+@@ -345,6 +345,13 @@ static const struct pwm_mediatek_of_data
+ .reg_offset = mtk_pwm_reg_offset_v1,
+ };
+
++static const struct pwm_mediatek_of_data mt7988_pwm_data = {
++ .num_pwms = 8,
++ .pwm45_fixup = false,
++ .has_ck_26m_sel = false,
++ .reg_offset = mtk_pwm_reg_offset_v2,
++};
++
+ static const struct pwm_mediatek_of_data mt8183_pwm_data = {
+ .num_pwms = 4,
+ .pwm45_fixup = false,
+@@ -375,6 +382,7 @@ static const struct of_device_id pwm_med
+ { .compatible = "mediatek,mt7629-pwm", .data = &mt7629_pwm_data },
+ { .compatible = "mediatek,mt7981-pwm", .data = &mt7981_pwm_data },
+ { .compatible = "mediatek,mt7986-pwm", .data = &mt7986_pwm_data },
++ { .compatible = "mediatek,mt7988-pwm", .data = &mt7988_pwm_data },
+ { .compatible = "mediatek,mt8183-pwm", .data = &mt8183_pwm_data },
+ { .compatible = "mediatek,mt8365-pwm", .data = &mt8365_pwm_data },
+ { .compatible = "mediatek,mt8516-pwm", .data = &mt8516_pwm_data },
--- /dev/null
+From 6cf96078969ec00b873db99bae4e47001290685e Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= <u.kleine-koenig@pengutronix.de>
+Date: Wed, 27 Sep 2023 21:37:23 +0200
+Subject: [PATCH 35/42] thermal: lvts: Convert to platform remove callback
+ returning void
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+The .remove() callback for a platform driver returns an int which makes
+many driver authors wrongly assume it's possible to do error handling by
+returning an error code. However the value returned is ignored (apart
+from emitting a warning) and this typically results in resource leaks.
+
+To improve here there is a quest to make the remove callback return
+void. In the first step of this quest all drivers are converted to
+.remove_new(), which already returns void. Eventually after all drivers
+are converted, .remove_new() will be renamed to .remove().
+
+Trivially convert this driver from always returning zero in the remove
+callback to the void returning variant.
+
+Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
+Acked-by: Daniel Lezcano <daniel.lezcano@linaro.org>
+Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
+---
+ drivers/thermal/mediatek/lvts_thermal.c | 6 ++----
+ 1 file changed, 2 insertions(+), 4 deletions(-)
+
+--- a/drivers/thermal/mediatek/lvts_thermal.c
++++ b/drivers/thermal/mediatek/lvts_thermal.c
+@@ -1249,7 +1249,7 @@ static int lvts_probe(struct platform_de
+ return 0;
+ }
+
+-static int lvts_remove(struct platform_device *pdev)
++static void lvts_remove(struct platform_device *pdev)
+ {
+ struct lvts_domain *lvts_td;
+ int i;
+@@ -1260,8 +1260,6 @@ static int lvts_remove(struct platform_d
+ lvts_ctrl_set_enable(&lvts_td->lvts_ctrl[i], false);
+
+ lvts_debugfs_exit(lvts_td);
+-
+- return 0;
+ }
+
+ static const struct lvts_ctrl_data mt8195_lvts_mcu_data_ctrl[] = {
+@@ -1362,7 +1360,7 @@ MODULE_DEVICE_TABLE(of, lvts_of_match);
+
+ static struct platform_driver lvts_driver = {
+ .probe = lvts_probe,
+- .remove = lvts_remove,
++ .remove_new = lvts_remove,
+ .driver = {
+ .name = "mtk-lvts-thermal",
+ .of_match_table = lvts_of_match,
--- /dev/null
+From 26cc18a3d6d9eac21c4f4b4bb96147b2c6617c86 Mon Sep 17 00:00:00 2001
+From: Frank Wunderlich <frank-w@public-files.de>
+Date: Fri, 22 Sep 2023 07:50:19 +0200
+Subject: [PATCH 36/42] thermal/drivers/mediatek/lvts_thermal: Make coeff
+ configurable
+
+The upcoming mt7988 has different temperature coefficients so we
+cannot use constants in the functions lvts_golden_temp_init,
+lvts_golden_temp_init and lvts_raw_to_temp anymore.
+
+Add a field in the lvts_ctrl pointing to the lvts_data which now
+contains the soc-specific temperature coefficents.
+
+To make the code better readable, rename static int coeff_b to
+golden_temp_offset, COEFF_A to temp_factor and COEFF_B to temp_offset.
+
+Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
+Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
+Tested-by: Daniel Golle <daniel@makrotopia.org>
+Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
+Link: https://lore.kernel.org/r/20230922055020.6436-4-linux@fw-web.de
+---
+ drivers/thermal/mediatek/lvts_thermal.c | 51 ++++++++++++++++---------
+ 1 file changed, 34 insertions(+), 17 deletions(-)
+
+--- a/drivers/thermal/mediatek/lvts_thermal.c
++++ b/drivers/thermal/mediatek/lvts_thermal.c
+@@ -80,8 +80,8 @@
+ #define LVTS_SENSOR_MAX 4
+ #define LVTS_GOLDEN_TEMP_MAX 62
+ #define LVTS_GOLDEN_TEMP_DEFAULT 50
+-#define LVTS_COEFF_A -250460
+-#define LVTS_COEFF_B 250460
++#define LVTS_COEFF_A_MT8195 -250460
++#define LVTS_COEFF_B_MT8195 250460
+
+ #define LVTS_MSR_IMMEDIATE_MODE 0
+ #define LVTS_MSR_FILTERED_MODE 1
+@@ -94,7 +94,7 @@
+ #define LVTS_MINIMUM_THRESHOLD 20000
+
+ static int golden_temp = LVTS_GOLDEN_TEMP_DEFAULT;
+-static int coeff_b = LVTS_COEFF_B;
++static int golden_temp_offset;
+
+ struct lvts_sensor_data {
+ int dt_id;
+@@ -112,6 +112,8 @@ struct lvts_ctrl_data {
+ struct lvts_data {
+ const struct lvts_ctrl_data *lvts_ctrl;
+ int num_lvts_ctrl;
++ int temp_factor;
++ int temp_offset;
+ };
+
+ struct lvts_sensor {
+@@ -126,6 +128,7 @@ struct lvts_sensor {
+
+ struct lvts_ctrl {
+ struct lvts_sensor sensors[LVTS_SENSOR_MAX];
++ const struct lvts_data *lvts_data;
+ u32 calibration[LVTS_SENSOR_MAX];
+ u32 hw_tshut_raw_temp;
+ int num_lvts_sensor;
+@@ -247,21 +250,21 @@ static void lvts_debugfs_exit(struct lvt
+
+ #endif
+
+-static int lvts_raw_to_temp(u32 raw_temp)
++static int lvts_raw_to_temp(u32 raw_temp, int temp_factor)
+ {
+ int temperature;
+
+- temperature = ((s64)(raw_temp & 0xFFFF) * LVTS_COEFF_A) >> 14;
+- temperature += coeff_b;
++ temperature = ((s64)(raw_temp & 0xFFFF) * temp_factor) >> 14;
++ temperature += golden_temp_offset;
+
+ return temperature;
+ }
+
+-static u32 lvts_temp_to_raw(int temperature)
++static u32 lvts_temp_to_raw(int temperature, int temp_factor)
+ {
+- u32 raw_temp = ((s64)(coeff_b - temperature)) << 14;
++ u32 raw_temp = ((s64)(golden_temp_offset - temperature)) << 14;
+
+- raw_temp = div_s64(raw_temp, -LVTS_COEFF_A);
++ raw_temp = div_s64(raw_temp, -temp_factor);
+
+ return raw_temp;
+ }
+@@ -269,6 +272,9 @@ static u32 lvts_temp_to_raw(int temperat
+ static int lvts_get_temp(struct thermal_zone_device *tz, int *temp)
+ {
+ struct lvts_sensor *lvts_sensor = thermal_zone_device_priv(tz);
++ struct lvts_ctrl *lvts_ctrl = container_of(lvts_sensor, struct lvts_ctrl,
++ sensors[lvts_sensor->id]);
++ const struct lvts_data *lvts_data = lvts_ctrl->lvts_data;
+ void __iomem *msr = lvts_sensor->msr;
+ u32 value;
+ int rc;
+@@ -301,7 +307,7 @@ static int lvts_get_temp(struct thermal_
+ if (rc)
+ return -EAGAIN;
+
+- *temp = lvts_raw_to_temp(value & 0xFFFF);
++ *temp = lvts_raw_to_temp(value & 0xFFFF, lvts_data->temp_factor);
+
+ return 0;
+ }
+@@ -348,10 +354,13 @@ static bool lvts_should_update_thresh(st
+ static int lvts_set_trips(struct thermal_zone_device *tz, int low, int high)
+ {
+ struct lvts_sensor *lvts_sensor = thermal_zone_device_priv(tz);
+- struct lvts_ctrl *lvts_ctrl = container_of(lvts_sensor, struct lvts_ctrl, sensors[lvts_sensor->id]);
++ struct lvts_ctrl *lvts_ctrl = container_of(lvts_sensor, struct lvts_ctrl,
++ sensors[lvts_sensor->id]);
++ const struct lvts_data *lvts_data = lvts_ctrl->lvts_data;
+ void __iomem *base = lvts_sensor->base;
+- u32 raw_low = lvts_temp_to_raw(low != -INT_MAX ? low : LVTS_MINIMUM_THRESHOLD);
+- u32 raw_high = lvts_temp_to_raw(high);
++ u32 raw_low = lvts_temp_to_raw(low != -INT_MAX ? low : LVTS_MINIMUM_THRESHOLD,
++ lvts_data->temp_factor);
++ u32 raw_high = lvts_temp_to_raw(high, lvts_data->temp_factor);
+ bool should_update_thresh;
+
+ lvts_sensor->low_thresh = low;
+@@ -694,7 +703,7 @@ static int lvts_calibration_read(struct
+ return 0;
+ }
+
+-static int lvts_golden_temp_init(struct device *dev, u32 *value)
++static int lvts_golden_temp_init(struct device *dev, u32 *value, int temp_offset)
+ {
+ u32 gt;
+
+@@ -707,7 +716,7 @@ static int lvts_golden_temp_init(struct
+ if (gt < LVTS_GOLDEN_TEMP_MAX)
+ golden_temp = gt;
+
+- coeff_b = golden_temp * 500 + LVTS_COEFF_B;
++ golden_temp_offset = golden_temp * 500 + temp_offset;
+
+ return 0;
+ }
+@@ -730,7 +739,7 @@ static int lvts_ctrl_init(struct device
+ * The golden temp information is contained in the first chunk
+ * of efuse data.
+ */
+- ret = lvts_golden_temp_init(dev, (u32 *)lvts_td->calib);
++ ret = lvts_golden_temp_init(dev, (u32 *)lvts_td->calib, lvts_data->temp_offset);
+ if (ret)
+ return ret;
+
+@@ -741,6 +750,7 @@ static int lvts_ctrl_init(struct device
+ for (i = 0; i < lvts_data->num_lvts_ctrl; i++) {
+
+ lvts_ctrl[i].base = lvts_td->base + lvts_data->lvts_ctrl[i].offset;
++ lvts_ctrl[i].lvts_data = lvts_data;
+
+ ret = lvts_sensor_init(dev, &lvts_ctrl[i],
+ &lvts_data->lvts_ctrl[i]);
+@@ -764,7 +774,8 @@ static int lvts_ctrl_init(struct device
+ * after initializing the calibration.
+ */
+ lvts_ctrl[i].hw_tshut_raw_temp =
+- lvts_temp_to_raw(lvts_data->lvts_ctrl[i].hw_tshut_temp);
++ lvts_temp_to_raw(lvts_data->lvts_ctrl[i].hw_tshut_temp,
++ lvts_data->temp_factor);
+
+ lvts_ctrl[i].low_thresh = INT_MIN;
+ lvts_ctrl[i].high_thresh = INT_MIN;
+@@ -1231,6 +1242,8 @@ static int lvts_probe(struct platform_de
+ if (irq < 0)
+ return irq;
+
++ golden_temp_offset = lvts_data->temp_offset;
++
+ ret = lvts_domain_init(dev, lvts_td, lvts_data);
+ if (ret)
+ return dev_err_probe(dev, ret, "Failed to initialize the lvts domain\n");
+@@ -1344,11 +1357,15 @@ static const struct lvts_ctrl_data mt819
+ static const struct lvts_data mt8195_lvts_mcu_data = {
+ .lvts_ctrl = mt8195_lvts_mcu_data_ctrl,
+ .num_lvts_ctrl = ARRAY_SIZE(mt8195_lvts_mcu_data_ctrl),
++ .temp_factor = LVTS_COEFF_A_MT8195,
++ .temp_offset = LVTS_COEFF_B_MT8195,
+ };
+
+ static const struct lvts_data mt8195_lvts_ap_data = {
+ .lvts_ctrl = mt8195_lvts_ap_data_ctrl,
+ .num_lvts_ctrl = ARRAY_SIZE(mt8195_lvts_ap_data_ctrl),
++ .temp_factor = LVTS_COEFF_A_MT8195,
++ .temp_offset = LVTS_COEFF_B_MT8195,
+ };
+
+ static const struct of_device_id lvts_of_match[] = {
--- /dev/null
+From be2cc09bd5b46f13629d4fcdeac7ad1b18bb1a0b Mon Sep 17 00:00:00 2001
+From: Frank Wunderlich <frank-w@public-files.de>
+Date: Fri, 22 Sep 2023 07:50:18 +0200
+Subject: [PATCH] dt-bindings: thermal: mediatek: Add LVTS thermal sensors for
+ mt7988
+
+Add sensor constants for MT7988.
+
+Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
+Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
+Acked-by: Conor Dooley <conor.dooley@microchip.com>
+Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
+Link: https://lore.kernel.org/r/20230922055020.6436-3-linux@fw-web.de
+---
+ include/dt-bindings/thermal/mediatek,lvts-thermal.h | 9 +++++++++
+ 1 file changed, 9 insertions(+)
+
+--- a/include/dt-bindings/thermal/mediatek,lvts-thermal.h
++++ b/include/dt-bindings/thermal/mediatek,lvts-thermal.h
+@@ -7,6 +7,15 @@
+ #ifndef __MEDIATEK_LVTS_DT_H
+ #define __MEDIATEK_LVTS_DT_H
+
++#define MT7988_CPU_0 0
++#define MT7988_CPU_1 1
++#define MT7988_ETH2P5G_0 2
++#define MT7988_ETH2P5G_1 3
++#define MT7988_TOPS_0 4
++#define MT7988_TOPS_1 5
++#define MT7988_ETHWARP_0 6
++#define MT7988_ETHWARP_1 7
++
+ #define MT8195_MCU_BIG_CPU0 0
+ #define MT8195_MCU_BIG_CPU1 1
+ #define MT8195_MCU_BIG_CPU2 2
--- /dev/null
+From 9924e9b91b43aaa1610a1d59c4caa43785948cf6 Mon Sep 17 00:00:00 2001
+From: Frank Wunderlich <frank-w@public-files.de>
+Date: Fri, 22 Sep 2023 07:50:20 +0200
+Subject: [PATCH 37/42] thermal/drivers/mediatek/lvts_thermal: Add mt7988
+ support
+
+Add Support for Mediatek Filogic 880/MT7988 LVTS.
+
+Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
+Tested-by: Daniel Golle <daniel@makrotopia.org>
+Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
+Link: https://lore.kernel.org/r/20230922055020.6436-5-linux@fw-web.de
+---
+ drivers/thermal/mediatek/lvts_thermal.c | 38 +++++++++++++++++++++++++
+ 1 file changed, 38 insertions(+)
+
+--- a/drivers/thermal/mediatek/lvts_thermal.c
++++ b/drivers/thermal/mediatek/lvts_thermal.c
+@@ -82,6 +82,8 @@
+ #define LVTS_GOLDEN_TEMP_DEFAULT 50
+ #define LVTS_COEFF_A_MT8195 -250460
+ #define LVTS_COEFF_B_MT8195 250460
++#define LVTS_COEFF_A_MT7988 -204650
++#define LVTS_COEFF_B_MT7988 204650
+
+ #define LVTS_MSR_IMMEDIATE_MODE 0
+ #define LVTS_MSR_FILTERED_MODE 1
+@@ -89,6 +91,7 @@
+ #define LVTS_MSR_READ_TIMEOUT_US 400
+ #define LVTS_MSR_READ_WAIT_US (LVTS_MSR_READ_TIMEOUT_US / 2)
+
++#define LVTS_HW_SHUTDOWN_MT7988 105000
+ #define LVTS_HW_SHUTDOWN_MT8195 105000
+
+ #define LVTS_MINIMUM_THRESHOLD 20000
+@@ -1275,6 +1278,33 @@ static void lvts_remove(struct platform_
+ lvts_debugfs_exit(lvts_td);
+ }
+
++static const struct lvts_ctrl_data mt7988_lvts_ap_data_ctrl[] = {
++ {
++ .cal_offset = { 0x00, 0x04, 0x08, 0x0c },
++ .lvts_sensor = {
++ { .dt_id = MT7988_CPU_0 },
++ { .dt_id = MT7988_CPU_1 },
++ { .dt_id = MT7988_ETH2P5G_0 },
++ { .dt_id = MT7988_ETH2P5G_1 }
++ },
++ .num_lvts_sensor = 4,
++ .offset = 0x0,
++ .hw_tshut_temp = LVTS_HW_SHUTDOWN_MT7988,
++ },
++ {
++ .cal_offset = { 0x14, 0x18, 0x1c, 0x20 },
++ .lvts_sensor = {
++ { .dt_id = MT7988_TOPS_0},
++ { .dt_id = MT7988_TOPS_1},
++ { .dt_id = MT7988_ETHWARP_0},
++ { .dt_id = MT7988_ETHWARP_1}
++ },
++ .num_lvts_sensor = 4,
++ .offset = 0x100,
++ .hw_tshut_temp = LVTS_HW_SHUTDOWN_MT7988,
++ }
++};
++
+ static const struct lvts_ctrl_data mt8195_lvts_mcu_data_ctrl[] = {
+ {
+ .cal_offset = { 0x04, 0x07 },
+@@ -1354,6 +1384,13 @@ static const struct lvts_ctrl_data mt819
+ }
+ };
+
++static const struct lvts_data mt7988_lvts_ap_data = {
++ .lvts_ctrl = mt7988_lvts_ap_data_ctrl,
++ .num_lvts_ctrl = ARRAY_SIZE(mt7988_lvts_ap_data_ctrl),
++ .temp_factor = LVTS_COEFF_A_MT7988,
++ .temp_offset = LVTS_COEFF_B_MT7988,
++};
++
+ static const struct lvts_data mt8195_lvts_mcu_data = {
+ .lvts_ctrl = mt8195_lvts_mcu_data_ctrl,
+ .num_lvts_ctrl = ARRAY_SIZE(mt8195_lvts_mcu_data_ctrl),
+@@ -1369,6 +1406,7 @@ static const struct lvts_data mt8195_lvt
+ };
+
+ static const struct of_device_id lvts_of_match[] = {
++ { .compatible = "mediatek,mt7988-lvts-ap", .data = &mt7988_lvts_ap_data },
+ { .compatible = "mediatek,mt8195-lvts-mcu", .data = &mt8195_lvts_mcu_data },
+ { .compatible = "mediatek,mt8195-lvts-ap", .data = &mt8195_lvts_ap_data },
+ {},
--- /dev/null
+From fb1bbb5b63e4e3c788a978724749ced57d208054 Mon Sep 17 00:00:00 2001
+From: Minjie Du <duminjie@vivo.com>
+Date: Thu, 21 Sep 2023 17:10:50 +0800
+Subject: [PATCH 38/42] thermal/drivers/mediatek/lvts_thermal: Fix error check
+ in lvts_debugfs_init()
+
+debugfs_create_dir() function returns an error value embedded in
+the pointer (PTR_ERR). Evaluate the return value using IS_ERR
+rather than checking for NULL.
+
+Signed-off-by: Minjie Du <duminjie@vivo.com>
+Reviewed-by: Alexandre Mergnat <amergnat@baylibre.com>
+Reviewed-by: Chen-Yu Tsai <wenst@chromium.org>
+Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
+Link: https://lore.kernel.org/r/20230921091057.3812-1-duminjie@vivo.com
+---
+ drivers/thermal/mediatek/lvts_thermal.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+--- a/drivers/thermal/mediatek/lvts_thermal.c
++++ b/drivers/thermal/mediatek/lvts_thermal.c
+@@ -219,7 +219,7 @@ static int lvts_debugfs_init(struct devi
+
+ sprintf(name, "controller%d", i);
+ dentry = debugfs_create_dir(name, lvts_td->dom_dentry);
+- if (!dentry)
++ if (IS_ERR(dentry))
+ continue;
+
+ regset = devm_kzalloc(dev, sizeof(*regset), GFP_KERNEL);
--- /dev/null
+From a1d874ef3376295ee8ed89b3b5315f4c840ff00b Mon Sep 17 00:00:00 2001
+From: Balsam CHIHI <bchihi@baylibre.com>
+Date: Tue, 17 Oct 2023 21:05:42 +0200
+Subject: [PATCH 40/42] thermal/drivers/mediatek/lvts_thermal: Add suspend and
+ resume
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Add suspend and resume support to LVTS driver.
+
+Signed-off-by: Balsam CHIHI <bchihi@baylibre.com>
+[bero@baylibre.com: suspend/resume in noirq phase]
+Co-developed-by: Bernhard Rosenkränzer <bero@baylibre.com>
+Signed-off-by: Bernhard Rosenkränzer <bero@baylibre.com>
+Reviewed-by: Matthias Brugger <matthias.bgg@gmail.com>
+Reviewed-by: Alexandre Mergnat <amergnat@baylibre.com>
+Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
+Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
+Link: https://lore.kernel.org/r/20231017190545.157282-3-bero@baylibre.com
+---
+ drivers/thermal/mediatek/lvts_thermal.c | 37 +++++++++++++++++++++++++
+ 1 file changed, 37 insertions(+)
+
+--- a/drivers/thermal/mediatek/lvts_thermal.c
++++ b/drivers/thermal/mediatek/lvts_thermal.c
+@@ -1305,6 +1305,38 @@ static const struct lvts_ctrl_data mt798
+ }
+ };
+
++static int lvts_suspend(struct device *dev)
++{
++ struct lvts_domain *lvts_td;
++ int i;
++
++ lvts_td = dev_get_drvdata(dev);
++
++ for (i = 0; i < lvts_td->num_lvts_ctrl; i++)
++ lvts_ctrl_set_enable(&lvts_td->lvts_ctrl[i], false);
++
++ clk_disable_unprepare(lvts_td->clk);
++
++ return 0;
++}
++
++static int lvts_resume(struct device *dev)
++{
++ struct lvts_domain *lvts_td;
++ int i, ret;
++
++ lvts_td = dev_get_drvdata(dev);
++
++ ret = clk_prepare_enable(lvts_td->clk);
++ if (ret)
++ return ret;
++
++ for (i = 0; i < lvts_td->num_lvts_ctrl; i++)
++ lvts_ctrl_set_enable(&lvts_td->lvts_ctrl[i], true);
++
++ return 0;
++}
++
+ static const struct lvts_ctrl_data mt8195_lvts_mcu_data_ctrl[] = {
+ {
+ .cal_offset = { 0x04, 0x07 },
+@@ -1413,12 +1445,17 @@ static const struct of_device_id lvts_of
+ };
+ MODULE_DEVICE_TABLE(of, lvts_of_match);
+
++static const struct dev_pm_ops lvts_pm_ops = {
++ NOIRQ_SYSTEM_SLEEP_PM_OPS(lvts_suspend, lvts_resume)
++};
++
+ static struct platform_driver lvts_driver = {
+ .probe = lvts_probe,
+ .remove_new = lvts_remove,
+ .driver = {
+ .name = "mtk-lvts-thermal",
+ .of_match_table = lvts_of_match,
++ .pm = &lvts_pm_ops,
+ },
+ };
+ module_platform_driver(lvts_driver);
--- /dev/null
+From 0bb4937b58ab712f158588376dbac97f8e9df68e Mon Sep 17 00:00:00 2001
+From: Balsam CHIHI <bchihi@baylibre.com>
+Date: Tue, 17 Oct 2023 21:05:41 +0200
+Subject: [PATCH] dt-bindings: thermal: mediatek: Add LVTS thermal controller
+ definition for mt8192
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Add LVTS thermal controller definition for MT8192.
+
+Signed-off-by: Balsam CHIHI <bchihi@baylibre.com>
+Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
+Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
+Signed-off-by: Bernhard Rosenkränzer <bero@baylibre.com>
+Reviewed-by: Matthias Brugger <matthias.bgg@gmail.com>
+Reviewed-by: Alexandre Mergnat <amergnat@baylibre.com>
+Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
+Link: https://lore.kernel.org/r/20231017190545.157282-2-bero@baylibre.com
+---
+ .../thermal/mediatek,lvts-thermal.h | 19 +++++++++++++++++++
+ 1 file changed, 19 insertions(+)
+
+--- a/include/dt-bindings/thermal/mediatek,lvts-thermal.h
++++ b/include/dt-bindings/thermal/mediatek,lvts-thermal.h
+@@ -35,4 +35,23 @@
+ #define MT8195_AP_CAM0 15
+ #define MT8195_AP_CAM1 16
+
++#define MT8192_MCU_BIG_CPU0 0
++#define MT8192_MCU_BIG_CPU1 1
++#define MT8192_MCU_BIG_CPU2 2
++#define MT8192_MCU_BIG_CPU3 3
++#define MT8192_MCU_LITTLE_CPU0 4
++#define MT8192_MCU_LITTLE_CPU1 5
++#define MT8192_MCU_LITTLE_CPU2 6
++#define MT8192_MCU_LITTLE_CPU3 7
++
++#define MT8192_AP_VPU0 8
++#define MT8192_AP_VPU1 9
++#define MT8192_AP_GPU0 10
++#define MT8192_AP_GPU1 11
++#define MT8192_AP_INFRA 12
++#define MT8192_AP_CAM 13
++#define MT8192_AP_MD0 14
++#define MT8192_AP_MD1 15
++#define MT8192_AP_MD2 16
++
+ #endif /* __MEDIATEK_LVTS_DT_H */
--- /dev/null
+From 7d8b3864b38d881cf105328ff8569f47446811ad Mon Sep 17 00:00:00 2001
+From: Balsam CHIHI <bchihi@baylibre.com>
+Date: Tue, 17 Oct 2023 21:05:43 +0200
+Subject: [PATCH 41/42] thermal/drivers/mediatek/lvts_thermal: Add mt8192
+ support
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Add LVTS Driver support for MT8192.
+
+Co-developed-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>
+Signed-off-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>
+Signed-off-by: Balsam CHIHI <bchihi@baylibre.com>
+Reviewed-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>
+[bero@baylibre.com: cosmetic changes, rebase]
+Signed-off-by: Bernhard Rosenkränzer <bero@baylibre.com>
+Reviewed-by: Matthias Brugger <matthias.bgg@gmail.com>
+Reviewed-by: Alexandre Mergnat <amergnat@baylibre.com>
+Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
+Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
+Link: https://lore.kernel.org/r/20231017190545.157282-4-bero@baylibre.com
+---
+ drivers/thermal/mediatek/lvts_thermal.c | 95 +++++++++++++++++++++++++
+ 1 file changed, 95 insertions(+)
+
+--- a/drivers/thermal/mediatek/lvts_thermal.c
++++ b/drivers/thermal/mediatek/lvts_thermal.c
+@@ -92,6 +92,7 @@
+ #define LVTS_MSR_READ_WAIT_US (LVTS_MSR_READ_TIMEOUT_US / 2)
+
+ #define LVTS_HW_SHUTDOWN_MT7988 105000
++#define LVTS_HW_SHUTDOWN_MT8192 105000
+ #define LVTS_HW_SHUTDOWN_MT8195 105000
+
+ #define LVTS_MINIMUM_THRESHOLD 20000
+@@ -1337,6 +1338,88 @@ static int lvts_resume(struct device *de
+ return 0;
+ }
+
++static const struct lvts_ctrl_data mt8192_lvts_mcu_data_ctrl[] = {
++ {
++ .cal_offset = { 0x04, 0x08 },
++ .lvts_sensor = {
++ { .dt_id = MT8192_MCU_BIG_CPU0 },
++ { .dt_id = MT8192_MCU_BIG_CPU1 }
++ },
++ .num_lvts_sensor = 2,
++ .offset = 0x0,
++ .hw_tshut_temp = LVTS_HW_SHUTDOWN_MT8192,
++ .mode = LVTS_MSR_FILTERED_MODE,
++ },
++ {
++ .cal_offset = { 0x0c, 0x10 },
++ .lvts_sensor = {
++ { .dt_id = MT8192_MCU_BIG_CPU2 },
++ { .dt_id = MT8192_MCU_BIG_CPU3 }
++ },
++ .num_lvts_sensor = 2,
++ .offset = 0x100,
++ .hw_tshut_temp = LVTS_HW_SHUTDOWN_MT8192,
++ .mode = LVTS_MSR_FILTERED_MODE,
++ },
++ {
++ .cal_offset = { 0x14, 0x18, 0x1c, 0x20 },
++ .lvts_sensor = {
++ { .dt_id = MT8192_MCU_LITTLE_CPU0 },
++ { .dt_id = MT8192_MCU_LITTLE_CPU1 },
++ { .dt_id = MT8192_MCU_LITTLE_CPU2 },
++ { .dt_id = MT8192_MCU_LITTLE_CPU3 }
++ },
++ .num_lvts_sensor = 4,
++ .offset = 0x200,
++ .hw_tshut_temp = LVTS_HW_SHUTDOWN_MT8192,
++ .mode = LVTS_MSR_FILTERED_MODE,
++ }
++};
++
++static const struct lvts_ctrl_data mt8192_lvts_ap_data_ctrl[] = {
++ {
++ .cal_offset = { 0x24, 0x28 },
++ .lvts_sensor = {
++ { .dt_id = MT8192_AP_VPU0 },
++ { .dt_id = MT8192_AP_VPU1 }
++ },
++ .num_lvts_sensor = 2,
++ .offset = 0x0,
++ .hw_tshut_temp = LVTS_HW_SHUTDOWN_MT8192,
++ },
++ {
++ .cal_offset = { 0x2c, 0x30 },
++ .lvts_sensor = {
++ { .dt_id = MT8192_AP_GPU0 },
++ { .dt_id = MT8192_AP_GPU1 }
++ },
++ .num_lvts_sensor = 2,
++ .offset = 0x100,
++ .hw_tshut_temp = LVTS_HW_SHUTDOWN_MT8192,
++ },
++ {
++ .cal_offset = { 0x34, 0x38 },
++ .lvts_sensor = {
++ { .dt_id = MT8192_AP_INFRA },
++ { .dt_id = MT8192_AP_CAM },
++ },
++ .num_lvts_sensor = 2,
++ .offset = 0x200,
++ .hw_tshut_temp = LVTS_HW_SHUTDOWN_MT8192,
++ },
++ {
++ .cal_offset = { 0x3c, 0x40, 0x44 },
++ .lvts_sensor = {
++ { .dt_id = MT8192_AP_MD0 },
++ { .dt_id = MT8192_AP_MD1 },
++ { .dt_id = MT8192_AP_MD2 }
++ },
++ .num_lvts_sensor = 3,
++ .offset = 0x300,
++ .hw_tshut_temp = LVTS_HW_SHUTDOWN_MT8192,
++ }
++};
++
+ static const struct lvts_ctrl_data mt8195_lvts_mcu_data_ctrl[] = {
+ {
+ .cal_offset = { 0x04, 0x07 },
+@@ -1423,6 +1506,16 @@ static const struct lvts_data mt7988_lvt
+ .temp_offset = LVTS_COEFF_B_MT7988,
+ };
+
++static const struct lvts_data mt8192_lvts_mcu_data = {
++ .lvts_ctrl = mt8192_lvts_mcu_data_ctrl,
++ .num_lvts_ctrl = ARRAY_SIZE(mt8192_lvts_mcu_data_ctrl),
++};
++
++static const struct lvts_data mt8192_lvts_ap_data = {
++ .lvts_ctrl = mt8192_lvts_ap_data_ctrl,
++ .num_lvts_ctrl = ARRAY_SIZE(mt8192_lvts_ap_data_ctrl),
++};
++
+ static const struct lvts_data mt8195_lvts_mcu_data = {
+ .lvts_ctrl = mt8195_lvts_mcu_data_ctrl,
+ .num_lvts_ctrl = ARRAY_SIZE(mt8195_lvts_mcu_data_ctrl),
+@@ -1439,6 +1532,8 @@ static const struct lvts_data mt8195_lvt
+
+ static const struct of_device_id lvts_of_match[] = {
+ { .compatible = "mediatek,mt7988-lvts-ap", .data = &mt7988_lvts_ap_data },
++ { .compatible = "mediatek,mt8192-lvts-mcu", .data = &mt8192_lvts_mcu_data },
++ { .compatible = "mediatek,mt8192-lvts-ap", .data = &mt8192_lvts_ap_data },
+ { .compatible = "mediatek,mt8195-lvts-mcu", .data = &mt8195_lvts_mcu_data },
+ { .compatible = "mediatek,mt8195-lvts-ap", .data = &mt8195_lvts_ap_data },
+ {},
--- /dev/null
+From 5d126a3c87cf7964b28bacf3826eea4266265bce Mon Sep 17 00:00:00 2001
+From: Balsam CHIHI <bchihi@baylibre.com>
+Date: Tue, 17 Oct 2023 21:05:45 +0200
+Subject: [PATCH 42/42] thermal/drivers/mediatek/lvts_thermal: Update
+ calibration data documentation
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Update LVTS calibration data documentation for mt8192 and mt8195.
+
+Signed-off-by: Balsam CHIHI <bchihi@baylibre.com>
+Reviewed-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>
+[bero@baylibre.com: Fix issues pointed out by Nícolas F. R. A. Prado <nfraprado@collabora.com>]
+Signed-off-by: Bernhard Rosenkränzer <bero@baylibre.com>
+Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
+Reviewed-by: Alexandre Mergnat <amergnat@baylibre.com>
+Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
+Link: https://lore.kernel.org/r/20231017190545.157282-6-bero@baylibre.com
+---
+ drivers/thermal/mediatek/lvts_thermal.c | 31 +++++++++++++++++++++++--
+ 1 file changed, 29 insertions(+), 2 deletions(-)
+
+--- a/drivers/thermal/mediatek/lvts_thermal.c
++++ b/drivers/thermal/mediatek/lvts_thermal.c
+@@ -616,7 +616,34 @@ static int lvts_sensor_init(struct devic
+ * The efuse blob values follows the sensor enumeration per thermal
+ * controller. The decoding of the stream is as follow:
+ *
+- * stream index map for MCU Domain :
++ * MT8192 :
++ * Stream index map for MCU Domain mt8192 :
++ *
++ * <-----mcu-tc#0-----> <-----sensor#0-----> <-----sensor#1----->
++ * 0x01 | 0x02 | 0x03 | 0x04 | 0x05 | 0x06 | 0x07 | 0x08 | 0x09 | 0x0A | 0x0B
++ *
++ * <-----sensor#2-----> <-----sensor#3----->
++ * 0x0C | 0x0D | 0x0E | 0x0F | 0x10 | 0x11 | 0x12 | 0x13
++ *
++ * <-----sensor#4-----> <-----sensor#5-----> <-----sensor#6-----> <-----sensor#7----->
++ * 0x14 | 0x15 | 0x16 | 0x17 | 0x18 | 0x19 | 0x1A | 0x1B | 0x1C | 0x1D | 0x1E | 0x1F | 0x20 | 0x21 | 0x22 | 0x23
++ *
++ * Stream index map for AP Domain mt8192 :
++ *
++ * <-----sensor#0-----> <-----sensor#1----->
++ * 0x24 | 0x25 | 0x26 | 0x27 | 0x28 | 0x29 | 0x2A | 0x2B
++ *
++ * <-----sensor#2-----> <-----sensor#3----->
++ * 0x2C | 0x2D | 0x2E | 0x2F | 0x30 | 0x31 | 0x32 | 0x33
++ *
++ * <-----sensor#4-----> <-----sensor#5----->
++ * 0x34 | 0x35 | 0x36 | 0x37 | 0x38 | 0x39 | 0x3A | 0x3B
++ *
++ * <-----sensor#6-----> <-----sensor#7-----> <-----sensor#8----->
++ * 0x3C | 0x3D | 0x3E | 0x3F | 0x40 | 0x41 | 0x42 | 0x43 | 0x44 | 0x45 | 0x46 | 0x47
++ *
++ * MT8195 :
++ * Stream index map for MCU Domain mt8195 :
+ *
+ * <-----mcu-tc#0-----> <-----sensor#0-----> <-----sensor#1----->
+ * 0x01 | 0x02 | 0x03 | 0x04 | 0x05 | 0x06 | 0x07 | 0x08 | 0x09
+@@ -627,7 +654,7 @@ static int lvts_sensor_init(struct devic
+ * <-----mcu-tc#2-----> <-----sensor#4-----> <-----sensor#5-----> <-----sensor#6-----> <-----sensor#7----->
+ * 0x13 | 0x14 | 0x15 | 0x16 | 0x17 | 0x18 | 0x19 | 0x1A | 0x1B | 0x1C | 0x1D | 0x1E | 0x1F | 0x20 | 0x21
+ *
+- * stream index map for AP Domain :
++ * Stream index map for AP Domain mt8195 :
+ *
+ * <-----ap--tc#0-----> <-----sensor#0-----> <-----sensor#1----->
+ * 0x22 | 0x23 | 0x24 | 0x25 | 0x26 | 0x27 | 0x28 | 0x29 | 0x2A
--- /dev/null
+From 3bf827929a44c17bfb1bf1000b143c02ce26a929 Mon Sep 17 00:00:00 2001
+From: Daniel Golle <daniel@makrotopia.org>
+Date: Sat, 26 Aug 2023 21:56:51 +0100
+Subject: [PATCH] i2c: mt65xx: allow optional pmic clock
+
+Using the I2C host controller on the MT7981 SoC requires 4 clocks to
+be enabled. One of them, the pmic clk, is only enabled in case
+'mediatek,have-pmic' is also set which has other consequences which
+are not desired in this case.
+
+Allow defining a pmic clk even in case the 'mediatek,have-pmic' propterty
+is not present and the bus is not used to connect to a pmic, but may
+still require to enable the pmic clock.
+
+Signed-off-by: Daniel Golle <daniel@makrotopia.org>
+---
+ drivers/i2c/busses/i2c-mt65xx.c | 12 ++++++++----
+ 1 file changed, 8 insertions(+), 4 deletions(-)
+
+--- a/drivers/i2c/busses/i2c-mt65xx.c
++++ b/drivers/i2c/busses/i2c-mt65xx.c
+@@ -1442,15 +1442,19 @@ static int mtk_i2c_probe(struct platform
+ if (IS_ERR(i2c->clocks[I2C_MT65XX_CLK_ARB].clk))
+ return PTR_ERR(i2c->clocks[I2C_MT65XX_CLK_ARB].clk);
+
++ i2c->clocks[I2C_MT65XX_CLK_PMIC].clk = devm_clk_get_optional(&pdev->dev, "pmic");
++ if (IS_ERR(i2c->clocks[I2C_MT65XX_CLK_PMIC].clk)) {
++ dev_err(&pdev->dev, "cannot get pmic clock\n");
++ return PTR_ERR(i2c->clocks[I2C_MT65XX_CLK_PMIC].clk);
++ }
++
+ if (i2c->have_pmic) {
+- i2c->clocks[I2C_MT65XX_CLK_PMIC].clk = devm_clk_get(&pdev->dev, "pmic");
+- if (IS_ERR(i2c->clocks[I2C_MT65XX_CLK_PMIC].clk)) {
++ if (!i2c->clocks[I2C_MT65XX_CLK_PMIC].clk) {
+ dev_err(&pdev->dev, "cannot get pmic clock\n");
+- return PTR_ERR(i2c->clocks[I2C_MT65XX_CLK_PMIC].clk);
++ return -ENODEV;
+ }
+ speed_clk = I2C_MT65XX_CLK_PMIC;
+ } else {
+- i2c->clocks[I2C_MT65XX_CLK_PMIC].clk = NULL;
+ speed_clk = I2C_MT65XX_CLK_MAIN;
+ }
+
--- /dev/null
+From f3f0934e5c7b9c16e0cb2435be3555382e6293ad Mon Sep 17 00:00:00 2001
+From: Maso Huang <maso.huang@mediatek.com>
+Date: Tue, 24 Oct 2023 11:50:17 +0800
+Subject: [PATCH 7/9] ASoC: mediatek: mt7986: drop the remove callback of
+ mt7986_wm8960
+
+Drop the remove callback of mt7986_wm8960.
+
+Signed-off-by: Maso Huang <maso.huang@mediatek.com>
+Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
+Link: https://lore.kernel.org/r/20231024035019.11732-2-maso.huang@mediatek.com
+Signed-off-by: Mark Brown <broonie@kernel.org>
+---
+ sound/soc/mediatek/mt7986/mt7986-wm8960.c | 10 ----------
+ 1 file changed, 10 deletions(-)
+
+--- a/sound/soc/mediatek/mt7986/mt7986-wm8960.c
++++ b/sound/soc/mediatek/mt7986/mt7986-wm8960.c
+@@ -163,15 +163,6 @@ err_of_node_put:
+ return ret;
+ }
+
+-static void mt7986_wm8960_machine_remove(struct platform_device *pdev)
+-{
+- struct snd_soc_card *card = platform_get_drvdata(pdev);
+- struct mt7986_wm8960_priv *priv = snd_soc_card_get_drvdata(card);
+-
+- of_node_put(priv->codec_node);
+- of_node_put(priv->platform_node);
+-}
+-
+ static const struct of_device_id mt7986_wm8960_machine_dt_match[] = {
+ {.compatible = "mediatek,mt7986-wm8960-sound"},
+ { /* sentinel */ }
+@@ -184,7 +175,6 @@ static struct platform_driver mt7986_wm8
+ .of_match_table = mt7986_wm8960_machine_dt_match,
+ },
+ .probe = mt7986_wm8960_machine_probe,
+- .remove_new = mt7986_wm8960_machine_remove,
+ };
+
+ module_platform_driver(mt7986_wm8960_machine);
--- /dev/null
+From 98b8fb2cb4fcab1903d0baf611bf0c3f822a08dc Mon Sep 17 00:00:00 2001
+From: Maso Huang <maso.huang@mediatek.com>
+Date: Tue, 24 Oct 2023 11:50:18 +0800
+Subject: [PATCH 8/9] ASoC: mediatek: mt7986: remove the mt7986_wm8960_priv
+ structure
+
+Remove the mt7986_wm8960_priv structure.
+
+Signed-off-by: Maso Huang <maso.huang@mediatek.com>
+Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
+Link: https://lore.kernel.org/r/20231024035019.11732-3-maso.huang@mediatek.com
+Signed-off-by: Mark Brown <broonie@kernel.org>
+---
+ sound/soc/mediatek/mt7986/mt7986-wm8960.c | 33 +++++++++--------------
+ 1 file changed, 12 insertions(+), 21 deletions(-)
+
+--- a/sound/soc/mediatek/mt7986/mt7986-wm8960.c
++++ b/sound/soc/mediatek/mt7986/mt7986-wm8960.c
+@@ -12,11 +12,6 @@
+
+ #include "mt7986-afe-common.h"
+
+-struct mt7986_wm8960_priv {
+- struct device_node *platform_node;
+- struct device_node *codec_node;
+-};
+-
+ static const struct snd_soc_dapm_widget mt7986_wm8960_widgets[] = {
+ SND_SOC_DAPM_HP("Headphone", NULL),
+ SND_SOC_DAPM_MIC("AMIC", NULL),
+@@ -92,20 +87,18 @@ static int mt7986_wm8960_machine_probe(s
+ struct snd_soc_card *card = &mt7986_wm8960_card;
+ struct snd_soc_dai_link *dai_link;
+ struct device_node *platform, *codec;
+- struct mt7986_wm8960_priv *priv;
++ struct device_node *platform_dai_node, *codec_dai_node;
+ int ret, i;
+
+- priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
+- if (!priv)
+- return -ENOMEM;
++ card->dev = &pdev->dev;
+
+ platform = of_get_child_by_name(pdev->dev.of_node, "platform");
+
+ if (platform) {
+- priv->platform_node = of_parse_phandle(platform, "sound-dai", 0);
++ platform_dai_node = of_parse_phandle(platform, "sound-dai", 0);
+ of_node_put(platform);
+
+- if (!priv->platform_node) {
++ if (!platform_dai_node) {
+ dev_err(&pdev->dev, "Failed to parse platform/sound-dai property\n");
+ return -EINVAL;
+ }
+@@ -117,24 +110,22 @@ static int mt7986_wm8960_machine_probe(s
+ for_each_card_prelinks(card, i, dai_link) {
+ if (dai_link->platforms->name)
+ continue;
+- dai_link->platforms->of_node = priv->platform_node;
++ dai_link->platforms->of_node = platform_dai_node;
+ }
+
+- card->dev = &pdev->dev;
+-
+ codec = of_get_child_by_name(pdev->dev.of_node, "codec");
+
+ if (codec) {
+- priv->codec_node = of_parse_phandle(codec, "sound-dai", 0);
++ codec_dai_node = of_parse_phandle(codec, "sound-dai", 0);
+ of_node_put(codec);
+
+- if (!priv->codec_node) {
+- of_node_put(priv->platform_node);
++ if (!codec_dai_node) {
++ of_node_put(platform_dai_node);
+ dev_err(&pdev->dev, "Failed to parse codec/sound-dai property\n");
+ return -EINVAL;
+ }
+ } else {
+- of_node_put(priv->platform_node);
++ of_node_put(platform_dai_node);
+ dev_err(&pdev->dev, "Property 'codec' missing or invalid\n");
+ return -EINVAL;
+ }
+@@ -142,7 +133,7 @@ static int mt7986_wm8960_machine_probe(s
+ for_each_card_prelinks(card, i, dai_link) {
+ if (dai_link->codecs->name)
+ continue;
+- dai_link->codecs->of_node = priv->codec_node;
++ dai_link->codecs->of_node = codec_dai_node;
+ }
+
+ ret = snd_soc_of_parse_audio_routing(card, "audio-routing");
+@@ -158,8 +149,8 @@ static int mt7986_wm8960_machine_probe(s
+ }
+
+ err_of_node_put:
+- of_node_put(priv->codec_node);
+- of_node_put(priv->platform_node);
++ of_node_put(platform_dai_node);
++ of_node_put(codec_dai_node);
+ return ret;
+ }
+
--- /dev/null
+From 4e229f4264f4be7a6a554487714c0913ef59cf7f Mon Sep 17 00:00:00 2001
+From: Maso Huang <maso.huang@mediatek.com>
+Date: Tue, 24 Oct 2023 11:50:19 +0800
+Subject: [PATCH 9/9] ASoC: mediatek: mt7986: add sample rate checker
+
+mt7986 only supports 8/12/16/24/32/48/96/192 kHz
+
+Signed-off-by: Maso Huang <maso.huang@mediatek.com>
+Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
+Link: https://lore.kernel.org/r/20231024035019.11732-4-maso.huang@mediatek.com
+Signed-off-by: Mark Brown <broonie@kernel.org>
+---
+ sound/soc/mediatek/mt7986/mt7986-dai-etdm.c | 23 +++++++++++++++++----
+ 1 file changed, 19 insertions(+), 4 deletions(-)
+
+--- a/sound/soc/mediatek/mt7986/mt7986-dai-etdm.c
++++ b/sound/soc/mediatek/mt7986/mt7986-dai-etdm.c
+@@ -237,12 +237,27 @@ static int mtk_dai_etdm_hw_params(struct
+ struct snd_pcm_hw_params *params,
+ struct snd_soc_dai *dai)
+ {
++ unsigned int rate = params_rate(params);
+ struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);
+
+- mtk_dai_etdm_config(afe, params, dai, SNDRV_PCM_STREAM_PLAYBACK);
+- mtk_dai_etdm_config(afe, params, dai, SNDRV_PCM_STREAM_CAPTURE);
+-
+- return 0;
++ switch (rate) {
++ case 8000:
++ case 12000:
++ case 16000:
++ case 24000:
++ case 32000:
++ case 48000:
++ case 96000:
++ case 192000:
++ mtk_dai_etdm_config(afe, params, dai, SNDRV_PCM_STREAM_PLAYBACK);
++ mtk_dai_etdm_config(afe, params, dai, SNDRV_PCM_STREAM_CAPTURE);
++ return 0;
++ default:
++ dev_err(afe->dev,
++ "Sample rate %d invalid. Supported rates: 8/12/16/24/32/48/96/192 kHz\n",
++ rate);
++ return -EINVAL;
++ }
+ }
+
+ static int mtk_dai_etdm_trigger(struct snd_pcm_substream *substream, int cmd,
--- /dev/null
+From e4cde335d1771863a60b6931e51357b8470e85c4 Mon Sep 17 00:00:00 2001
+From: Daniel Golle <daniel@makrotopia.org>
+Date: Sun, 10 Dec 2023 22:41:39 +0000
+Subject: [PATCH] ASoC: mediatek: mt7986: silence error in case of
+ -EPROBE_DEFER
+
+If probe is defered no error should be printed. Mute it.
+
+Signed-off-by: Daniel Golle <daniel@makrotopia.org>
+---
+ sound/soc/mediatek/mt7986/mt7986-wm8960.c | 4 +++-
+ 1 file changed, 3 insertions(+), 1 deletion(-)
+
+--- a/sound/soc/mediatek/mt7986/mt7986-wm8960.c
++++ b/sound/soc/mediatek/mt7986/mt7986-wm8960.c
+@@ -144,7 +144,9 @@ static int mt7986_wm8960_machine_probe(s
+
+ ret = devm_snd_soc_register_card(&pdev->dev, card);
+ if (ret) {
+- dev_err(&pdev->dev, "%s snd_soc_register_card fail: %d\n", __func__, ret);
++ if (ret != -EPROBE_DEFER)
++ dev_err(&pdev->dev, "%s snd_soc_register_card fail: %d\n", __func__, ret);
++
+ goto err_of_node_put;
+ }
+
--- /dev/null
+From 1c09b694a1e9378931085e77d834a4d9786a5356 Mon Sep 17 00:00:00 2001
+From: Maso Huang <maso.huang@mediatek.com>
+Date: Thu, 7 Sep 2023 10:54:37 +0800
+Subject: [PATCH] arm64: dts: mt7986: add afe
+
+---
+ arch/arm64/boot/dts/mediatek/mt7986a.dtsi | 23 +++++++++++
+ 1 files changed, 23 insertions(+)
+
+--- a/arch/arm64/boot/dts/mediatek/mt7986a.dtsi
++++ b/arch/arm64/boot/dts/mediatek/mt7986a.dtsi
+@@ -202,6 +202,29 @@
+ #interrupt-cells = <2>;
+ };
+
++ afe: audio-controller@11210000 {
++ compatible = "mediatek,mt7986-afe";
++ reg = <0 0x11210000 0 0x9000>;
++ #sound-dai-cells = <0>;
++ interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
++ clocks = <&infracfg CLK_INFRA_AUD_BUS_CK>,
++ <&infracfg CLK_INFRA_AUD_26M_CK>,
++ <&infracfg CLK_INFRA_AUD_L_CK>,
++ <&infracfg CLK_INFRA_AUD_AUD_CK>,
++ <&infracfg CLK_INFRA_AUD_EG2_CK>;
++ clock-names = "aud_bus_ck",
++ "aud_26m_ck",
++ "aud_l_ck",
++ "aud_aud_ck",
++ "aud_eg2_ck";
++ assigned-clocks = <&topckgen CLK_TOP_A1SYS_SEL>,
++ <&topckgen CLK_TOP_AUD_L_SEL>,
++ <&topckgen CLK_TOP_A_TUNER_SEL>;
++ assigned-clock-parents = <&topckgen CLK_TOP_APLL2_D4>,
++ <&apmixedsys CLK_APMIXED_APLL2>,
++ <&topckgen CLK_TOP_APLL2_D4>;
++ };
++
+ pwm: pwm@10048000 {
+ compatible = "mediatek,mt7986-pwm";
+ reg = <0 0x10048000 0 0x1000>;
--- /dev/null
+From 1c09b694a1e9378931085e77d834a4d9786a5356 Mon Sep 17 00:00:00 2001
+From: Maso Huang <maso.huang@mediatek.com>
+Date: Thu, 7 Sep 2023 10:54:37 +0800
+Subject: [PATCH] arm64: dts: mt7986: add sound wm8960
+
+---
+ .../dts/mediatek/mt7986a-rfb-spim-nand.dts | 39 +++++++++++++++++++
+ 1 files changed, 39 insertions(+)
+
+--- a/arch/arm64/boot/dts/mediatek/mt7986a-rfb-spim-nand.dts
++++ b/arch/arm64/boot/dts/mediatek/mt7986a-rfb-spim-nand.dts
+@@ -4,6 +4,36 @@
+
+ / {
+ compatible = "mediatek,mt7986a-rfb-snand";
++
++ sound_wm8960 {
++ compatible = "mediatek,mt7986-wm8960-sound";
++ audio-routing = "Headphone", "HP_L",
++ "Headphone", "HP_R",
++ "LINPUT1", "AMIC",
++ "RINPUT1", "AMIC";
++
++ status = "okay";
++
++ platform {
++ sound-dai = <&afe>;
++ };
++
++ codec {
++ sound-dai = <&wm8960>;
++ };
++ };
++};
++
++&i2c0 {
++ pinctrl-names = "default";
++ pinctrl-0 = <&i2c_pins>;
++ status = "okay";
++
++ wm8960: wm8960@1a {
++ compatible = "wlf,wm8960";
++ #sound-dai-cells = <0>;
++ reg = <0x1a>;
++ };
+ };
+
+ &spi0 {
+@@ -50,3 +80,13 @@
+ &wifi {
+ mediatek,mtd-eeprom = <&factory 0>;
+ };
++
++&pio {
++ i2c_pins: i2c-pins-3-4 {
++ mux {
++ function = "i2c";
++ groups = "i2c";
++ };
++ };
++};
++
--- /dev/null
+--- /dev/null
++++ b/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-respeaker-2mics.dtso
+@@ -0,0 +1,65 @@
++// SPDX-License-Identifier: (GPL-2.0 OR MIT)
++/*
++ * Copyright (C) 2023 MediaTek Inc.
++ * Author: Maso Huang <Maso.Huang@mediatek.com>
++ */
++
++/dts-v1/;
++/plugin/;
++
++/ {
++ compatible = "bananapi,bpi-r3", "mediatek,mt7986a";
++
++ fragment@0 {
++ target-path = "/";
++ __overlay__ {
++ sound_wm8960 {
++ compatible = "mediatek,mt7986-wm8960-sound";
++ audio-routing = "Headphone", "HP_L",
++ "Headphone", "HP_R",
++ "LINPUT1", "AMIC",
++ "RINPUT1", "AMIC";
++
++ status = "okay";
++
++ platform {
++ sound-dai = <&afe>;
++ };
++
++ codec {
++ sound-dai = <&wm8960>;
++ };
++ };
++ };
++ };
++
++ fragment@1 {
++ target = <&i2c0>;
++ __overlay__ {
++ #address-cells = <1>;
++ #size-cells = <0>;
++ pinctrl-names = "default";
++ pinctrl-0 = <&i2c_pins>;
++ clock-frequency = <400000>;
++ status = "okay";
++
++ wm8960: wm8960@1a {
++ compatible = "wlf,wm8960";
++ #sound-dai-cells = <0>;
++ reg = <0x1a>;
++ };
++ };
++ };
++
++ fragment@2 {
++ target = <&pio>;
++ __overlay__ {
++ i2c_pins: i2c-pins-3-4 {
++ mux {
++ function = "i2c";
++ groups = "i2c";
++ };
++ };
++ };
++ };
++};
+--- a/arch/arm64/boot/dts/mediatek/Makefile
++++ b/arch/arm64/boot/dts/mediatek/Makefile
+@@ -13,6 +13,7 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += mt7986a-b
+ dtb-$(CONFIG_ARCH_MEDIATEK) += mt7986a-bananapi-bpi-r3-nand.dtbo
+ dtb-$(CONFIG_ARCH_MEDIATEK) += mt7986a-bananapi-bpi-r3-nor.dtbo
+ dtb-$(CONFIG_ARCH_MEDIATEK) += mt7986a-bananapi-bpi-r3-sd.dtbo
++dtb-$(CONFIG_ARCH_MEDIATEK) += mt7986a-bananapi-bpi-r3-respeaker-2mics.dtbo
+ dtb-$(CONFIG_ARCH_MEDIATEK) += mt7986a-rfb.dtb
+ dtb-$(CONFIG_ARCH_MEDIATEK) += mt7986b-rfb.dtb
+ dtb-$(CONFIG_ARCH_MEDIATEK) += mt8167-pumpkin.dtb
--- /dev/null
+--- a/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts
++++ b/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts
+@@ -312,7 +312,7 @@
+ /* Attention: GPIO 90 is used to switch between PCIe@1,0 and
+ * SATA functions. i.e. output-high: PCIe, output-low: SATA
+ */
+- asm_sel {
++ asmsel: asm_sel {
+ gpio-hog;
+ gpios = <90 GPIO_ACTIVE_HIGH>;
+ output-high;
+--- /dev/null
++++ b/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64-sata.dtso
+@@ -0,0 +1,31 @@
++/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */
++
++#include <dt-bindings/gpio/gpio.h>
++
++/dts-v1/;
++/plugin/;
++
++/ {
++ compatible = "bananapi,bpi-r64", "mediatek,mt7622";
++
++ fragment@0 {
++ target = <&asmsel>;
++ __overlay__ {
++ gpios = <90 GPIO_ACTIVE_LOW>;
++ };
++ };
++
++ fragment@1 {
++ target = <&sata>;
++ __overlay__ {
++ status = "okay";
++ };
++ };
++
++ fragment@2 {
++ target = <&sata_phy>;
++ __overlay__ {
++ status = "okay";
++ };
++ };
++};
+--- /dev/null
++++ b/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64-pcie1.dtso
+@@ -0,0 +1,17 @@
++/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */
++
++#include <dt-bindings/gpio/gpio.h>
++
++/dts-v1/;
++/plugin/;
++
++/ {
++ compatible = "bananapi,bpi-r64", "mediatek,mt7622";
++
++ fragment@0 {
++ target = <&asmsel>;
++ __overlay__ {
++ gpios = <90 GPIO_ACTIVE_HIGH>;
++ };
++ };
++};
--- /dev/null
+--- a/arch/arm/Kconfig
++++ b/arch/arm/Kconfig
+@@ -1568,6 +1568,14 @@ config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEN
+
+ endchoice
+
++config CMDLINE_OVERRIDE
++ bool "Use alternative cmdline from device tree"
++ help
++ Some bootloaders may have uneditable bootargs. While CMDLINE_FORCE can
++ be used, this is not a good option for kernels that are shared across
++ devices. This setting enables using "chosen/cmdline-override" as the
++ cmdline if it exists in the device tree.
++
+ config CMDLINE
+ string "Default kernel command string"
+ default ""
+--- a/drivers/of/fdt.c
++++ b/drivers/of/fdt.c
+@@ -1190,6 +1190,17 @@ int __init early_init_dt_scan_chosen(cha
+ if (p != NULL && l > 0)
+ strlcat(cmdline, p, min_t(int, strlen(cmdline) + (int)l, COMMAND_LINE_SIZE));
+
++ /* CONFIG_CMDLINE_OVERRIDE is used to fallback to a different
++ * device tree option of chosen/bootargs-override. This is
++ * helpful on boards where u-boot sets bootargs, and is unable
++ * to be modified.
++ */
++#ifdef CONFIG_CMDLINE_OVERRIDE
++ p = of_get_flat_dt_prop(node, "bootargs-override", &l);
++ if (p != NULL && l > 0)
++ strlcpy(cmdline, p, min((int)l, COMMAND_LINE_SIZE));
++#endif
++
+ handle_cmdline:
+ /*
+ * CONFIG_CMDLINE is meant to be a default in case nothing else
+--- a/arch/arm64/Kconfig
++++ b/arch/arm64/Kconfig
+@@ -2309,6 +2309,14 @@ config CMDLINE_FORCE
+
+ endchoice
+
++config CMDLINE_OVERRIDE
++ bool "Use alternative cmdline from device tree"
++ help
++ Some bootloaders may have uneditable bootargs. While CMDLINE_FORCE can
++ be used, this is not a good option for kernels that are shared across
++ devices. This setting enables using "chosen/cmdline-override" as the
++ cmdline if it exists in the device tree.
++
+ config EFI_STUB
+ bool
+
--- /dev/null
+--- a/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts
++++ b/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts
+@@ -639,5 +639,28 @@
+ };
+
+ &wmac {
++ mediatek,eeprom-data = <0x22760500 0x0 0x0 0x0
++ 0x0 0x0 0x0 0x0
++ 0x0 0x0 0x0 0x0
++ 0x0 0x44000020 0x0 0x10002000
++ 0x4400 0x4000000 0x0 0x0
++ 0x200000b3 0x40b6c3c3 0x26000000 0x41c42600
++ 0x41c4 0x26000000 0xc0c52600 0x0
++ 0x0 0x0 0x0 0x0
++ 0x0 0x0 0x0 0x0
++ 0x0 0x0 0x0 0x0
++ 0x0 0x0 0x0 0x0
++ 0x0 0x0 0x0 0xc6c6
++ 0xc3c3c2c1 0xc300c3 0x818181 0x83c1c182
++ 0x83838382 0x0 0x0 0x0
++ 0x0 0x0 0x0 0x0
++ 0x84002e00 0x90000087 0x8a000000 0x0
++ 0x0 0x0 0x0 0x0
++ 0x0 0x0 0x0 0x0
++ 0xb000009 0x0 0x0 0x0
++ 0x0 0x0 0x0 0x0
++ 0x0 0x0 0x0 0x0
++ 0x0 0x0 0x0 0x7707>;
++
+ status = "okay";
+ };
--- /dev/null
+--- a/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts
++++ b/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts
+@@ -32,6 +32,9 @@
+ chosen {
+ stdout-path = "serial0:115200n8";
+ bootargs = "earlycon=uart8250,mmio32,0x11002000 console=ttyS0,115200n1 swiotlb=512";
++ rootdisk-emmc = <&emmc_rootfs>;
++ rootdisk-sd = <&sd_rootfs>;
++ rootdisk-snfi = <&ubi_rootfs>;
+ };
+
+ cpus {
+@@ -234,6 +237,28 @@
+ assigned-clocks = <&topckgen CLK_TOP_MSDC30_0_SEL>;
+ assigned-clock-parents = <&topckgen CLK_TOP_UNIV48M>;
+ non-removable;
++ #address-cells = <1>;
++ #size-cells = <0>;
++
++ card@0 {
++ compatible = "mmc-card";
++ reg = <0>;
++
++ block {
++ compatible = "block-device";
++ partitions {
++ block-partition-env {
++ partname = "ubootenv";
++ nvmem-layout {
++ compatible = "u-boot,env";
++ };
++ };
++ emmc_rootfs: block-partition-production {
++ partname = "production";
++ };
++ };
++ };
++ };
+ };
+
+ &mmc1 {
+@@ -249,6 +274,28 @@
+ vqmmc-supply = <®_3p3v>;
+ assigned-clocks = <&topckgen CLK_TOP_MSDC30_1_SEL>;
+ assigned-clock-parents = <&topckgen CLK_TOP_UNIV48M>;
++ #address-cells = <1>;
++ #size-cells = <0>;
++
++ card@0 {
++ compatible = "mmc-card";
++ reg = <0>;
++
++ block {
++ compatible = "block-device";
++ partitions {
++ block-partition-env {
++ partname = "ubootenv";
++ nvmem-layout {
++ compatible = "u-boot,env";
++ };
++ };
++ sd_rootfs: block-partition-production {
++ partname = "production";
++ };
++ };
++ };
++ };
+ };
+
+ &nandc {
+@@ -282,15 +329,30 @@
+ read-only;
+ };
+
+- partition@80000 {
+- label = "fip";
+- reg = <0x80000 0x200000>;
+- read-only;
+- };
+-
+- ubi: partition@280000 {
++ ubi: partition@80000 {
+ label = "ubi";
+- reg = <0x280000 0x7d80000>;
++ reg = <0x80000 0x7f80000>;
++ compatible = "linux,ubi";
++
++ volumes {
++ ubi-volume-ubootenv {
++ volname = "ubootenv";
++ nvmem-layout {
++ compatible = "u-boot,env-redundant-bool";
++ };
++ };
++
++ ubi-volume-ubootenv2 {
++ volname = "ubootenv2";
++ nvmem-layout {
++ compatible = "u-boot,env-redundant-bool";
++ };
++ };
++
++ ubi_rootfs: ubi-volume-fit {
++ volname = "fit";
++ };
++ };
+ };
+ };
+ };
--- /dev/null
+--- a/drivers/spi/spi-mt65xx.c
++++ b/drivers/spi/spi-mt65xx.c
+@@ -1228,8 +1228,15 @@ static int mtk_spi_probe(struct platform
+ if (ret < 0)
+ return dev_err_probe(dev, ret, "failed to enable hclk\n");
+
++ ret = clk_prepare_enable(mdata->sel_clk);
++ if (ret < 0) {
++ clk_disable_unprepare(mdata->spi_hclk);
++ return dev_err_probe(dev, ret, "failed to enable sel_clk\n");
++ }
++
+ ret = clk_prepare_enable(mdata->spi_clk);
+ if (ret < 0) {
++ clk_disable_unprepare(mdata->sel_clk);
+ clk_disable_unprepare(mdata->spi_hclk);
+ return dev_err_probe(dev, ret, "failed to enable spi_clk\n");
+ }
--- /dev/null
+From 3cf212c4ce6cd72c09bc47f35f539ba0afd4d106 Mon Sep 17 00:00:00 2001
+Message-Id: <3cf212c4ce6cd72c09bc47f35f539ba0afd4d106.1678716918.git.lorenzo@kernel.org>
+From: Lorenzo Bianconi <lorenzo@kernel.org>
+Date: Sun, 12 Mar 2023 16:40:31 +0100
+Subject: [PATCH net-next 1/2] net: ethernet: mtk_wed: rename
+ mtk_wed_get_memory_region in mtk_wed_get_reserved_memory_region
+
+This is a preliminary patch to move wed ilm/dlm and cpuboot properties in
+dedicated dts nodes.
+
+Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
+---
+ drivers/net/ethernet/mediatek/mtk_wed_mcu.c | 8 ++++----
+ 1 file changed, 4 insertions(+), 4 deletions(-)
+
+--- a/drivers/net/ethernet/mediatek/mtk_wed_mcu.c
++++ b/drivers/net/ethernet/mediatek/mtk_wed_mcu.c
+@@ -234,8 +234,8 @@ int mtk_wed_mcu_msg_update(struct mtk_we
+ }
+
+ static int
+-mtk_wed_get_memory_region(struct mtk_wed_hw *hw, int index,
+- struct mtk_wed_wo_memory_region *region)
++mtk_wed_get_reserved_memory_region(struct mtk_wed_hw *hw, int index,
++ struct mtk_wed_wo_memory_region *region)
+ {
+ struct reserved_mem *rmem;
+ struct device_node *np;
+@@ -325,7 +325,7 @@ mtk_wed_mcu_load_firmware(struct mtk_wed
+ if (index < 0)
+ continue;
+
+- ret = mtk_wed_get_memory_region(wo->hw, index, &mem_region[i]);
++ ret = mtk_wed_get_reserved_memory_region(wo->hw, index, &mem_region[i]);
+ if (ret)
+ return ret;
+ }
--- /dev/null
+From 247e566e3459481f1fa98733534bfed767e18b42 Mon Sep 17 00:00:00 2001
+Message-Id: <247e566e3459481f1fa98733534bfed767e18b42.1678620342.git.lorenzo@kernel.org>
+From: Lorenzo Bianconi <lorenzo@kernel.org>
+Date: Sat, 11 Mar 2023 16:32:41 +0100
+Subject: [PATCH net-next] arm64: dts: mt7986: move cpuboot in a dedicated node
+
+Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
+---
+ arch/arm64/boot/dts/mediatek/mt7986a.dtsi | 21 +++++++++++----------
+ 1 file changed, 11 insertions(+), 10 deletions(-)
+
+--- a/arch/arm64/boot/dts/mediatek/mt7986a.dtsi
++++ b/arch/arm64/boot/dts/mediatek/mt7986a.dtsi
+@@ -121,12 +121,6 @@
+ reg = <0 0x151f8000 0 0x2000>;
+ no-map;
+ };
+-
+- wo_boot: wo-boot@15194000 {
+- reg = <0 0x15194000 0 0x1000>;
+- no-map;
+- };
+-
+ };
+
+ soc {
+@@ -533,10 +527,11 @@
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>;
+ memory-region = <&wo_emi0>, <&wo_ilm0>, <&wo_dlm0>,
+- <&wo_data>, <&wo_boot>;
++ <&wo_data>;
+ memory-region-names = "wo-emi", "wo-ilm", "wo-dlm",
+- "wo-data", "wo-boot";
++ "wo-data";
+ mediatek,wo-ccif = <&wo_ccif0>;
++ mediatek,wo-cpuboot = <&wo_cpuboot>;
+ };
+
+ wed1: wed@15011000 {
+@@ -546,10 +541,11 @@
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>;
+ memory-region = <&wo_emi1>, <&wo_ilm1>, <&wo_dlm1>,
+- <&wo_data>, <&wo_boot>;
++ <&wo_data>;
+ memory-region-names = "wo-emi", "wo-ilm", "wo-dlm",
+- "wo-data", "wo-boot";
++ "wo-data";
+ mediatek,wo-ccif = <&wo_ccif1>;
++ mediatek,wo-cpuboot = <&wo_cpuboot>;
+ };
+
+ eth: ethernet@15100000 {
+@@ -607,6 +603,11 @@
+ interrupts = <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
++ wo_cpuboot: syscon@15194000 {
++ compatible = "mediatek,mt7986-wo-cpuboot", "syscon";
++ reg = <0 0x15194000 0 0x1000>;
++ };
++
+ wifi: wifi@18000000 {
+ compatible = "mediatek,mt7986-wmac";
+ reg = <0 0x18000000 0 0x1000000>,
--- /dev/null
+From f292d1bf83ec160bef2532b58aa08f5b71041923 Mon Sep 17 00:00:00 2001
+Message-Id: <f292d1bf83ec160bef2532b58aa08f5b71041923.1678716918.git.lorenzo@kernel.org>
+In-Reply-To: <3cf212c4ce6cd72c09bc47f35f539ba0afd4d106.1678716918.git.lorenzo@kernel.org>
+References: <3cf212c4ce6cd72c09bc47f35f539ba0afd4d106.1678716918.git.lorenzo@kernel.org>
+From: Lorenzo Bianconi <lorenzo@kernel.org>
+Date: Sat, 11 Mar 2023 18:13:04 +0100
+Subject: [PATCH net-next 2/2] net: ethernet: mtk_wed: move cpuboot in a
+ dedicated dts node
+
+Since the cpuboot memory region is not part of the RAM SoC, move cpuboot
+in a deidicated syscon node.
+This patch helps to keep backward-compatibility with older version of
+uboot codebase where we have a limit of 8 reserved-memory dts child
+nodes.
+Keep backward-compatibility with older dts version where cpuboot was
+defined as reserved-memory child node.
+
+Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
+---
+ drivers/net/ethernet/mediatek/mtk_wed_mcu.c | 34 +++++++++++++++++----
+ drivers/net/ethernet/mediatek/mtk_wed_wo.h | 3 +-
+ 2 files changed, 30 insertions(+), 7 deletions(-)
+
+--- a/drivers/net/ethernet/mediatek/mtk_wed_mcu.c
++++ b/drivers/net/ethernet/mediatek/mtk_wed_mcu.c
+@@ -32,14 +32,25 @@ static struct mtk_wed_wo_memory_region m
+ },
+ };
+
+-static u32 wo_r32(u32 reg)
++static u32 wo_r32(struct mtk_wed_wo *wo, u32 reg)
+ {
+- return readl(mem_region[MTK_WED_WO_REGION_BOOT].addr + reg);
++ u32 val;
++
++ if (!wo->boot_regmap)
++ return readl(mem_region[MTK_WED_WO_REGION_BOOT].addr + reg);
++
++ if (regmap_read(wo->boot_regmap, reg, &val))
++ val = ~0;
++
++ return val;
+ }
+
+-static void wo_w32(u32 reg, u32 val)
++static void wo_w32(struct mtk_wed_wo *wo, u32 reg, u32 val)
+ {
+- writel(val, mem_region[MTK_WED_WO_REGION_BOOT].addr + reg);
++ if (wo->boot_regmap)
++ regmap_write(wo->boot_regmap, reg, val);
++ else
++ writel(val, mem_region[MTK_WED_WO_REGION_BOOT].addr + reg);
+ }
+
+ static struct sk_buff *
+@@ -317,6 +328,9 @@ mtk_wed_mcu_load_firmware(struct mtk_wed
+ u32 val, boot_cr;
+ int ret, i;
+
++ wo->boot_regmap = syscon_regmap_lookup_by_phandle(wo->hw->node,
++ "mediatek,wo-cpuboot");
++
+ /* load firmware region metadata */
+ for (i = 0; i < ARRAY_SIZE(mem_region); i++) {
+ int index = of_property_match_string(wo->hw->node,
+@@ -325,6 +339,9 @@ mtk_wed_mcu_load_firmware(struct mtk_wed
+ if (index < 0)
+ continue;
+
++ if (index == MTK_WED_WO_REGION_BOOT && !IS_ERR(wo->boot_regmap))
++ continue;
++
+ ret = mtk_wed_get_reserved_memory_region(wo->hw, index, &mem_region[i]);
+ if (ret)
+ return ret;
+@@ -373,13 +390,13 @@ mtk_wed_mcu_load_firmware(struct mtk_wed
+ boot_cr = MTK_WO_MCU_CFG_LS_WA_BOOT_ADDR_ADDR;
+ else
+ boot_cr = MTK_WO_MCU_CFG_LS_WM_BOOT_ADDR_ADDR;
+- wo_w32(boot_cr, mem_region[MTK_WED_WO_REGION_EMI].phy_addr >> 16);
++ wo_w32(wo, boot_cr, mem_region[MTK_WED_WO_REGION_EMI].phy_addr >> 16);
+ /* wo firmware reset */
+- wo_w32(MTK_WO_MCU_CFG_LS_WF_MCCR_CLR_ADDR, 0xc00);
++ wo_w32(wo, MTK_WO_MCU_CFG_LS_WF_MCCR_CLR_ADDR, 0xc00);
+
+- val = wo_r32(MTK_WO_MCU_CFG_LS_WF_MCU_CFG_WM_WA_ADDR) |
++ val = wo_r32(wo, MTK_WO_MCU_CFG_LS_WF_MCU_CFG_WM_WA_ADDR) |
+ MTK_WO_MCU_CFG_LS_WF_WM_WA_WM_CPU_RSTB_MASK;
+- wo_w32(MTK_WO_MCU_CFG_LS_WF_MCU_CFG_WM_WA_ADDR, val);
++ wo_w32(wo, MTK_WO_MCU_CFG_LS_WF_MCU_CFG_WM_WA_ADDR, val);
+ out:
+ release_firmware(fw);
+
+--- a/drivers/net/ethernet/mediatek/mtk_wed_wo.h
++++ b/drivers/net/ethernet/mediatek/mtk_wed_wo.h
+@@ -231,6 +231,7 @@ struct mtk_wed_wo_queue {
+ struct mtk_wed_wo {
+ struct mtk_wed_hw *hw;
+
++ struct regmap *boot_regmap;
+ struct mtk_wed_wo_queue q_tx;
+ struct mtk_wed_wo_queue q_rx;
+
--- /dev/null
+From f3565e6c2276411275e707a5442d3f69cc111273 Mon Sep 17 00:00:00 2001
+Message-Id: <f3565e6c2276411275e707a5442d3f69cc111273.1678718888.git.lorenzo@kernel.org>
+From: Lorenzo Bianconi <lorenzo@kernel.org>
+Date: Sun, 12 Mar 2023 18:51:47 +0100
+Subject: [PATCH net-next 1/3] net: ethernet: mtk_wed: move ilm a dedicated dts
+ node
+
+Since the ilm memory region is not part of the RAM SoC, move ilm in a
+deidicated syscon node.
+This patch helps to keep backward-compatibility with older version of
+uboot codebase where we have a limit of 8 reserved-memory dts child
+nodes.
+Keep backward-compatibility with older dts version where ilm was defined
+as reserved-memory child node.
+
+Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
+---
+ drivers/net/ethernet/mediatek/mtk_wed_mcu.c | 55 ++++++++++++++++++---
+ 1 file changed, 49 insertions(+), 6 deletions(-)
+
+--- a/drivers/net/ethernet/mediatek/mtk_wed_mcu.c
++++ b/drivers/net/ethernet/mediatek/mtk_wed_mcu.c
+@@ -320,6 +320,39 @@ next:
+ }
+
+ static int
++mtk_wed_mcu_load_ilm(struct mtk_wed_wo *wo)
++{
++ struct mtk_wed_wo_memory_region *ilm_region;
++ struct resource res;
++ struct device_node *np;
++ int ret;
++
++ np = of_parse_phandle(wo->hw->node, "mediatek,wo-ilm", 0);
++ if (!np)
++ return 0;
++
++ ret = of_address_to_resource(np, 0, &res);
++ of_node_put(np);
++
++ if (ret < 0)
++ return ret;
++
++ ilm_region = &mem_region[MTK_WED_WO_REGION_ILM];
++ ilm_region->phy_addr = res.start;
++ ilm_region->size = resource_size(&res);
++ ilm_region->addr = devm_ioremap(wo->hw->dev, res.start,
++ resource_size(&res));
++
++ if (!IS_ERR(ilm_region->addr))
++ return 0;
++
++ ret = PTR_ERR(ilm_region->addr);
++ ilm_region->addr = NULL;
++
++ return ret;
++}
++
++static int
+ mtk_wed_mcu_load_firmware(struct mtk_wed_wo *wo)
+ {
+ const struct mtk_wed_fw_trailer *trailer;
+@@ -328,14 +361,20 @@ mtk_wed_mcu_load_firmware(struct mtk_wed
+ u32 val, boot_cr;
+ int ret, i;
+
++ mtk_wed_mcu_load_ilm(wo);
+ wo->boot_regmap = syscon_regmap_lookup_by_phandle(wo->hw->node,
+ "mediatek,wo-cpuboot");
+
+ /* load firmware region metadata */
+ for (i = 0; i < ARRAY_SIZE(mem_region); i++) {
+- int index = of_property_match_string(wo->hw->node,
+- "memory-region-names",
+- mem_region[i].name);
++ int index;
++
++ if (mem_region[i].addr)
++ continue;
++
++ index = of_property_match_string(wo->hw->node,
++ "memory-region-names",
++ mem_region[i].name);
+ if (index < 0)
+ continue;
+
--- /dev/null
+From b74ba226be2c45091b93bd49192bdd6d2178729e Mon Sep 17 00:00:00 2001
+Message-Id: <b74ba226be2c45091b93bd49192bdd6d2178729e.1678718888.git.lorenzo@kernel.org>
+In-Reply-To: <f3565e6c2276411275e707a5442d3f69cc111273.1678718888.git.lorenzo@kernel.org>
+References: <f3565e6c2276411275e707a5442d3f69cc111273.1678718888.git.lorenzo@kernel.org>
+From: Lorenzo Bianconi <lorenzo@kernel.org>
+Date: Mon, 13 Mar 2023 15:45:16 +0100
+Subject: [PATCH net-next 3/3] net: ethernet: mtk_wed: move dlm a dedicated dts
+ node
+
+Since the dlm memory region is not part of the RAM SoC, move dlm in a
+deidicated syscon node.
+This patch helps to keep backward-compatibility with older version of
+uboot codebase where we have a limit of 8 reserved-memory dts child
+nodes.
+Keep backward-compatibility with older dts version where dlm was defined
+as reserved-memory child node.
+
+Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
+---
+ drivers/net/ethernet/mediatek/mtk_wed.c | 19 +++++++++++++++++++
+ 1 file changed, 19 insertions(+)
+
+--- a/drivers/net/ethernet/mediatek/mtk_wed.c
++++ b/drivers/net/ethernet/mediatek/mtk_wed.c
+@@ -1322,6 +1322,24 @@ mtk_wed_rro_alloc(struct mtk_wed_device
+ struct device_node *np;
+ int index;
+
++ np = of_parse_phandle(dev->hw->node, "mediatek,wo-dlm", 0);
++ if (np) {
++ struct resource res;
++ int ret;
++
++ ret = of_address_to_resource(np, 0, &res);
++ of_node_put(np);
++
++ if (ret < 0)
++ return ret;
++
++ dev->rro.miod_phys = res.start;
++ goto out;
++ }
++
++ /* For backward compatibility, we need to check if DLM
++ * node is defined through reserved memory property.
++ */
+ index = of_property_match_string(dev->hw->node, "memory-region-names",
+ "wo-dlm");
+ if (index < 0)
+@@ -1338,6 +1356,7 @@ mtk_wed_rro_alloc(struct mtk_wed_device
+ return -ENODEV;
+
+ dev->rro.miod_phys = rmem->base;
++out:
+ dev->rro.fdbk_phys = MTK_WED_MIOD_COUNT + dev->rro.miod_phys;
+
+ return mtk_wed_rro_ring_alloc(dev, &dev->rro.ring,
--- /dev/null
+From 01561065af5bf1d2a4244896d897e3a1eafbcd46 Mon Sep 17 00:00:00 2001
+Message-Id: <01561065af5bf1d2a4244896d897e3a1eafbcd46.1678717704.git.lorenzo@kernel.org>
+From: Lorenzo Bianconi <lorenzo@kernel.org>
+Date: Mon, 13 Mar 2023 15:10:56 +0100
+Subject: [PATCH net-next] arm64: dts: mt7986: move ilm in a dedicated node
+
+Since the ilm memory region is not part of the RAM SoC, move ilm in a
+deidicated syscon node.
+This patch helps to keep backward-compatibility with older version of
+uboot codebase where we have a limit of 8 reserved-memory dts child
+nodes.
+
+Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
+---
+ arch/arm64/boot/dts/mediatek/mt7986a.dtsi | 34 +++++++++++------------
+ 1 file changed, 16 insertions(+), 18 deletions(-)
+
+--- a/arch/arm64/boot/dts/mediatek/mt7986a.dtsi
++++ b/arch/arm64/boot/dts/mediatek/mt7986a.dtsi
+@@ -97,16 +97,6 @@
+ no-map;
+ };
+
+- wo_ilm0: wo-ilm@151e0000 {
+- reg = <0 0x151e0000 0 0x8000>;
+- no-map;
+- };
+-
+- wo_ilm1: wo-ilm@151f0000 {
+- reg = <0 0x151f0000 0 0x8000>;
+- no-map;
+- };
+-
+ wo_data: wo-data@4fd80000 {
+ reg = <0 0x4fd80000 0 0x240000>;
+ no-map;
+@@ -526,11 +516,10 @@
+ reg = <0 0x15010000 0 0x1000>;
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>;
+- memory-region = <&wo_emi0>, <&wo_ilm0>, <&wo_dlm0>,
+- <&wo_data>;
+- memory-region-names = "wo-emi", "wo-ilm", "wo-dlm",
+- "wo-data";
++ memory-region = <&wo_emi0>, <&wo_dlm0>, <&wo_data>;
++ memory-region-names = "wo-emi", "wo-dlm", "wo-data";
+ mediatek,wo-ccif = <&wo_ccif0>;
++ mediatek,wo-ilm = <&wo_ilm0>;
+ mediatek,wo-cpuboot = <&wo_cpuboot>;
+ };
+
+@@ -540,11 +529,10 @@
+ reg = <0 0x15011000 0 0x1000>;
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>;
+- memory-region = <&wo_emi1>, <&wo_ilm1>, <&wo_dlm1>,
+- <&wo_data>;
+- memory-region-names = "wo-emi", "wo-ilm", "wo-dlm",
+- "wo-data";
++ memory-region = <&wo_emi1>, <&wo_dlm1>, <&wo_data>;
++ memory-region-names = "wo-emi", "wo-dlm", "wo-data";
+ mediatek,wo-ccif = <&wo_ccif1>;
++ mediatek,wo-ilm = <&wo_ilm1>;
+ mediatek,wo-cpuboot = <&wo_cpuboot>;
+ };
+
+@@ -603,6 +591,16 @@
+ interrupts = <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
++ wo_ilm0: syscon@151e0000 {
++ compatible = "mediatek,mt7986-wo-ilm", "syscon";
++ reg = <0 0x151e0000 0 0x8000>;
++ };
++
++ wo_ilm1: syscon@151f0000 {
++ compatible = "mediatek,mt7986-wo-ilm", "syscon";
++ reg = <0 0x151f0000 0 0x8000>;
++ };
++
+ wo_cpuboot: syscon@15194000 {
+ compatible = "mediatek,mt7986-wo-cpuboot", "syscon";
+ reg = <0 0x15194000 0 0x1000>;
--- /dev/null
+From 9f76be683a8ec498563c294bc1cc279468058302 Mon Sep 17 00:00:00 2001
+Message-Id: <9f76be683a8ec498563c294bc1cc279468058302.1678719283.git.lorenzo@kernel.org>
+From: Lorenzo Bianconi <lorenzo@kernel.org>
+Date: Mon, 13 Mar 2023 15:53:30 +0100
+Subject: [PATCH net-next] arm64: dts: mt7986: move dlm in a dedicated node
+
+Since the dlm memory region is not part of the RAM SoC, move dlm in a
+deidicated syscon node.
+This patch helps to keep backward-compatibility with older version of
+uboot codebase where we have a limit of 8 reserved-memory dts child
+nodes.
+
+Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
+---
+ arch/arm64/boot/dts/mediatek/mt7986a.dtsi | 30 ++++++++++++-----------
+ 1 file changed, 16 insertions(+), 14 deletions(-)
+
+--- a/arch/arm64/boot/dts/mediatek/mt7986a.dtsi
++++ b/arch/arm64/boot/dts/mediatek/mt7986a.dtsi
+@@ -101,16 +101,6 @@
+ reg = <0 0x4fd80000 0 0x240000>;
+ no-map;
+ };
+-
+- wo_dlm0: wo-dlm@151e8000 {
+- reg = <0 0x151e8000 0 0x2000>;
+- no-map;
+- };
+-
+- wo_dlm1: wo-dlm@151f8000 {
+- reg = <0 0x151f8000 0 0x2000>;
+- no-map;
+- };
+ };
+
+ soc {
+@@ -516,10 +506,11 @@
+ reg = <0 0x15010000 0 0x1000>;
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>;
+- memory-region = <&wo_emi0>, <&wo_dlm0>, <&wo_data>;
+- memory-region-names = "wo-emi", "wo-dlm", "wo-data";
++ memory-region = <&wo_emi0>, <&wo_data>;
++ memory-region-names = "wo-emi", "wo-data";
+ mediatek,wo-ccif = <&wo_ccif0>;
+ mediatek,wo-ilm = <&wo_ilm0>;
++ mediatek,wo-dlm = <&wo_dlm0>;
+ mediatek,wo-cpuboot = <&wo_cpuboot>;
+ };
+
+@@ -529,10 +520,11 @@
+ reg = <0 0x15011000 0 0x1000>;
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>;
+- memory-region = <&wo_emi1>, <&wo_dlm1>, <&wo_data>;
+- memory-region-names = "wo-emi", "wo-dlm", "wo-data";
++ memory-region = <&wo_emi1>, <&wo_data>;
++ memory-region-names = "wo-emi", "wo-data";
+ mediatek,wo-ccif = <&wo_ccif1>;
+ mediatek,wo-ilm = <&wo_ilm1>;
++ mediatek,wo-dlm = <&wo_dlm1>;
+ mediatek,wo-cpuboot = <&wo_cpuboot>;
+ };
+
+@@ -601,6 +593,16 @@
+ reg = <0 0x151f0000 0 0x8000>;
+ };
+
++ wo_dlm0: syscon@151e8000 {
++ compatible = "mediatek,mt7986-wo-dlm", "syscon";
++ reg = <0 0x151e8000 0 0x2000>;
++ };
++
++ wo_dlm1: syscon@151f8000 {
++ compatible = "mediatek,mt7986-wo-dlm", "syscon";
++ reg = <0 0x151f8000 0 0x2000>;
++ };
++
+ wo_cpuboot: syscon@15194000 {
+ compatible = "mediatek,mt7986-wo-cpuboot", "syscon";
+ reg = <0 0x15194000 0 0x1000>;
--- /dev/null
+---
+ drivers/leds/Kconfig | 10 ++++++++++
+ drivers/leds/Makefile | 1 +
+ 2 files changed, 11 insertions(+)
+
+--- a/drivers/leds/Kconfig
++++ b/drivers/leds/Kconfig
+@@ -911,6 +911,16 @@ source "drivers/leds/flash/Kconfig"
+ comment "RGB LED drivers"
+ source "drivers/leds/rgb/Kconfig"
+
++config LEDS_SMARTRG_LED
++ tristate "LED support for Adtran SmartRG"
++ depends on LEDS_CLASS && I2C && OF
++ help
++ This option enables support for the Adtran SmartRG platform
++ system LED driver.
++
++ To compile this driver as a module, choose M here: the module
++ will be called leds-smartrg-system.
++
+ comment "LED Triggers"
+ source "drivers/leds/trigger/Kconfig"
+
+--- a/drivers/leds/Makefile
++++ b/drivers/leds/Makefile
+@@ -78,6 +78,7 @@ obj-$(CONFIG_LEDS_POWERNV) += leds-powe
+ obj-$(CONFIG_LEDS_PWM) += leds-pwm.o
+ obj-$(CONFIG_LEDS_REGULATOR) += leds-regulator.o
+ obj-$(CONFIG_LEDS_SC27XX_BLTC) += leds-sc27xx-bltc.o
++obj-$(CONFIG_LEDS_SMARTRG_LED) += leds-smartrg-system.o
+ obj-$(CONFIG_LEDS_ST1202) += leds-st1202.o
+ obj-$(CONFIG_LEDS_SUNFIRE) += leds-sunfire.o
+ obj-$(CONFIG_LEDS_SYSCON) += leds-syscon.o
--- /dev/null
+--- a/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3.dts
++++ b/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3.dts
+@@ -195,6 +195,7 @@
+ phy-mode = "2500base-x";
+ sfp = <&sfp1>;
+ managed = "in-band-status";
++ openwrt,netdev-name = "sfp1";
+ };
+
+ mdio: mdio-bus {
--- /dev/null
+From 30a04cf5b6ffa1249df72ccd98cef05f37890f89 Mon Sep 17 00:00:00 2001
+From: Daniel Golle <daniel@makrotopia.org>
+Date: Thu, 6 Feb 2025 05:07:20 +0000
+Subject: [PATCH] mtd: spinand: add work-around to prevent bootloader wiping
+ mtdparts
+
+ASUS makes use of U-Boot's fdt_fixup_mtdparts() function which applies
+the partitions defined in U-Boot's mtdparts and mtdids environment
+variables to the devicetree passed over to Linux.
+
+The undesired side-effect is that in this way also all additional
+properties and child nodes get wiped, preventing NVMEM cells to be
+defined for MTD partitions or UBI volumes.
+
+To work-around this issue, add an additional compatible string
+'u-boot-dont-touch-spi-nand' which can be used instead of 'spi-nand' in
+case the replacement of the MTD partitions by U-Boot should be skipped
+alltogether.
+
+In practise this is mostly relevant for SPI-NAND which anyway comes only
+with two partitions nowadays: 'Bootloader' and 'UBI_DEV'. Hence this
+work-around is applicable for SPI-NAND only. Similar work-arounds for
+other MTD devices can be created as well should they actually be needed.
+
+Signed-off-by: Daniel Golle <daniel@makrotopia.org>
+---
+ drivers/mtd/nand/spi/core.c | 2 ++
+ 1 file changed, 2 insertions(+)
+
+--- a/drivers/mtd/nand/spi/core.c
++++ b/drivers/mtd/nand/spi/core.c
+@@ -1441,6 +1441,7 @@ static int spinand_remove(struct spi_mem
+
+ static const struct spi_device_id spinand_ids[] = {
+ { .name = "spi-nand" },
++ { .name = "u-boot-dont-touch-spi-nand" },
+ { /* sentinel */ },
+ };
+ MODULE_DEVICE_TABLE(spi, spinand_ids);
+@@ -1448,6 +1449,7 @@ MODULE_DEVICE_TABLE(spi, spinand_ids);
+ #ifdef CONFIG_OF
+ static const struct of_device_id spinand_of_ids[] = {
+ { .compatible = "spi-nand" },
++ { .compatible = "u-boot-dont-touch-spi-nand" },
+ { /* sentinel */ },
+ };
+ MODULE_DEVICE_TABLE(of, spinand_of_ids);
projects / thirdparty / openwrt.git / commitdiff
