]> git.ipfire.org Git - thirdparty/kernel/linux.git/commitdiff
drm/msm/dpu: get rid of DPU_DSC_OUTPUT_CTRL
authorDmitry Baryshkov <dmitry.baryshkov@linaro.org>
Thu, 22 May 2025 19:03:43 +0000 (22:03 +0300)
committerDmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Fri, 4 Jul 2025 13:35:17 +0000 (16:35 +0300)
Continue migration to the MDSS-revision based checks and replace
DPU_DSC_OUTPUT_CTRL feature bit with the core_major_ver >= 5 check.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Patchwork: https://patchwork.freedesktop.org/patch/655404/
Link: https://lore.kernel.org/r/20250522-dpu-drop-features-v5-24-3b2085a07884@oss.qualcomm.com
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_2_sm7150.h
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.c
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.h
drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c

index 8e37c40620b62aacdcb47c7a04bcfce944ab0b4c..5d3b864d28a86fb86fc4576210c9418604afd844 100644 (file)
@@ -259,19 +259,15 @@ static const struct dpu_dsc_cfg sm8150_dsc[] = {
        {
                .name = "dsc_0", .id = DSC_0,
                .base = 0x80000, .len = 0x140,
-               .features = BIT(DPU_DSC_OUTPUT_CTRL),
        }, {
                .name = "dsc_1", .id = DSC_1,
                .base = 0x80400, .len = 0x140,
-               .features = BIT(DPU_DSC_OUTPUT_CTRL),
        }, {
                .name = "dsc_2", .id = DSC_2,
                .base = 0x80800, .len = 0x140,
-               .features = BIT(DPU_DSC_OUTPUT_CTRL),
        }, {
                .name = "dsc_3", .id = DSC_3,
                .base = 0x80c00, .len = 0x140,
-               .features = BIT(DPU_DSC_OUTPUT_CTRL),
        },
 };
 
index a05d2ef8fc9d217898b8c12d4639563b28b4477b..a6e9dfc583f283d752545b3f700c3d509e2a2965 100644 (file)
@@ -259,27 +259,21 @@ static const struct dpu_dsc_cfg sc8180x_dsc[] = {
        {
                .name = "dsc_0", .id = DSC_0,
                .base = 0x80000, .len = 0x140,
-               .features = BIT(DPU_DSC_OUTPUT_CTRL),
        }, {
                .name = "dsc_1", .id = DSC_1,
                .base = 0x80400, .len = 0x140,
-               .features = BIT(DPU_DSC_OUTPUT_CTRL),
        }, {
                .name = "dsc_2", .id = DSC_2,
                .base = 0x80800, .len = 0x140,
-               .features = BIT(DPU_DSC_OUTPUT_CTRL),
        }, {
                .name = "dsc_3", .id = DSC_3,
                .base = 0x80c00, .len = 0x140,
-               .features = BIT(DPU_DSC_OUTPUT_CTRL),
        }, {
                .name = "dsc_4", .id = DSC_4,
                .base = 0x81000, .len = 0x140,
-               .features = BIT(DPU_DSC_OUTPUT_CTRL),
        }, {
                .name = "dsc_5", .id = DSC_5,
                .base = 0x81400, .len = 0x140,
-               .features = BIT(DPU_DSC_OUTPUT_CTRL),
        },
 };
 
index cb0b5687b5239418f50c539447f9cfa56e81fcc6..fe9c9301e3d9d2d3a0a34ab9aed0f307d08c34ca 100644 (file)
@@ -193,11 +193,9 @@ static const struct dpu_dsc_cfg sm7150_dsc[] = {
        {
                .name = "dsc_0", .id = DSC_0,
                .base = 0x80000, .len = 0x140,
-               .features = BIT(DPU_DSC_OUTPUT_CTRL),
        }, {
                .name = "dsc_1", .id = DSC_1,
                .base = 0x80400, .len = 0x140,
-               .features = BIT(DPU_DSC_OUTPUT_CTRL),
        },
 };
 
index 17fa0ef9ac03e4649a218cd837b296211ef4506c..9ceff398fd6f554085440f509b6f8398b4fbf304 100644 (file)
@@ -258,19 +258,15 @@ static const struct dpu_dsc_cfg sm8250_dsc[] = {
        {
                .name = "dsc_0", .id = DSC_0,
                .base = 0x80000, .len = 0x140,
-               .features = BIT(DPU_DSC_OUTPUT_CTRL),
        }, {
                .name = "dsc_1", .id = DSC_1,
                .base = 0x80400, .len = 0x140,
-               .features = BIT(DPU_DSC_OUTPUT_CTRL),
        }, {
                .name = "dsc_2", .id = DSC_2,
                .base = 0x80800, .len = 0x140,
-               .features = BIT(DPU_DSC_OUTPUT_CTRL),
        }, {
                .name = "dsc_3", .id = DSC_3,
                .base = 0x80c00, .len = 0x140,
-               .features = BIT(DPU_DSC_OUTPUT_CTRL),
        },
 };
 
index 06bcaf4d8b0db74c349112af6884f7f3139a7ff8..a46e9e3ff565ba5ef233af76f1c6cebb1d0c318a 100644 (file)
@@ -135,7 +135,6 @@ static const struct dpu_dsc_cfg sm6350_dsc[] = {
        {
                .name = "dsc_0", .id = DSC_0,
                .base = 0x80000, .len = 0x140,
-               .features = BIT(DPU_DSC_OUTPUT_CTRL),
        },
 };
 
index 9c4e8450b67760c880d9bd2528c6a954a0282e08..98190ee7ec7aca6835376b030379a5a3d8b0859b 100644 (file)
@@ -87,7 +87,6 @@ static const struct dpu_dsc_cfg sm6375_dsc[] = {
        {
                .name = "dsc_0", .id = DSC_0,
                .base = 0x80000, .len = 0x140,
-               .features = BIT(DPU_DSC_OUTPUT_CTRL),
        },
 };
 
index 01430ff90ab0988bdaa91b85458dd649aab543b3..41906dadff5a8ef39b2e90f3e80bb699a5cf59b7 100644 (file)
@@ -174,14 +174,11 @@ enum {
 
 /**
  * DSC sub-blocks/features
- * @DPU_DSC_OUTPUT_CTRL       Configure which PINGPONG block gets
- *                            the pixel output from this DSC.
  * @DPU_DSC_NATIVE_42x_EN     Supports NATIVE_422_EN and NATIVE_420_EN encoding
  * @DPU_DSC_MAX
  */
 enum {
-       DPU_DSC_OUTPUT_CTRL = 0x1,
-       DPU_DSC_NATIVE_42x_EN,
+       DPU_DSC_NATIVE_42x_EN = 0x1,
        DPU_DSC_MAX
 };
 
index c7db917afd27e3daf1e8aad2ad671246bf6c8fbf..3a149caa7ff4f20dc7a902033cf29a168268839e 100644 (file)
@@ -186,11 +186,13 @@ static void dpu_hw_dsc_bind_pingpong_blk(
  * @dev:  Corresponding device for devres management
  * @cfg:  DSC catalog entry for which driver object is required
  * @addr: Mapped register io address of MDP
+ * @mdss_ver: dpu core's major and minor versions
  * Return: Error code or allocated dpu_hw_dsc context
  */
 struct dpu_hw_dsc *dpu_hw_dsc_init(struct drm_device *dev,
                                   const struct dpu_dsc_cfg *cfg,
-                                  void __iomem *addr)
+                                  void __iomem *addr,
+                                  const struct dpu_mdss_version *mdss_ver)
 {
        struct dpu_hw_dsc *c;
 
@@ -207,7 +209,7 @@ struct dpu_hw_dsc *dpu_hw_dsc_init(struct drm_device *dev,
        c->ops.dsc_disable = dpu_hw_dsc_disable;
        c->ops.dsc_config = dpu_hw_dsc_config;
        c->ops.dsc_config_thresh = dpu_hw_dsc_config_thresh;
-       if (c->caps->features & BIT(DPU_DSC_OUTPUT_CTRL))
+       if (mdss_ver->core_major_ver >= 5)
                c->ops.dsc_bind_pingpong_blk = dpu_hw_dsc_bind_pingpong_blk;
 
        return c;
index fc171bdeca488f6287cf2ba7362ed330ad55b28f..b7013c9822d23238eb5411a5e284bb072ecc3395 100644 (file)
@@ -64,7 +64,8 @@ struct dpu_hw_dsc {
 
 struct dpu_hw_dsc *dpu_hw_dsc_init(struct drm_device *dev,
                                   const struct dpu_dsc_cfg *cfg,
-                                  void __iomem *addr);
+                                  void __iomem *addr,
+                                  const struct dpu_mdss_version *mdss_ver);
 
 struct dpu_hw_dsc *dpu_hw_dsc_init_1_2(struct drm_device *dev,
                                       const struct dpu_dsc_cfg *cfg,
index c2a659512cb747e1dd5ed9e28534286ff8d67f4f..a2219c4f55a45db894ff18c1fd0a810c1a3cf811 100644 (file)
@@ -171,7 +171,7 @@ int dpu_rm_init(struct drm_device *dev,
                if (cat->mdss_ver->core_major_ver >= 7)
                        hw = dpu_hw_dsc_init_1_2(dev, dsc, mmio);
                else
-                       hw = dpu_hw_dsc_init(dev, dsc, mmio);
+                       hw = dpu_hw_dsc_init(dev, dsc, mmio, cat->mdss_ver);
 
                if (IS_ERR(hw)) {
                        rc = PTR_ERR(hw);