mips: clean-up in hardware detection (Cavium/DSP ASEs)

This change is a clean up in MIPS hardware detection code.
New flag for Cavium Company ID is added, as well as the codes for 34K and
74K processors (MIPS Company ID). The later two represent platforms with DSP
ASEs implemented (Rev 1 and Rev 2 respectively). Macros to detect these two
platforms have been added as well.

Additional macros to extract Company ID out of hwcaps added as well, and
used where possible.

git-svn-id: svn://svn.valgrind.org/vex/trunk@2764

diff --git a/VEX/priv/guest_mips_toIR.c b/VEX/priv/guest_mips_toIR.c
index 7c248edae16d1908d0e9f43b8ba8afb976b7a0be..a92c33a8da25f35bcaa006b028fae246a5450845 100644 (file)
--- a/VEX/priv/guest_mips_toIR.c
+++ b/VEX/priv/guest_mips_toIR.c
@@ -13551,7 +13551,7 @@ static DisResult disInstr_MIPS_WRK ( Bool(*resteerOkFn) (/*opaque */void *,
                putLO(mkWidenFrom32(ty, unop(Iop_64to32, mkexpr(t5)), True));
             } else {
                if ( (1 <= ac) && ( 3 >= ac) ) {
-                  if ((archinfo->hwcaps & VEX_MIPS_ASE_DSP)) {
+                  if (VEX_MIPS_PROC_DSP(archinfo->hwcaps)) {
                      /* If DSP is present -> DSP ASE MADD */
                      UInt retVal = disDSPInstr_MIPS_WRK ( cins );
                      if (0 != retVal ) {
@@ -13614,7 +13614,7 @@ static DisResult disInstr_MIPS_WRK ( Bool(*resteerOkFn) (/*opaque */void *,
             putLO(mkWidenFrom32(ty, unop(Iop_64to32, mkexpr(t5)), True));
          } else {
             if ( (1 <= ac) && ( 3 >= ac) ) {
-               if ((archinfo->hwcaps & VEX_MIPS_ASE_DSP)) {
+               if (VEX_MIPS_PROC_DSP(archinfo->hwcaps)) {
                   /* If DSP is present -> DSP ASE MADDU */
                   UInt retVal = disDSPInstr_MIPS_WRK ( cins );
                   if (0 != retVal ) {
@@ -13676,7 +13676,7 @@ static DisResult disInstr_MIPS_WRK ( Bool(*resteerOkFn) (/*opaque */void *,
             putLO(mkWidenFrom32(ty, unop(Iop_64to32, mkexpr(t5)), True));
          } else {
             if ( (1 <= ac) && ( 3 >= ac) ) {
-               if ((archinfo->hwcaps & VEX_MIPS_ASE_DSP)) {
+               if (VEX_MIPS_PROC_DSP(archinfo->hwcaps)) {
                   /* If DSP is present -> DSP ASE MSUB */
                   UInt retVal = disDSPInstr_MIPS_WRK ( cins );
                   if (0 != retVal ) {
@@ -13742,7 +13742,7 @@ static DisResult disInstr_MIPS_WRK ( Bool(*resteerOkFn) (/*opaque */void *,
             putLO(mkWidenFrom32(ty, unop(Iop_64to32, mkexpr(t5)), True));
          } else {
             if ( (1 <= ac) && ( 3 >= ac) ) {
-               if ((archinfo->hwcaps & VEX_MIPS_ASE_DSP)) {
+               if (VEX_MIPS_PROC_DSP(archinfo->hwcaps)) {
                   /* If DSP is present -> DSP ASE MSUBU */
                   UInt retVal = disDSPInstr_MIPS_WRK ( cins );
                   if (0 != retVal ) {
@@ -14332,7 +14332,7 @@ static DisResult disInstr_MIPS_WRK ( Bool(*resteerOkFn) (/*opaque */void *,
       case 0xA:  /* LX */
       case 0xC:  /* INSV */
       case 0x38: {  /* EXTR.W */
-         if ((archinfo->hwcaps & VEX_MIPS_ASE_DSP)) {
+         if (VEX_MIPS_PROC_DSP(archinfo->hwcaps)) {
             UInt retVal = disDSPInstr_MIPS_WRK ( cins );
             if (0 != retVal ) {
                goto decode_failure_dsp;
@@ -14348,7 +14348,7 @@ static DisResult disInstr_MIPS_WRK ( Bool(*resteerOkFn) (/*opaque */void *,
             case  0xC:  /* SUBU_S.PH */
             case  0xD:  /* ADDU_S.PH */
             case 0x1E: {  /* MULQ_S.PH */
-               if ((archinfo->hwcaps & VEX_MIPS_ASE_DSP2P)) {
+               if (VEX_MIPS_PROC_DSP2(archinfo->hwcaps)) {
                   UInt retVal = disDSPInstr_MIPS_WRK ( cins );
                   if (0 != retVal ) {
                      goto decode_failure_dsp;
@@ -14360,7 +14360,7 @@ static DisResult disInstr_MIPS_WRK ( Bool(*resteerOkFn) (/*opaque */void *,
                break;
             }
             default: {
-               if ((archinfo->hwcaps & VEX_MIPS_ASE_DSP)) {
+               if (VEX_MIPS_PROC_DSP(archinfo->hwcaps)) {
                   UInt retVal = disDSPInstr_MIPS_WRK ( cins );
                   if (0 != retVal ) {
                      goto decode_failure_dsp;
@@ -14382,7 +14382,7 @@ static DisResult disInstr_MIPS_WRK ( Bool(*resteerOkFn) (/*opaque */void *,
             case 0x0D:  /* PRECR.QB.PH */
             case 0x1E:  /* PRECR_SRA.PH.W */
             case 0x1F: {  /* PRECR_SRA_R.PH.W */
-               if ((archinfo->hwcaps & VEX_MIPS_ASE_DSP2P)) {
+               if (VEX_MIPS_PROC_DSP2(archinfo->hwcaps)) {
                   UInt retVal = disDSPInstr_MIPS_WRK ( cins );
                   if (0 != retVal ) {
                      goto decode_failure_dsp;
@@ -14394,7 +14394,7 @@ static DisResult disInstr_MIPS_WRK ( Bool(*resteerOkFn) (/*opaque */void *,
                break;
             }
             default: {
-               if ((archinfo->hwcaps & VEX_MIPS_ASE_DSP)) {
+               if (VEX_MIPS_PROC_DSP(archinfo->hwcaps)) {
                   UInt retVal = disDSPInstr_MIPS_WRK ( cins );
                   if (0 != retVal ) {
                      goto decode_failure_dsp;
@@ -14411,7 +14411,7 @@ static DisResult disInstr_MIPS_WRK ( Bool(*resteerOkFn) (/*opaque */void *,
       case 0x12: {  /* ABSQ_S.PH */
          switch(sa){
             case 0x1: {  /* ABSQ_S.QB */
-               if ((archinfo->hwcaps & VEX_MIPS_ASE_DSP2P)) {
+               if (VEX_MIPS_PROC_DSP2(archinfo->hwcaps)) {
                   UInt retVal = disDSPInstr_MIPS_WRK ( cins );
                   if (0 != retVal ) {
                      goto decode_failure_dsp;
@@ -14423,7 +14423,7 @@ static DisResult disInstr_MIPS_WRK ( Bool(*resteerOkFn) (/*opaque */void *,
                break;
             }
             default: {
-               if ((archinfo->hwcaps & VEX_MIPS_ASE_DSP)) {
+               if (VEX_MIPS_PROC_DSP(archinfo->hwcaps)) {
                   UInt retVal = disDSPInstr_MIPS_WRK ( cins );
                   if (0 != retVal ) {
                      goto decode_failure_dsp;
@@ -14445,7 +14445,7 @@ static DisResult disInstr_MIPS_WRK ( Bool(*resteerOkFn) (/*opaque */void *,
             case 0x07:  /* SHRAV_R.QB */
             case 0x19:  /* SHLR.PH */
             case 0x1B: {  /* SHLRV.PH */
-               if ((archinfo->hwcaps & VEX_MIPS_ASE_DSP2P)) {
+               if (VEX_MIPS_PROC_DSP2(archinfo->hwcaps)) {
                   UInt retVal = disDSPInstr_MIPS_WRK ( cins );
                   if (0 != retVal ) {
                      goto decode_failure_dsp;
@@ -14457,7 +14457,7 @@ static DisResult disInstr_MIPS_WRK ( Bool(*resteerOkFn) (/*opaque */void *,
                break;
             }
             default: {
-               if ((archinfo->hwcaps & VEX_MIPS_ASE_DSP)) {
+               if (VEX_MIPS_PROC_DSP(archinfo->hwcaps)) {
                   UInt retVal = disDSPInstr_MIPS_WRK ( cins );
                   if (0 != retVal ) {
                      goto decode_failure_dsp;
@@ -14482,7 +14482,7 @@ static DisResult disInstr_MIPS_WRK ( Bool(*resteerOkFn) (/*opaque */void *,
             case 0x1B:  /* DPSQX_SA.W.PH */
             case  0x9:  /* DPSX.W.PH */
             case  0x2: {  /* MULSA.W.PH */
-               if ((archinfo->hwcaps & VEX_MIPS_ASE_DSP2P)) {
+               if (VEX_MIPS_PROC_DSP2(archinfo->hwcaps)) {
                   UInt retVal = disDSPInstr_MIPS_WRK ( cins );
                   if (0 != retVal ) {
                      goto decode_failure_dsp;
@@ -14494,7 +14494,7 @@ static DisResult disInstr_MIPS_WRK ( Bool(*resteerOkFn) (/*opaque */void *,
                break;
             }
             default: {
-               if ((archinfo->hwcaps & VEX_MIPS_ASE_DSP)) {
+               if (VEX_MIPS_PROC_DSP(archinfo->hwcaps)) {
                   UInt retVal = disDSPInstr_MIPS_WRK ( cins );
                   if (0 != retVal ) {
                      goto decode_failure_dsp;
@@ -14510,7 +14510,7 @@ static DisResult disInstr_MIPS_WRK ( Bool(*resteerOkFn) (/*opaque */void *,
       }
       case 0x18:  /* ADDUH.QB/MUL.PH */
       case 0x31: {  /* APPEND */
-         if ((archinfo->hwcaps & VEX_MIPS_ASE_DSP2P)) {
+         if (VEX_MIPS_PROC_DSP2(archinfo->hwcaps)) {
             UInt retVal = disDSPInstr_MIPS_WRK ( cins );
             if (0 != retVal ) {
                goto decode_failure_dsp;
@@ -14527,7 +14527,8 @@ static DisResult disInstr_MIPS_WRK ( Bool(*resteerOkFn) (/*opaque */void *,
       break;  /* Special3 */
 
    case 0x3B:
-      if (0x3B == function && (archinfo->hwcaps & VEX_PRID_COMP_BROADCOM)) {
+      if (0x3B == function &&
+          (VEX_MIPS_COMP_ID(archinfo->hwcaps) == VEX_PRID_COMP_BROADCOM)) {
          /*RDHWR*/
          DIP("rdhwr r%d, r%d", rt, rd);
          if (rd == 29) {
@@ -14634,7 +14635,7 @@ static DisResult disInstr_MIPS_WRK ( Bool(*resteerOkFn) (/*opaque */void *,
 
       case 0x18:  {  /* MULT */
          if ( (1 <= ac) && ( 3 >= ac) ) {
-            if ((archinfo->hwcaps & VEX_MIPS_ASE_DSP)) {
+            if (VEX_MIPS_PROC_DSP(archinfo->hwcaps)) {
                /* If DSP is present -> DSP ASE MULT */
                UInt retVal = disDSPInstr_MIPS_WRK ( cins );
                if (0 != retVal ) {
@@ -14658,7 +14659,7 @@ static DisResult disInstr_MIPS_WRK ( Bool(*resteerOkFn) (/*opaque */void *,
       }
       case 0x19:  {  /* MULTU */
          if ( (1 <= ac) && ( 3 >= ac) ) {
-            if ((archinfo->hwcaps & VEX_MIPS_ASE_DSP)) {
+            if (VEX_MIPS_PROC_DSP(archinfo->hwcaps)) {
                /* If DSP is present -> DSP ASE MULTU */
                UInt retVal = disDSPInstr_MIPS_WRK ( cins );
                if (0 != retVal ) {
@@ -14810,7 +14811,7 @@ static DisResult disInstr_MIPS_WRK ( Bool(*resteerOkFn) (/*opaque */void *,
          break;
 
       case 0x10: {  /* MFHI */
-         if ((archinfo->hwcaps & VEX_MIPS_ASE_DSP)) {
+         if (VEX_MIPS_PROC_DSP(archinfo->hwcaps)) {
             /* If DSP is present -> DSP ASE MFHI */
             UInt retVal = disDSPInstr_MIPS_WRK ( cins );
             if (0 != retVal ) {
@@ -14825,7 +14826,7 @@ static DisResult disInstr_MIPS_WRK ( Bool(*resteerOkFn) (/*opaque */void *,
       }
 
       case 0x11:  {  /* MTHI */
-         if ((archinfo->hwcaps & VEX_MIPS_ASE_DSP)) {
+         if (VEX_MIPS_PROC_DSP(archinfo->hwcaps)) {
             /* If DSP is present -> DSP ASE MTHI */
             UInt retVal = disDSPInstr_MIPS_WRK ( cins );
             if (0 != retVal ) {
@@ -14840,7 +14841,7 @@ static DisResult disInstr_MIPS_WRK ( Bool(*resteerOkFn) (/*opaque */void *,
       }
 
       case 0x12:  {  /* MFLO */
-         if ((archinfo->hwcaps & VEX_MIPS_ASE_DSP)) {
+         if (VEX_MIPS_PROC_DSP(archinfo->hwcaps)) {
             /* If DSP is present -> DSP ASE MFLO */
             UInt retVal = disDSPInstr_MIPS_WRK ( cins );
             if (0 != retVal ) {
@@ -14855,7 +14856,7 @@ static DisResult disInstr_MIPS_WRK ( Bool(*resteerOkFn) (/*opaque */void *,
       }
 
       case 0x13:  {  /* MTLO */
-         if ((archinfo->hwcaps & VEX_MIPS_ASE_DSP)) {
+         if (VEX_MIPS_PROC_DSP(archinfo->hwcaps)) {
             /* If DSP is present -> DSP ASE MTLO */
             UInt retVal = disDSPInstr_MIPS_WRK ( cins );
             if (0 != retVal ) {

diff --git a/VEX/priv/main_main.c b/VEX/priv/main_main.c
index ceb83769511174bbfc1f20d7b266b7c1107f7814..0f74429dd2c0f3f7f0e2deb33846614a464a912e 100644 (file)
--- a/VEX/priv/main_main.c
+++ b/VEX/priv/main_main.c
@@ -1428,28 +1428,33 @@ static const HChar* show_hwcaps_s390x ( UInt hwcaps )
 static const HChar* show_hwcaps_mips32 ( UInt hwcaps )
 {
    /* MIPS baseline. */
-   if (hwcaps & VEX_PRID_COMP_MIPS == VEX_PRID_COMP_MIPS) {
+   if (VEX_MIPS_COMP_ID(hwcaps) == VEX_PRID_COMP_MIPS) {
       /* MIPS baseline with dspr2. */
-      if (hwcaps & VEX_MIPS_ASE_DSP2P == VEX_MIPS_ASE_DSP2P) {
+      if (VEX_MIPS_PROC_DSP2(hwcaps)) {
          return "MIPS-baseline-dspr2";
       }
       /* MIPS baseline with dsp. */
-      if (hwcaps & VEX_MIPS_ASE_DSP == VEX_MIPS_ASE_DSP) {
+      if (VEX_MIPS_PROC_DSP(hwcaps)) {
          return "MIPS-baseline-dsp";
       }
       return "MIPS-baseline";
    }
 
    /* Broadcom baseline. */
-   if (hwcaps & VEX_PRID_COMP_BROADCOM == VEX_PRID_COMP_BROADCOM) {
+   if (VEX_MIPS_COMP_ID(hwcaps) == VEX_PRID_COMP_BROADCOM) {
       return "Broadcom-baseline";
    }
 
    /* Netlogic baseline. */
-   if (hwcaps & VEX_PRID_COMP_NETLOGIC == VEX_PRID_COMP_NETLOGIC) {
+   if (VEX_MIPS_COMP_ID(hwcaps) == VEX_PRID_COMP_NETLOGIC) {
       return "Netlogic-baseline";
    }
 
+   /* Cavium baseline. */
+   if (VEX_MIPS_COMP_ID(hwcaps) == VEX_PRID_COMP_CAVIUM) {
+      return "Cavium-baseline";
+   }
+
    return NULL;
 }
 

diff --git a/VEX/pub/libvex.h b/VEX/pub/libvex.h
index c8b5892078b90325510a855d58f387b9130546e6..56dd61ab0f491a3ee2ebf495b37fc1d34388c9b0 100644 (file)
--- a/VEX/pub/libvex.h
+++ b/VEX/pub/libvex.h
@@ -187,11 +187,26 @@ typedef
 
 #define VEX_PRID_COMP_MIPS      0x00010000
 #define VEX_PRID_COMP_BROADCOM  0x00020000
-#define VEX_PRID_COMP_NETLOGIC  0x000c0000
+#define VEX_PRID_COMP_NETLOGIC  0x000C0000
+#define VEX_PRID_COMP_CAVIUM    0x000D0000
 
-/* MIPS additional capabilities */
-#define VEX_MIPS_ASE_DSP    0x00000010  /* Signal Processing ASE */
-#define VEX_MIPS_ASE_DSP2P  0x00000040  /* Signal Processing ASE Rev 2 */
+/*
+ * These are the PRID's for when 23:16 == PRID_COMP_MIPS
+ */
+#define VEX_PRID_IMP_34K        0x9500
+#define VEX_PRID_IMP_74K        0x9700
+
+/* Get MIPS Company ID from HWCAPS */
+#define VEX_MIPS_COMP_ID(x) ((x) & 0x00FF0000)
+/* Get MIPS Processor ID from HWCAPS */
+#define VEX_MIPS_PROC_ID(x) ((x) & 0x0000FFFF)
+/* Check if the processor supports DSP ASE Rev 2. */
+#define VEX_MIPS_PROC_DSP2(x) ((VEX_MIPS_COMP_ID(x) == VEX_PRID_COMP_MIPS) && \
+                               (VEX_MIPS_PROC_ID(x) == VEX_PRID_IMP_74K))
+/* Check if the processor supports DSP ASE Rev 1. */
+#define VEX_MIPS_PROC_DSP(x)  (VEX_MIPS_PROC_DSP2(x) || \
+                               ((VEX_MIPS_COMP_ID(x) == VEX_PRID_COMP_MIPS) && \
+                               (VEX_MIPS_PROC_ID(x) == VEX_PRID_IMP_34K)))
 
 /* These return statically allocated strings. */