.class_init = vtd_class_init,
};
+static int vtd_attrs_to_index(IOMMUMemoryRegion *iommu_mr, MemTxAttrs attrs)
+{
+ return attrs.address_type == PCI_AT_TRANSLATED ?
+ VTD_IDX_TRANSLATED : VTD_IDX_UNTRANSLATED;
+}
+
+static int vtd_num_indexes(IOMMUMemoryRegion *iommu)
+{
+ return VTD_IDX_COUNT;
+}
+
static void vtd_iommu_memory_region_class_init(ObjectClass *klass,
const void *data)
{
imrc->translate = vtd_iommu_translate;
imrc->notify_flag_changed = vtd_iommu_notify_flag_changed;
imrc->replay = vtd_iommu_replay;
+ imrc->attrs_to_index = vtd_attrs_to_index;
+ imrc->num_indexes = vtd_num_indexes;
}
static const TypeInfo vtd_iommu_memory_region_info = {
/* Bits to decide the offset for each level */
#define VTD_LEVEL_BITS 9
+/* IOMMU Index */
+typedef enum VTDIOMMUIndex {
+ VTD_IDX_UNTRANSLATED = 0, /* Default */
+ VTD_IDX_TRANSLATED = 1,
+ VTD_IDX_COUNT = 2, /* Number of supported indexes */
+} VTDIOMMUIndex;
+
typedef struct VTDHostIOMMUDevice {
IntelIOMMUState *iommu_state;
PCIBus *bus;