Each board wires one reset line that resets the AQR113C PHYs as a
group: GPIO 71 on SDG-8733/SDG-8734 and GPIO 62 on SDG-8733A.
Describe that line as the MDIO bus reset with the same assert and
deassert times.
Drop the per-PHY reset-gpios. On SDG-8733 the second AQR113C
claimed GPIO 62, which is not connected on that board.
Signed-off-by: Chad Monroe <chad@monroe.io>
Link: https://github.com/openwrt/openwrt/pull/24352
Signed-off-by: Jonas Jelonek <jelonek.jonas@gmail.com>
compatible = "ethernet-phy-ieee802.3-c45";
reg = <0>;
- reset-gpios = <&pio 62 GPIO_ACTIVE_LOW>;
- reset-assert-us = <100000>;
- reset-deassert-us = <1000000>;
-
leds {
#address-cells = <1>;
#size-cells = <0>;
};
&mdio_bus {
+ reset-gpios = <&pio 71 GPIO_ACTIVE_LOW>;
+ reset-delay-us = <100000>;
+ reset-post-delay-us = <1000000>;
+
phy8: ethernet-phy@8 {
/* AQR113C */
compatible = "ethernet-phy-ieee802.3-c45";
reg = <8>;
- reset-gpios = <&pio 71 GPIO_ACTIVE_LOW>;
- reset-assert-us = <100000>;
- reset-deassert-us = <1000000>;
-
leds {
#address-cells = <1>;
#size-cells = <0>;
};
&mdio_bus {
+ reset-gpios = <&pio 62 GPIO_ACTIVE_LOW>;
+ reset-delay-us = <100000>;
+ reset-post-delay-us = <1000000>;
+
phy8: ethernet-phy@8 {
/* AQR113C */
compatible = "ethernet-phy-ieee802.3-c45";
reg = <8>;
- reset-gpios = <&pio 62 GPIO_ACTIVE_LOW>;
- reset-assert-us = <100000>;
- reset-deassert-us = <1000000>;
-
marvell,mdi-cfg-order = <0>;
leds {