#include "phy-qcom-qmp-pcs-misc-v3.h"
#define PHY_INIT_COMPLETE_TIMEOUT 10000
+#define SW_PORTSELECT_VAL BIT(0)
+#define SW_PORTSELECT_MUX BIT(1)
/* set of registers with offsets different per-PHY */
enum qphy_reg_layout {
{
struct qmp_usbc *qmp = phy_get_drvdata(phy);
const struct qmp_phy_cfg *cfg = qmp->cfg;
- void __iomem *pcs = qmp->pcs;
- u32 val = 0;
int ret;
ret = regulator_bulk_enable(cfg->num_vregs, qmp->vregs);
if (ret)
goto err_assert_reset;
- qphy_setbits(pcs, cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL], SW_PWRDN);
-
-#define SW_PORTSELECT_VAL BIT(0)
-#define SW_PORTSELECT_MUX BIT(1)
- /* Use software based port select and switch on typec orientation */
- val = SW_PORTSELECT_MUX;
- if (qmp->orientation == TYPEC_ORIENTATION_REVERSE)
- val |= SW_PORTSELECT_VAL;
- writel(val, qmp->pcs_misc);
-
return 0;
err_assert_reset:
unsigned int val;
int ret;
+ qphy_setbits(qmp->pcs, cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL], SW_PWRDN);
+
+ /* Use software based port select and switch on typec orientation */
+ val = SW_PORTSELECT_MUX;
+ if (qmp->orientation == TYPEC_ORIENTATION_REVERSE)
+ val |= SW_PORTSELECT_VAL;
+ writel(val, qmp->pcs_misc);
+
qmp_configure(qmp->dev, qmp->serdes, cfg->serdes_tbl,
cfg->serdes_tbl_num);