drm/i915/irq: rename irq_mask to gen2_imr_mask

Rename the struct drm_i915_private irq_mask member to gen2_imr_mask to
reflect its usage more accurately.

Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://lore.kernel.org/r/2c193663cd3ae524d8159b4216e45462017042fa.1758198300.git.jani.nikula@intel.com
Signed-off-by: Jani Nikula <jani.nikula@intel.com>

diff --git a/drivers/gpu/drm/i915/gt/gen2_engine_cs.c b/drivers/gpu/drm/i915/gt/gen2_engine_cs.c
index 8116fd5987e2b77eff1afdc874f500cdfbc8eb57..8c01fb6d4e7b46b60fb43aff8eca14dd431c7d26 100644 (file)
--- a/drivers/gpu/drm/i915/gt/gen2_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/gen2_engine_cs.c
@@ -292,15 +292,15 @@ int gen4_emit_bb_start(struct i915_request *rq,
 
 void gen2_irq_enable(struct intel_engine_cs *engine)
 {
-       engine->i915->irq_mask &= ~engine->irq_enable_mask;
-       intel_uncore_write(engine->uncore, GEN2_IMR, engine->i915->irq_mask);
+       engine->i915->gen2_imr_mask &= ~engine->irq_enable_mask;
+       intel_uncore_write(engine->uncore, GEN2_IMR, engine->i915->gen2_imr_mask);
        intel_uncore_posting_read_fw(engine->uncore, GEN2_IMR);
 }
 
 void gen2_irq_disable(struct intel_engine_cs *engine)
 {
-       engine->i915->irq_mask |= engine->irq_enable_mask;
-       intel_uncore_write(engine->uncore, GEN2_IMR, engine->i915->irq_mask);
+       engine->i915->gen2_imr_mask |= engine->irq_enable_mask;
+       intel_uncore_write(engine->uncore, GEN2_IMR, engine->i915->gen2_imr_mask);
 }
 
 void gen5_irq_enable(struct intel_engine_cs *engine)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 37970d8db25550c5ca38ebfed56d667886ebdfba..03e497d2081e45474e9f1574d3327711a0b3e87c 100644 (file)
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -234,8 +234,8 @@ struct drm_i915_private {
        /* Sideband mailbox protection */
        struct mutex sb_lock;
 
-       /** Cached value of IMR to avoid reads in updating the bitfield */
-       u32 irq_mask;
+       /* Cached value of gen 2-4 IMR to avoid reads in updating the bitfield */
+       u32 gen2_imr_mask;
 
        bool preserve_bios_swizzle;
 

diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index e5fdfd51b549ecac9aa7d88431f1f5e771b01a17..ab65402bc6bf07132535967e4a11c9524d32321e 100644 (file)
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -897,7 +897,7 @@ static void i915_irq_reset(struct drm_i915_private *dev_priv)
 
        gen2_error_reset(uncore, GEN2_ERROR_REGS);
        gen2_irq_reset(uncore, GEN2_IRQ_REGS);
-       dev_priv->irq_mask = ~0u;
+       dev_priv->gen2_imr_mask = ~0u;
 }
 
 static void i915_irq_postinstall(struct drm_i915_private *dev_priv)
@@ -908,7 +908,7 @@ static void i915_irq_postinstall(struct drm_i915_private *dev_priv)
 
        gen2_error_init(uncore, GEN2_ERROR_REGS, ~i9xx_error_mask(dev_priv));
 
-       dev_priv->irq_mask =
+       dev_priv->gen2_imr_mask =
                ~(I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
                  I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
                  I915_MASTER_ERROR_INTERRUPT);
@@ -920,16 +920,16 @@ static void i915_irq_postinstall(struct drm_i915_private *dev_priv)
                I915_USER_INTERRUPT;
 
        if (DISPLAY_VER(display) >= 3) {
-               dev_priv->irq_mask &= ~I915_ASLE_INTERRUPT;
+               dev_priv->gen2_imr_mask &= ~I915_ASLE_INTERRUPT;
                enable_mask |= I915_ASLE_INTERRUPT;
        }
 
        if (HAS_HOTPLUG(display)) {
-               dev_priv->irq_mask &= ~I915_DISPLAY_PORT_INTERRUPT;
+               dev_priv->gen2_imr_mask &= ~I915_DISPLAY_PORT_INTERRUPT;
                enable_mask |= I915_DISPLAY_PORT_INTERRUPT;
        }
 
-       gen2_irq_init(uncore, GEN2_IRQ_REGS, dev_priv->irq_mask, enable_mask);
+       gen2_irq_init(uncore, GEN2_IRQ_REGS, dev_priv->gen2_imr_mask, enable_mask);
 
        i915_display_irq_postinstall(display);
 }
@@ -999,7 +999,7 @@ static void i965_irq_reset(struct drm_i915_private *dev_priv)
 
        gen2_error_reset(uncore, GEN2_ERROR_REGS);
        gen2_irq_reset(uncore, GEN2_IRQ_REGS);
-       dev_priv->irq_mask = ~0u;
+       dev_priv->gen2_imr_mask = ~0u;
 }
 
 static u32 i965_error_mask(struct drm_i915_private *i915)
@@ -1029,7 +1029,7 @@ static void i965_irq_postinstall(struct drm_i915_private *dev_priv)
 
        gen2_error_init(uncore, GEN2_ERROR_REGS, ~i965_error_mask(dev_priv));
 
-       dev_priv->irq_mask =
+       dev_priv->gen2_imr_mask =
                ~(I915_ASLE_INTERRUPT |
                  I915_DISPLAY_PORT_INTERRUPT |
                  I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
@@ -1047,7 +1047,7 @@ static void i965_irq_postinstall(struct drm_i915_private *dev_priv)
        if (IS_G4X(dev_priv))
                enable_mask |= I915_BSD_USER_INTERRUPT;
 
-       gen2_irq_init(uncore, GEN2_IRQ_REGS, dev_priv->irq_mask, enable_mask);
+       gen2_irq_init(uncore, GEN2_IRQ_REGS, dev_priv->gen2_imr_mask, enable_mask);
 
        i965_display_irq_postinstall(display);
 }