Add documentation for the Last Level Cache Controller (LLCC) bindings
to support Hawi SoC where the System Cache Table (SCT) is programmed
by firmware outside of Linux.
Introduce a property that specifies the base address of the shared
memory region from which the driver should read SCT descriptors
provided by firmware.
Signed-off-by: Francisco Munoz Ruiz <francisco.ruiz@oss.qualcomm.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20260407-external_llcc_changes2set-v2-1-b5017ce2020b@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
compatible:
enum:
- qcom,glymur-llcc
+ - qcom,hawi-llcc
- qcom,ipq5424-llcc
- qcom,kaanapali-llcc
- qcom,qcs615-llcc
interrupts:
maxItems: 1
+ memory-region:
+ maxItems: 1
+ description: handle to a reserved-memory node used for firmware-populated
+ SLC/SCT shared memory.
+
nvmem-cells:
items:
- description: Reference to an nvmem node for multi channel DDR
contains:
enum:
- qcom,kaanapali-llcc
+ - qcom,hawi-llcc
- qcom,sm8450-llcc
- qcom,sm8550-llcc
- qcom,sm8650-llcc
- const: llcc3_base
- const: llcc_broadcast_base
- const: llcc_broadcast_and_base
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - qcom,hawi-llcc
+ then:
+ required:
+ - memory-region
+ else:
+ properties:
+ memory-region: false
additionalProperties: false