arm64: dts: imx95-19x19-evk: add flexspi and child node

Add flexspi and child flash node.

Signed-off-by: Frank Li <Frank.Li@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>

diff --git a/arch/arm64/boot/dts/freescale/imx95-19x19-evk.dts b/arch/arm64/boot/dts/freescale/imx95-19x19-evk.dts
index 660e623f4f96470fb04c807af42145664184df10..2b820a961c173476b5744a064a053cadf825ecc4 100644 (file)
--- a/arch/arm64/boot/dts/freescale/imx95-19x19-evk.dts
+++ b/arch/arm64/boot/dts/freescale/imx95-19x19-evk.dts
@@ -163,6 +163,25 @@
        };
 };
 
+&flexspi1 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_flexspi1>;
+       status = "okay";
+
+       flash@0 {
+               compatible = "jedec,spi-nor";
+               reg = <0>;
+               pinctrl-names = "default";
+               pinctrl-0 = <&pinctrl_flexspi1_reset>;
+               reset-gpios = <&gpio5 11 GPIO_ACTIVE_LOW>;
+               #address-cells = <1>;
+               #size-cells = <1>;
+               spi-max-frequency = <200000000>;
+               spi-tx-bus-width = <8>;
+               spi-rx-bus-width = <8>;
+       };
+};
+
 &lpi2c4 {
        clock-frequency = <400000>;
        pinctrl-names = "default";
@@ -336,6 +355,28 @@
 };
 
 &scmi_iomuxc {
+       pinctrl_flexspi1: flexspi1grp {
+               fsl,pins = <
+                       IMX95_PAD_XSPI1_SS0_B__FLEXSPI1_A_SS0_B                 0x3fe
+                       IMX95_PAD_XSPI1_SCLK__FLEXSPI1_A_SCLK                   0x3fe
+                       IMX95_PAD_XSPI1_DQS__FLEXSPI1_A_DQS                     0x3fe
+                       IMX95_PAD_XSPI1_DATA0__FLEXSPI1_A_DATA_BIT0             0x3fe
+                       IMX95_PAD_XSPI1_DATA1__FLEXSPI1_A_DATA_BIT1             0x3fe
+                       IMX95_PAD_XSPI1_DATA2__FLEXSPI1_A_DATA_BIT2             0x3fe
+                       IMX95_PAD_XSPI1_DATA3__FLEXSPI1_A_DATA_BIT3             0x3fe
+                       IMX95_PAD_XSPI1_DATA4__FLEXSPI1_A_DATA_BIT4             0x3fe
+                       IMX95_PAD_XSPI1_DATA5__FLEXSPI1_A_DATA_BIT5             0x3fe
+                       IMX95_PAD_XSPI1_DATA6__FLEXSPI1_A_DATA_BIT6             0x3fe
+                       IMX95_PAD_XSPI1_DATA7__FLEXSPI1_A_DATA_BIT7             0x3fe
+               >;
+       };
+
+       pinctrl_flexspi1_reset: flexspi1-reset-grp {
+               fsl,pins = <
+                       IMX95_PAD_XSPI1_SS1_B__GPIO5_IO_BIT11                   0x3fe
+               >;
+       };
+
        pinctrl_hp: hpgrp {
                fsl,pins = <
                        IMX95_PAD_GPIO_IO11__GPIO2_IO_BIT11             0x31e