Fix cfa offset for saved registers in PPC sqrt implementations.

(cherry picked from commit 3f241d758415e050269ebd9b3b909f3d007f89e5)

diff --git a/ChangeLog b/ChangeLog
index 8d2284aff48de52fec3d7831908ebae2fa136441..3620d6252b4ead0e4ea9da1dcf635e866aaaa3b7 100644 (file)
--- a/ChangeLog
+++ b/ChangeLog
@@ -1,3 +1,11 @@
+2009-06-24  Andreas Schwab  <aschwab@redhat.com>
+
+       * sysdeps/powerpc/powerpc32/power4/fpu/w_sqrtf.S: Fix cfa offset
+       for saved registers.
+       * sysdeps/powerpc/powerpc32/power4/fpu/w_sqrt.S: Likewise.
+       * sysdeps/powerpc/powerpc32/power5/fpu/w_sqrtf.S: Likewise.
+       * sysdeps/powerpc/powerpc32/power5/fpu/w_sqrt.S: Likewise.
+
 2009-06-23  Andreas Schwab  <aschwab@redhat.com>
 
        * time/tzfile.c (__tzfile_read): Don't use an empty TZ string.

diff --git a/sysdeps/powerpc/powerpc32/power4/fpu/w_sqrt.S b/sysdeps/powerpc/powerpc32/power4/fpu/w_sqrt.S
index 6aef4e301baf003a6010fbff30b384ab2e8dc3fa..95a0b3915d43008fbe3fe3c37ed3fd727162997b 100644 (file)
--- a/sysdeps/powerpc/powerpc32/power4/fpu/w_sqrt.S
+++ b/sysdeps/powerpc/powerpc32/power4/fpu/w_sqrt.S
@@ -60,8 +60,8 @@ EALIGN (__sqrt, 5, 0)
        fmr     fp12,fp2
        stw     r0,20(r1)
        stw     r30,8(r1)
-       cfi_offset(lr,20)
-       cfi_offset(r30,8)
+       cfi_offset(lr,20-16)
+       cfi_offset(r30,8-16)
 #ifdef SHARED
 # ifdef HAVE_ASM_PPC_REL16
        bcl     20,31,.LCF1

diff --git a/sysdeps/powerpc/powerpc32/power4/fpu/w_sqrtf.S b/sysdeps/powerpc/powerpc32/power4/fpu/w_sqrtf.S
index e5b8b9d5654035909a1073be3c88b74104164f0e..c31555194b2dc7e40140437964f7760a7aa36a6b 100644 (file)
--- a/sysdeps/powerpc/powerpc32/power4/fpu/w_sqrtf.S
+++ b/sysdeps/powerpc/powerpc32/power4/fpu/w_sqrtf.S
@@ -60,8 +60,8 @@ EALIGN (__sqrtf, 5, 0)
        fmr     fp12,fp2
        stw     r0,20(r1)
        stw     r30,8(r1)
-       cfi_offset(lr,20)
-       cfi_offset(r30,8)
+       cfi_offset(lr,20-16)
+       cfi_offset(r30,8-16)
 #ifdef SHARED
 # ifdef HAVE_ASM_PPC_REL16
        bcl     20,31,.LCF1

diff --git a/sysdeps/powerpc/powerpc32/power5/fpu/w_sqrt.S b/sysdeps/powerpc/powerpc32/power5/fpu/w_sqrt.S
index 925930bf779a13e94429fe8cbdafb1ad52b77336..105b5912a1b2ec4d84bf670a9c9194026ea9ec0a 100644 (file)
--- a/sysdeps/powerpc/powerpc32/power5/fpu/w_sqrt.S
+++ b/sysdeps/powerpc/powerpc32/power5/fpu/w_sqrt.S
@@ -60,8 +60,8 @@ EALIGN (__sqrt, 5, 0)
        fmr     fp12,fp2
        stw     r0,20(r1)
        stw     r30,8(r1)
-       cfi_offset(lr,20)
-       cfi_offset(r30,8)
+       cfi_offset(lr,20-16)
+       cfi_offset(r30,8-16)
 #ifdef SHARED
 # ifdef HAVE_ASM_PPC_REL16
        bcl     20,31,.LCF1

diff --git a/sysdeps/powerpc/powerpc32/power5/fpu/w_sqrtf.S b/sysdeps/powerpc/powerpc32/power5/fpu/w_sqrtf.S
index 891e69c9c0244c4e3808709e8f099e150ed1b81b..14bc0a2ceb5c9fb4500de35af3c555ab8aa5d4bf 100644 (file)
--- a/sysdeps/powerpc/powerpc32/power5/fpu/w_sqrtf.S
+++ b/sysdeps/powerpc/powerpc32/power5/fpu/w_sqrtf.S
@@ -60,8 +60,8 @@ EALIGN (__sqrtf, 5, 0)
        fmr     fp12,fp2
        stw     r0,20(r1)
        stw     r30,8(r1)
-       cfi_offset(lr,20)
-       cfi_offset(r30,8)
+       cfi_offset(lr,20-16)
+       cfi_offset(r30,8-16)
 #ifdef SHARED
 # ifdef HAVE_ASM_PPC_REL16
        bcl     20,31,.LCF1