- LDAPR, LDAR, LDXP, LDAXP, LDXR, LDAXR, LDCT, LDNP, LDP.
- STXR, STLXR, STLR, STXP, STLXP, STCT, STNP, STP.
gas/ChangeLog:
2020-10-20 Siddhesh Poyarekar <siddesh.poyarekar@arm.com>
* config/tc-aarch64.c (parse_operands, fix_insn): Add
A64C_ADDR_SIMM7.
* testsuite/gas/aarch64/morello_ldst-c64.d: Add tests.
* testsuite/gas/aarch64/morello_ldst.d: Likewise.
* testsuite/gas/aarch64/morello_ldst.s: Likewise.
include/ChangeLog:
2020-10-20 Siddhesh Poyarekar <siddesh.poyarekar@arm.com>
* opcode/aarch64.h (aarch64_opnd): Add A64C_ADDR_SIMM7.
opcodes/ChangeLog:
2020-10-20 Siddhesh Poyarekar <siddesh.poyarekar@arm.com>
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc-2.c: Regenerate.
* aarch64-opc.c (fields): Add a64c_index2.
(operand_general_constraint_met_p, aarch64_print_operand): Add
A64C_ADDR_SIMM7.
* aarch64-opc.h (aarch64_field_kind): Add FLD_a64c_index2.
* aarch64-tbl.h (QL2_A64C_CA_ADDR, QL2_A64C_X_ADDR,
QL3_A64C_W_CA_ADDR, QL4_A64C_W_CA_CA_ADDR): New macros.
(aarch64_opcode_table): New instructions.
(AARCH64_OPERANDS): New operands.
+2020-10-20 Siddhesh Poyarekar <siddesh.poyarekar@arm.com>
+
+ * config/tc-aarch64.c (parse_operands, fix_insn): Add
+ A64C_ADDR_SIMM7.
+ * testsuite/gas/aarch64/morello_ldst-c64.d: Add tests.
+ * testsuite/gas/aarch64/morello_ldst.d: Likewise.
+ * testsuite/gas/aarch64/morello_ldst.s: Likewise.
+
2020-10-20 Siddhesh Poyarekar <siddesh.poyarekar@arm.com>
* config/tc-aarch64.c (aarch64_addr_reg_parse): Add capability
break;
}
+ case AARCH64_OPND_A64C_ADDR_SIMM7:
case AARCH64_OPND_ADDR_SIMM7:
po_misc_or_fail (parse_address (&str, info));
if (info->addr.pcrel || info->addr.offset.is_reg
if ((aarch64_get_operand_class (opnds[0].type)
== AARCH64_OPND_CLASS_INT_REG)
&& (aarch64_get_operand_class (opnds[1].type)
- == AARCH64_OPND_CLASS_INT_REG))
+ == AARCH64_OPND_CLASS_INT_REG
+ || (aarch64_get_operand_class (opnds[1].type)
+ == AARCH64_OPND_CLASS_CAP_REG)))
{
if ((opcode->opcode & (1 << 22)))
{
fix_mov_imm_insn (fixP, buf, new_inst, value);
break;
+ case AARCH64_OPND_A64C_ADDR_SIMM7:
case AARCH64_OPND_ADDR_SIMM7:
case AARCH64_OPND_ADDR_SIMM9:
case AARCH64_OPND_ADDR_SIMM9_2:
.*: a2e483e2 swpal c4, c2, \[csp\]
.*: a22483e2 swp c4, c2, \[csp\]
.*: a26483e2 swpl c4, c2, \[csp\]
+.*: a23fc302 ldapr c2, \[c24\]
+.*: 425fff02 ldar c2, \[c24\]
+.*: 225fff02 ldaxr c2, \[c24\]
+.*: 225f7f02 ldxr c2, \[c24\]
+.*: 421fff02 stlr c2, \[c24\]
+.*: a23fc3e2 ldapr c2, \[csp\]
+.*: 425fffe2 ldar c2, \[csp\]
+.*: 225fffe2 ldaxr c2, \[csp\]
+.*: 225f7fe2 ldxr c2, \[csp\]
+.*: 421fffe2 stlr c2, \[csp\]
+.*: c2c4b302 ldct x2, \[c24\]
+.*: c2c49302 stct x2, \[c24\]
+.*: c2c4b3e2 ldct x2, \[csp\]
+.*: c2c493e2 stct x2, \[csp\]
+.*: 227f8f02 ldaxp c2, c3, \[c24\]
+.*: 227f0f02 ldxp c2, c3, \[c24\]
+.*: 227f97e2 ldaxp c2, c5, \[csp\]
+.*: 227f17e2 ldxp c2, c5, \[csp\]
+.*: 2202ff01 stlxr w2, c1, \[c24\]
+.*: 22027f01 stxr w2, c1, \[c24\]
+.*: 2202fffd stlxr w2, c29, \[csp\]
+.*: 22027ffd stxr w2, c29, \[csp\]
+.*: 22229704 stlxp w2, c4, c5, \[c24\]
+.*: 22221704 stxp w2, c4, c5, \[c24\]
+.*: 2222f7e4 stlxp w2, c4, c29, \[csp\]
+.*: 222277e4 stxp w2, c4, c29, \[csp\]
+.*: 42df9704 ldp c4, c5, \[c24, #1008\]
+.*: 42e01704 ldp c4, c5, \[c24, #-1024\]
+.*: 42c09704 ldp c4, c5, \[c24, #16\]
+.*: 42ff1704 ldp c4, c5, \[c24, #-32\]
+.*: 429f9704 stp c4, c5, \[c24, #1008\]
+.*: 42a01704 stp c4, c5, \[c24, #-1024\]
+.*: 42809704 stp c4, c5, \[c24, #16\]
+.*: 42bf1704 stp c4, c5, \[c24, #-32\]
+.*: 625f9704 ldnp c4, c5, \[c24, #1008\]
+.*: 62601704 ldnp c4, c5, \[c24, #-1024\]
+.*: 62409704 ldnp c4, c5, \[c24, #16\]
+.*: 627f1704 ldnp c4, c5, \[c24, #-32\]
+.*: 621f9704 stnp c4, c5, \[c24, #1008\]
+.*: 62201704 stnp c4, c5, \[c24, #-1024\]
+.*: 62009704 stnp c4, c5, \[c24, #16\]
+.*: 623f1704 stnp c4, c5, \[c24, #-32\]
+.*: 42df9be4 ldp c4, c6, \[csp, #1008\]
+.*: 42e01be4 ldp c4, c6, \[csp, #-1024\]
+.*: 42c09be4 ldp c4, c6, \[csp, #16\]
+.*: 42ff1be4 ldp c4, c6, \[csp, #-32\]
+.*: 429f9be4 stp c4, c6, \[csp, #1008\]
+.*: 42a01be4 stp c4, c6, \[csp, #-1024\]
+.*: 42809be4 stp c4, c6, \[csp, #16\]
+.*: 42bf1be4 stp c4, c6, \[csp, #-32\]
+.*: 625f9be4 ldnp c4, c6, \[csp, #1008\]
+.*: 62601be4 ldnp c4, c6, \[csp, #-1024\]
+.*: 62409be4 ldnp c4, c6, \[csp, #16\]
+.*: 627f1be4 ldnp c4, c6, \[csp, #-32\]
+.*: 621f9be4 stnp c4, c6, \[csp, #1008\]
+.*: 62201be4 stnp c4, c6, \[csp, #-1024\]
+.*: 62009be4 stnp c4, c6, \[csp, #16\]
+.*: 623f1be4 stnp c4, c6, \[csp, #-32\]
+.*: 62c11303 ldp c3, c4, \[c24, #32\]!
+.*: 22c11303 ldp c3, c4, \[c24\], #32
+.*: 62e01303 ldp c3, c4, \[c24, #-1024\]!
+.*: 22e01303 ldp c3, c4, \[c24\], #-1024
+.*: 62df9303 ldp c3, c4, \[c24, #1008\]!
+.*: 22df9303 ldp c3, c4, \[c24\], #1008
+.*: 62811303 stp c3, c4, \[c24, #32\]!
+.*: 22811303 stp c3, c4, \[c24\], #32
+.*: 62a01303 stp c3, c4, \[c24, #-1024\]!
+.*: 22a01303 stp c3, c4, \[c24\], #-1024
+.*: 629f9303 stp c3, c4, \[c24, #1008\]!
+.*: 229f9303 stp c3, c4, \[c24\], #1008
+.*: 62c117e4 ldp c4, c5, \[csp, #32\]!
+.*: 22c117e4 ldp c4, c5, \[csp\], #32
+.*: 62e017e4 ldp c4, c5, \[csp, #-1024\]!
+.*: 22e017e4 ldp c4, c5, \[csp\], #-1024
+.*: 62df97e4 ldp c4, c5, \[csp, #1008\]!
+.*: 22df97e4 ldp c4, c5, \[csp\], #1008
+.*: 628117e4 stp c4, c5, \[csp, #32\]!
+.*: 228117e4 stp c4, c5, \[csp\], #32
+.*: 62a017e4 stp c4, c5, \[csp, #-1024\]!
+.*: 22a017e4 stp c4, c5, \[csp\], #-1024
+.*: 629f97e4 stp c4, c5, \[csp, #1008\]!
+.*: 229f97e4 stp c4, c5, \[csp\], #1008
.*: c2d813e1 blr \[csp, #-1024\]
.*: c2d7f3e1 blr \[csp, #1008\]
.*: c2d033e1 blr \[csp, #16\]
.*: a2e483e2 swpal c4, c2, \[sp\]
.*: a22483e2 swp c4, c2, \[sp\]
.*: a26483e2 swpl c4, c2, \[sp\]
+.*: a23fc162 ldapr c2, \[x11\]
+.*: 425ffd62 ldar c2, \[x11\]
+.*: 225ffd62 ldaxr c2, \[x11\]
+.*: 225f7d62 ldxr c2, \[x11\]
+.*: 421ffd62 stlr c2, \[x11\]
+.*: a23fc3e2 ldapr c2, \[sp\]
+.*: 425fffe2 ldar c2, \[sp\]
+.*: 225fffe2 ldaxr c2, \[sp\]
+.*: 225f7fe2 ldxr c2, \[sp\]
+.*: 421fffe2 stlr c2, \[sp\]
+.*: c2c4b162 ldct x2, \[x11\]
+.*: c2c49162 stct x2, \[x11\]
+.*: c2c4b3e2 ldct x2, \[sp\]
+.*: c2c493e2 stct x2, \[sp\]
+.*: 227f8d62 ldaxp c2, c3, \[x11\]
+.*: 227f0d62 ldxp c2, c3, \[x11\]
+.*: 227f97e2 ldaxp c2, c5, \[sp\]
+.*: 227f17e2 ldxp c2, c5, \[sp\]
+.*: 2202fd61 stlxr w2, c1, \[x11\]
+.*: 22027d61 stxr w2, c1, \[x11\]
+.*: 2202fffd stlxr w2, c29, \[sp\]
+.*: 22027ffd stxr w2, c29, \[sp\]
+.*: 22229564 stlxp w2, c4, c5, \[x11\]
+.*: 22221564 stxp w2, c4, c5, \[x11\]
+.*: 2222f7e4 stlxp w2, c4, c29, \[sp\]
+.*: 222277e4 stxp w2, c4, c29, \[sp\]
+.*: 42df9564 ldp c4, c5, \[x11, #1008\]
+.*: 42e01564 ldp c4, c5, \[x11, #-1024\]
+.*: 42c09564 ldp c4, c5, \[x11, #16\]
+.*: 42ff1564 ldp c4, c5, \[x11, #-32\]
+.*: 429f9564 stp c4, c5, \[x11, #1008\]
+.*: 42a01564 stp c4, c5, \[x11, #-1024\]
+.*: 42809564 stp c4, c5, \[x11, #16\]
+.*: 42bf1564 stp c4, c5, \[x11, #-32\]
+.*: 625f9564 ldnp c4, c5, \[x11, #1008\]
+.*: 62601564 ldnp c4, c5, \[x11, #-1024\]
+.*: 62409564 ldnp c4, c5, \[x11, #16\]
+.*: 627f1564 ldnp c4, c5, \[x11, #-32\]
+.*: 621f9564 stnp c4, c5, \[x11, #1008\]
+.*: 62201564 stnp c4, c5, \[x11, #-1024\]
+.*: 62009564 stnp c4, c5, \[x11, #16\]
+.*: 623f1564 stnp c4, c5, \[x11, #-32\]
+.*: 42df9be4 ldp c4, c6, \[sp, #1008\]
+.*: 42e01be4 ldp c4, c6, \[sp, #-1024\]
+.*: 42c09be4 ldp c4, c6, \[sp, #16\]
+.*: 42ff1be4 ldp c4, c6, \[sp, #-32\]
+.*: 429f9be4 stp c4, c6, \[sp, #1008\]
+.*: 42a01be4 stp c4, c6, \[sp, #-1024\]
+.*: 42809be4 stp c4, c6, \[sp, #16\]
+.*: 42bf1be4 stp c4, c6, \[sp, #-32\]
+.*: 625f9be4 ldnp c4, c6, \[sp, #1008\]
+.*: 62601be4 ldnp c4, c6, \[sp, #-1024\]
+.*: 62409be4 ldnp c4, c6, \[sp, #16\]
+.*: 627f1be4 ldnp c4, c6, \[sp, #-32\]
+.*: 621f9be4 stnp c4, c6, \[sp, #1008\]
+.*: 62201be4 stnp c4, c6, \[sp, #-1024\]
+.*: 62009be4 stnp c4, c6, \[sp, #16\]
+.*: 623f1be4 stnp c4, c6, \[sp, #-32\]
+.*: 62c11163 ldp c3, c4, \[x11, #32\]!
+.*: 22c11163 ldp c3, c4, \[x11\], #32
+.*: 62e01163 ldp c3, c4, \[x11, #-1024\]!
+.*: 22e01163 ldp c3, c4, \[x11\], #-1024
+.*: 62df9163 ldp c3, c4, \[x11, #1008\]!
+.*: 22df9163 ldp c3, c4, \[x11\], #1008
+.*: 62811163 stp c3, c4, \[x11, #32\]!
+.*: 22811163 stp c3, c4, \[x11\], #32
+.*: 62a01163 stp c3, c4, \[x11, #-1024\]!
+.*: 22a01163 stp c3, c4, \[x11\], #-1024
+.*: 629f9163 stp c3, c4, \[x11, #1008\]!
+.*: 229f9163 stp c3, c4, \[x11\], #1008
+.*: 62c117e4 ldp c4, c5, \[sp, #32\]!
+.*: 22c117e4 ldp c4, c5, \[sp\], #32
+.*: 62e017e4 ldp c4, c5, \[sp, #-1024\]!
+.*: 22e017e4 ldp c4, c5, \[sp\], #-1024
+.*: 62df97e4 ldp c4, c5, \[sp, #1008\]!
+.*: 22df97e4 ldp c4, c5, \[sp\], #1008
+.*: 628117e4 stp c4, c5, \[sp, #32\]!
+.*: 228117e4 stp c4, c5, \[sp\], #32
+.*: 62a017e4 stp c4, c5, \[sp, #-1024\]!
+.*: 22a017e4 stp c4, c5, \[sp\], #-1024
+.*: 629f97e4 stp c4, c5, \[sp, #1008\]!
+.*: 229f97e4 stp c4, c5, \[sp\], #1008
.*: c2d813e1 blr \[csp, #-1024\]
.*: c2d7f3e1 blr \[csp, #1008\]
.*: c2d033e1 blr \[csp, #16\]
morello_swp c4, c2, VAREG
morello_swp c4, c2, SP_
+ .macro morello_ldst_base ct, xnsp
+ .irp op, ldapr, ldar, ldaxr, ldxr, stlr
+ \op \ct, [\xnsp]
+ .endr
+ .endm
+morello_ldst_base c2, VAREG
+morello_ldst_base c2, SP_
+
+ .macro morello_ldst_basex xt, xnsp
+ .irp op, ldct, stct
+ \op \xt, [\xnsp]
+ .endr
+ .endm
+morello_ldst_basex x2, VAREG
+morello_ldst_basex x2, SP_
+
+ .macro morello_ldp_base ct1, ct2, xnsp
+ .irp op, ldaxp, ldxp
+ \op \ct1, \ct2, [\xnsp]
+ .endr
+ .endm
+morello_ldp_base c2, c3, VAREG
+morello_ldp_base c2, c5, SP_
+
+ .macro morello_str_base ct, xnsp
+ .irp op, stlxr, stxr
+ \op w2, \ct, [\xnsp]
+ .endr
+ .endm
+morello_str_base c1, VAREG
+morello_str_base c29, SP_
+
+ .macro morello_stp_base ct1, ct2, xnsp
+ .irp op, stlxp, stxp
+ \op w2, \ct1, \ct2, [\xnsp]
+ .endr
+ .endm
+morello_stp_base c4, c5, VAREG
+morello_stp_base c4, c29, SP_
+
+// Base + immediate offset
+
+ .macro morello_simm_pair ct, ct2, xnsp
+ .irp op, ldp, stp, ldnp, stnp
+ \op \ct, \ct2, [\xnsp, #1008]
+ \op \ct, \ct2, [\xnsp, #-1024]
+ \op \ct, \ct2, [\xnsp, #16]
+ \op \ct, \ct2, [\xnsp, #-32]
+ .endr
+ .endm
+morello_simm_pair c4, c5, VAREG
+morello_simm_pair c4, c6, SP_
+
+// Indexed
+
+ .macro morello_index_pair ct, ct2, xnsp
+ .irp op, ldp, stp
+ \op \ct, \ct2, [\xnsp, #32]!
+ \op \ct, \ct2, [\xnsp], #32
+ \op \ct, \ct2, [\xnsp, #-1024]!
+ \op \ct, \ct2, [\xnsp], #-1024
+ \op \ct, \ct2, [\xnsp, #1008]!
+ \op \ct, \ct2, [\xnsp], #1008
+ .endr
+ .endm
+morello_index_pair c3, c4, VAREG
+morello_index_pair c4, c5, SP_
+
// Branch and Load, Prefetch, etc.
.macro morello_branch_load cnsp
+2020-10-20 Siddhesh Poyarekar <siddesh.poyarekar@arm.com>
+
+ * opcode/aarch64.h (aarch64_opnd): Add A64C_ADDR_SIMM7.
+
2020-10-20 Siddhesh Poyarekar <siddesh.poyarekar@arm.com>
* opcode/aarch64.h (aarch64_opnd): Add CAPADDR_SIMPLE and
AARCH64_OPND_CAPADDR_SIMM7, /* Immediate offset with capability base for
BLR/BR. */
AARCH64_OPND_CAPADDR_SIMPLE, /* Simple base address with no offset. */
+ AARCH64_OPND_A64C_ADDR_SIMM7, /* Address with 7-bit immediate offset. */
};
/* Qualifier constrains an operand. It either specifies a variant of an
+2020-10-20 Siddhesh Poyarekar <siddesh.poyarekar@arm.com>
+
+ * aarch64-asm-2.c: Regenerate.
+ * aarch64-dis-2.c: Regenerate.
+ * aarch64-opc-2.c: Regenerate.
+ * aarch64-opc.c (fields): Add a64c_index2.
+ (operand_general_constraint_met_p, aarch64_print_operand): Add
+ A64C_ADDR_SIMM7.
+ * aarch64-opc.h (aarch64_field_kind): Add FLD_a64c_index2.
+ * aarch64-tbl.h (QL2_A64C_CA_ADDR, QL2_A64C_X_ADDR,
+ QL3_A64C_W_CA_ADDR, QL4_A64C_W_CA_CA_ADDR): New macros.
+ (aarch64_opcode_table): New instructions.
+ (AARCH64_OPERANDS): New operands.
+
2020-10-20 Siddhesh Poyarekar <siddesh.poyarekar@arm.com>
* aarch64-asm.c (aarch64_ins_addr_simple): Fix comment.
{ 13, 3 }, /* perm: permission specifier in clrperm. */
{ 13, 2 }, /* form: form specifier in seal. */
{ 13, 7 }, /* capaddr_simm7: Signed immediate for BLR/BR. */
+ { 30, 1 }, /* a64c_index2: in ld/st pair inst deciding the pre/post-index. */
};
enum aarch64_operand_class
}
switch (type)
{
+ case AARCH64_OPND_A64C_ADDR_SIMM7:
case AARCH64_OPND_CAPADDR_SIMM7:
case AARCH64_OPND_ADDR_SIMM7:
/* Scaled signed 7 bits immediate offset. */
(buf, size, opnd, get_cap_reg_name (opnd->addr.base_regno, 1));
break;
+ case AARCH64_OPND_A64C_ADDR_SIMM7:
case AARCH64_OPND_ADDR_SIMM7:
case AARCH64_OPND_ADDR_SIMM9:
case AARCH64_OPND_ADDR_SIMM9_2:
FLD_perm,
FLD_form,
FLD_capaddr_simm7,
+ FLD_a64c_index2,
};
/* Field description. */
QLF2(CA, S_Q), \
}
+/* LDAPR Ct, [<Xn|SP>] */
+#define QL2_A64C_CA_ADDR \
+{ \
+ QLF2(CA, S_Q), \
+}
+
+#define QL2_A64C_X_ADDR \
+{ \
+ QLF2(X, S_D), \
+}
+
#define QL3_A64C_CA_CA_NIL \
{ \
QLF3(CA, CA, NIL), \
{ \
QLF3(CA, CA, S_Q), \
}
+
+#define QL3_A64C_W_CA_ADDR \
+{ \
+ QLF3(W, CA, S_Q), \
+}
+
+#define QL4_A64C_W_CA_CA_ADDR \
+{ \
+ QLF4(W, CA, CA, S_Q), \
+}
+
/* e.g. CSEL <Cad>, <Can>, <Cam>, <cond>. */
#define QL4_A64C_CSEL \
{ \
A64C_INSN ("gctype", 0xc2c0f000, 0xfffffc00, a64c, 0, OP2 (Rd, Can_SP), QL2_A64C_X_CA, 0),
A64C_INSN ("gcvalue", 0xc2c05000, 0xfffffc00, a64c, 0, OP2 (Rd, Can_SP), QL2_A64C_X_CA, 0),
+ /* Load capabilities. */
+ A64C_INSN ("ldapr", 0xa23fc000, 0xfffffc00, ldstexcl, 0, OP2 (Cat, ADDR_SIMPLE), QL2_A64C_CA_ADDR, 0),
+ A64C_INSN ("ldar", 0x425ffc00, 0xfffffc00, ldstexcl, 0, OP2 (Cat, ADDR_SIMPLE), QL2_A64C_CA_ADDR, 0),
+ A64C_INSN ("ldaxp", 0x227f8000, 0xffff8000, ldstexcl, 0, OP3 (Cat, Cat2, ADDR_SIMPLE), QL3_A64C_CA_CA_ADDR, 0),
+ A64C_INSN ("ldaxr", 0x225ffc00, 0xfffffc00, ldstexcl, 0, OP2 (Cat, ADDR_SIMPLE), QL2_A64C_CA_ADDR, 0),
+ A64C_INSN ("ldxr", 0x225f7c00, 0xfffffc00, ldstexcl, 0, OP2 (Cat, ADDR_SIMPLE), QL2_A64C_CA_ADDR, 0),
+ A64C_INSN ("ldxp", 0x227f0000, 0xffff8000, ldstexcl, 0, OP3 (Cat, Cat2, ADDR_SIMPLE), QL3_A64C_CA_CA_ADDR, 0),
+ A64C_INSN ("stxr", 0x22007c00, 0xffe0fc00, ldstexcl, 0, OP3 (Rs, Cat, ADDR_SIMPLE), QL3_A64C_W_CA_ADDR, 0),
+ A64C_INSN ("stlxr", 0x2200fc00, 0xffe0fc00, ldstexcl, 0, OP3 (Rs, Cat, ADDR_SIMPLE), QL3_A64C_W_CA_ADDR, 0),
+ A64C_INSN ("stlr", 0x421ffc00, 0xfffffc00, ldstexcl, 0, OP2 (Cat, ADDR_SIMPLE), QL2_A64C_CA_ADDR, 0),
+ A64C_INSN ("stxp", 0x22200000, 0xffe08000, ldstexcl, 0, OP4 (Rs, Cat, Cat2, ADDR_SIMPLE), QL4_A64C_W_CA_CA_ADDR, 0),
+ A64C_INSN ("stlxp", 0x22208000, 0xffe08000, ldstexcl, 0, OP4 (Rs, Cat, Cat2, ADDR_SIMPLE), QL4_A64C_W_CA_CA_ADDR, 0),
+
+ A64C_INSN ("ldnp", 0x62400000, 0xffc00000, ldstnapair_offs, 0, OP3 (Cat, Cat2, ADDR_SIMM7), QL3_A64C_CA_CA_ADDR, 0),
+ A64C_INSN ("stnp", 0x62000000, 0xffc00000, ldstnapair_offs, 0, OP3 (Cat, Cat2, ADDR_SIMM7), QL3_A64C_CA_CA_ADDR, 0),
+ A64C_INSN ("ldp", 0x42c00000, 0xffc00000, ldstpair_off, 0, OP3 (Cat, Cat2, ADDR_SIMM7), QL3_A64C_CA_CA_ADDR, 0),
+ A64C_INSN ("stp", 0x42800000, 0xffc00000, ldstpair_off, 0, OP3 (Cat, Cat2, ADDR_SIMM7), QL3_A64C_CA_CA_ADDR, 0),
+ A64C_INSN ("ldp", 0x22c00000, 0xbfc00000, ldstpair_indexed, 0, OP3 (Cat, Cat2, A64C_ADDR_SIMM7), QL3_A64C_CA_CA_ADDR, 0),
+ A64C_INSN ("stp", 0x22800000, 0xbfc00000, ldstpair_indexed, 0, OP3 (Cat, Cat2, A64C_ADDR_SIMM7), QL3_A64C_CA_CA_ADDR, 0),
+
+ A64C_INSN ("ldct", 0xc2c4b000, 0xfffffc00, a64c, 0, OP2 (Rt, ADDR_SIMPLE), QL2_A64C_X_ADDR, 0),
+ A64C_INSN ("stct", 0xc2c49000, 0xfffffc00, a64c, 0, OP2 (Rt, ADDR_SIMPLE), QL2_A64C_X_ADDR, 0),
+
/* Swap capabilities in memory. */
A64C_INSN ("swp", 0xa2208000, 0xffe0fc00, a64c, 0, OP3 (Cas, Cat, ADDR_SIMPLE), QL3_A64C_CA_CA_ADDR, 0),
A64C_INSN ("swpa", 0xa2a08000, 0xffe0fc00, a64c, 0, OP3 (Cas, Cat, ADDR_SIMPLE), QL3_A64C_CA_CA_ADDR, 0),
Y(ADDRESS, addr_simm, "CAPADDR_SIMM7", 0, F(FLD_capaddr_simm7), \
"a capability based address with 7-bit signed immediate offset") \
Y(ADDRESS, addr_simple, "CAPADDR_SIMPLE", 0, F(), \
- "a capability address with base register (no offset)")
+ "a capability address with base register (no offset)") \
+ Y(ADDRESS, addr_simm, "A64C_ADDR_SIMM7", 0, \
+ F(FLD_imm7,FLD_a64c_index2), \
+ "an address with 7-bit signed immediate offset")
projects / thirdparty / binutils-gdb.git / commitdiff
