net/mlx5: Expose disciplined_fr_counter through HCA capabilities in mlx5_ifc

Introduce the `disciplined_fr_counter` capability bit to indicate that
the device’s free-running cycle counter is disciplined to real-time.

Signed-off-by: Carolina Jubran <cjubran@nvidia.com>
Reviewed-by: Dragos Tatulea <dtatulea@nvidia.com>
Signed-off-by: Tariq Toukan <tariqt@nvidia.com>
Link: https://patch.msgid.link/1752064867-16874-2-git-send-email-tariqt@nvidia.com
Signed-off-by: Leon Romanovsky <leon@kernel.org>

diff --git a/include/linux/mlx5/mlx5_ifc.h b/include/linux/mlx5/mlx5_ifc.h
index a1bd92ed8f3a9ea9f7fe919e44ed53e2fe208924..d7684bb28a3a2530440767348ea587b551b4d924 100644 (file)
--- a/include/linux/mlx5/mlx5_ifc.h
+++ b/include/linux/mlx5/mlx5_ifc.h
@@ -1846,7 +1846,8 @@ struct mlx5_ifc_cmd_hca_cap_bits {
 
        u8         log_bf_reg_size[0x5];
 
-       u8         reserved_at_270[0x3];
+       u8         disciplined_fr_counter[0x1];
+       u8         reserved_at_271[0x2];
        u8         qp_error_syndrome[0x1];
        u8         reserved_at_274[0x2];
        u8         lag_dct[0x2];