#define EXYNOS5_FSEL_26MHZ 0x6
#define EXYNOS5_FSEL_50MHZ 0x7
+/* USB 3.2 DRD 4nm PHY link controller registers */
+#define EXYNOS2200_DRD_CLKRST 0x0c
+#define EXYNOS2200_CLKRST_LINK_PCLK_SEL BIT(1)
+
+#define EXYNOS2200_DRD_UTMI 0x10
+#define EXYNOS2200_UTMI_FORCE_VBUSVALID BIT(1)
+#define EXYNOS2200_UTMI_FORCE_BVALID BIT(0)
+
+#define EXYNOS2200_DRD_HSP_MISC 0x114
+#define HSP_MISC_SET_REQ_IN2 BIT(4)
+#define HSP_MISC_RES_TUNE GENMASK(1, 0)
+#define RES_TUNE_PHY1_PHY2 0x1
+#define RES_TUNE_PHY1 0x2
+#define RES_TUNE_PHY2 0x3
+
/* Exynos5: USB 3.0 DRD PHY registers */
#define EXYNOS5_DRD_LINKSYSTEM 0x04
#define LINKSYSTEM_XHCI_VERSION_CONTROL BIT(27)
* @clks: clocks for register access
* @core_clks: core clocks for phy (ref, pipe3, utmi+, ITP, etc. as required)
* @drv_data: pointer to SoC level driver data structure
+ * @hs_phy: pointer to non-Samsung IP high-speed phy controller
* @phy_mutex: mutex protecting phy_init/exit & TCPC callbacks
* @phys: array for 'EXYNOS5_DRDPHYS_NUM' number of PHY
* instances each with its 'phy' and 'phy_cfg'.
struct clk_bulk_data *clks;
struct clk_bulk_data *core_clks;
const struct exynos5_usbdrd_phy_drvdata *drv_data;
+ struct phy *hs_phy;
struct mutex phy_mutex;
struct phy_usb_instance {
struct phy *phy;
.owner = THIS_MODULE,
};
+static void exynos2200_usbdrd_utmi_init(struct exynos5_usbdrd_phy *phy_drd)
+{
+ /* Configure non-Samsung IP PHY, responsible for UTMI */
+ phy_init(phy_drd->hs_phy);
+}
+
+static void exynos2200_usbdrd_link_init(struct exynos5_usbdrd_phy *phy_drd)
+{
+ void __iomem *regs_base = phy_drd->reg_phy;
+ u32 reg;
+
+ /*
+ * Disable HWACG (hardware auto clock gating control). This will force
+ * QACTIVE signal in Q-Channel interface to HIGH level, to make sure
+ * the PHY clock is not gated by the hardware.
+ */
+ reg = readl(regs_base + EXYNOS850_DRD_LINKCTRL);
+ reg |= LINKCTRL_FORCE_QACT;
+ writel(reg, regs_base + EXYNOS850_DRD_LINKCTRL);
+
+ /* De-assert link reset */
+ reg = readl(regs_base + EXYNOS2200_DRD_CLKRST);
+ reg &= ~CLKRST_LINK_SW_RST;
+ writel(reg, regs_base + EXYNOS2200_DRD_CLKRST);
+
+ /* Set link VBUS Valid */
+ reg = readl(regs_base + EXYNOS2200_DRD_UTMI);
+ reg |= EXYNOS2200_UTMI_FORCE_BVALID | EXYNOS2200_UTMI_FORCE_VBUSVALID;
+ writel(reg, regs_base + EXYNOS2200_DRD_UTMI);
+}
+
+static void
+exynos2200_usbdrd_link_attach_detach_pipe3_phy(struct phy_usb_instance *inst)
+{
+ struct exynos5_usbdrd_phy *phy_drd = to_usbdrd_phy(inst);
+ void __iomem *regs_base = phy_drd->reg_phy;
+ u32 reg;
+
+ reg = readl(regs_base + EXYNOS850_DRD_LINKCTRL);
+ if (inst->phy_cfg->id == EXYNOS5_DRDPHY_UTMI) {
+ /* force pipe3 signal for link */
+ reg &= ~LINKCTRL_FORCE_PHYSTATUS;
+ reg |= LINKCTRL_FORCE_PIPE_EN | LINKCTRL_FORCE_RXELECIDLE;
+ } else {
+ /* disable forcing pipe interface */
+ reg &= ~LINKCTRL_FORCE_PIPE_EN;
+ }
+ writel(reg, regs_base + EXYNOS850_DRD_LINKCTRL);
+
+ reg = readl(regs_base + EXYNOS2200_DRD_HSP_MISC);
+ if (inst->phy_cfg->id == EXYNOS5_DRDPHY_UTMI) {
+ /* calibrate only eUSB phy */
+ reg |= FIELD_PREP(HSP_MISC_RES_TUNE, RES_TUNE_PHY1);
+ reg |= HSP_MISC_SET_REQ_IN2;
+ } else {
+ /* calibrate for dual phy */
+ reg |= FIELD_PREP(HSP_MISC_RES_TUNE, RES_TUNE_PHY1_PHY2);
+ reg &= ~HSP_MISC_SET_REQ_IN2;
+ }
+ writel(reg, regs_base + EXYNOS2200_DRD_HSP_MISC);
+
+ reg = readl(regs_base + EXYNOS2200_DRD_CLKRST);
+ if (inst->phy_cfg->id == EXYNOS5_DRDPHY_UTMI)
+ reg &= ~EXYNOS2200_CLKRST_LINK_PCLK_SEL;
+ else
+ reg |= EXYNOS2200_CLKRST_LINK_PCLK_SEL;
+
+ writel(reg, regs_base + EXYNOS2200_DRD_CLKRST);
+}
+
+static int exynos2200_usbdrd_phy_init(struct phy *phy)
+{
+ struct phy_usb_instance *inst = phy_get_drvdata(phy);
+ struct exynos5_usbdrd_phy *phy_drd = to_usbdrd_phy(inst);
+ int ret;
+
+ if (inst->phy_cfg->id == EXYNOS5_DRDPHY_UTMI) {
+ /* Power-on PHY ... */
+ ret = regulator_bulk_enable(phy_drd->drv_data->n_regulators,
+ phy_drd->regulators);
+ if (ret) {
+ dev_err(phy_drd->dev,
+ "Failed to enable PHY regulator(s)\n");
+ return ret;
+ }
+ }
+ /*
+ * ... and ungate power via PMU. Without this here, we get an SError
+ * trying to access PMA registers
+ */
+ exynos5_usbdrd_phy_isol(inst, false);
+
+ ret = clk_bulk_prepare_enable(phy_drd->drv_data->n_clks, phy_drd->clks);
+ if (ret)
+ return ret;
+
+ /* Set up the link controller */
+ exynos2200_usbdrd_link_init(phy_drd);
+
+ /* UTMI or PIPE3 link preparation */
+ exynos2200_usbdrd_link_attach_detach_pipe3_phy(inst);
+
+ /* UTMI or PIPE3 specific init */
+ inst->phy_cfg->phy_init(phy_drd);
+
+ clk_bulk_disable_unprepare(phy_drd->drv_data->n_clks, phy_drd->clks);
+
+ return 0;
+}
+
+static int exynos2200_usbdrd_phy_exit(struct phy *phy)
+{
+ struct phy_usb_instance *inst = phy_get_drvdata(phy);
+ struct exynos5_usbdrd_phy *phy_drd = to_usbdrd_phy(inst);
+ void __iomem *regs_base = phy_drd->reg_phy;
+ u32 reg;
+ int ret;
+
+ ret = clk_bulk_prepare_enable(phy_drd->drv_data->n_clks, phy_drd->clks);
+ if (ret)
+ return ret;
+
+ reg = readl(regs_base + EXYNOS2200_DRD_UTMI);
+ reg &= ~(EXYNOS2200_UTMI_FORCE_BVALID | EXYNOS2200_UTMI_FORCE_VBUSVALID);
+ writel(reg, regs_base + EXYNOS2200_DRD_UTMI);
+
+ reg = readl(regs_base + EXYNOS2200_DRD_CLKRST);
+ reg |= CLKRST_LINK_SW_RST;
+ writel(reg, regs_base + EXYNOS2200_DRD_CLKRST);
+
+ clk_bulk_disable_unprepare(phy_drd->drv_data->n_clks, phy_drd->clks);
+
+ exynos5_usbdrd_phy_isol(inst, true);
+ return regulator_bulk_disable(phy_drd->drv_data->n_regulators,
+ phy_drd->regulators);
+}
+
+static const struct phy_ops exynos2200_usbdrd_phy_ops = {
+ .init = exynos2200_usbdrd_phy_init,
+ .exit = exynos2200_usbdrd_phy_exit,
+ .owner = THIS_MODULE,
+};
+
static void
exynos5_usbdrd_usb_v3p1_pipe_override(struct exynos5_usbdrd_phy *phy_drd)
{
return dev_err_probe(phy_drd->dev, ret,
"failed to get phy core clock(s)\n");
- ref_clk = NULL;
- for (int i = 0; i < phy_drd->drv_data->n_core_clks; ++i) {
- if (!strcmp(phy_drd->core_clks[i].id, "ref")) {
- ref_clk = phy_drd->core_clks[i].clk;
- break;
+ if (phy_drd->drv_data->n_core_clks) {
+ ref_clk = NULL;
+ for (int i = 0; i < phy_drd->drv_data->n_core_clks; ++i) {
+ if (!strcmp(phy_drd->core_clks[i].id, "ref")) {
+ ref_clk = phy_drd->core_clks[i].clk;
+ break;
+ }
}
- }
- if (!ref_clk)
- return dev_err_probe(phy_drd->dev, -ENODEV,
- "failed to find phy reference clock\n");
+ if (!ref_clk)
+ return dev_err_probe(phy_drd->dev, -ENODEV,
+ "failed to find phy reference clock\n");
- ref_rate = clk_get_rate(ref_clk);
- ret = exynos5_rate_to_clk(ref_rate, &phy_drd->extrefclk);
- if (ret)
- return dev_err_probe(phy_drd->dev, ret,
- "clock rate (%ld) not supported\n",
- ref_rate);
+ ref_rate = clk_get_rate(ref_clk);
+ ret = exynos5_rate_to_clk(ref_rate, &phy_drd->extrefclk);
+ if (ret)
+ return dev_err_probe(phy_drd->dev, ret,
+ "clock rate (%ld) not supported\n",
+ ref_rate);
+ }
return 0;
}
+static const struct exynos5_usbdrd_phy_config phy_cfg_exynos2200[] = {
+ {
+ .id = EXYNOS5_DRDPHY_UTMI,
+ .phy_isol = exynos5_usbdrd_phy_isol,
+ .phy_init = exynos2200_usbdrd_utmi_init,
+ },
+};
+
static int exynos5_usbdrd_orien_sw_set(struct typec_switch_dev *sw,
enum typec_orientation orientation)
{
"vbus", "vbus-boost",
};
+static const struct exynos5_usbdrd_phy_drvdata exynos2200_usb32drd_phy = {
+ .phy_cfg = phy_cfg_exynos2200,
+ .phy_ops = &exynos2200_usbdrd_phy_ops,
+ .pmu_offset_usbdrd0_phy = EXYNOS2200_PHY_CTRL_USB20,
+ .clk_names = exynos5_clk_names,
+ .n_clks = ARRAY_SIZE(exynos5_clk_names),
+ /* clocks and regulators are specific to the underlying PHY blocks */
+ .core_clk_names = NULL,
+ .n_core_clks = 0,
+ .regulator_names = NULL,
+ .n_regulators = 0,
+};
+
static const struct exynos5_usbdrd_phy_drvdata exynos5420_usbdrd_phy = {
.phy_cfg = phy_cfg_exynos5,
.phy_ops = &exynos5_usbdrd_phy_ops,
{
.compatible = "google,gs101-usb31drd-phy",
.data = &gs101_usbd31rd_phy
+ }, {
+ .compatible = "samsung,exynos2200-usb32drd-phy",
+ .data = &exynos2200_usb32drd_phy,
}, {
.compatible = "samsung,exynos5250-usbdrd-phy",
.data = &exynos5250_usbdrd_phy
return PTR_ERR(phy_drd->reg_phy);
}
+ /*
+ * USB32DRD 4nm controller implements Synopsys eUSB2.0 PHY
+ * and Synopsys SS/USBDP COMBOPHY, managed by external code.
+ */
+ if (of_property_present(dev->of_node, "phy-names")) {
+ phy_drd->hs_phy = devm_of_phy_get(dev, dev->of_node, "hs");
+ if (IS_ERR(phy_drd->hs_phy))
+ return dev_err_probe(dev, PTR_ERR(phy_drd->hs_phy),
+ "failed to get hs_phy\n");
+ }
+
ret = exynos5_usbdrd_phy_clk_handle(phy_drd);
if (ret)
return ret;
projects / thirdparty / linux.git / commitdiff
