Fix Bug 327284. The condition code of risbg was not correct.

This instruction might be used by by gcc for masking out bits,
e.g. code like
 n &= 3;
  if (n == 0)

might result in
        risbg   %r4,%r4,62,128+63,0
        je      <target>

The old code set the condition code depending on the operand before
masking. Fix it. This patch also indicates that we need test suite
coverage for risbg and friends.

git-svn-id: svn://svn.valgrind.org/vex/trunk@2798

diff --git a/VEX/priv/guest_s390_toIR.c b/VEX/priv/guest_s390_toIR.c
index 7c5d80857414c891a8f3ce5412d02d9b5afbaf70..eb750a87946c30656108f1fe134457b4afcf2563 100644 (file)
--- a/VEX/priv/guest_s390_toIR.c
+++ b/VEX/priv/guest_s390_toIR.c
@@ -7606,7 +7606,7 @@ s390_irgen_RISBG(UChar r1, UChar r2, UChar i3, UChar i4, UChar i5)
       put_gpr_dw0(r1, binop(Iop_And64, mkexpr(op2), mkU64(mask)));
    }
    assign(result, get_gpr_dw0(r1));
-   s390_cc_thunk_putS(S390_CC_OP_LOAD_AND_TEST, op2);
+   s390_cc_thunk_putS(S390_CC_OP_LOAD_AND_TEST, result);
 
    return "risbg";
 }