qualcommbe: ipq95xx: pcs: support 2.5G PHY

Fixes to PCS driver to support 2.5G PHY

Signed-off-by: Mantas Pucka <mantas@8devices.com>
Link: https://github.com/openwrt/openwrt/pull/18459
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>

diff --git a/target/linux/qualcommbe/patches-6.6/700-net-pcs-ipq-uniphy-keep-autoneg-enabled-in-SGMII-mod.patch b/target/linux/qualcommbe/patches-6.6/700-net-pcs-ipq-uniphy-keep-autoneg-enabled-in-SGMII-mod.patch
new file mode 100644 (file)
index 0000000..8ba365e
--- /dev/null
+++ b/target/linux/qualcommbe/patches-6.6/700-net-pcs-ipq-uniphy-keep-autoneg-enabled-in-SGMII-mod.patch
@@ -0,0 +1,48 @@
+From 4c432babdc195a0dbef70ca67c92cec8adf01e30 Mon Sep 17 00:00:00 2001
+From: Mantas Pucka <mantas@8devices.com>
+Date: Fri, 28 Mar 2025 14:22:21 +0200
+Subject: [PATCH 5/6] net: pcs: ipq-uniphy: keep autoneg enabled in SGMII mode
+
+For PHYs that don't use in-band-status (e.g. 2.5G PHY swiching between
+SGMII and 2500base-x), SGMII autoneg still must be enabled. Only mode
+that should use forced speed is 1000base-x
+
+Signed-off-by: Mantas Pucka <mantas@8devices.com>
+---
+ drivers/net/pcs/pcs-qcom-ipq-uniphy.c | 9 +++++----
+ 1 file changed, 5 insertions(+), 4 deletions(-)
+
+--- a/drivers/net/pcs/pcs-qcom-ipq-uniphy.c
++++ b/drivers/net/pcs/pcs-qcom-ipq-uniphy.c
+@@ -520,7 +520,7 @@ static int ipq_unipcs_config_sgmii(struc
+               mutex_unlock(&qunipcs->shared_lock);
+ 
+       /* In-band autoneg mode is enabled by default for each PCS channel */
+-      if (neg_mode == PHYLINK_PCS_NEG_INBAND_ENABLED)
++      if (interface != PHY_INTERFACE_MODE_1000BASEX)
+               return 0;
+ 
+       /* Force speed mode */
+@@ -758,10 +758,11 @@ ipq_unipcs_link_up_clock_rate_set(struct
+ static void ipq_unipcs_link_up_config_sgmii(struct ipq_uniphy_pcs *qunipcs,
+                                           int channel,
+                                           unsigned int neg_mode,
+-                                          int speed)
++                                          int speed,
++                                          phy_interface_t interface)
+ {
+       /* No need to config PCS speed if in-band autoneg is enabled */
+-      if (neg_mode == PHYLINK_PCS_NEG_INBAND_ENABLED)
++      if (interface != PHY_INTERFACE_MODE_1000BASEX)
+               goto pcs_adapter_reset;
+ 
+       /* PCS speed set for force mode */
+@@ -966,7 +967,7 @@ static void ipq_unipcs_link_up(struct ph
+       case PHY_INTERFACE_MODE_PSGMII:
+       case PHY_INTERFACE_MODE_1000BASEX:
+               ipq_unipcs_link_up_config_sgmii(qunipcs, channel,
+-                                              neg_mode, speed);
++                                              neg_mode, speed, interface);
+               break;
+       case PHY_INTERFACE_MODE_2500BASEX:
+               ipq_unipcs_link_up_config_2500basex(qunipcs,

diff --git a/target/linux/qualcommbe/patches-6.6/701-net-pcs-ipq-uniphy-control-MISC2-register-for-2.5G-s.patch b/target/linux/qualcommbe/patches-6.6/701-net-pcs-ipq-uniphy-control-MISC2-register-for-2.5G-s.patch
new file mode 100644 (file)
index 0000000..8430127
--- /dev/null
+++ b/target/linux/qualcommbe/patches-6.6/701-net-pcs-ipq-uniphy-control-MISC2-register-for-2.5G-s.patch
@@ -0,0 +1,64 @@
+From 3bbf1aad312de653b894c2e60ea1b37ce912c6fe Mon Sep 17 00:00:00 2001
+From: Mantas Pucka <mantas@8devices.com>
+Date: Fri, 28 Mar 2025 14:10:22 +0200
+Subject: [PATCH 3/6] net: pcs: ipq-uniphy: control MISC2 register for 2.5G
+ support
+
+When 2500base-x mode is enabled MISC2 regsister needs to have different
+value than for other 1G modes.
+
+Signed-off-by: Mantas Pucka <mantas@8devices.com>
+---
+ drivers/net/pcs/pcs-qcom-ipq-uniphy.c | 16 ++++++++++++++++
+ 1 file changed, 16 insertions(+)
+
+--- a/drivers/net/pcs/pcs-qcom-ipq-uniphy.c
++++ b/drivers/net/pcs/pcs-qcom-ipq-uniphy.c
+@@ -20,6 +20,11 @@
+ #define PCS_CALIBRATION                       0x1e0
+ #define PCS_CALIBRATION_DONE          BIT(7)
+ 
++#define PCS_MISC2                     0x218
++#define PCS_MISC2_MODE_MASK           GENMASK(6, 5)
++#define PCS_MISC2_MODE_SGMII          FIELD_PREP(PCS_MISC2_MODE_MASK, 0x1)
++#define PCS_MISC2_MODE_SGMII_PLUS     FIELD_PREP(PCS_MISC2_MODE_MASK, 0x2)
++
+ #define PCS_MODE_CTRL                 0x46c
+ #define PCS_MODE_SEL_MASK             GENMASK(12, 8)
+ #define PCS_MODE_SGMII                        FIELD_PREP(PCS_MODE_SEL_MASK, 0x4)
+@@ -422,6 +427,9 @@ static int ipq_unipcs_config_mode(struct
+               ipq_unipcs_reg_modify32(qunipcs, PCS_MODE_CTRL,
+                                       PCS_MODE_SEL_MASK | PCS_MODE_AN_MODE,
+                                       PCS_MODE_SGMII);
++              ipq_unipcs_reg_modify32(qunipcs, PCS_MISC2,
++                                      PCS_MISC2_MODE_MASK,
++                                      PCS_MISC2_MODE_SGMII);
+               break;
+       case PHY_INTERFACE_MODE_QSGMII:
+               rate = 125000000;
+@@ -438,17 +446,25 @@ static int ipq_unipcs_config_mode(struct
+                                       PCS_MODE_PSGMII);
+               break;
+       case PHY_INTERFACE_MODE_1000BASEX:
++              rate = 125000000;
+               ipq_unipcs_reg_modify32(qunipcs, PCS_MODE_CTRL,
+                                       PCS_MODE_SEL_MASK |
+                                       PCS_MODE_SGMII_CTRL_MASK,
+                                       PCS_MODE_SGMII |
+                                       PCS_MODE_SGMII_CTRL_1000BASEX);
++              ipq_unipcs_reg_modify32(qunipcs, PCS_MISC2,
++                                      PCS_MISC2_MODE_MASK,
++                                      PCS_MISC2_MODE_SGMII);
+               break;
+       case PHY_INTERFACE_MODE_2500BASEX:
+               rate = 312500000;
+               ipq_unipcs_reg_modify32(qunipcs, PCS_MODE_CTRL,
+                                       PCS_MODE_SEL_MASK,
+                                       PCS_MODE_SGMII_PLUS);
++              ipq_unipcs_reg_modify32(qunipcs, PCS_MISC2,
++                                      PCS_MISC2_MODE_MASK,
++                                      PCS_MISC2_MODE_SGMII_PLUS);
++
+               break;
+       case PHY_INTERFACE_MODE_USXGMII:
+       case PHY_INTERFACE_MODE_10GBASER: