]> git.ipfire.org Git - thirdparty/linux.git/commitdiff
arm64: dts: rockchip: fix unit-address for RK3588 NPU's core1 and core2's IOMMU
authorQuentin Schulz <quentin.schulz@cherry.de>
Mon, 15 Dec 2025 16:45:56 +0000 (17:45 +0100)
committerHeiko Stuebner <heiko@sntech.de>
Mon, 22 Dec 2025 12:44:34 +0000 (13:44 +0100)
The Device Tree specification specifies[1] that

"""
Each node in the devicetree is named according to the following
convention:
node-name@unit-address
[...]
The unit-address must match the first address specified in the reg
property of the node.
"""

The first address in the reg property is fdaXa000 and not fdaX9000. This
is likely a copy-paste error as the IOMMU for core0 has two entries in
the reg property, the first one being fdab9000 and the second fdaba000.

Let's fix this oversight to match what the spec is expecting.

[1] https://github.com/devicetree-org/devicetree-specification/releases/download/v0.4/devicetree-specification-v0.4.pdf 2.2.1 Node Names

Fixes: a31dfc060a74 ("arm64: dts: rockchip: Add nodes for NPU and its MMU to rk3588-base")
Cc: stable@vger.kernel.org
Signed-off-by: Quentin Schulz <quentin.schulz@cherry.de>
Link: https://patch.msgid.link/20251215-npu-dt-node-address-v1-1-840093e8a2bf@cherry.de
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
arch/arm64/boot/dts/rockchip/rk3588-base.dtsi

index 2a79217930206bd1b8097c8effda5877c0557551..7ab12d1054a73bbde041cb6896fdeb4b16279dc2 100644 (file)
                status = "disabled";
        };
 
-       rknn_mmu_1: iommu@fdac9000 {
+       rknn_mmu_1: iommu@fdaca000 {
                compatible = "rockchip,rk3588-iommu", "rockchip,rk3568-iommu";
                reg = <0x0 0xfdaca000 0x0 0x100>;
                interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH 0>;
                status = "disabled";
        };
 
-       rknn_mmu_2: iommu@fdad9000 {
+       rknn_mmu_2: iommu@fdada000 {
                compatible = "rockchip,rk3588-iommu", "rockchip,rk3568-iommu";
                reg = <0x0 0xfdada000 0x0 0x100>;
                interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH 0>;