MAINTAINERS: Add myself as a reviewer for RISC-V TCG CPUs

Add myself as a reviewer for RISC-V TCG CPU related code to better
participate in patch review.

Signed-off-by: Chao Liu <chao.liu.zevorn@gmail.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Daniel Henrique Barboza <daniel.barboza@oss.qualcomm.com>
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Message-ID: <20260226102008.146928-1-chao.liu.zevorn@gmail.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>

diff --git a/MAINTAINERS b/MAINTAINERS
index 62fb18d1255236bfbcf87df4078359c7c0cffc15..25fb621c30a402e0c5af8a853461798827331b83 100644 (file)
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -343,6 +343,7 @@ M: Alistair Francis <alistair.francis@wdc.com>
 R: Weiwei Li <liwei1518@gmail.com>
 R: Daniel Henrique Barboza <daniel.barboza@oss.qualcomm.com>
 R: Liu Zhiwei <zhiwei_liu@linux.alibaba.com>
+R: Chao Liu <chao.liu.zevorn@gmail.com>
 L: qemu-riscv@nongnu.org
 S: Supported
 F: configs/targets/riscv*