drm/amd/display: Always update divider settings for DP tunnel

[Why]
When transitioning from 640x480 at RBRx1 to HBR3x1,
both output pixel mode and pixel rate divider should update.
The needs_divider_update flag was only for 8b10b and 128b132b transition.

[How]
For DP tunneling, always update divider settings.

Reviewed-by: Jerry Zuo <jerry.zuo@amd.com>
Signed-off-by: Cruise Hung <Cruise.Hung@amd.com>
Signed-off-by: Matthew Stewart <matthew.stewart2@amd.com>
Tested-by: Dan Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/display/dc/link/accessories/link_dp_cts.c b/drivers/gpu/drm/amd/display/dc/link/accessories/link_dp_cts.c
index 5a547d41d4a1bbbfe0396b682f92a6f6d2826191..693d852b1c40300d510f7a2c26c9463c7c394d54 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/link/accessories/link_dp_cts.c
+++ b/drivers/gpu/drm/amd/display/dc/link/accessories/link_dp_cts.c
@@ -70,6 +70,7 @@ static void dp_retrain_link_dp_test(struct dc_link *link,
        struct dc_state *state = link->dc->current_state;
        struct dc_stream_update stream_update = { 0 };
        bool dpms_off = false;
+       bool needs_divider_update = false;
        bool was_hpo_acquired = resource_is_hpo_acquired(link->dc->current_state);
        bool is_hpo_acquired;
        uint8_t count;
@@ -79,6 +80,10 @@ static void dp_retrain_link_dp_test(struct dc_link *link,
        int num_streams_on_link = 0;
        struct dc *dc = (struct dc *)link->dc;
 
+       needs_divider_update = (link->dc->link_srv->dp_get_encoding_format(link_setting) !=
+               link->dc->link_srv->dp_get_encoding_format((const struct dc_link_settings *) &link->cur_link_settings))
+               || link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA;
+
        udelay(100);
 
        link_get_master_pipes_with_dpms_on(link, state, &count, pipes);
@@ -95,7 +100,7 @@ static void dp_retrain_link_dp_test(struct dc_link *link,
                pipes[i]->stream_res.tg->funcs->disable_crtc(pipes[i]->stream_res.tg);
        }
 
-       if (link->dc->res_pool->funcs->update_dc_state_for_encoder_switch) {
+       if (needs_divider_update && link->dc->res_pool->funcs->update_dc_state_for_encoder_switch) {
                link->dc->res_pool->funcs->update_dc_state_for_encoder_switch(link,
                                link_setting, count,
                                *pipes, &audio_output[0]);

diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c
index 0d667b54ccf8128faff698ae05220663b3d5f8d5..e853ea110310153ee44255d77d8a9018b6d5823f 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c
@@ -2250,12 +2250,15 @@ enum dc_status dcn31_update_dc_state_for_encoder_switch(struct dc_link *link,
        int i;
 
 #if defined(CONFIG_DRM_AMD_DC_FP)
-       for (i = 0; i < state->stream_count; i++)
-               if (state->streams[i] && state->streams[i]->link && state->streams[i]->link == link)
-                       link->dc->hwss.calculate_pix_rate_divider((struct dc *)link->dc, state, state->streams[i]);
+       if (link->dc->hwss.calculate_pix_rate_divider) {
+               for (i = 0; i < state->stream_count; i++)
+                       if (state->streams[i] && state->streams[i]->link && state->streams[i]->link == link)
+                               link->dc->hwss.calculate_pix_rate_divider((struct dc *)link->dc, state, state->streams[i]);
+       }
 
        for (i = 0; i < pipe_count; i++) {
-               link->dc->res_pool->funcs->build_pipe_pix_clk_params(&pipes[i]);
+               if (link->dc->res_pool->funcs->build_pipe_pix_clk_params)
+                       link->dc->res_pool->funcs->build_pipe_pix_clk_params(&pipes[i]);
 
                // Setup audio
                if (pipes[i].stream_res.audio != NULL)