ARM: dts: renesas: r8a7794: Move interrupt-parent to root node

Move the "interrupt-parent = <&gic>" property from the soc node to the
root node, and simplify "interrupts-extended = <&gic ...>" to
"interrupts = <...>".

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Link: https://patch.msgid.link/e0fd5e98d27c266e9498350a44747d314ce87e71.1759414774.git.geert+renesas@glider.be

diff --git a/arch/arm/boot/dts/renesas/r8a7794.dtsi b/arch/arm/boot/dts/renesas/r8a7794.dtsi
index 92010d09f6c40aa00f941003fc9194fed1877a3d..7669a67377c98900dd14f2ce3b55b1ba4f6f89b0 100644 (file)
--- a/arch/arm/boot/dts/renesas/r8a7794.dtsi
+++ b/arch/arm/boot/dts/renesas/r8a7794.dtsi
@@ -15,6 +15,7 @@
        compatible = "renesas,r8a7794";
        #address-cells = <2>;
        #size-cells = <2>;
+       interrupt-parent = <&gic>;
 
        aliases {
                i2c0 = &i2c0;
@@ -104,8 +105,8 @@
 
        pmu {
                compatible = "arm,cortex-a7-pmu";
-               interrupts-extended = <&gic GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>,
-                                     <&gic GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
+               interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>,
+                            <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
                interrupt-affinity = <&cpu0>, <&cpu1>;
        };
 
@@ -119,7 +120,6 @@
 
        soc {
                compatible = "simple-bus";
-               interrupt-parent = <&gic>;
                bootph-all;
 
                #address-cells = <2>;
@@ -1485,10 +1485,10 @@
 
        timer {
                compatible = "arm,armv7-timer";
-               interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
-                                     <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
-                                     <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
-                                     <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
+               interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
+                            <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
+                            <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
+                            <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
                interrupt-names = "sec-phys", "phys", "virt", "hyp-phys";
        };