drm/xe: Stop programming BLIT_CCTL on Xe2 and later platforms

Xe1 platforms used the BLIT_CCTL register to specify the MOCS value that
would be used for BCS engine instructions that did not have a way of
specifying a MOCS index directly.  From Xe2 onward, all BCS instructions
now have explicit instruction fields for specifying a MOCS index and the
BLIT_CCTL register is now a dummy register with no valid fields.
Although continuing to write to it today has no effect, the register
could repurposed in future platforms, so restrict the BLIT_CCTL RTP
entry to only apply to Xe1 platforms.

Bspec: 60280
Reviewed-by: Shuicheng Lin <shuicheng.lin@intel.com>
Link: https://patch.msgid.link/20260424-engine-setup-v2-3-59cc620a25f1@intel.com
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>

diff --git a/drivers/gpu/drm/xe/xe_hw_engine.c b/drivers/gpu/drm/xe/xe_hw_engine.c
index c7d211178300ff013bbbea29f3f50b5414f01cae..0419cd0450904bed1992061c4bf8195a0cf81aae 100644 (file)
--- a/drivers/gpu/drm/xe/xe_hw_engine.c
+++ b/drivers/gpu/drm/xe/xe_hw_engine.c
@@ -384,7 +384,7 @@ xe_hw_engine_setup_default_lrc_state(struct xe_hw_engine *hwe)
                 * BLIT_CCTL registers are needed to be programmed to un-cached.
                 */
                { XE_RTP_NAME("BLIT_CCTL_default_MOCS"),
-                 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, XE_RTP_END_VERSION_UNDEFINED),
+                 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, 1274),
                               ENGINE_CLASS(COPY)),
                  XE_RTP_ACTIONS(FIELD_SET(BLIT_CCTL(0),
                                 BLIT_CCTL_DST_MOCS_MASK |