ARM: dts: aspeed: Harma: revise gpio bride pin for battery

Update the GPIO bridge pin configuration for the battery circuit
on the Harma platform to reflect the correct hardware design.

Signed-off-by: Peter Yin <peteryin.openbmc@gmail.com>
Link: https://patch.msgid.link/20250611080514.3123335-5-peteryin.openbmc@gmail.com
Signed-off-by: Andrew Jeffery <andrew@codeconstruct.com.au>

diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-harma.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-harma.dts
index 25b873ace2eac862c048d6671602c7f09bfdba5a..fb026c8fb0ee51c737a444a7d2772d3938678d94 100644 (file)
--- a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-harma.dts
+++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-harma.dts
@@ -643,7 +643,7 @@
        /*T0-T7*/       "","","","","","","","",
        /*U0-U7*/       "","","","","","","led-identify-gate","",
        /*V0-V7*/       "","","","",
-                       "rtc-battery-voltage-read-enable","",
+                       "","",
                        "","",
        /*W0-W7*/       "","","","","","","","",
        /*X0-X7*/       "","","","","","","","",
@@ -728,7 +728,7 @@
        "presence-cmm","ac-control-n",
        /*G0-G3 line 96-103*/
        "FM_CPU_CORETYPE2","",
-       "FM_CPU_CORETYPE1","",
+       "FM_CPU_CORETYPE1","rtc-battery-voltage-read-enable",
        "FM_CPU_CORETYPE0","",
        "FM_BOARD_REV_ID5","",
        /*G4-G7 line 104-111*/