ARM: tegra: Add missing HOST1X device nodes on Tegra114

Add nodes for devices on the HOST1X bus: VI, EPP, ISP, MSENC and TSEC.

Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
Reviewed-by: Mikko Perttunen <mperttunen@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>

diff --git a/arch/arm/boot/dts/nvidia/tegra114.dtsi b/arch/arm/boot/dts/nvidia/tegra114.dtsi
index a2a50f959927ddfe3461135a8337cd51f6b68747..a98667641be202209732d39e85f7c2a6ab905602 100644 (file)
--- a/arch/arm/boot/dts/nvidia/tegra114.dtsi
+++ b/arch/arm/boot/dts/nvidia/tegra114.dtsi
@@ -48,6 +48,45 @@
 
                ranges = <0x54000000 0x54000000 0x01000000>;
 
+               vi@54080000 {
+                       compatible = "nvidia,tegra114-vi";
+                       reg = <0x54080000 0x00040000>;
+                       interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&tegra_car TEGRA114_CLK_VI>;
+                       resets = <&tegra_car 20>;
+                       reset-names = "vi";
+
+                       iommus = <&mc TEGRA_SWGROUP_VI>;
+
+                       status = "disabled";
+               };
+
+               epp@540c0000 {
+                       compatible = "nvidia,tegra114-epp";
+                       reg = <0x540c0000 0x00040000>;
+                       interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&tegra_car TEGRA114_CLK_EPP>;
+                       resets = <&tegra_car TEGRA114_CLK_EPP>;
+                       reset-names = "epp";
+
+                       iommus = <&mc TEGRA_SWGROUP_EPP>;
+
+                       status = "disabled";
+               };
+
+               isp@54100000 {
+                       compatible = "nvidia,tegra114-isp";
+                       reg = <0x54100000 0x00040000>;
+                       interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&tegra_car TEGRA114_CLK_ISP>;
+                       resets = <&tegra_car TEGRA114_CLK_ISP>;
+                       reset-names = "isp";
+
+                       iommus = <&mc TEGRA_SWGROUP_ISP>;
+
+                       status = "disabled";
+               };
+
                gr2d@54140000 {
                        compatible = "nvidia,tegra114-gr2d";
                        reg = <0x54140000 0x00040000>;
@@ -150,6 +189,31 @@
                        #address-cells = <1>;
                        #size-cells = <0>;
                };
+
+               msenc@544c0000 {
+                       compatible = "nvidia,tegra114-msenc";
+                       reg = <0x544c0000 0x00040000>;
+                       interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&tegra_car TEGRA114_CLK_MSENC>;
+                       resets = <&tegra_car TEGRA114_CLK_MSENC>;
+                       reset-names = "mpe";
+
+                       iommus = <&mc TEGRA_SWGROUP_MSENC>;
+
+                       status = "disabled";
+               };
+
+               tsec@54500000 {
+                       compatible = "nvidia,tegra114-tsec";
+                       reg = <0x54500000 0x00040000>;
+                       interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&tegra_car TEGRA114_CLK_TSEC>;
+                       resets = <&tegra_car TEGRA114_CLK_TSEC>;
+
+                       iommus = <&mc TEGRA_SWGROUP_TSEC>;
+
+                       status = "disabled";
+               };
        };
 
        gic: interrupt-controller@50041000 {