HInstrArray* (*iselSB) ( IRSB*, VexArch, VexArchInfo*,
VexAbiInfo* );
Int (*emit) ( UChar*, Int, HInstr*, Bool, void* );
- IRExpr* (*specHelper) ( HChar*, IRExpr** );
+ IRExpr* (*specHelper) ( HChar*, IRExpr**, IRStmt**, Int );
Bool (*preciseMemExnsFn) ( Int, Int );
DisOneInstrFn disInstrFn;
/* Clean it up, hopefully a lot. */
irsb = do_iropt_BB ( irsb, specHelper, preciseMemExnsFn,
- vta->guest_bytes_addr );
+ vta->guest_bytes_addr,
+ vta->arch_guest );
sanityCheckIRSB( irsb, "after initial iropt",
True/*must be flat*/, guest_word_type );
static HChar* show_hwcaps_arm ( UInt hwcaps )
{
- if (hwcaps == 0) return "arm-baseline";
+ Bool N = ((hwcaps & VEX_HWCAPS_ARM_NEON) != 0);
+ Bool vfp = ((hwcaps & (VEX_HWCAPS_ARM_VFP |
+ VEX_HWCAPS_ARM_VFP2 | VEX_HWCAPS_ARM_VFP3)) != 0);
+ switch (VEX_ARM_ARCHLEVEL(hwcaps)) {
+ case 5:
+ if (N)
+ return NULL;
+ if (vfp)
+ return "ARMv5-vfp";
+ else
+ return "ARMv5";
+ return NULL;
+ case 6:
+ if (N)
+ return NULL;
+ if (vfp)
+ return "ARMv6-vfp";
+ else
+ return "ARMv6";
+ return NULL;
+ case 7:
+ if (vfp) {
+ if (N)
+ return "ARMv7-vfp-neon";
+ else
+ return "ARMv7-vfp";
+ } else {
+ if (N)
+ return "ARMv7-neon";
+ else
+ return "ARMv7";
+ }
+ default:
+ return NULL;
+ }
return NULL;
}
(fres,frsqrte,fsel,stfiwx) */
/* arm: baseline capability is ARMv4 */
-/* No extra capabilities */
-
+/* Bits 5:0 - architecture level (e.g. 5 for v5, 6 for v6 etc) */
+#define VEX_HWCAPS_ARM_VFP (1<<6) /* VFP extension */
+#define VEX_HWCAPS_ARM_VFP2 (1<<7) /* VFPv2 */
+#define VEX_HWCAPS_ARM_VFP3 (1<<8) /* VFPv3 */
+/* Bits 15:10 reserved for (possible) future VFP revisions */
+#define VEX_HWCAPS_ARM_NEON (1<<16) /* Advanced SIMD also known as NEON */
+
+/* Get an ARM architecure level from HWCAPS */
+#define VEX_ARM_ARCHLEVEL(x) ((x) & 0x3f)
/* These return statically allocated strings. */