Daily bump.

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 7d2f7583128ec89d63eabe0ca32894b9a3cfc95a..f0eba6d52a5da6358b145101e25e072f097a125b 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,380 @@
+2024-11-20  Lewis Hyatt  <lhyatt@gmail.com>
+
+       * tree-cfg.cc (assign_discriminators): Fix incorrect value passed to
+       next_discriminator_for_locus().
+
+2024-11-20  Vladimir N. Makarov  <vmakarov@redhat.com>
+
+       PR target/116587
+       * lra-assigns.cc (find_all_spills_for): Consider all pseudos whose
+       classes intersect given pseudo class.
+
+2024-11-20  Andrew Pinski  <quic_apinski@quicinc.com>
+
+       * read-md.h (class rtx_reader): Don't include m_reuse_rtx_by_id
+       when GENERATOR_FILE is defined.
+       * read-rtl.cc (rtx_reader::read_rtx_code): Disable reuse_rtx
+       support when GENERATOR_FILE is defined.
+
+2024-11-20  Richard Biener  <rguenther@suse.de>
+
+       PR tree-optimization/117709
+       * tree-vect-stmts.cc (get_group_load_store_type): Only
+       set *poffset when we end up with VMAT_CONTIGUOUS_DOWN
+       or VMAT_CONTIGUOUS_REVERSE.
+
+2024-11-20  Richard Biener  <rguenther@suse.de>
+
+       PR tree-optimization/117698
+       * tree-vect-stmts.cc (get_group_load_store_type): Properly
+       disregard alignment for VMAT_STRIDED_SLP and VMAT_INVARIANT.
+       (vectorizable_load): Adjust guard for dumping whether we
+       vectorize and unaligned access.
+       (vectorizable_store): Likewise.
+
+2024-11-20  Paul-Antoine Arras  <parras@baylibre.com>
+
+       * builtins.cc (builtin_fnspec): Handle BUILT_IN_OMP_GET_MAPPED_PTR.
+       * gimple-low.cc (lower_stmt): Handle GIMPLE_OMP_DISPATCH.
+       * gimple-pretty-print.cc (dump_gimple_omp_dispatch): New function.
+       (pp_gimple_stmt_1): Handle GIMPLE_OMP_DISPATCH.
+       * gimple-walk.cc (walk_gimple_stmt): Likewise.
+       * gimple.cc (gimple_build_omp_dispatch): New function.
+       (gimple_copy): Handle GIMPLE_OMP_DISPATCH.
+       * gimple.def (GIMPLE_OMP_DISPATCH): Define.
+       * gimple.h (gimple_build_omp_dispatch): Declare.
+       (gimple_has_substatements): Handle GIMPLE_OMP_DISPATCH.
+       (gimple_omp_dispatch_clauses): New function.
+       (gimple_omp_dispatch_clauses_ptr): Likewise.
+       (gimple_omp_dispatch_set_clauses): Likewise.
+       (gimple_return_set_retval): Handle GIMPLE_OMP_DISPATCH.
+       * gimplify.cc (enum omp_region_type): Add ORT_DISPATCH.
+       (struct gimplify_omp_ctx): Add in_call_args.
+       (gimplify_call_expr): Handle need_device_ptr arguments.
+       (is_gimple_stmt): Handle OMP_DISPATCH.
+       (gimplify_scan_omp_clauses): Handle OMP_CLAUSE_DEVICE in a dispatch
+       construct. Handle OMP_CLAUSE_NOVARIANTS and OMP_CLAUSE_NOCONTEXT.
+       (omp_has_novariants): New function.
+       (omp_has_nocontext): Likewise.
+       (omp_construct_selector_matches): Handle OMP_DISPATCH with nocontext
+       clause.
+       (find_ifn_gomp_dispatch): New function.
+       (gimplify_omp_dispatch): Likewise.
+       (gimplify_expr): Handle OMP_DISPATCH.
+       * gimplify.h (omp_has_novariants): Declare.
+       * internal-fn.cc (expand_GOMP_DISPATCH): New function.
+       * internal-fn.def (GOMP_DISPATCH): Define.
+       * omp-builtins.def (BUILT_IN_OMP_GET_MAPPED_PTR): Define.
+       (BUILT_IN_OMP_GET_DEFAULT_DEVICE): Define.
+       (BUILT_IN_OMP_SET_DEFAULT_DEVICE): Define.
+       * omp-general.cc (omp_construct_traits_to_codes): Add OMP_DISPATCH.
+       (struct omp_ts_info): Add dispatch.
+       (omp_resolve_declare_variant): Handle novariants. Adjust
+       DECL_ASSEMBLER_NAME.
+       * omp-low.cc (scan_omp_1_stmt): Handle GIMPLE_OMP_DISPATCH.
+       (lower_omp_dispatch): New function.
+       (lower_omp_1): Call it.
+       * tree-inline.cc (remap_gimple_stmt): Handle GIMPLE_OMP_DISPATCH.
+       (estimate_num_insns): Handle GIMPLE_OMP_DISPATCH.
+
+2024-11-20  Paul-Antoine Arras  <parras@baylibre.com>
+
+       * builtin-types.def (BT_FN_PTR_CONST_PTR_INT): New.
+       * omp-selectors.h (enum omp_ts_code): Add OMP_TRAIT_CONSTRUCT_DISPATCH.
+       * tree-core.h (enum omp_clause_code): Add OMP_CLAUSE_NOVARIANTS and
+       OMP_CLAUSE_NOCONTEXT.
+       * tree-pretty-print.cc (dump_omp_clause): Handle OMP_CLAUSE_NOVARIANTS
+       and OMP_CLAUSE_NOCONTEXT.
+       (dump_generic_node): Handle OMP_DISPATCH.
+       * tree.cc (omp_clause_num_ops): Add OMP_CLAUSE_NOVARIANTS and
+       OMP_CLAUSE_NOCONTEXT.
+       (omp_clause_code_name): Add "novariants" and "nocontext".
+       * tree.def (OMP_DISPATCH): New.
+       * tree.h (OMP_DISPATCH_BODY): New macro.
+       (OMP_DISPATCH_CLAUSES): New macro.
+       (OMP_CLAUSE_NOVARIANTS_EXPR): New macro.
+       (OMP_CLAUSE_NOCONTEXT_EXPR): New macro.
+
+2024-11-20  Richard Sandiford  <richard.sandiford@arm.com>
+
+       * config/aarch64/aarch64-option-extensions.def (sme2p1): New extension.
+       * doc/invoke.texi: Document it.
+       * config/aarch64/aarch64.h (TARGET_STREAMING_SME2p1): New macro.
+       * config/aarch64/aarch64-c.cc (aarch64_update_cpp_builtins):
+       Conditionally define __ARM_FEATURE_SME2p1.
+       * config/aarch64/iterators.md (UNSPEC_SME_READZ, UNSPEC_SME_READZ_HOR)
+       (UNSPEC_SME_READZ_VER): New unspecs.
+       (optab, hv): Handle them.
+       (SME_READZ_HV): New int iterator.
+       * config/aarch64/aarch64-sme.md
+       (UNSPEC_SME_ZERO_SLICES): New unspec.
+       (@aarch64_sme_<SME_READZ_HV:optab><v_int_container><mode>)
+       (*aarch64_sme_<SME_READZ_HV:optab><v_int_container><mode>_plus)
+       (@aarch64_sme_<SME_READZ_HV:optab><VNx1TI_ONLY:mode><SVE_FULL:mode>)
+       (@aarch64_sme_<SME_READZ_HV:optab><SVE_FULLx24:mode><mode>)
+       (*aarch64_sme_<SME_READZ_HV:optab><SVE_FULLx24:mode><mode>_plus)
+       (@aarch64_sme_readz<mode>, *aarch64_sme_readz<mode>_plus)
+       (@aarch64_sme_zero_za_slices<mode>): New patterns.
+       (*aarch64_sme_zero_za_slices<mode>_plus): Likewise.
+       * config/aarch64/aarch64-sve-builtins-shapes.h
+       (inherent_za_slice): Declare.
+       * config/aarch64/aarch64-sve-builtins-shapes.cc
+       (inherent_za_slice_def, inherent_za_slice): New shape.
+       * config/aarch64/aarch64-sve-builtins-sme.h (svreadz_za)
+       (svreadz_hor_za, svreadz_ver_za): Declare.
+       * config/aarch64/aarch64-sve-builtins-sme.cc
+       (svread_za_slice_base): New class, split out from...
+       (svread_za_impl): ...here.
+       (svreadz_za_impl, svreadz_za_tile_impl): New type aliases.
+       (zero_slices_mode): New function.
+       (svzero_za_impl::expand): Handle the slice forms.
+       (svreadz_za, svreadz_hor_za, svreadz_ver_za): New functions.
+       * config/aarch64/aarch64-sve-builtins-sme.def: Add the SME2p1
+       instructions.
+
+2024-11-20  Richard Sandiford  <richard.sandiford@arm.com>
+
+       * config/aarch64/aarch64-option-extensions.def
+       (sme-b16b16): New extension.
+       * doc/invoke.texi: Document it.
+       * config/aarch64/aarch64.h (TARGET_STREAMING_SME_B16B16): New macro.
+       * config/aarch64/aarch64-c.cc (aarch64_update_cpp_builtins):
+       Conditionally define __ARM_FEATURE_SME_B16B16.
+       * config/aarch64/aarch64-sve-builtins-sme.def: Add SME_B16B16 forms
+       of existing intrinsics.
+       * config/aarch64/aarch64-sme.md
+       (@aarch64_sme_<SME_BINARY_SLICE_HSDF:optab><mode>)
+       (*aarch64_sme_<SME_BINARY_SLICE_HSDF:optab><mode>_plus)
+       (@aarch64_sme_<SME_FP_TERNARY_SLICE:optab><mode><mode>)
+       (*aarch64_sme_<SME_FP_TERNARY_SLICE:optab><mode><mode>_plus)
+       (@aarch64_sme_single_<SME_FP_TERNARY_SLICE:optab><mode><mode>)
+       (*aarch64_sme_single_<SME_FP_TERNARY_SLICE:optab><mode><mode>_plus)
+       (@aarch64_sme_lane_<SME_FP_TERNARY_SLICE:optab><mode><mode>)
+       (*aarch64_sme_lane_<SME_FP_TERNARY_SLICE:optab><mode><mode>)
+       (@aarch64_sme_<SME_FP_MOP:optab><mode><mode>): Extend to BF16 modes.
+       * config/aarch64/aarch64-sve-builtins.cc (TYPES_za_h_bfloat): New
+       type macro.
+       * config/aarch64/iterators.md (SME_ZA_HSDFx24): Add BF16 modes.
+       (SME_MOP_HSDF): Likewise.
+
+2024-11-20  Richard Sandiford  <richard.sandiford@arm.com>
+
+       * config/aarch64/aarch64-option-extensions.def
+       (sme-f16f16): New extension.
+       * doc/invoke.texi: Document it.  Also document that sme-i16i64 and
+       sme-f64f64 enable SME.
+       * config/aarch64/aarch64.h (TARGET_STREAMING_SME_F16F16): New macro.
+       * config/aarch64/aarch64-c.cc (aarch64_update_cpp_builtins):
+       Conditionally define __ARM_FEATURE_SME_F16F16.
+       * config/aarch64/aarch64-sve-builtins-sve2.def (svcvt, svcvtl): Add
+       new SME_F16F16 intrinsics.
+       * config/aarch64/aarch64-sve-builtins-sme.def: Add SME_F16F16 forms
+       of existing intrinsics.
+       * config/aarch64/aarch64-sve-builtins.cc (TYPES_h_float)
+       (TYPES_cvt_f32_f16, TYPES_za_h_float): New type macros.
+       * config/aarch64/aarch64-sve-builtins-base.cc
+       (svcvt_impl::expand): Add sext_optab as another possibility.
+       * config/aarch64/aarch64-sve-builtins-sve2.h (svcvtl): Declare.
+       * config/aarch64/aarch64-sve-builtins-sve2.cc (svcvtl_impl): New class.
+       (svcvtl): New function.
+       * config/aarch64/iterators.md (VNx8SF_ONLY): New mode iterator.
+       (SME_ZA_SDFx24): Replace with...
+       (SME_ZA_HSDFx24): ...this.
+       (SME_MOP_SDF): Replace with...
+       (SME_MOP_HSDF): ...this.
+       (SME_BINARY_SLICE_SDF): Replace with...
+       (SME_BINARY_SLICE_HSDF): ...this.
+       * config/aarch64/aarch64-sve2.md (extendvnx8hfvnx8sf2)
+       (@aarch64_sve_cvtl<mode>): New patterns.
+       * config/aarch64/aarch64-sme.md
+       (@aarch64_sme_<SME_BINARY_SLICE_SDF:optab><mode>): Extend to...
+       (@aarch64_sme_<SME_BINARY_SLICE_HSDF:optab><mode>): ...this.
+       (*aarch64_sme_<SME_BINARY_SLICE_SDF:optab><mode>_plus): Extend to...
+       (*aarch64_sme_<SME_BINARY_SLICE_HSDF:optab><mode>_plus): ...this.
+       (@aarch64_sme_<SME_FP_TERNARY_SLICE:optab><mode><mode>): Extend to
+       HF modes.
+       (*aarch64_sme_<SME_FP_TERNARY_SLICE:optab><mode><mode>_plus)
+       (@aarch64_sme_single_<SME_FP_TERNARY_SLICE:optab><mode><mode>)
+       (*aarch64_sme_single_<SME_FP_TERNARY_SLICE:optab><mode><mode>_plus)
+       (@aarch64_sme_lane_<SME_FP_TERNARY_SLICE:optab><mode><mode>)
+       (*aarch64_sme_lane_<SME_FP_TERNARY_SLICE:optab><mode><mode>)
+       (@aarch64_sme_<SME_FP_MOP:optab><mode><mode>): Likewise.
+
+2024-11-20  Richard Sandiford  <richard.sandiford@arm.com>
+
+       * config/aarch64/aarch64-option-extensions.def
+       (sve-b16b16): New extension.
+       * doc/invoke.texi: Document it.
+       * config/aarch64/aarch64.h (TARGET_SME_B16B16, TARGET_SVE2_OR_SME2)
+       (TARGET_SSVE_B16B16): New macros.
+       * config/aarch64/aarch64-c.cc (aarch64_update_cpp_builtins):
+       Conditionally define __ARM_FEATURE_SVE_B16B16
+       * config/aarch64/aarch64-sve-builtins-sve2.def: Add AARCH64_FL_SVE2
+       to the SVE2p1 requirements.  Add SVE_B16B16 forms of existing
+       intrinsics.
+       * config/aarch64/aarch64-sve-builtins.cc (type_suffixes): Treat
+       bfloat as a floating-point type.
+       (TYPES_h_bfloat): New macro.
+       * config/aarch64/aarch64.md (is_bf16, is_rev, supports_bf16_rev)
+       (mode_enabled): New attributes.
+       (enabled): Test mode_enabled.
+       * config/aarch64/iterators.md (SVE_FULL_F_BF): New mode iterator.
+       (SVE_CLAMP_F): Likewise.
+       (SVE_Fx24): Add BF16 modes when TARGET_SSVE_B16B16.
+       (sve_lane_con): Handle BF16 modes.
+       (b): Handle SF and DF modes.
+       (is_bf16): New mode attribute.
+       (supports_bf16, supports_bf16_rev): New int attributes.
+       * config/aarch64/predicates.md
+       (aarch64_sve_float_maxmin_immediate): Reject BF16 modes.
+       * config/aarch64/aarch64-sve.md
+       (*post_ra_<sve_fp_op><mode>3): Add BF16 support, and likewise
+       for the associated define_split.
+       (<optab:SVE_COND_FP_BINARY_OPTAB><mode>): Add BF16 support.
+       (@cond_<optab:SVE_COND_FP_BINARY><mode>): Likewise.
+       (*cond_<optab:SVE_COND_FP_BINARY><mode>_2_relaxed): Likewise.
+       (*cond_<optab:SVE_COND_FP_BINARY><mode>_2_strict): Likewise.
+       (*cond_<optab:SVE_COND_FP_BINARY><mode>_3_relaxed): Likewise.
+       (*cond_<optab:SVE_COND_FP_BINARY><mode>_3_strict): Likewise.
+       (*cond_<optab:SVE_COND_FP_BINARY><mode>_any_relaxed): Likewise.
+       (*cond_<optab:SVE_COND_FP_BINARY><mode>_any_strict): Likewise.
+       (@aarch64_mul_lane_<mode>): Likewise.
+       (<optab:SVE_COND_FP_TERNARY><mode>): Likewise.
+       (@aarch64_pred_<optab:SVE_COND_FP_TERNARY><mode>): Likewise.
+       (@cond_<optab:SVE_COND_FP_TERNARY><mode>): Likewise.
+       (*cond_<optab:SVE_COND_FP_TERNARY><mode>_4_relaxed): Likewise.
+       (*cond_<optab:SVE_COND_FP_TERNARY><mode>_4_strict): Likewise.
+       (*cond_<optab:SVE_COND_FP_TERNARY><mode>_any_relaxed): Likewise.
+       (*cond_<optab:SVE_COND_FP_TERNARY><mode>_any_strict): Likewise.
+       (@aarch64_<optab:SVE_FP_TERNARY_LANE>_lane_<mode>): Likewise.
+       * config/aarch64/aarch64-sve2.md
+       (@aarch64_pred_<optab:SVE_COND_FP_BINARY><mode>): Define BF16 version.
+       (@aarch64_sve_fclamp<mode>): Add BF16 support.
+       (*aarch64_sve_fclamp<mode>_x): Likewise.
+       (*aarch64_sve_<maxmin_uns_op><SVE_Fx24:mode>): Likewise.
+       (*aarch64_sve_single_<maxmin_uns_op><SVE_Fx24:mode>): Likewise.
+       * config/aarch64/aarch64.cc (aarch64_sve_float_arith_immediate_p)
+       (aarch64_sve_float_mul_immediate_p): Return false for BF16 modes.
+
+2024-11-20  Richard Sandiford  <richard.sandiford@arm.com>
+
+       * config/aarch64/aarch64-sme.md (@aarch64_sme_write<mode>)
+       (*aarch64_sme_write<mode>_plus): Use UNSPEC_SME_WRITE instead
+       of UNSPEC_SME_READ.
+
+2024-11-20  Richard Sandiford  <richard.sandiford@arm.com>
+
+       * config/aarch64/iterators.md (SME_READ): Rename to...
+       (SME_READ_HV): ...this.
+       (SME_WRITE): Rename to...
+       (SME_WRITE_HV): ...this.
+       * config/aarch64/aarch64-sme.md: Update accordingly.
+
+2024-11-20  Richard Sandiford  <richard.sandiford@arm.com>
+
+       * config/aarch64/iterators.md (SVE_COND_FP): New code attribute.
+       * config/aarch64/aarch64-sve.md: Use a single define_split to
+       handle the conversion of predicated FADD, FSUB, and FMUL into
+       unpredicated forms.
+
+2024-11-20  Richard Sandiford  <richard.sandiford@arm.com>
+
+       * config/aarch64/iterators.md (SME_ZA_SDF_I): Delete.
+       (SME_MOP_HSDF): Replace with...
+       (SME_MOP_SDF): ...this.
+       * config/aarch64/aarch64-sme.md: Change the non-widening FMLA and
+       FMLS patterns so that both mode parameters are the same, rather than
+       using both SME_ZA_SDF_I and SME_ZA_SDFx24 and checking that their
+       element sizes are the same.  Split the FMOPA and FMOPS patterns
+       into separate non-widening and widening forms, then update the
+       non-widening forms in a similar way to FMLA and FMLS.
+       * config/aarch64/aarch64-sve-builtins-functions.h
+       (sme_2mode_function_t::expand): If the two type suffixes have the same
+       element size, use the vector tuple mode for both mode parameters.
+
+2024-11-20  Uros Bizjak  <ubizjak@gmail.com>
+
+       * config/i386/i386.cc (legitimize_tls_address)
+       <TLS_MODEL_INITIAL_EXEC>: Remove 64-bit Solaris ld workaround.
+       * config/i386/i386.md (UNSPEC_TLS_IE_SUN): Remove.
+       (tls_initial_exec_64_sun): Remove.
+
+2024-11-20  Richard Biener  <rguenther@suse.de>
+
+       PR tree-optimization/117574
+       * tree-ssa-loop-niter.cc (number_of_iterations_lt_to_ne):
+       Use the obvious may_be_zero condition.
+
+2024-11-20  Richard Sandiford  <richard.sandiford@arm.com>
+
+       * machmode.h (opt_mode::opt_mode): New overload.
+       * optabs-query.h (get_absneg_bit_mode): Declare.
+       * optabs-query.cc (get_absneg_bit_mode): New function, split
+       out from expand_absneg_bit.
+       (can_open_code_p): Use get_absneg_bit_mode.
+       * optabs.cc (expand_absneg_bit): Likewise.  Take an outer and inner
+       mode, rather than just one.  Handle vector modes.
+       (expand_unop, expand_abs_nojump): Update calls accordingly.
+       Handle vector modes.
+
+2024-11-20  Richard Sandiford  <richard.sandiford@arm.com>
+
+       * tree-vect-data-refs.cc (vect_supportable_dr_alignment): Use
+       can_implement_p instead of optab_handler.
+       * tree-vect-generic.cc (add_rshift, expand_vector_divmod): Likewise.
+       (optimize_vector_constructor, type_for_widest_vector_mode): Likewise.
+       (lower_vec_perm, expand_vector_operations_1): Likewise.
+       * tree-vect-loop.cc (have_whole_vector_shift): Likewise.
+       * tree-vect-patterns.cc (vect_recog_rotate_pattern): Likewise.
+       (target_has_vecop_for_code, vect_recog_mult_pattern): Likewise.
+       (vect_recog_divmod_pattern): Likewise.
+       * tree-vect-stmts.cc (vect_supportable_shift, vectorizable_shift)
+       (scan_store_can_perm_p, check_scan_store, vectorizable_store)
+       (vectorizable_load, vectorizable_condition): Likewise.
+       (vectorizable_comparison_1): Likewise.
+
+2024-11-20  Richard Sandiford  <richard.sandiford@arm.com>
+
+       * optabs-query.cc (can_open_code_p, can_implement_p): Declare.
+       * optabs-query.h (can_open_code_p, can_implement_p): New functions.
+       * optabs-tree.cc (target_supports_op_p): Use can_implement_p.
+       * tree-vect-stmts.cc (vectorizable_operation): Likewise.
+       * tree-vect-generic.cc (get_compute_type): Likewise.  Remove code
+       parameter.
+       (expand_vector_scalar_condition, expand_vector_conversion)
+       (expand_vector_operations_1): Update calls accordingly.
+
+2024-11-20  Andre Vieira  <andre.simoesdiasvieira@arm.com>
+
+       * config/arm/arm.cc (arm_mve_dlstp_check_dec_counter): Call
+       single_pred_p to verify it's safe to call single_pred.
+
+2024-11-20  Feng Wang  <wangfeng@eswincomputing.com>
+
+       PR target/117669
+       * config/riscv/vector-iterators.md:
+
+2024-11-20  MayShao-oc  <MayShao-oc@zhaoxin.com>
+
+       PR target/117438
+       * config/i386/i386-features.cc (TARGET_ALIGN_TIGHT_LOOPS):
+       default true in all processors except for m_ZHAOXIN, m_CASCADELAKE, and
+       m_SKYLAKE_AVX512.
+       * config/i386/i386.h (TARGET_ALIGN_TIGHT_LOOPS): New Macro.
+       * config/i386/x86-tune.def (X86_TUNE_ALIGN_TIGHT_LOOPS):
+       New tune
+
+2024-11-20  yulong  <shiyulong@iscas.ac.cn>
+
+       * common/config/riscv/riscv-common.cc: New.
+       * config/riscv/riscv.opt: New.
+
+2024-11-20  Jeff Law  <jlaw@ventanamicro.com>
+
+       PR target/117649
+       * config/riscv/riscv.md (branch on masked/shifted operands): Use
+       arithmetic rather than logical shift for operand 1.
+
 2024-11-19  Georg-Johann Lay  <avr@gjlay.de>
 
        PR target/54378

diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP
index 837c384969573f559ca769d713dff5c8bcc70cd4..5116abdc66f4e32b83f756382a6ecfaeccd464a8 100644 (file)
--- a/gcc/DATESTAMP
+++ b/gcc/DATESTAMP
@@ -1 +1 @@
-20241120
+20241121

diff --git a/gcc/ada/ChangeLog b/gcc/ada/ChangeLog
index 52f08f8dbcf3ddfc57bc5496a4c2eaee2b117245..c41fbb8bc2115f35e9690adc848a60ea6ae4bd15 100644 (file)
--- a/gcc/ada/ChangeLog
+++ b/gcc/ada/ChangeLog
@@ -1,3 +1,20 @@
+2024-11-20  Eric Botcazou  <ebotcazou@adacore.com>
+
+       PR ada/117538
+       PR ada/117708
+       * Makefile.rtl (GNU Hurd): Add $(TRASYM_DWARF_UNIX_PAIRS).
+       (x86-64 kfreebsd): Likewise.
+       (aarch64 FreeBSD): Likewise.
+       (x86-64 DragonFly): Likewise.
+       (S390 Linux): Likewise and add Linux version of s-tsmona.adb.
+       (Mips Linux): Likewise.
+       (SPARC Linux): Likewise.
+       (HP/PA Linux): Linux.
+       (M68K Linux): Likewise.
+       (SH4 Linux): Likewise.
+       (Alpha Linux): Likewise.
+       (RISC-V Linux): Likewise.
+
 2024-11-19  Eric Botcazou  <ebotcazou@adacore.com>
 
        PR ada/117538

diff --git a/gcc/c-family/ChangeLog b/gcc/c-family/ChangeLog
index bb688d5334e36f1ec4b6864079f38ece7a9fe53d..9bb99f9546744723c08e070b4069eb3940d4d218 100644 (file)
--- a/gcc/c-family/ChangeLog
+++ b/gcc/c-family/ChangeLog
@@ -1,3 +1,13 @@
+2024-11-20  Paul-Antoine Arras  <parras@baylibre.com>
+
+       * c-attribs.cc (c_common_gnu_attributes): Add attribute for adjust_args
+       need_device_ptr.
+       * c-omp.cc (c_omp_directives): Uncomment dispatch.
+       * c-pragma.cc (omp_pragmas): Add dispatch.
+       * c-pragma.h (enum pragma_kind): Add PRAGMA_OMP_DISPATCH.
+       (enum pragma_omp_clause): Add PRAGMA_OMP_CLAUSE_NOCONTEXT and
+       PRAGMA_OMP_CLAUSE_NOVARIANTS.
+
 2024-11-19  Jakub Jelinek  <jakub@redhat.com>
 
        PR c/117641

diff --git a/gcc/c/ChangeLog b/gcc/c/ChangeLog
index 6bac14abde41ae0b57d1414291ab128617887c26..4289945062ccca29939f5d598ff7814ae751aebc 100644 (file)
--- a/gcc/c/ChangeLog
+++ b/gcc/c/ChangeLog
@@ -1,3 +1,31 @@
+2024-11-20  Joseph Myers  <josmyers@redhat.com>
+
+       PR c/114266
+       * c-decl.cc (build_compound_literal): Diagnose array of unknown
+       size with empty initializer for C23.
+
+2024-11-20  Paul-Antoine Arras  <parras@baylibre.com>
+
+       * c-parser.cc (c_parser_omp_dispatch): New function.
+       (c_parser_omp_clause_name): Handle nocontext and novariants clauses.
+       (c_parser_omp_clause_novariants): New function.
+       (c_parser_omp_clause_nocontext): Likewise.
+       (c_parser_omp_all_clauses): Handle nocontext and novariants clauses.
+       (c_parser_omp_dispatch_body): New function adapted from
+       c_parser_expr_no_commas.
+       (OMP_DISPATCH_CLAUSE_MASK): Define.
+       (c_parser_omp_dispatch): New function.
+       (c_finish_omp_declare_variant): Parse adjust_args.
+       (c_parser_omp_construct): Handle PRAGMA_OMP_DISPATCH.
+       * c-typeck.cc (c_finish_omp_clauses): Handle OMP_CLAUSE_NOVARIANTS and
+       OMP_CLAUSE_NOCONTEXT.
+
+2024-11-20  Joseph Myers  <josmyers@redhat.com>
+
+       PR c/115515
+       * c-typeck.cc (check_constexpr_init): Do not call int_fits_type_p
+       for arguments that are not integer constant expressions.
+
 2024-11-19  Joseph Myers  <josmyers@redhat.com>
 
        PR c/114869

diff --git a/gcc/cp/ChangeLog b/gcc/cp/ChangeLog
index 1ce7e6b9ea9e4d7b8cc722ef913249bff62f1ae6..67061e0db0c9370a4504023e132455e242d2015a 100644 (file)
--- a/gcc/cp/ChangeLog
+++ b/gcc/cp/ChangeLog
@@ -1,3 +1,33 @@
+2024-11-20  Paul-Antoine Arras  <parras@baylibre.com>
+
+       * decl.cc (omp_declare_variant_finalize_one): Set adjust_args
+       need_device_ptr attribute.
+       * parser.cc (cp_parser_direct_declarator): Update call to
+       cp_parser_late_return_type_opt.
+       (cp_parser_late_return_type_opt): Add 'tree parms' parameter. Update
+       call to cp_parser_late_parsing_omp_declare_simd.
+       (cp_parser_omp_clause_name): Handle nocontext and novariants clauses.
+       (cp_parser_omp_clause_novariants): New function.
+       (cp_parser_omp_clause_nocontext): Likewise.
+       (cp_parser_omp_all_clauses): Handle PRAGMA_OMP_CLAUSE_NOVARIANTS and
+       PRAGMA_OMP_CLAUSE_NOCONTEXT.
+       (cp_parser_omp_dispatch_body): New function, inspired from
+       cp_parser_assignment_expression and cp_parser_postfix_expression.
+       (OMP_DISPATCH_CLAUSE_MASK): Define.
+       (cp_parser_omp_dispatch): New function.
+       (cp_finish_omp_declare_variant): Add parameter. Handle adjust_args
+       clause.
+       (cp_parser_late_parsing_omp_declare_simd): Add parameter. Update calls
+       to cp_finish_omp_declare_variant and cp_finish_omp_declare_variant.
+       (cp_parser_omp_construct): Handle PRAGMA_OMP_DISPATCH.
+       (cp_parser_pragma): Likewise.
+       * semantics.cc (finish_omp_clauses): Handle OMP_CLAUSE_NOCONTEXT and
+       OMP_CLAUSE_NOVARIANTS.
+       * pt.cc (tsubst_omp_clauses): Handle OMP_CLAUSE_NOCONTEXT and
+       OMP_CLAUSE_NOVARIANTS.
+       (tsubst_stmt): Handle OMP_DISPATCH.
+       (tsubst_expr): Handle IFN_GOMP_DISPATCH.
+
 2024-11-19  Jason Merrill  <jason@redhat.com>
 
        * decl2.cc (cp_handle_deprecated_or_unavailable): Avoid redundant

diff --git a/gcc/fortran/ChangeLog b/gcc/fortran/ChangeLog
index 968883f4ddfdc0fe67979716fe651306f9fdf48e..fce3ebd2fecee34378efb55e4f327af9f34dc9df 100644 (file)
--- a/gcc/fortran/ChangeLog
+++ b/gcc/fortran/ChangeLog
@@ -1,3 +1,29 @@
+2024-11-20  Harald Anlauf  <anlauf@gmx.de>
+
+       PR fortran/83135
+       * expr.cc (sym_is_from_ancestor): New helper function.
+       (gfc_check_vardef_context): Refine checking of PROTECTED attribute
+       of symbols that are indirectly use-associated in a submodule.
+
+2024-11-20  Paul-Antoine Arras  <parras@baylibre.com>
+
+       * types.def (BT_FN_PTR_CONST_PTR_INT): Declare.
+
+2024-11-20  Mikael Morin  <mikael@gcc.gnu.org>
+
+       PR fortran/90608
+       * trans-intrinsic.cc
+       (walk_inline_intrinsic_minmaxloc): Add a scalar element for BACK as
+       first item of the chain if BACK is present and there will be nested
+       loops.
+       (gfc_conv_intrinsic_minmaxloc): Evaluate BACK using an inherited
+       scalarization chain if there is a nested loop.
+
+2024-11-20  Mikael Morin  <mikael@gcc.gnu.org>
+
+       * trans-intrinsic.cc (gfc_conv_intrinsic_minmaxloc): Only get the size
+       along DIM instead of the full size if DIM is present.
+
 2024-11-19  Mikael Morin  <mikael@gcc.gnu.org>
 
        PR fortran/90608

diff --git a/gcc/jit/ChangeLog b/gcc/jit/ChangeLog
index 3b6eb6ea37f64ad986fd1e1b9add06b8aff15557..3502edd750550e22a5416144dc8bf18df9087ecc 100644 (file)
--- a/gcc/jit/ChangeLog
+++ b/gcc/jit/ChangeLog
@@ -1,3 +1,133 @@
+2024-11-20  Antoni Boucher  <bouanto@zoho.com>
+
+       * docs/topics/compatibility.rst (LIBGCCJIT_ABI_34): New ABI tag.
+       * docs/topics/contexts.rst: Document gcc_jit_context_set_output_ident.
+       * jit-playback.cc (set_output_ident): New method.
+       * jit-playback.h (set_output_ident): New method.
+       * jit-recording.cc (recording::context::set_output_ident,
+       recording::output_ident::output_ident,
+       recording::output_ident::~output_ident,
+       recording::output_ident::replay_into,
+       recording::output_ident::make_debug_string,
+       recording::output_ident::write_reproducer): New methods.
+       * jit-recording.h (class output_ident): New class.
+       * libgccjit.cc (gcc_jit_context_set_output_ident): New function.
+       * libgccjit.h (gcc_jit_context_set_output_ident): New function.
+       * libgccjit.map: New function.
+
+2024-01-18  Antoni Boucher  <bouanto@zoho.com>
+
+       * docs/topics/compatibility.rst (LIBGCCJIT_ABI_33): New ABI tag.
+       * docs/topics/functions.rst: Document gcc_jit_function_new_temp.
+       * jit-playback.cc (new_local): Add support for temporary
+       variables.
+       * jit-recording.cc (recording::function::new_temp): New method.
+       (recording::local::write_reproducer): Support temporary
+       variables.
+       * jit-recording.h (new_temp): New method.
+       * libgccjit.cc (gcc_jit_function_new_temp): New function.
+       * libgccjit.h (gcc_jit_function_new_temp): New function.
+       * libgccjit.map: New function.
+
+2024-11-20  Antoni Boucher  <bouanto@zoho.com>
+
+       PR jit/108762
+       * docs/topics/compatibility.rst (LIBGCCJIT_ABI_32): New ABI tag.
+       * docs/topics/functions.rst: Add documentation for the function
+       gcc_jit_context_get_target_builtin_function.
+       * dummy-frontend.cc: Include headers target.h, jit-recording.h,
+       print-tree.h, unordered_map and string, new variables (target_builtins,
+       target_function_types, and target_builtins_ctxt), new function
+       (tree_type_to_jit_type).
+       * jit-builtins.cc: Specify that the function types are not from
+       target builtins.
+       * jit-playback.cc: New argument is_target_builtin to new_function.
+       * jit-playback.h: New argument is_target_builtin to
+       new_function.
+       * jit-recording.cc: New argument is_target_builtin to
+       new_function_type, function_type constructor and function
+       constructor, new function
+       (get_target_builtin_function).
+       * jit-recording.h: Include headers string and unordered_map, new
+       variable target_function_types, new argument is_target_builtin
+       to new_function_type, function_type and function, new functions
+       (get_target_builtin_function, copy).
+       * libgccjit.cc: New function
+       (gcc_jit_context_get_target_builtin_function).
+       * libgccjit.h: New function
+       (gcc_jit_context_get_target_builtin_function).
+       * libgccjit.map: New functions
+       (gcc_jit_context_get_target_builtin_function).
+
+2024-11-20  Antoni Boucher  <bouanto@zoho.com>
+
+       * jit-common.h: Add forward declaration of memento_of_get_aligned.
+       * jit-recording.h (type::is_same_type_as): Compare integer
+       types.
+       (dyn_cast_aligned_type): New method.
+       (type::is_aligned, memento_of_get_aligned::is_same_type_as,
+       memento_of_get_aligned::is_aligned): new methods.
+
+2024-11-20  Antoni Boucher  <bouanto@zoho.com>
+
+       * docs/topics/contexts.rst: Add documentation for new option.
+       * jit-recording.cc (recording::context::get_str_option): New
+       method.
+       * jit-recording.h (get_str_option): New method.
+       * libgccjit.cc (gcc_jit_context_new_function): Allow special
+       characters in function names.
+       * libgccjit.h (enum gcc_jit_str_option): New option.
+
+2024-11-20  Antoni Boucher  <bouanto@zoho.com>
+
+       PR jit/112602
+       * docs/topics/compatibility.rst (LIBGCCJIT_ABI_31): New ABI tag.
+       * docs/topics/expressions.rst: Document
+       gcc_jit_context_new_rvalue_vector_perm and
+       gcc_jit_context_new_vector_access.
+       * jit-playback.cc (playback::context::new_rvalue_vector_perm,
+       common_mark_addressable_vec,
+       gnu_vector_type_p,
+       lvalue_p,
+       convert_vector_to_array_for_subscript,
+       new_vector_access): new functions.
+       * jit-playback.h (new_rvalue_vector_perm, new_vector_access):
+       New functions.
+       * jit-recording.cc (recording::context::new_rvalue_vector_perm,
+       recording::context::new_vector_access,
+       memento_of_new_rvalue_vector_perm,
+       recording::memento_of_new_rvalue_vector_perm::replay_into,
+       recording::memento_of_new_rvalue_vector_perm::visit_children,
+       recording::memento_of_new_rvalue_vector_perm::make_debug_string,
+       recording::memento_of_new_rvalue_vector_perm::write_reproducer,
+       recording::vector_access::replay_into,
+       recording::vector_access::visit_children,
+       recording::vector_access::make_debug_string,
+       recording::vector_access::write_reproducer): New methods.
+       * jit-recording.h (class memento_of_new_rvalue_vector_perm,
+       class vector_access): New classes.
+       * libgccjit.cc (gcc_jit_context_new_vector_access,
+       gcc_jit_context_new_rvalue_vector_perm): New functions.
+       * libgccjit.h (gcc_jit_context_new_rvalue_vector_perm,
+       gcc_jit_context_new_vector_access): New functions.
+       * libgccjit.map: New functions.
+
+2024-11-20  Antoni Boucher  <bouanto@zoho.com>
+
+       PR jit/113343
+       * jit-playback.cc (new_rvalue_from_const): Fix to have the
+       correct value when cross-compiling.
+
+2024-11-20  Antoni Boucher  <bouanto@zoho.com>
+
+       * libgccjit.cc (RETURN_IF_FAIL_PRINTF3): New macro.
+       (gcc_jit_block_add_assignment_op): Add numeric checks.
+
+2024-11-20  Antoni Boucher  <bouanto@zoho.com>
+
+       * dummy-frontend.cc (jit_langhook_init): Send flag_signed_char
+       argument to build_common_tree_nodes.
+
 2024-11-04  Antoni Boucher  <bouanto@zoho.com>
 
        * docs/topics/compatibility.rst (LIBGCCJIT_ABI_30): New ABI tag.

diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index 467bd64f1aa97e965523ddeebf6eec497401b16b..e9ba4e2da06f69dd8b17d292d44b09891bf26fa3 100644 (file)
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,1088 @@
+2024-11-20  Harald Anlauf  <anlauf@gmx.de>
+
+       PR fortran/83135
+       * gfortran.dg/protected_10.f90: New test.
+
+2024-11-20  Joseph Myers  <josmyers@redhat.com>
+
+       PR c/114266
+       * gcc.dg/c23-empty-init-4.c: New test.
+
+2024-11-20  Antoni Boucher  <bouanto@zoho.com>
+
+       * jit.dg/all-non-failing-tests.h: New test.
+       * jit.dg/test-output-ident.c: New test.
+
+2024-01-18  Antoni Boucher  <bouanto@zoho.com>
+
+       * jit.dg/all-non-failing-tests.h: Mention test-temp.c.
+       * jit.dg/test-temp.c: New test.
+
+2024-11-20  Vladimir N. Makarov  <vmakarov@redhat.com>
+
+       PR target/116587
+       * gcc.target/i386/pr116587.c: New test.
+
+2024-11-20  Antoni Boucher  <bouanto@zoho.com>
+
+       PR jit/108762
+       * jit.dg/all-non-failing-tests.h: New test test-target-builtins.c.
+       * jit.dg/test-target-builtins.c: New test.
+
+2024-11-20  Andrew Pinski  <quic_apinski@quicinc.com>
+
+       PR testsuite/117680
+       * gcc.target/aarch64/pic-constantpool1.c: Add -Wno-old-style-definition.
+       * gcc.target/aarch64/pic-symrefplus.c: Likewise.
+       * gcc.target/aarch64/pr113573.c: Add `-std=gnu17`
+       * gcc.target/aarch64/sme/streaming_mode_1.c: Correct testcase.
+       * gcc.target/aarch64/sme/za_state_1.c: Likewise.
+       * gcc.target/aarch64/sme/za_state_2.c: Likewise.
+
+2024-11-20  Edwin Lu  <ewlu@rivosinc.com>
+
+       * gcc.target/riscv/pr117595.c: Restrict to non vector targets.
+
+2024-11-20  Antoni Boucher  <bouanto@zoho.com>
+
+       * jit.dg/test-types.c: Add checks comparing aligned types.
+
+2024-11-20  Antoni Boucher  <bouanto@zoho.com>
+
+       * jit.dg/test-special-chars.c: New test.
+
+2024-11-20  Antoni Boucher  <bouanto@zoho.com>
+
+       PR jit/112602
+       * jit.dg/all-non-failing-tests.h: New test test-vector-perm.c.
+       * jit.dg/test-vector-perm.c: New test.
+
+2024-11-20  Paul-Antoine Arras  <parras@baylibre.com>
+
+       * c-c++-common/gomp/declare-variant-2.c: Adjust dg-error directives.
+       * c-c++-common/gomp/adjust-args-1.c: New test.
+       * c-c++-common/gomp/adjust-args-2.c: New test.
+       * c-c++-common/gomp/declare-variant-dup-match-clause.c: New test.
+       * c-c++-common/gomp/dispatch-1.c: New test.
+       * c-c++-common/gomp/dispatch-2.c: New test.
+       * c-c++-common/gomp/dispatch-3.c: New test.
+       * c-c++-common/gomp/dispatch-4.c: New test.
+       * c-c++-common/gomp/dispatch-5.c: New test.
+       * c-c++-common/gomp/dispatch-6.c: New test.
+       * c-c++-common/gomp/dispatch-7.c: New test.
+       * c-c++-common/gomp/dispatch-8.c: New test.
+       * c-c++-common/gomp/dispatch-9.c: New test.
+       * c-c++-common/gomp/dispatch-10.c: New test.
+
+2024-11-20  Paul-Antoine Arras  <parras@baylibre.com>
+
+       * g++.dg/gomp/adjust-args-1.C: New test.
+       * g++.dg/gomp/adjust-args-2.C: New test.
+       * g++.dg/gomp/adjust-args-3.C: New test.
+       * g++.dg/gomp/dispatch-1.C: New test.
+       * g++.dg/gomp/dispatch-2.C: New test.
+       * g++.dg/gomp/dispatch-3.C: New test.
+       * g++.dg/gomp/dispatch-4.C: New test.
+       * g++.dg/gomp/dispatch-5.C: New test.
+       * g++.dg/gomp/dispatch-6.C: New test.
+       * g++.dg/gomp/dispatch-7.C: New test.
+
+2024-11-20  Paul-Antoine Arras  <parras@baylibre.com>
+
+       * gcc.dg/gomp/adjust-args-1.c: New test.
+       * gcc.dg/gomp/dispatch-1.c: New test.
+       * gcc.dg/gomp/dispatch-2.c: New test.
+       * gcc.dg/gomp/dispatch-3.c: New test.
+       * gcc.dg/gomp/dispatch-4.c: New test.
+       * gcc.dg/gomp/dispatch-5.c: New test.
+
+2024-11-20  Antoni Boucher  <bouanto@zoho.com>
+
+       * jit.dg/test-error-bad-assignment-op.c: New test.
+
+2024-11-20  Antoni Boucher  <bouanto@zoho.com>
+
+       * jit.dg/all-non-failing-tests.h: Add test-signed-char.c.
+       * jit.dg/test-signed-char.c: New test.
+
+2024-11-20  Richard Sandiford  <richard.sandiford@arm.com>
+
+       * lib/target-supports.exp: Test the assembler for sve-b16b16 support.
+       * gcc.target/aarch64/pragma_cpp_predefs_4.c: Add tests for
+       __ARM_FEATURE_SME2p1.
+       * gcc.target/aarch64/sme2/acle-asm/readz_hor_za128.c: New test.
+       * gcc.target/aarch64/sme2/acle-asm/readz_hor_za16.c: Likewise.
+       * gcc.target/aarch64/sme2/acle-asm/readz_hor_za16_vg2.c: Likewise.
+       * gcc.target/aarch64/sme2/acle-asm/readz_hor_za16_vg4.c: Likewise.
+       * gcc.target/aarch64/sme2/acle-asm/readz_hor_za32.c: Likewise.
+       * gcc.target/aarch64/sme2/acle-asm/readz_hor_za32_vg2.c: Likewise.
+       * gcc.target/aarch64/sme2/acle-asm/readz_hor_za32_vg4.c: Likewise.
+       * gcc.target/aarch64/sme2/acle-asm/readz_hor_za64.c: Likewise.
+       * gcc.target/aarch64/sme2/acle-asm/readz_hor_za64_vg2.c: Likewise.
+       * gcc.target/aarch64/sme2/acle-asm/readz_hor_za64_vg4.c: Likewise.
+       * gcc.target/aarch64/sme2/acle-asm/readz_hor_za8.c: Likewise.
+       * gcc.target/aarch64/sme2/acle-asm/readz_hor_za8_vg2.c: Likewise.
+       * gcc.target/aarch64/sme2/acle-asm/readz_hor_za8_vg4.c: Likewise.
+       * gcc.target/aarch64/sme2/acle-asm/readz_ver_za16.c: Likewise.
+       * gcc.target/aarch64/sme2/acle-asm/readz_ver_za16_vg2.c: Likewise.
+       * gcc.target/aarch64/sme2/acle-asm/readz_ver_za16_vg4.c: Likewise.
+       * gcc.target/aarch64/sme2/acle-asm/readz_ver_za32.c: Likewise.
+       * gcc.target/aarch64/sme2/acle-asm/readz_ver_za32_vg2.c: Likewise.
+       * gcc.target/aarch64/sme2/acle-asm/readz_ver_za32_vg4.c: Likewise.
+       * gcc.target/aarch64/sme2/acle-asm/readz_ver_za64.c: Likewise.
+       * gcc.target/aarch64/sme2/acle-asm/readz_ver_za64_vg2.c: Likewise.
+       * gcc.target/aarch64/sme2/acle-asm/readz_ver_za64_vg4.c: Likewise.
+       * gcc.target/aarch64/sme2/acle-asm/readz_ver_za8.c: Likewise.
+       * gcc.target/aarch64/sme2/acle-asm/readz_ver_za8_vg2.c: Likewise.
+       * gcc.target/aarch64/sme2/acle-asm/readz_ver_za8_vg4.c: Likewise.
+       * gcc.target/aarch64/sme2/acle-asm/readz_za16_vg1x2.c: Likewise.
+       * gcc.target/aarch64/sme2/acle-asm/readz_za16_vg1x4.c: Likewise.
+       * gcc.target/aarch64/sme2/acle-asm/readz_za32_vg1x2.c: Likewise.
+       * gcc.target/aarch64/sme2/acle-asm/readz_za32_vg1x4.c: Likewise.
+       * gcc.target/aarch64/sme2/acle-asm/readz_za64_vg1x2.c: Likewise.
+       * gcc.target/aarch64/sme2/acle-asm/readz_za64_vg1x4.c: Likewise.
+       * gcc.target/aarch64/sme2/acle-asm/readz_za8_vg1x2.c: Likewise.
+       * gcc.target/aarch64/sme2/acle-asm/readz_za8_vg1x4.c: Likewise.
+       * gcc.target/aarch64/sme2/acle-asm/zero_za64_vg1x2.c: Likewise.
+       * gcc.target/aarch64/sme2/acle-asm/zero_za64_vg1x4.c: Likewise.
+       * gcc.target/aarch64/sme2/acle-asm/zero_za64_vg2x1.c: Likewise.
+       * gcc.target/aarch64/sme2/acle-asm/zero_za64_vg2x2.c: Likewise.
+       * gcc.target/aarch64/sme2/acle-asm/zero_za64_vg2x4.c: Likewise.
+       * gcc.target/aarch64/sme2/acle-asm/zero_za64_vg4x1.c: Likewise.
+       * gcc.target/aarch64/sme2/acle-asm/zero_za64_vg4x2.c: Likewise.
+       * gcc.target/aarch64/sme2/acle-asm/zero_za64_vg4x4.c: Likewise.
+
+2024-11-20  Richard Sandiford  <richard.sandiford@arm.com>
+
+       * lib/target-supports.exp: Test the assembler for sve-b16b16 support.
+       * gcc.target/aarch64/pragma_cpp_predefs_4.c: Add tests for
+       __ARM_FEATURE_SME_B16B16.
+       * gcc.target/aarch64/sme2/acle-asm/add_za16_bf16_vg1x2.c: New test.
+       * gcc.target/aarch64/sme2/acle-asm/add_za16_bf16_vg1x4.c: Likewise.
+       * gcc.target/aarch64/sme2/acle-asm/mla_lane_za16_bf16_vg1x2.c: Likewise.
+       * gcc.target/aarch64/sme2/acle-asm/mla_lane_za16_bf16_vg1x4.c: Likewise.
+       * gcc.target/aarch64/sme2/acle-asm/mla_za16_bf16_vg1x2.c: Likewise.
+       * gcc.target/aarch64/sme2/acle-asm/mla_za16_bf16_vg1x4.c: Likewise.
+       * gcc.target/aarch64/sme2/acle-asm/mls_lane_za16_bf16_vg1x2.c: Likewise.
+       * gcc.target/aarch64/sme2/acle-asm/mls_lane_za16_bf16_vg1x4.c: Likewise.
+       * gcc.target/aarch64/sme2/acle-asm/mls_za16_bf16_vg1x2.c: Likewise.
+       * gcc.target/aarch64/sme2/acle-asm/mls_za16_bf16_vg1x4.c: Likewise.
+       * gcc.target/aarch64/sme2/acle-asm/mopa_za16_bf16.c: Likewise.
+       * gcc.target/aarch64/sme2/acle-asm/mops_za16_bf16.c: Likewise.
+       * gcc.target/aarch64/sme2/acle-asm/sub_za16_bf16_vg1x2.c: Likewise.
+       * gcc.target/aarch64/sme2/acle-asm/sub_za16_bf16_vg1x4.c: Likewise.
+
+2024-11-20  Richard Sandiford  <richard.sandiford@arm.com>
+
+       * lib/target-supports.exp: Test the assembler for sve-f16f16 support.
+       * gcc.target/aarch64/pragma_cpp_predefs_4.c: Add tests for
+       __ARM_FEATURE_SME_F16F16.  Also extend the existing SME tests.
+       * gcc.target/aarch64/sve/acle/asm/test_sve_acle.h
+       (TEST_X2_WIDE): New macro
+       * gcc.target/aarch64/sme2/acle-asm/add_za16_f16_vg1x2.c: New test.
+       * gcc.target/aarch64/sme2/acle-asm/add_za16_f16_vg1x4.c: Likewise.
+       * gcc.target/aarch64/sme2/acle-asm/cvt_f32_f16_x2.c: Likewise.
+       * gcc.target/aarch64/sme2/acle-asm/cvtl_f32_f16_x2.c: Likewise.
+       * gcc.target/aarch64/sme2/acle-asm/mla_lane_za16_f16_vg1x2.c: Likewise.
+       * gcc.target/aarch64/sme2/acle-asm/mla_lane_za16_f16_vg1x4.c: Likewise.
+       * gcc.target/aarch64/sme2/acle-asm/mla_za16_f16_vg1x2.c: Likewise.
+       * gcc.target/aarch64/sme2/acle-asm/mla_za16_f16_vg1x4.c: Likewise.
+       * gcc.target/aarch64/sme2/acle-asm/mls_lane_za16_f16_vg1x2.c: Likewise.
+       * gcc.target/aarch64/sme2/acle-asm/mls_lane_za16_f16_vg1x4.c: Likewise.
+       * gcc.target/aarch64/sme2/acle-asm/mls_za16_f16_vg1x2.c: Likewise.
+       * gcc.target/aarch64/sme2/acle-asm/mls_za16_f16_vg1x4.c: Likewise.
+       * gcc.target/aarch64/sme2/acle-asm/mopa_za16_f16.c: Likewise.
+       * gcc.target/aarch64/sme2/acle-asm/mops_za16_f16.c: Likewise.
+       * gcc.target/aarch64/sme2/acle-asm/sub_za16_f16_vg1x2.c: Likewise.
+       * gcc.target/aarch64/sme2/acle-asm/sub_za16_f16_vg1x4.c: Likewise.
+
+2024-11-20  Richard Sandiford  <richard.sandiford@arm.com>
+
+       * lib/target-supports.exp: Test the assembler for sve-b16b16 support.
+       * gcc.target/aarch64/pragma_cpp_predefs_4.c: Test the new B16B16
+       macros.
+       * gcc.target/aarch64/sve/fmad_1.c: Test bfloat16 too.
+       * gcc.target/aarch64/sve/fmla_1.c: Likewise.
+       * gcc.target/aarch64/sve/fmls_1.c: Likewise.
+       * gcc.target/aarch64/sve/fmsb_1.c: Likewise.
+       * gcc.target/aarch64/sve/cond_mla_9.c: New test.
+       * gcc.target/aarch64/sme2/acle-asm/clamp_bf16_x2.c: Likewise.
+       * gcc.target/aarch64/sme2/acle-asm/clamp_bf16_x4.c: Likewise.
+       * gcc.target/aarch64/sme2/acle-asm/max_bf16_x2.c: Likewise.
+       * gcc.target/aarch64/sme2/acle-asm/max_bf16_x4.c: Likewise.
+       * gcc.target/aarch64/sme2/acle-asm/maxnm_bf16_x2.c: Likewise.
+       * gcc.target/aarch64/sme2/acle-asm/maxnm_bf16_x4.c: Likewise.
+       * gcc.target/aarch64/sme2/acle-asm/min_bf16_x2.c: Likewise.
+       * gcc.target/aarch64/sme2/acle-asm/min_bf16_x4.c: Likewise.
+       * gcc.target/aarch64/sme2/acle-asm/minnm_bf16_x2.c: Likewise.
+       * gcc.target/aarch64/sme2/acle-asm/minnm_bf16_x4.c: Likewise.
+       * gcc.target/aarch64/sve/bf16_arith_1.c: Likewise.
+       * gcc.target/aarch64/sve/bf16_arith_1.h: Likewise.
+       * gcc.target/aarch64/sve/bf16_arith_2.c: Likewise.
+       * gcc.target/aarch64/sve/bf16_arith_3.c: Likewise.
+       * gcc.target/aarch64/sve2/acle/asm/add_bf16.c: Likewise.
+       * gcc.target/aarch64/sve2/acle/asm/clamp_bf16.c: Likewise.
+       * gcc.target/aarch64/sve2/acle/asm/max_bf16.c: Likewise.
+       * gcc.target/aarch64/sve2/acle/asm/maxnm_bf16.c: Likewise.
+       * gcc.target/aarch64/sve2/acle/asm/min_bf16.c: Likewise.
+       * gcc.target/aarch64/sve2/acle/asm/minnm_bf16.c: Likewise.
+       * gcc.target/aarch64/sve2/acle/asm/mla_bf16.c: Likewise.
+       * gcc.target/aarch64/sve2/acle/asm/mla_lane_bf16.c: Likewise.
+       * gcc.target/aarch64/sve2/acle/asm/mls_bf16.c: Likewise.
+       * gcc.target/aarch64/sve2/acle/asm/mls_lane_bf16.c: Likewise.
+       * gcc.target/aarch64/sve2/acle/asm/mul_bf16.c: Likewise.
+       * gcc.target/aarch64/sve2/acle/asm/mul_lane_bf16.c: Likewise.
+       * gcc.target/aarch64/sve2/acle/asm/sub_bf16.c: Likewise.
+
+2024-11-20  Mikael Morin  <mikael@gcc.gnu.org>
+
+       PR fortran/90608
+       * gfortran.dg/maxloc_8.f90: New test.
+       * gfortran.dg/minloc_9.f90: New test.
+
+2024-11-20  Rainer Orth  <ro@CeBiTec.Uni-Bielefeld.DE>
+
+       * gcc.target/i386/pr117232-1.c (scan-assembler-times): Allow for
+       cmovl.nc etc.
+       * gcc.target/i386/pr117232-apx-1.c: Likewise.
+
+2024-11-20  Pan Li  <pan2.li@intel.com>
+
+       * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-1-s16.c: Remove
+       the unnecessary option and refine the rtl IFN dump check.
+       * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-1-s32.c: Ditto.
+       * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-1-s64.c: Ditto.
+       * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-1-s8.c: Ditto.
+       * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-2-s16.c: Ditto.
+       * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-2-s32.c: Ditto.
+       * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-2-s64.c: Ditto.
+       * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-2-s8.c: Ditto.
+       * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-3-s16.c: Ditto.
+       * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-3-s32.c: Ditto.
+       * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-3-s64.c: Ditto.
+       * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-3-s8.c: Ditto.
+       * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-4-s16.c: Ditto.
+       * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-4-s32.c: Ditto.
+       * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-4-s64.c: Ditto.
+       * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-4-s8.c: Ditto.
+       * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-run-1-s16.c: Ditto.
+       * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-run-1-s32.c: Ditto.
+       * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-run-1-s64.c: Ditto.
+       * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-run-1-s8.c: Ditto.
+       * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-run-2-s16.c: Ditto.
+       * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-run-2-s32.c: Ditto.
+       * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-run-2-s64.c: Ditto.
+       * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-run-2-s8.c: Ditto.
+       * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-run-3-s16.c: Ditto.
+       * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-run-3-s32.c: Ditto.
+       * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-run-3-s64.c: Ditto.
+       * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-run-3-s8.c: Ditto.
+       * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-run-4-s16.c: Ditto.
+       * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-run-4-s32.c: Ditto.
+       * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-run-4-s64.c: Ditto.
+       * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-run-4-s8.c: Ditto.
+       * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-1-u16.c: Ditto.
+       * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-1-u32.c: Ditto.
+       * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-1-u64.c: Ditto.
+       * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-1-u8.c: Ditto.
+       * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-2-u16.c: Ditto.
+       * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-2-u32.c: Ditto.
+       * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-2-u64.c: Ditto.
+       * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-2-u8.c: Ditto.
+       * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-3-u16.c: Ditto.
+       * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-3-u32.c: Ditto.
+       * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-3-u64.c: Ditto.
+       * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-3-u8.c: Ditto.
+       * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-4-u16.c: Ditto.
+       * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-4-u32.c: Ditto.
+       * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-4-u64.c: Ditto.
+       * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-4-u8.c: Ditto.
+       * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-5-u16.c: Ditto.
+       * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-5-u32.c: Ditto.
+       * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-5-u64.c: Ditto.
+       * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-5-u8.c: Ditto.
+       * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-6-u16.c: Ditto.
+       * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-6-u32.c: Ditto.
+       * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-6-u64.c: Ditto.
+       * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-6-u8.c: Ditto.
+       * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-7-u16.c: Ditto.
+       * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-7-u32.c: Ditto.
+       * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-7-u64.c: Ditto.
+       * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-7-u8.c: Ditto.
+       * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-8-u16.c: Ditto.
+       * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-8-u32.c: Ditto.
+       * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-8-u64.c: Ditto.
+       * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-8-u8.c: Ditto.
+       * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-1-u16.c: Ditto.
+       * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-1-u32.c: Ditto.
+       * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-1-u64.c: Ditto.
+       * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-1-u8.c: Ditto.
+       * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-2-u16.c: Ditto.
+       * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-2-u32.c: Ditto.
+       * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-2-u64.c: Ditto.
+       * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-2-u8.c: Ditto.
+       * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-3-u16.c: Ditto.
+       * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-3-u32.c: Ditto.
+       * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-3-u64.c: Ditto.
+       * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-3-u8.c: Ditto.
+       * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-4-u16.c: Ditto.
+       * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-4-u32.c: Ditto.
+       * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-4-u64.c: Ditto.
+       * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-4-u8.c: Ditto.
+       * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-5-u16.c: Ditto.
+       * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-5-u32.c: Ditto.
+       * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-5-u64.c: Ditto.
+       * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-5-u8.c: Ditto.
+       * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-6-u16.c: Ditto.
+       * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-6-u32.c: Ditto.
+       * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-6-u64.c: Ditto.
+       * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-6-u8.c: Ditto.
+       * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-7-u16.c: Ditto.
+       * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-7-u32.c: Ditto.
+       * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-7-u64.c: Ditto.
+       * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-7-u8.c: Ditto.
+       * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-8-u16.c: Ditto.
+       * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-8-u32.c: Ditto.
+       * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-8-u64.c: Ditto.
+       * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-8-u8.c: Ditto.
+       * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-1-u16.c: Ditto.
+       * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-1-u32.c: Ditto.
+       * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-1-u64.c: Ditto.
+       * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-1-u8.c: Ditto.
+       * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-2-u16.c: Ditto.
+       * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-2-u32.c: Ditto.
+       * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-2-u64.c: Ditto.
+       * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-2-u8.c: Ditto.
+       * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-3-u16.c: Ditto.
+       * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-3-u32.c: Ditto.
+       * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-3-u64.c: Ditto.
+       * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-3-u8.c: Ditto.
+       * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-4-u16.c: Ditto.
+       * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-4-u32.c: Ditto.
+       * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-4-u64.c: Ditto.
+       * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-4-u8.c: Ditto.
+       * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-run-1-u16.c: Ditto.
+       * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-run-1-u32.c: Ditto.
+       * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-run-1-u64.c: Ditto.
+       * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-run-1-u8.c: Ditto.
+       * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-run-2-u16.c: Ditto.
+       * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-run-2-u32.c: Ditto.
+       * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-run-2-u64.c: Ditto.
+       * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-run-2-u8.c: Ditto.
+       * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-run-3-u16.c: Ditto.
+       * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-run-3-u32.c: Ditto.
+       * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-run-3-u64.c: Ditto.
+       * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-run-3-u8.c: Ditto.
+       * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-run-4-u16.c: Ditto.
+       * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-run-4-u32.c: Ditto.
+       * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-run-4-u64.c: Ditto.
+       * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-run-4-u8.c: Ditto.
+       * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-1-u16.c: Ditto.
+       * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-1-u32.c: Ditto.
+       * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-1-u64.c: Ditto.
+       * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-1-u8.c: Ditto.
+       * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-2-u16.c: Ditto.
+       * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-2-u32.c: Ditto.
+       * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-2-u64.c: Ditto.
+       * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-2-u8.c: Ditto.
+       * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-3-u16.c: Ditto.
+       * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-3-u32.c: Ditto.
+       * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-3-u64.c: Ditto.
+       * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-3-u8.c: Ditto.
+       * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-4-u16.c: Ditto.
+       * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-4-u32.c: Ditto.
+       * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-4-u8.c: Ditto.
+
+2024-11-20  Pan Li  <pan2.li@intel.com>
+
+       * gcc.target/riscv/rvv/rvv.exp: Add the vector sat folder to
+       the rvv.exp testsuite.
+
+2024-11-20  Pan Li  <pan2.li@intel.com>
+
+       * gcc.target/riscv/rvv/autovec/binop/vec_sat_s_add-2.c: Move to...
+       * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-1-s16.c: ...here.
+       * gcc.target/riscv/rvv/autovec/binop/vec_sat_s_add-3.c: Move to...
+       * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-1-s32.c: ...here.
+       * gcc.target/riscv/rvv/autovec/binop/vec_sat_s_add-4.c: Move to...
+       * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-1-s64.c: ...here.
+       * gcc.target/riscv/rvv/autovec/binop/vec_sat_s_add-1.c: Move to...
+       * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-1-s8.c: ...here.
+       * gcc.target/riscv/rvv/autovec/binop/vec_sat_s_add-6.c: Move to...
+       * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-2-s16.c: ...here.
+       * gcc.target/riscv/rvv/autovec/binop/vec_sat_s_add-7.c: Move to...
+       * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-2-s32.c: ...here.
+       * gcc.target/riscv/rvv/autovec/binop/vec_sat_s_add-8.c: Move to...
+       * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-2-s64.c: ...here.
+       * gcc.target/riscv/rvv/autovec/binop/vec_sat_s_add-5.c: Move to...
+       * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-2-s8.c: ...here.
+       * gcc.target/riscv/rvv/autovec/binop/vec_sat_s_add-10.c: Move to...
+       * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-3-s16.c: ...here.
+       * gcc.target/riscv/rvv/autovec/binop/vec_sat_s_add-11.c: Move to...
+       * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-3-s32.c: ...here.
+       * gcc.target/riscv/rvv/autovec/binop/vec_sat_s_add-12.c: Move to...
+       * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-3-s64.c: ...here.
+       * gcc.target/riscv/rvv/autovec/binop/vec_sat_s_add-9.c: Move to...
+       * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-3-s8.c: ...here.
+       * gcc.target/riscv/rvv/autovec/binop/vec_sat_s_add-14.c: Move to...
+       * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-4-s16.c: ...here.
+       * gcc.target/riscv/rvv/autovec/binop/vec_sat_s_add-15.c: Move to...
+       * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-4-s32.c: ...here.
+       * gcc.target/riscv/rvv/autovec/binop/vec_sat_s_add-16.c: Move to...
+       * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-4-s64.c: ...here.
+       * gcc.target/riscv/rvv/autovec/binop/vec_sat_s_add-13.c: Move to...
+       * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-4-s8.c: ...here.
+       * gcc.target/riscv/rvv/autovec/binop/vec_sat_s_add-run-2.c: Move to...
+       * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-run-1-s16.c: ...here.
+       * gcc.target/riscv/rvv/autovec/binop/vec_sat_s_add-run-3.c: Move to...
+       * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-run-1-s32.c: ...here.
+       * gcc.target/riscv/rvv/autovec/binop/vec_sat_s_add-run-4.c: Move to...
+       * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-run-1-s64.c: ...here.
+       * gcc.target/riscv/rvv/autovec/binop/vec_sat_s_add-run-1.c: Move to...
+       * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-run-1-s8.c: ...here.
+       * gcc.target/riscv/rvv/autovec/binop/vec_sat_s_add-run-6.c: Move to...
+       * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-run-2-s16.c: ...here.
+       * gcc.target/riscv/rvv/autovec/binop/vec_sat_s_add-run-7.c: Move to...
+       * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-run-2-s32.c: ...here.
+       * gcc.target/riscv/rvv/autovec/binop/vec_sat_s_add-run-8.c: Move to...
+       * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-run-2-s64.c: ...here.
+       * gcc.target/riscv/rvv/autovec/binop/vec_sat_s_add-run-5.c: Move to...
+       * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-run-2-s8.c: ...here.
+       * gcc.target/riscv/rvv/autovec/binop/vec_sat_s_add-run-10.c: Move to...
+       * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-run-3-s16.c: ...here.
+       * gcc.target/riscv/rvv/autovec/binop/vec_sat_s_add-run-11.c: Move to...
+       * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-run-3-s32.c: ...here.
+       * gcc.target/riscv/rvv/autovec/binop/vec_sat_s_add-run-12.c: Move to...
+       * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-run-3-s64.c: ...here.
+       * gcc.target/riscv/rvv/autovec/binop/vec_sat_s_add-run-9.c: Move to...
+       * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-run-3-s8.c: ...here.
+       * gcc.target/riscv/rvv/autovec/binop/vec_sat_s_add-run-14.c: Move to...
+       * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-run-4-s16.c: ...here.
+       * gcc.target/riscv/rvv/autovec/binop/vec_sat_s_add-run-15.c: Move to...
+       * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-run-4-s32.c: ...here.
+       * gcc.target/riscv/rvv/autovec/binop/vec_sat_s_add-run-16.c: Move to...
+       * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-run-4-s64.c: ...here.
+       * gcc.target/riscv/rvv/autovec/binop/vec_sat_s_add-run-13.c: Move to...
+       * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-run-4-s8.c: ...here.
+       * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-2.c: Move to...
+       * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-1-u16.c: ...here.
+       * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-3.c: Move to...
+       * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-1-u32.c: ...here.
+       * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-4.c: Move to...
+       * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-1-u64.c: ...here.
+       * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-1.c: Move to...
+       * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-1-u8.c: ...here.
+       * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-6.c: Move to...
+       * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-2-u16.c: ...here.
+       * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-7.c: Move to...
+       * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-2-u32.c: ...here.
+       * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-8.c: Move to...
+       * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-2-u64.c: ...here.
+       * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-5.c: Move to...
+       * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-2-u8.c: ...here.
+       * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-10.c: Move to...
+       * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-3-u16.c: ...here.
+       * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-11.c: Move to...
+       * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-3-u32.c: ...here.
+       * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-12.c: Move to...
+       * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-3-u64.c: ...here.
+       * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-9.c: Move to...
+       * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-3-u8.c: ...here.
+       * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-14.c: Move to...
+       * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-4-u16.c: ...here.
+       * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-15.c: Move to...
+       * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-4-u32.c: ...here.
+       * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-16.c: Move to...
+       * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-4-u64.c: ...here.
+       * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-13.c: Move to...
+       * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-4-u8.c: ...here.
+       * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-18.c: Move to...
+       * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-5-u16.c: ...here.
+       * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-19.c: Move to...
+       * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-5-u32.c: ...here.
+       * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-20.c: Move to...
+       * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-5-u64.c: ...here.
+       * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-17.c: Move to...
+       * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-5-u8.c: ...here.
+       * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-22.c: Move to...
+       * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-6-u16.c: ...here.
+       * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-23.c: Move to...
+       * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-6-u32.c: ...here.
+       * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-24.c: Move to...
+       * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-6-u64.c: ...here.
+       * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-21.c: Move to...
+       * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-6-u8.c: ...here.
+       * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-26.c: Move to...
+       * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-7-u16.c: ...here.
+       * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-27.c: Move to...
+       * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-7-u32.c: ...here.
+       * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-28.c: Move to...
+       * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-7-u64.c: ...here.
+       * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-25.c: Move to...
+       * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-7-u8.c: ...here.
+       * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-30.c: Move to...
+       * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-8-u16.c: ...here.
+       * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-31.c: Move to...
+       * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-8-u32.c: ...here.
+       * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-32.c: Move to...
+       * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-8-u64.c: ...here.
+       * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-29.c: Move to...
+       * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-8-u8.c: ...here.
+       * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-2.c: Move to...
+       * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-1-u16.c: ...here.
+       * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-3.c: Move to...
+       * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-1-u32.c: ...here.
+       * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-4.c: Move to...
+       * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-1-u64.c: ...here.
+       * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-1.c: Move to...
+       * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-1-u8.c: ...here.
+       * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-6.c: Move to...
+       * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-2-u16.c: ...here.
+       * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-7.c: Move to...
+       * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-2-u32.c: ...here.
+       * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-8.c: Move to...
+       * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-2-u64.c: ...here.
+       * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-5.c: Move to...
+       * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-2-u8.c: ...here.
+       * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-10.c: Move to...
+       * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-3-u16.c: ...here.
+       * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-11.c: Move to...
+       * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-3-u32.c: ...here.
+       * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-12.c: Move to...
+       * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-3-u64.c: ...here.
+       * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-9.c: Move to...
+       * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-3-u8.c: ...here.
+       * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-14.c: Move to...
+       * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-4-u16.c: ...here.
+       * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-15.c: Move to...
+       * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-4-u32.c: ...here.
+       * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-16.c: Move to...
+       * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-4-u64.c: ...here.
+       * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-13.c: Move to...
+       * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-4-u8.c: ...here.
+       * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-18.c: Move to...
+       * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-5-u16.c: ...here.
+       * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-19.c: Move to...
+       * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-5-u32.c: ...here.
+       * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-20.c: Move to...
+       * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-5-u64.c: ...here.
+       * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-17.c: Move to...
+       * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-5-u8.c: ...here.
+       * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-22.c: Move to...
+       * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-6-u16.c: ...here.
+       * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-23.c: Move to...
+       * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-6-u32.c: ...here.
+       * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-24.c: Move to...
+       * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-6-u64.c: ...here.
+       * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-21.c: Move to...
+       * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-6-u8.c: ...here.
+       * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-26.c: Move to...
+       * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-7-u16.c: ...here.
+       * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-27.c: Move to...
+       * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-7-u32.c: ...here.
+       * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-28.c: Move to...
+       * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-7-u64.c: ...here.
+       * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-25.c: Move to...
+       * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-7-u8.c: ...here.
+       * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-30.c: Move to...
+       * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-8-u16.c: ...here.
+       * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-31.c: Move to...
+       * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-8-u32.c: ...here.
+       * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-32.c: Move to...
+       * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-8-u64.c: ...here.
+       * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-29.c: Move to...
+       * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-8-u8.c: ...here.
+       * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-2.c: Move to...
+       * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-1-u16.c: ...here.
+       * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-3.c: Move to...
+       * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-1-u32.c: ...here.
+       * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-4.c: Move to...
+       * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-1-u64.c: ...here.
+       * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-1.c: Move to...
+       * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-1-u8.c: ...here.
+       * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-6.c: Move to...
+       * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-2-u16.c: ...here.
+       * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-7.c: Move to...
+       * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-2-u32.c: ...here.
+       * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-8.c: Move to...
+       * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-2-u64.c: ...here.
+       * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-5.c: Move to...
+       * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-2-u8.c: ...here.
+       * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-10.c: Move to...
+       * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-3-u16.c: ...here.
+       * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-11.c: Move to...
+       * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-3-u32.c: ...here.
+       * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-12.c: Move to...
+       * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-3-u64.c: ...here.
+       * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-9.c: Move to...
+       * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-3-u8.c: ...here.
+       * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-14.c: Move to...
+       * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-4-u16.c: ...here.
+       * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-15.c: Move to...
+       * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-4-u32.c: ...here.
+       * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-16.c: Move to...
+       * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-4-u64.c: ...here.
+       * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-13.c: Move to...
+       * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-4-u8.c: ...here.
+       * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-run-2.c: Move to...
+       * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-run-1-u16.c: ...here.
+       * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-run-3.c: Move to...
+       * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-run-1-u32.c: ...here.
+       * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-run-4.c: Move to...
+       * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-run-1-u64.c: ...here.
+       * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-run-1.c: Move to...
+       * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-run-1-u8.c: ...here.
+       * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-run-6.c: Move to...
+       * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-run-2-u16.c: ...here.
+       * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-run-7.c: Move to...
+       * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-run-2-u32.c: ...here.
+       * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-run-8.c: Move to...
+       * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-run-2-u64.c: ...here.
+       * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-run-5.c: Move to...
+       * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-run-2-u8.c: ...here.
+       * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-run-10.c: Move to...
+       * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-run-3-u16.c: ...here.
+       * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-run-11.c: Move to...
+       * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-run-3-u32.c: ...here.
+       * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-run-12.c: Move to...
+       * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-run-3-u64.c: ...here.
+       * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-run-9.c: Move to...
+       * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-run-3-u8.c: ...here.
+       * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-run-14.c: Move to...
+       * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-run-4-u16.c: ...here.
+       * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-run-15.c: Move to...
+       * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-run-4-u32.c: ...here.
+       * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-run-16.c: Move to...
+       * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-run-4-u64.c: ...here.
+       * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-run-13.c: Move to...
+       * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-run-4-u8.c: ...here.
+       * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm_reconcile-2.c: Move to...
+       * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-1-u16.c: ...here.
+       * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm_reconcile-3.c: Move to...
+       * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-1-u32.c: ...here.
+       * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm_reconcile-4.c: Move to...
+       * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-1-u64.c: ...here.
+       * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm_reconcile-1.c: Move to...
+       * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-1-u8.c: ...here.
+       * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm_reconcile-6.c: Move to...
+       * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-2-u16.c: ...here.
+       * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm_reconcile-7.c: Move to...
+       * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-2-u32.c: ...here.
+       * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm_reconcile-8.c: Move to...
+       * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-2-u64.c: ...here.
+       * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm_reconcile-5.c: Move to...
+       * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-2-u8.c: ...here.
+       * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm_reconcile-10.c: Move to...
+       * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-3-u16.c: ...here.
+       * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm_reconcile-11.c: Move to...
+       * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-3-u32.c: ...here.
+       * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm_reconcile-12.c: Move to...
+       * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-3-u64.c: ...here.
+       * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm_reconcile-9.c: Move to...
+       * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-3-u8.c: ...here.
+       * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm_reconcile-14.c: Move to...
+       * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-4-u16.c: ...here.
+       * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm_reconcile-15.c: Move to...
+       * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-4-u32.c: ...here.
+       * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm_reconcile-13.c: Move to...
+       * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-4-u8.c: ...here.
+       * gcc.target/riscv/rvv/autovec/sat/vec_sat_arith.h: New test.
+       * gcc.target/riscv/rvv/autovec/sat/vec_sat_binary_vvv_run.h: New test.
+       * gcc.target/riscv/rvv/autovec/sat/vec_sat_binary_vvx_run.h: New test.
+       * gcc.target/riscv/rvv/autovec/sat/vec_sat_binary_vx_run.h: New test.
+       * gcc.target/riscv/rvv/autovec/sat/vec_sat_data.h: New test.
+
+2024-11-20  Richard Biener  <rguenther@suse.de>
+
+       PR tree-optimization/117574
+       * gcc.dg/torture/pr117574-1.c: New testcase.
+
+2024-11-20  Richard Sandiford  <richard.sandiford@arm.com>
+
+       * gcc.target/aarch64/abs_bf_1.c: New test.
+       * gcc.target/aarch64/neg_bf_1.c: Likewise.
+       * gcc.target/aarch64/neg_bf_2.c: Likewise.
+
+2024-11-20  Andre Vieira  <andre.simoesdiasvieira@arm.com>
+
+       * gcc.target/arm/mve/dlstp-loop-form.c: Add loop that triggered ICE.
+
+2024-11-20  Mikael Morin  <mikael@gcc.gnu.org>
+
+       * gfortran.dg/minmaxloc_22.f90: New test.
+
+2024-11-20  Torbjörn SVENSSON  <torbjorn.svensson@foss.st.com>
+
+       * gcc.target/arm/pure-code/no-literal-pool-m0.c: Only check for
+       absence of literal pools.
+
+2024-11-20  Pan Li  <pan2.li@intel.com>
+
+       * gcc.target/riscv/rvv/autovec/strided/strided_ld_st-1-f16.c: Remove
+       unnecessary optimization option and xfail O2/O3 diff IFN times
+       from the rtl expand dump.
+       * gcc.target/riscv/rvv/autovec/strided/strided_ld_st-1-f32.c: Ditto.
+       * gcc.target/riscv/rvv/autovec/strided/strided_ld_st-1-f64.c: Ditto.
+       * gcc.target/riscv/rvv/autovec/strided/strided_ld_st-1-i16.c: Ditto.
+       * gcc.target/riscv/rvv/autovec/strided/strided_ld_st-1-i32.c: Ditto.
+       * gcc.target/riscv/rvv/autovec/strided/strided_ld_st-1-i64.c: Ditto.
+       * gcc.target/riscv/rvv/autovec/strided/strided_ld_st-1-i8.c: Ditto.
+       * gcc.target/riscv/rvv/autovec/strided/strided_ld_st-1-u16.c: Ditto.
+       * gcc.target/riscv/rvv/autovec/strided/strided_ld_st-1-u32.c: Ditto.
+       * gcc.target/riscv/rvv/autovec/strided/strided_ld_st-1-u64.c: Ditto.
+       * gcc.target/riscv/rvv/autovec/strided/strided_ld_st-1-u8.c: Ditto.
+
+2024-11-20  Pan Li  <pan2.li@intel.com>
+
+       * gcc.target/riscv/rvv/rvv.exp: Fix the incorrect optimization options.
+
+2024-11-20  yulong  <shiyulong@iscas.ac.cn>
+
+       * gcc.target/riscv/predef-sf-3.c: New test.
+       * gcc.target/riscv/predef-sf-4.c: New test.
+       * gcc.target/riscv/predef-sf-5.c: New test.
+
+2024-11-20  Jeff Law  <jlaw@ventanamicro.com>
+
+       PR target/117649
+       * gcc.target/riscv/branch-1.c: Update expected output.
+       * gcc.target/riscv/pr117649.c: New test.
+
+2024-11-20  Joseph Myers  <josmyers@redhat.com>
+
+       PR c/115515
+       * gcc.dg/c23-constexpr-10.c, gcc.dg/gnu23-constexpr-2.c: New
+       tests.
+
+2024-11-20  Pan Li  <pan2.li@intel.com>
+
+       * gcc.target/riscv/sat/sat_s_sub-1-i16.c: Remove flto
+       dg-skip workaround and -O3 option.
+       * gcc.target/riscv/sat/sat_s_sub-1-i32.c: Ditto.
+       * gcc.target/riscv/sat/sat_s_sub-1-i64.c: Ditto.
+       * gcc.target/riscv/sat/sat_s_sub-1-i8.c: Ditto.
+       * gcc.target/riscv/sat/sat_s_sub-2-i16.c: Ditto.
+       * gcc.target/riscv/sat/sat_s_sub-2-i32.c: Ditto.
+       * gcc.target/riscv/sat/sat_s_sub-2-i64.c: Ditto.
+       * gcc.target/riscv/sat/sat_s_sub-2-i8.c: Ditto.
+       * gcc.target/riscv/sat/sat_s_sub-3-i16.c: Ditto.
+       * gcc.target/riscv/sat/sat_s_sub-3-i32.c: Ditto.
+       * gcc.target/riscv/sat/sat_s_sub-3-i64.c: Ditto.
+       * gcc.target/riscv/sat/sat_s_sub-3-i8.c: Ditto.
+       * gcc.target/riscv/sat/sat_s_sub-4-i16.c: Ditto.
+       * gcc.target/riscv/sat/sat_s_sub-4-i32.c: Ditto.
+       * gcc.target/riscv/sat/sat_s_sub-4-i64.c: Ditto.
+       * gcc.target/riscv/sat/sat_s_sub-4-i8.c: Ditto.
+       * gcc.target/riscv/sat/sat_s_trunc-1-i16-to-i8.c: Ditto.
+       * gcc.target/riscv/sat/sat_s_trunc-1-i32-to-i16.c: Ditto.
+       * gcc.target/riscv/sat/sat_s_trunc-1-i32-to-i8.c: Ditto.
+       * gcc.target/riscv/sat/sat_s_trunc-1-i64-to-i16.c: Ditto.
+       * gcc.target/riscv/sat/sat_s_trunc-1-i64-to-i32.c: Ditto.
+       * gcc.target/riscv/sat/sat_s_trunc-1-i64-to-i8.c: Ditto.
+       * gcc.target/riscv/sat/sat_s_trunc-2-i16-to-i8.c: Ditto.
+       * gcc.target/riscv/sat/sat_s_trunc-2-i32-to-i16.c: Ditto.
+       * gcc.target/riscv/sat/sat_s_trunc-2-i32-to-i8.c: Ditto.
+       * gcc.target/riscv/sat/sat_s_trunc-2-i64-to-i16.c: Ditto.
+       * gcc.target/riscv/sat/sat_s_trunc-2-i64-to-i32.c: Ditto.
+       * gcc.target/riscv/sat/sat_s_trunc-2-i64-to-i8.c: Ditto.
+       * gcc.target/riscv/sat/sat_s_trunc-3-i16-to-i8.c: Ditto.
+       * gcc.target/riscv/sat/sat_s_trunc-3-i32-to-i16.c: Ditto.
+       * gcc.target/riscv/sat/sat_s_trunc-3-i32-to-i8.c: Ditto.
+       * gcc.target/riscv/sat/sat_s_trunc-3-i64-to-i16.c: Ditto.
+       * gcc.target/riscv/sat/sat_s_trunc-3-i64-to-i32.c: Ditto.
+       * gcc.target/riscv/sat/sat_s_trunc-3-i64-to-i8.c: Ditto.
+       * gcc.target/riscv/sat/sat_s_trunc-4-i16-to-i8.c: Ditto.
+       * gcc.target/riscv/sat/sat_s_trunc-4-i32-to-i16.c: Ditto.
+       * gcc.target/riscv/sat/sat_s_trunc-4-i32-to-i8.c: Ditto.
+       * gcc.target/riscv/sat/sat_s_trunc-4-i64-to-i16.c: Ditto.
+       * gcc.target/riscv/sat/sat_s_trunc-4-i64-to-i32.c: Ditto.
+       * gcc.target/riscv/sat/sat_s_trunc-4-i64-to-i8.c: Ditto.
+       * gcc.target/riscv/sat/sat_s_trunc-5-i16-to-i8.c: Ditto.
+       * gcc.target/riscv/sat/sat_s_trunc-5-i32-to-i16.c: Ditto.
+       * gcc.target/riscv/sat/sat_s_trunc-5-i32-to-i8.c: Ditto.
+       * gcc.target/riscv/sat/sat_s_trunc-5-i64-to-i16.c: Ditto.
+       * gcc.target/riscv/sat/sat_s_trunc-5-i64-to-i32.c: Ditto.
+       * gcc.target/riscv/sat/sat_s_trunc-5-i64-to-i8.c: Ditto.
+       * gcc.target/riscv/sat/sat_s_trunc-6-i16-to-i8.c: Ditto.
+       * gcc.target/riscv/sat/sat_s_trunc-6-i32-to-i16.c: Ditto.
+       * gcc.target/riscv/sat/sat_s_trunc-6-i32-to-i8.c: Ditto.
+       * gcc.target/riscv/sat/sat_s_trunc-6-i64-to-i16.c: Ditto.
+       * gcc.target/riscv/sat/sat_s_trunc-6-i64-to-i32.c: Ditto.
+       * gcc.target/riscv/sat/sat_s_trunc-6-i64-to-i8.c: Ditto.
+       * gcc.target/riscv/sat/sat_s_trunc-7-i16-to-i8.c: Ditto.
+       * gcc.target/riscv/sat/sat_s_trunc-7-i32-to-i16.c: Ditto.
+       * gcc.target/riscv/sat/sat_s_trunc-7-i32-to-i8.c: Ditto.
+       * gcc.target/riscv/sat/sat_s_trunc-7-i64-to-i16.c: Ditto.
+       * gcc.target/riscv/sat/sat_s_trunc-7-i64-to-i32.c: Ditto.
+       * gcc.target/riscv/sat/sat_s_trunc-7-i64-to-i8.c: Ditto.
+       * gcc.target/riscv/sat/sat_s_trunc-8-i16-to-i8.c: Ditto.
+       * gcc.target/riscv/sat/sat_s_trunc-8-i32-to-i16.c: Ditto.
+       * gcc.target/riscv/sat/sat_s_trunc-8-i32-to-i8.c: Ditto.
+       * gcc.target/riscv/sat/sat_s_trunc-8-i64-to-i16.c: Ditto.
+       * gcc.target/riscv/sat/sat_s_trunc-8-i64-to-i32.c: Ditto.
+       * gcc.target/riscv/sat/sat_s_trunc-8-i64-to-i8.c: Ditto.
+
+2024-11-20  Pan Li  <pan2.li@intel.com>
+
+       * gcc.target/riscv/sat_s_sub-1-i16.c: Move to...
+       * gcc.target/riscv/sat/sat_s_sub-1-i16.c: ...here.
+       * gcc.target/riscv/sat_s_sub-1-i32.c: Move to...
+       * gcc.target/riscv/sat/sat_s_sub-1-i32.c: ...here.
+       * gcc.target/riscv/sat_s_sub-1-i64.c: Move to...
+       * gcc.target/riscv/sat/sat_s_sub-1-i64.c: ...here.
+       * gcc.target/riscv/sat_s_sub-1-i8.c: Move to...
+       * gcc.target/riscv/sat/sat_s_sub-1-i8.c: ...here.
+       * gcc.target/riscv/sat_s_sub-2-i16.c: Move to...
+       * gcc.target/riscv/sat/sat_s_sub-2-i16.c: ...here.
+       * gcc.target/riscv/sat_s_sub-2-i32.c: Move to...
+       * gcc.target/riscv/sat/sat_s_sub-2-i32.c: ...here.
+       * gcc.target/riscv/sat_s_sub-2-i64.c: Move to...
+       * gcc.target/riscv/sat/sat_s_sub-2-i64.c: ...here.
+       * gcc.target/riscv/sat_s_sub-2-i8.c: Move to...
+       * gcc.target/riscv/sat/sat_s_sub-2-i8.c: ...here.
+       * gcc.target/riscv/sat_s_sub-3-i16.c: Move to...
+       * gcc.target/riscv/sat/sat_s_sub-3-i16.c: ...here.
+       * gcc.target/riscv/sat_s_sub-3-i32.c: Move to...
+       * gcc.target/riscv/sat/sat_s_sub-3-i32.c: ...here.
+       * gcc.target/riscv/sat_s_sub-3-i64.c: Move to...
+       * gcc.target/riscv/sat/sat_s_sub-3-i64.c: ...here.
+       * gcc.target/riscv/sat_s_sub-3-i8.c: Move to...
+       * gcc.target/riscv/sat/sat_s_sub-3-i8.c: ...here.
+       * gcc.target/riscv/sat_s_sub-4-i16.c: Move to...
+       * gcc.target/riscv/sat/sat_s_sub-4-i16.c: ...here.
+       * gcc.target/riscv/sat_s_sub-4-i32.c: Move to...
+       * gcc.target/riscv/sat/sat_s_sub-4-i32.c: ...here.
+       * gcc.target/riscv/sat_s_sub-4-i64.c: Move to...
+       * gcc.target/riscv/sat/sat_s_sub-4-i64.c: ...here.
+       * gcc.target/riscv/sat_s_sub-4-i8.c: Move to...
+       * gcc.target/riscv/sat/sat_s_sub-4-i8.c: ...here.
+       * gcc.target/riscv/sat_s_sub-run-1-i16.c: Move to...
+       * gcc.target/riscv/sat/sat_s_sub-run-1-i16.c: ...here.
+       * gcc.target/riscv/sat_s_sub-run-1-i32.c: Move to...
+       * gcc.target/riscv/sat/sat_s_sub-run-1-i32.c: ...here.
+       * gcc.target/riscv/sat_s_sub-run-1-i64.c: Move to...
+       * gcc.target/riscv/sat/sat_s_sub-run-1-i64.c: ...here.
+       * gcc.target/riscv/sat_s_sub-run-1-i8.c: Move to...
+       * gcc.target/riscv/sat/sat_s_sub-run-1-i8.c: ...here.
+       * gcc.target/riscv/sat_s_sub-run-2-i16.c: Move to...
+       * gcc.target/riscv/sat/sat_s_sub-run-2-i16.c: ...here.
+       * gcc.target/riscv/sat_s_sub-run-2-i32.c: Move to...
+       * gcc.target/riscv/sat/sat_s_sub-run-2-i32.c: ...here.
+       * gcc.target/riscv/sat_s_sub-run-2-i64.c: Move to...
+       * gcc.target/riscv/sat/sat_s_sub-run-2-i64.c: ...here.
+       * gcc.target/riscv/sat_s_sub-run-2-i8.c: Move to...
+       * gcc.target/riscv/sat/sat_s_sub-run-2-i8.c: ...here.
+       * gcc.target/riscv/sat_s_sub-run-3-i16.c: Move to...
+       * gcc.target/riscv/sat/sat_s_sub-run-3-i16.c: ...here.
+       * gcc.target/riscv/sat_s_sub-run-3-i32.c: Move to...
+       * gcc.target/riscv/sat/sat_s_sub-run-3-i32.c: ...here.
+       * gcc.target/riscv/sat_s_sub-run-3-i64.c: Move to...
+       * gcc.target/riscv/sat/sat_s_sub-run-3-i64.c: ...here.
+       * gcc.target/riscv/sat_s_sub-run-3-i8.c: Move to...
+       * gcc.target/riscv/sat/sat_s_sub-run-3-i8.c: ...here.
+       * gcc.target/riscv/sat_s_sub-run-4-i16.c: Move to...
+       * gcc.target/riscv/sat/sat_s_sub-run-4-i16.c: ...here.
+       * gcc.target/riscv/sat_s_sub-run-4-i32.c: Move to...
+       * gcc.target/riscv/sat/sat_s_sub-run-4-i32.c: ...here.
+       * gcc.target/riscv/sat_s_sub-run-4-i64.c: Move to...
+       * gcc.target/riscv/sat/sat_s_sub-run-4-i64.c: ...here.
+       * gcc.target/riscv/sat_s_sub-run-4-i8.c: Move to...
+       * gcc.target/riscv/sat/sat_s_sub-run-4-i8.c: ...here.
+       * gcc.target/riscv/sat_s_trunc-1-i16-to-i8.c: Move to...
+       * gcc.target/riscv/sat/sat_s_trunc-1-i16-to-i8.c: ...here.
+       * gcc.target/riscv/sat_s_trunc-1-i32-to-i16.c: Move to...
+       * gcc.target/riscv/sat/sat_s_trunc-1-i32-to-i16.c: ...here.
+       * gcc.target/riscv/sat_s_trunc-1-i32-to-i8.c: Move to...
+       * gcc.target/riscv/sat/sat_s_trunc-1-i32-to-i8.c: ...here.
+       * gcc.target/riscv/sat_s_trunc-1-i64-to-i16.c: Move to...
+       * gcc.target/riscv/sat/sat_s_trunc-1-i64-to-i16.c: ...here.
+       * gcc.target/riscv/sat_s_trunc-1-i64-to-i32.c: Move to...
+       * gcc.target/riscv/sat/sat_s_trunc-1-i64-to-i32.c: ...here.
+       * gcc.target/riscv/sat_s_trunc-1-i64-to-i8.c: Move to...
+       * gcc.target/riscv/sat/sat_s_trunc-1-i64-to-i8.c: ...here.
+       * gcc.target/riscv/sat_s_trunc-2-i16-to-i8.c: Move to...
+       * gcc.target/riscv/sat/sat_s_trunc-2-i16-to-i8.c: ...here.
+       * gcc.target/riscv/sat_s_trunc-2-i32-to-i16.c: Move to...
+       * gcc.target/riscv/sat/sat_s_trunc-2-i32-to-i16.c: ...here.
+       * gcc.target/riscv/sat_s_trunc-2-i32-to-i8.c: Move to...
+       * gcc.target/riscv/sat/sat_s_trunc-2-i32-to-i8.c: ...here.
+       * gcc.target/riscv/sat_s_trunc-2-i64-to-i16.c: Move to...
+       * gcc.target/riscv/sat/sat_s_trunc-2-i64-to-i16.c: ...here.
+       * gcc.target/riscv/sat_s_trunc-2-i64-to-i32.c: Move to...
+       * gcc.target/riscv/sat/sat_s_trunc-2-i64-to-i32.c: ...here.
+       * gcc.target/riscv/sat_s_trunc-2-i64-to-i8.c: Move to...
+       * gcc.target/riscv/sat/sat_s_trunc-2-i64-to-i8.c: ...here.
+       * gcc.target/riscv/sat_s_trunc-3-i16-to-i8.c: Move to...
+       * gcc.target/riscv/sat/sat_s_trunc-3-i16-to-i8.c: ...here.
+       * gcc.target/riscv/sat_s_trunc-3-i32-to-i16.c: Move to...
+       * gcc.target/riscv/sat/sat_s_trunc-3-i32-to-i16.c: ...here.
+       * gcc.target/riscv/sat_s_trunc-3-i32-to-i8.c: Move to...
+       * gcc.target/riscv/sat/sat_s_trunc-3-i32-to-i8.c: ...here.
+       * gcc.target/riscv/sat_s_trunc-3-i64-to-i16.c: Move to...
+       * gcc.target/riscv/sat/sat_s_trunc-3-i64-to-i16.c: ...here.
+       * gcc.target/riscv/sat_s_trunc-3-i64-to-i32.c: Move to...
+       * gcc.target/riscv/sat/sat_s_trunc-3-i64-to-i32.c: ...here.
+       * gcc.target/riscv/sat_s_trunc-3-i64-to-i8.c: Move to...
+       * gcc.target/riscv/sat/sat_s_trunc-3-i64-to-i8.c: ...here.
+       * gcc.target/riscv/sat_s_trunc-4-i16-to-i8.c: Move to...
+       * gcc.target/riscv/sat/sat_s_trunc-4-i16-to-i8.c: ...here.
+       * gcc.target/riscv/sat_s_trunc-4-i32-to-i16.c: Move to...
+       * gcc.target/riscv/sat/sat_s_trunc-4-i32-to-i16.c: ...here.
+       * gcc.target/riscv/sat_s_trunc-4-i32-to-i8.c: Move to...
+       * gcc.target/riscv/sat/sat_s_trunc-4-i32-to-i8.c: ...here.
+       * gcc.target/riscv/sat_s_trunc-4-i64-to-i16.c: Move to...
+       * gcc.target/riscv/sat/sat_s_trunc-4-i64-to-i16.c: ...here.
+       * gcc.target/riscv/sat_s_trunc-4-i64-to-i32.c: Move to...
+       * gcc.target/riscv/sat/sat_s_trunc-4-i64-to-i32.c: ...here.
+       * gcc.target/riscv/sat_s_trunc-4-i64-to-i8.c: Move to...
+       * gcc.target/riscv/sat/sat_s_trunc-4-i64-to-i8.c: ...here.
+       * gcc.target/riscv/sat_s_trunc-5-i16-to-i8.c: Move to...
+       * gcc.target/riscv/sat/sat_s_trunc-5-i16-to-i8.c: ...here.
+       * gcc.target/riscv/sat_s_trunc-5-i32-to-i16.c: Move to...
+       * gcc.target/riscv/sat/sat_s_trunc-5-i32-to-i16.c: ...here.
+       * gcc.target/riscv/sat_s_trunc-5-i32-to-i8.c: Move to...
+       * gcc.target/riscv/sat/sat_s_trunc-5-i32-to-i8.c: ...here.
+       * gcc.target/riscv/sat_s_trunc-5-i64-to-i16.c: Move to...
+       * gcc.target/riscv/sat/sat_s_trunc-5-i64-to-i16.c: ...here.
+       * gcc.target/riscv/sat_s_trunc-5-i64-to-i32.c: Move to...
+       * gcc.target/riscv/sat/sat_s_trunc-5-i64-to-i32.c: ...here.
+       * gcc.target/riscv/sat_s_trunc-5-i64-to-i8.c: Move to...
+       * gcc.target/riscv/sat/sat_s_trunc-5-i64-to-i8.c: ...here.
+       * gcc.target/riscv/sat_s_trunc-6-i16-to-i8.c: Move to...
+       * gcc.target/riscv/sat/sat_s_trunc-6-i16-to-i8.c: ...here.
+       * gcc.target/riscv/sat_s_trunc-6-i32-to-i16.c: Move to...
+       * gcc.target/riscv/sat/sat_s_trunc-6-i32-to-i16.c: ...here.
+       * gcc.target/riscv/sat_s_trunc-6-i32-to-i8.c: Move to...
+       * gcc.target/riscv/sat/sat_s_trunc-6-i32-to-i8.c: ...here.
+       * gcc.target/riscv/sat_s_trunc-6-i64-to-i16.c: Move to...
+       * gcc.target/riscv/sat/sat_s_trunc-6-i64-to-i16.c: ...here.
+       * gcc.target/riscv/sat_s_trunc-6-i64-to-i32.c: Move to...
+       * gcc.target/riscv/sat/sat_s_trunc-6-i64-to-i32.c: ...here.
+       * gcc.target/riscv/sat_s_trunc-6-i64-to-i8.c: Move to...
+       * gcc.target/riscv/sat/sat_s_trunc-6-i64-to-i8.c: ...here.
+       * gcc.target/riscv/sat_s_trunc-7-i16-to-i8.c: Move to...
+       * gcc.target/riscv/sat/sat_s_trunc-7-i16-to-i8.c: ...here.
+       * gcc.target/riscv/sat_s_trunc-7-i32-to-i16.c: Move to...
+       * gcc.target/riscv/sat/sat_s_trunc-7-i32-to-i16.c: ...here.
+       * gcc.target/riscv/sat_s_trunc-7-i32-to-i8.c: Move to...
+       * gcc.target/riscv/sat/sat_s_trunc-7-i32-to-i8.c: ...here.
+       * gcc.target/riscv/sat_s_trunc-7-i64-to-i16.c: Move to...
+       * gcc.target/riscv/sat/sat_s_trunc-7-i64-to-i16.c: ...here.
+       * gcc.target/riscv/sat_s_trunc-7-i64-to-i32.c: Move to...
+       * gcc.target/riscv/sat/sat_s_trunc-7-i64-to-i32.c: ...here.
+       * gcc.target/riscv/sat_s_trunc-7-i64-to-i8.c: Move to...
+       * gcc.target/riscv/sat/sat_s_trunc-7-i64-to-i8.c: ...here.
+       * gcc.target/riscv/sat_s_trunc-8-i16-to-i8.c: Move to...
+       * gcc.target/riscv/sat/sat_s_trunc-8-i16-to-i8.c: ...here.
+       * gcc.target/riscv/sat_s_trunc-8-i32-to-i16.c: Move to...
+       * gcc.target/riscv/sat/sat_s_trunc-8-i32-to-i16.c: ...here.
+       * gcc.target/riscv/sat_s_trunc-8-i32-to-i8.c: Move to...
+       * gcc.target/riscv/sat/sat_s_trunc-8-i32-to-i8.c: ...here.
+       * gcc.target/riscv/sat_s_trunc-8-i64-to-i16.c: Move to...
+       * gcc.target/riscv/sat/sat_s_trunc-8-i64-to-i16.c: ...here.
+       * gcc.target/riscv/sat_s_trunc-8-i64-to-i32.c: Move to...
+       * gcc.target/riscv/sat/sat_s_trunc-8-i64-to-i32.c: ...here.
+       * gcc.target/riscv/sat_s_trunc-8-i64-to-i8.c: Move to...
+       * gcc.target/riscv/sat/sat_s_trunc-8-i64-to-i8.c: ...here.
+       * gcc.target/riscv/sat_s_trunc-run-1-i16-to-i8.c: Move to...
+       * gcc.target/riscv/sat/sat_s_trunc-run-1-i16-to-i8.c: ...here.
+       * gcc.target/riscv/sat_s_trunc-run-1-i32-to-i16.c: Move to...
+       * gcc.target/riscv/sat/sat_s_trunc-run-1-i32-to-i16.c: ...here.
+       * gcc.target/riscv/sat_s_trunc-run-1-i32-to-i8.c: Move to...
+       * gcc.target/riscv/sat/sat_s_trunc-run-1-i32-to-i8.c: ...here.
+       * gcc.target/riscv/sat_s_trunc-run-1-i64-to-i16.c: Move to...
+       * gcc.target/riscv/sat/sat_s_trunc-run-1-i64-to-i16.c: ...here.
+       * gcc.target/riscv/sat_s_trunc-run-1-i64-to-i32.c: Move to...
+       * gcc.target/riscv/sat/sat_s_trunc-run-1-i64-to-i32.c: ...here.
+       * gcc.target/riscv/sat_s_trunc-run-1-i64-to-i8.c: Move to...
+       * gcc.target/riscv/sat/sat_s_trunc-run-1-i64-to-i8.c: ...here.
+       * gcc.target/riscv/sat_s_trunc-run-2-i16-to-i8.c: Move to...
+       * gcc.target/riscv/sat/sat_s_trunc-run-2-i16-to-i8.c: ...here.
+       * gcc.target/riscv/sat_s_trunc-run-2-i32-to-i16.c: Move to...
+       * gcc.target/riscv/sat/sat_s_trunc-run-2-i32-to-i16.c: ...here.
+       * gcc.target/riscv/sat_s_trunc-run-2-i32-to-i8.c: Move to...
+       * gcc.target/riscv/sat/sat_s_trunc-run-2-i32-to-i8.c: ...here.
+       * gcc.target/riscv/sat_s_trunc-run-2-i64-to-i16.c: Move to...
+       * gcc.target/riscv/sat/sat_s_trunc-run-2-i64-to-i16.c: ...here.
+       * gcc.target/riscv/sat_s_trunc-run-2-i64-to-i32.c: Move to...
+       * gcc.target/riscv/sat/sat_s_trunc-run-2-i64-to-i32.c: ...here.
+       * gcc.target/riscv/sat_s_trunc-run-2-i64-to-i8.c: Move to...
+       * gcc.target/riscv/sat/sat_s_trunc-run-2-i64-to-i8.c: ...here.
+       * gcc.target/riscv/sat_s_trunc-run-3-i16-to-i8.c: Move to...
+       * gcc.target/riscv/sat/sat_s_trunc-run-3-i16-to-i8.c: ...here.
+       * gcc.target/riscv/sat_s_trunc-run-3-i32-to-i16.c: Move to...
+       * gcc.target/riscv/sat/sat_s_trunc-run-3-i32-to-i16.c: ...here.
+       * gcc.target/riscv/sat_s_trunc-run-3-i32-to-i8.c: Move to...
+       * gcc.target/riscv/sat/sat_s_trunc-run-3-i32-to-i8.c: ...here.
+       * gcc.target/riscv/sat_s_trunc-run-3-i64-to-i16.c: Move to...
+       * gcc.target/riscv/sat/sat_s_trunc-run-3-i64-to-i16.c: ...here.
+       * gcc.target/riscv/sat_s_trunc-run-3-i64-to-i32.c: Move to...
+       * gcc.target/riscv/sat/sat_s_trunc-run-3-i64-to-i32.c: ...here.
+       * gcc.target/riscv/sat_s_trunc-run-3-i64-to-i8.c: Move to...
+       * gcc.target/riscv/sat/sat_s_trunc-run-3-i64-to-i8.c: ...here.
+       * gcc.target/riscv/sat_s_trunc-run-4-i16-to-i8.c: Move to...
+       * gcc.target/riscv/sat/sat_s_trunc-run-4-i16-to-i8.c: ...here.
+       * gcc.target/riscv/sat_s_trunc-run-4-i32-to-i16.c: Move to...
+       * gcc.target/riscv/sat/sat_s_trunc-run-4-i32-to-i16.c: ...here.
+       * gcc.target/riscv/sat_s_trunc-run-4-i32-to-i8.c: Move to...
+       * gcc.target/riscv/sat/sat_s_trunc-run-4-i32-to-i8.c: ...here.
+       * gcc.target/riscv/sat_s_trunc-run-4-i64-to-i16.c: Move to...
+       * gcc.target/riscv/sat/sat_s_trunc-run-4-i64-to-i16.c: ...here.
+       * gcc.target/riscv/sat_s_trunc-run-4-i64-to-i32.c: Move to...
+       * gcc.target/riscv/sat/sat_s_trunc-run-4-i64-to-i32.c: ...here.
+       * gcc.target/riscv/sat_s_trunc-run-4-i64-to-i8.c: Move to...
+       * gcc.target/riscv/sat/sat_s_trunc-run-4-i64-to-i8.c: ...here.
+       * gcc.target/riscv/sat_s_trunc-run-5-i16-to-i8.c: Move to...
+       * gcc.target/riscv/sat/sat_s_trunc-run-5-i16-to-i8.c: ...here.
+       * gcc.target/riscv/sat_s_trunc-run-5-i32-to-i16.c: Move to...
+       * gcc.target/riscv/sat/sat_s_trunc-run-5-i32-to-i16.c: ...here.
+       * gcc.target/riscv/sat_s_trunc-run-5-i32-to-i8.c: Move to...
+       * gcc.target/riscv/sat/sat_s_trunc-run-5-i32-to-i8.c: ...here.
+       * gcc.target/riscv/sat_s_trunc-run-5-i64-to-i16.c: Move to...
+       * gcc.target/riscv/sat/sat_s_trunc-run-5-i64-to-i16.c: ...here.
+       * gcc.target/riscv/sat_s_trunc-run-5-i64-to-i32.c: Move to...
+       * gcc.target/riscv/sat/sat_s_trunc-run-5-i64-to-i32.c: ...here.
+       * gcc.target/riscv/sat_s_trunc-run-5-i64-to-i8.c: Move to...
+       * gcc.target/riscv/sat/sat_s_trunc-run-5-i64-to-i8.c: ...here.
+       * gcc.target/riscv/sat_s_trunc-run-6-i16-to-i8.c: Move to...
+       * gcc.target/riscv/sat/sat_s_trunc-run-6-i16-to-i8.c: ...here.
+       * gcc.target/riscv/sat_s_trunc-run-6-i32-to-i16.c: Move to...
+       * gcc.target/riscv/sat/sat_s_trunc-run-6-i32-to-i16.c: ...here.
+       * gcc.target/riscv/sat_s_trunc-run-6-i32-to-i8.c: Move to...
+       * gcc.target/riscv/sat/sat_s_trunc-run-6-i32-to-i8.c: ...here.
+       * gcc.target/riscv/sat_s_trunc-run-6-i64-to-i16.c: Move to...
+       * gcc.target/riscv/sat/sat_s_trunc-run-6-i64-to-i16.c: ...here.
+       * gcc.target/riscv/sat_s_trunc-run-6-i64-to-i32.c: Move to...
+       * gcc.target/riscv/sat/sat_s_trunc-run-6-i64-to-i32.c: ...here.
+       * gcc.target/riscv/sat_s_trunc-run-6-i64-to-i8.c: Move to...
+       * gcc.target/riscv/sat/sat_s_trunc-run-6-i64-to-i8.c: ...here.
+       * gcc.target/riscv/sat_s_trunc-run-7-i16-to-i8.c: Move to...
+       * gcc.target/riscv/sat/sat_s_trunc-run-7-i16-to-i8.c: ...here.
+       * gcc.target/riscv/sat_s_trunc-run-7-i32-to-i16.c: Move to...
+       * gcc.target/riscv/sat/sat_s_trunc-run-7-i32-to-i16.c: ...here.
+       * gcc.target/riscv/sat_s_trunc-run-7-i32-to-i8.c: Move to...
+       * gcc.target/riscv/sat/sat_s_trunc-run-7-i32-to-i8.c: ...here.
+       * gcc.target/riscv/sat_s_trunc-run-7-i64-to-i16.c: Move to...
+       * gcc.target/riscv/sat/sat_s_trunc-run-7-i64-to-i16.c: ...here.
+       * gcc.target/riscv/sat_s_trunc-run-7-i64-to-i32.c: Move to...
+       * gcc.target/riscv/sat/sat_s_trunc-run-7-i64-to-i32.c: ...here.
+       * gcc.target/riscv/sat_s_trunc-run-7-i64-to-i8.c: Move to...
+       * gcc.target/riscv/sat/sat_s_trunc-run-7-i64-to-i8.c: ...here.
+       * gcc.target/riscv/sat_s_trunc-run-8-i16-to-i8.c: Move to...
+       * gcc.target/riscv/sat/sat_s_trunc-run-8-i16-to-i8.c: ...here.
+       * gcc.target/riscv/sat_s_trunc-run-8-i32-to-i16.c: Move to...
+       * gcc.target/riscv/sat/sat_s_trunc-run-8-i32-to-i16.c: ...here.
+       * gcc.target/riscv/sat_s_trunc-run-8-i32-to-i8.c: Move to...
+       * gcc.target/riscv/sat/sat_s_trunc-run-8-i32-to-i8.c: ...here.
+       * gcc.target/riscv/sat_s_trunc-run-8-i64-to-i16.c: Move to...
+       * gcc.target/riscv/sat/sat_s_trunc-run-8-i64-to-i16.c: ...here.
+       * gcc.target/riscv/sat_s_trunc-run-8-i64-to-i32.c: Move to...
+       * gcc.target/riscv/sat/sat_s_trunc-run-8-i64-to-i32.c: ...here.
+       * gcc.target/riscv/sat_s_trunc-run-8-i64-to-i8.c: Move to...
+       * gcc.target/riscv/sat/sat_s_trunc-run-8-i64-to-i8.c: ...here.
+       * gcc.target/riscv/sat_arith.h: Removed.
+       * gcc.target/riscv/sat_arith_data.h: Removed.
+
 2024-11-19  Mikael Morin  <mikael@gcc.gnu.org>
 
        PR fortran/90608

diff --git a/libgm2/ChangeLog b/libgm2/ChangeLog
index 6a19c73817f1c87619561e61ddeecfab95f3404e..ebee2c0c6ed5014fb40666f3ddc7ab7a7820ff4e 100644 (file)
--- a/libgm2/ChangeLog
+++ b/libgm2/ChangeLog
@@ -1,3 +1,9 @@
+2024-11-20  Gaius Mulley  <gaiusmod2@gmail.com>
+
+       PR modula2/117703
+       * configure: Regenerate.
+       * configure.ac (libtool_VERSION): Bump to 20:0:0.
+
 2024-05-29  Gaius Mulley  <gaiusmod2@gmail.com>
 
        PR modula2/115276

diff --git a/libgomp/ChangeLog b/libgomp/ChangeLog
index 393f8ba5ac7156498801185a1100eb6c4059edac..456a179b9bb0ba4489883d2d68776fc341561631 100644 (file)
--- a/libgomp/ChangeLog
+++ b/libgomp/ChangeLog
@@ -1,3 +1,8 @@
+2024-11-20  Paul-Antoine Arras  <parras@baylibre.com>
+
+       * testsuite/libgomp.c-c++-common/dispatch-1.c: New test.
+       * testsuite/libgomp.c-c++-common/dispatch-2.c: New test.
+
 2024-11-18  David Malcolm  <dmalcolm@redhat.com>
 
        * testsuite/lib/libgomp.exp: Add

diff --git a/libstdc++-v3/ChangeLog b/libstdc++-v3/ChangeLog
index 2c89a8e19ae3d02556bb9222709316ba86e72996..79703985204359588a5ef461ae085072e277cda9 100644 (file)
--- a/libstdc++-v3/ChangeLog
+++ b/libstdc++-v3/ChangeLog
@@ -1,3 +1,16 @@
+2024-11-20  Jonathan Wakely  <jwakely@redhat.com>
+
+       * include/bits/stl_set.h (set::find): Use const_iterator in
+       return type, not iterator.
+
+2024-11-20  Jonathan Wakely  <jwakely@redhat.com>
+
+       PR libstdc++/117686
+       * include/bits/hashtable.h (_Hashtable::_M_emplace_uniq):
+       Adjust usage of __is_key_type to avoid false positive.
+       * testsuite/23_containers/unordered_set/insert/117686.cc:
+       New test.
+
 2024-11-19  Jason Merrill  <jason@redhat.com>
 
        * src/c++23/libstdc++.modules.json.in: Remove C++ comment.