arm64: dts: mediatek: mt8188: Add missing #reset-cells property

The binding now require the '#reset-cells' property but the
devicetree has not been updated which trigger dtb-check errors.

Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Signed-off-by: Julien Massot <julien.massot@collabora.com>
Link: https://lore.kernel.org/r/20250516-dtb-check-mt8188-v2-2-fb60bef1b8e1@collabora.com
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>

diff --git a/arch/arm64/boot/dts/mediatek/mt8188.dtsi b/arch/arm64/boot/dts/mediatek/mt8188.dtsi
index 296090fbaf4953db8075f72073509b731dc41e51..dec6ce3e94e92c8e1e2c3680cb3584394d9058bd 100644 (file)
--- a/arch/arm64/boot/dts/mediatek/mt8188.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8188.dtsi
@@ -2647,36 +2647,42 @@
                        compatible = "mediatek,mt8188-imgsys1-dip-top";
                        reg = <0 0x15110000 0 0x1000>;
                        #clock-cells = <1>;
+                       #reset-cells = <1>;
                };
 
                imgsys1_dip_nr: clock-controller@15130000 {
                        compatible = "mediatek,mt8188-imgsys1-dip-nr";
                        reg = <0 0x15130000 0 0x1000>;
                        #clock-cells = <1>;
+                       #reset-cells = <1>;
                };
 
                imgsys_wpe1: clock-controller@15220000 {
                        compatible = "mediatek,mt8188-imgsys-wpe1";
                        reg = <0 0x15220000 0 0x1000>;
                        #clock-cells = <1>;
+                       #reset-cells = <1>;
                };
 
                ipesys: clock-controller@15330000 {
                        compatible = "mediatek,mt8188-ipesys";
                        reg = <0 0x15330000 0 0x1000>;
                        #clock-cells = <1>;
+                       #reset-cells = <1>;
                };
 
                imgsys_wpe2: clock-controller@15520000 {
                        compatible = "mediatek,mt8188-imgsys-wpe2";
                        reg = <0 0x15520000 0 0x1000>;
                        #clock-cells = <1>;
+                       #reset-cells = <1>;
                };
 
                imgsys_wpe3: clock-controller@15620000 {
                        compatible = "mediatek,mt8188-imgsys-wpe3";
                        reg = <0 0x15620000 0 0x1000>;
                        #clock-cells = <1>;
+                       #reset-cells = <1>;
                };
 
                camsys: clock-controller@16000000 {
@@ -2689,24 +2695,28 @@
                        compatible = "mediatek,mt8188-camsys-rawa";
                        reg = <0 0x1604f000 0 0x1000>;
                        #clock-cells = <1>;
+                       #reset-cells = <1>;
                };
 
                camsys_yuva: clock-controller@1606f000 {
                        compatible = "mediatek,mt8188-camsys-yuva";
                        reg = <0 0x1606f000 0 0x1000>;
                        #clock-cells = <1>;
+                       #reset-cells = <1>;
                };
 
                camsys_rawb: clock-controller@1608f000 {
                        compatible = "mediatek,mt8188-camsys-rawb";
                        reg = <0 0x1608f000 0 0x1000>;
                        #clock-cells = <1>;
+                       #reset-cells = <1>;
                };
 
                camsys_yuvb: clock-controller@160af000 {
                        compatible = "mediatek,mt8188-camsys-yuvb";
                        reg = <0 0x160af000 0 0x1000>;
                        #clock-cells = <1>;
+                       #reset-cells = <1>;
                };
 
                ccusys: clock-controller@17200000 {