arm, mve: Fix scan-assembler for test7 in dlstp-compile-asm-2.c

After the changes to the vctp intrinsic codegen changed slightly, where we now
unfortunately seem to be generating unneeded moves and extends of the mask.
These are however not incorrect and we don't have a fix for the unneeded
codegen right now, so changing the testcase to accept them so we can catch
other changes if they occur.

gcc/testsuite/ChangeLog:

	PR target/117814
	* gcc.target/arm/mve/dlstp-compile-asm-2.c (test7): Add an optional
	vmsr to the check-function-bodies.

diff --git a/gcc/testsuite/gcc.target/arm/mve/dlstp-compile-asm-2.c b/gcc/testsuite/gcc.target/arm/mve/dlstp-compile-asm-2.c
index c62f592a60dd87bee785a70c25c977e76c88c0a5..210930447084fce2c200e482a06e3f1e8c2c417c 100644 (file)
--- a/gcc/testsuite/gcc.target/arm/mve/dlstp-compile-asm-2.c
+++ b/gcc/testsuite/gcc.target/arm/mve/dlstp-compile-asm-2.c
@@ -216,7 +216,12 @@ void test7 (int32_t *a, int32_t *b, int32_t *c, int n, int g)
 **...
 **     dlstp.32        lr, r3
 **     vldrw.32        q[0-9]+, \[r0\], #16
+** (
+**     vmsr    p0, .*
 **     vpst
+** |
+**     vpst
+** )
 **     vldrwt.32       q[0-9]+, \[r1\], #16
 **     vadd.i32        (q[0-9]+), q[0-9]+, q[0-9]+
 **     vstrw.32        \1, \[r2\], #16