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[Morello] Loads and stores with alternate base
authorSiddhesh Poyarekar <siddesh.poyarekar@arm.com>
Fri, 11 Sep 2020 03:48:07 +0000 (09:18 +0530)
committerJohn Baldwin <jhb@FreeBSD.org>
Thu, 1 Sep 2022 22:53:21 +0000 (15:53 -0700)
These are loads that use a capability base register in A64 and 64-bit
integer register in C64.

This patch implements LDAR, LDARB, STLR and STLRB.

gas/ChangeLog:

2020-10-20  Siddhesh Poyarekar  <siddesh.poyarekar@arm.com>

* config/tc-aarch64.c (parse_operands): Add Wt.
* testsuite/gas/aarch64/morello_ldst-c64.d: Add tests.
* testsuite/gas/aarch64/morello_ldst.d: Likewise.
* testsuite/gas/aarch64/morello_ldst.s: Likewise.

include/ChangeLog:

2020-10-20  Siddhesh Poyarekar  <siddesh.poyarekar@arm.com>

* opcode/aarch64.h (aarch64_opnd): Add Wt.

opcodes/ChangeLog:

2020-10-20  Siddhesh Poyarekar  <siddesh.poyarekar@arm.com>

* aarch64-opc.c (get_altbase_reg_name): New function.
(aarch64_print_operand): Use it.  Add Wt.
* aarch64-tbl.h (QL2_A64C_W_CAPADDR): New macro.
(aarch64_opcode_table): Add instructions.
(AARCH64_OPERANDS): New operand.
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc-2.c: Regenerate.

gas/ChangeLog patch | blob | blame | history
gas/config/tc-aarch64.c patch | blob | blame | history
gas/testsuite/gas/aarch64/morello_ldst-c64.d patch | blob | blame | history
gas/testsuite/gas/aarch64/morello_ldst.d patch | blob | blame | history
gas/testsuite/gas/aarch64/morello_ldst.s patch | blob | blame | history
include/ChangeLog patch | blob | blame | history
include/opcode/aarch64.h patch | blob | blame | history
opcodes/ChangeLog patch | blob | blame | history
opcodes/aarch64-opc.c patch | blob | blame | history
opcodes/aarch64-tbl.h patch | blob | blame | history

diff --git a/gas/ChangeLog b/gas/ChangeLog
index 1f85fddd0813a5f5f8841c21f466099d353b6443..725661c755424f78a3130ae60eea65e9b26a65b4 100644 (file)
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,3 +1,10 @@
+2020-10-20  Siddhesh Poyarekar  <siddesh.poyarekar@arm.com>
+
+       * config/tc-aarch64.c (parse_operands): Add Wt.
+       * testsuite/gas/aarch64/morello_ldst-c64.d: Add tests.
+       * testsuite/gas/aarch64/morello_ldst.d: Likewise.
+       * testsuite/gas/aarch64/morello_ldst.s: Likewise.
+
 2020-10-20  Siddhesh Poyarekar  <siddesh.poyarekar@arm.com>
 
        * config/tc-aarch64.c (parse_operands, fix_insn): Add
diff --git a/gas/config/tc-aarch64.c b/gas/config/tc-aarch64.c
index e0ee563c66c6fb044a8719a0f5cb2eca8a8a4dab..abe88e354cb83d09201dfb4730d97f60d2ea5ab3 100644 (file)
--- a/gas/config/tc-aarch64.c
+++ b/gas/config/tc-aarch64.c
@@ -6444,6 +6444,10 @@ parse_operands (char *str, const aarch64_opcode *opcode)
 
       switch (operands[i])
        {
+       case AARCH64_OPND_Wt:
+         po_int_reg_or_fail (REG_TYPE_R_32);
+         break;
+
        case AARCH64_OPND_Rd:
        case AARCH64_OPND_Rn:
        case AARCH64_OPND_Rm:
diff --git a/gas/testsuite/gas/aarch64/morello_ldst-c64.d b/gas/testsuite/gas/aarch64/morello_ldst-c64.d
index cfc650360433eeb6781ae0c0d95232502989853e..a200110fbb4a6de4ed4c26ae677f145c219a982f 100644 (file)
--- a/gas/testsuite/gas/aarch64/morello_ldst-c64.d
+++ b/gas/testsuite/gas/aarch64/morello_ldst-c64.d
@@ -214,3 +214,15 @@ Disassembly of section \.text:
 .*:    c2c413e2        ldpbr   c2, \[csp\]
 .*:    c2c43042        ldpblr  c2, \[c2\]
 .*:    c2c41042        ldpbr   c2, \[c2\]
+.*:    425f7d82        ldar    c2, \[x12\]
+.*:    421f7d82        stlr    c2, \[x12\]
+.*:    425f7fe2        ldar    c2, \[sp\]
+.*:    421f7fe2        stlr    c2, \[sp\]
+.*:    427f7d82        ldarb   w2, \[x12\]
+.*:    427ffd82        ldar    w2, \[x12\]
+.*:    423f7d82        stlrb   w2, \[x12\]
+.*:    423ffd82        stlr    w2, \[x12\]
+.*:    427f7fe2        ldarb   w2, \[sp\]
+.*:    427fffe2        ldar    w2, \[sp\]
+.*:    423f7fe2        stlrb   w2, \[sp\]
+.*:    423fffe2        stlr    w2, \[sp\]
diff --git a/gas/testsuite/gas/aarch64/morello_ldst.d b/gas/testsuite/gas/aarch64/morello_ldst.d
index 49a57a68c3bf6d73b35fb97ff20f36ea12fc52f4..70c1c59cd0f3983a5fd7c2b4418092aef0f43cd6 100644 (file)
--- a/gas/testsuite/gas/aarch64/morello_ldst.d
+++ b/gas/testsuite/gas/aarch64/morello_ldst.d
@@ -213,3 +213,15 @@ Disassembly of section \.text:
 .*:    c2c413e2        ldpbr   c2, \[csp\]
 .*:    c2c43042        ldpblr  c2, \[c2\]
 .*:    c2c41042        ldpbr   c2, \[c2\]
+.*:    425f7ea2        ldar    c2, \[c21\]
+.*:    421f7ea2        stlr    c2, \[c21\]
+.*:    425f7fe2        ldar    c2, \[csp\]
+.*:    421f7fe2        stlr    c2, \[csp\]
+.*:    427f7ea2        ldarb   w2, \[c21\]
+.*:    427ffea2        ldar    w2, \[c21\]
+.*:    423f7ea2        stlrb   w2, \[c21\]
+.*:    423ffea2        stlr    w2, \[c21\]
+.*:    427f7fe2        ldarb   w2, \[csp\]
+.*:    427fffe2        ldar    w2, \[csp\]
+.*:    423f7fe2        stlrb   w2, \[csp\]
+.*:    423fffe2        stlr    w2, \[csp\]
diff --git a/gas/testsuite/gas/aarch64/morello_ldst.s b/gas/testsuite/gas/aarch64/morello_ldst.s
index 6de19b0e6a111fde04c7197b260439cf12e3f737..98db4907c3dfb5973bc4fff79599776e9bf8bf25 100644 (file)
--- a/gas/testsuite/gas/aarch64/morello_ldst.s
+++ b/gas/testsuite/gas/aarch64/morello_ldst.s
@@ -163,3 +163,21 @@ morello_branch_load c2
        .endm
 morello_branch_load2 csp
 morello_branch_load2 c2
+
+// Alternate base loads and stores.
+
+       .macro morello_ldst_alt_base ct, cnsp
+         .irp op,ldar, stlr
+           \op    \ct, [\cnsp]
+         .endr
+       .endm
+morello_ldst_alt_base c2, ALTVAREG
+morello_ldst_alt_base c2, ALTSP
+
+       .macro morello_ldst_alt_basew wt, cnsp
+         .irp op, ldarb, ldar, stlrb, stlr
+           \op    \wt, [\cnsp]
+         .endr
+       .endm
+morello_ldst_alt_basew w2, ALTVAREG
+morello_ldst_alt_basew w2, ALTSP
diff --git a/include/ChangeLog b/include/ChangeLog
index 710db31c272d906f1ec9fa414fbd1866d06b0350..937e34f7b99ae3c7c36e7d557f1ea6672d09995a 100644 (file)
--- a/include/ChangeLog
+++ b/include/ChangeLog
@@ -1,3 +1,7 @@
+2020-10-20  Siddhesh Poyarekar  <siddesh.poyarekar@arm.com>
+
+       * opcode/aarch64.h (aarch64_opnd): Add Wt.
+
 2020-10-20  Siddhesh Poyarekar  <siddesh.poyarekar@arm.com>
 
        * opcode/aarch64.h (aarch64_opnd): Add A64C_ADDR_SIMM9.
diff --git a/include/opcode/aarch64.h b/include/opcode/aarch64.h
index 4366b2a2d68de2d8df6d9d6294f18adfe6a69644..b55d459f9e31471929729e2ea64ae21eb7d5aaeb 100644 (file)
--- a/include/opcode/aarch64.h
+++ b/include/opcode/aarch64.h
@@ -252,6 +252,8 @@ enum aarch64_opnd
   AARCH64_OPND_Rn,     /* Integer register as source.  */
   AARCH64_OPND_Rm,     /* Integer register as source.  */
   AARCH64_OPND_Rt,     /* Integer register used in ld/st instructions.  */
+  AARCH64_OPND_Wt,     /* 32-bit integer register used in ld/st
+                          instructions.  */
   AARCH64_OPND_Rt2,    /* Integer register used in ld/st pair instructions.  */
   AARCH64_OPND_Rt_LS64,        /* Integer register used in LS64 instructions.  */
   AARCH64_OPND_Rt_SP,  /* Integer Rt or SP used in STG instructions.  */
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index 5cdc946836ced748158f691d773f090c450238c8..4fd084b8ac2822ba75b51917f081f0f47d75aa19 100644 (file)
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,14 @@
+2020-10-20  Siddhesh Poyarekar  <siddesh.poyarekar@arm.com>
+
+       * aarch64-opc.c (get_altbase_reg_name): New function.
+       (aarch64_print_operand): Use it.  Add Wt.
+       * aarch64-tbl.h (QL2_A64C_W_CAPADDR): New macro.
+       (aarch64_opcode_table): Add instructions.
+       (AARCH64_OPERANDS): New operand.
+       * aarch64-asm-2.c: Regenerate.
+       * aarch64-dis-2.c: Regenerate.
+       * aarch64-opc-2.c: Regenerate.
+
 2020-10-20  Siddhesh Poyarekar  <siddesh.poyarekar@arm.com>
 
        * aarch64-asm.c (aarch64_ins_addr_simm): Support scaling.
diff --git a/opcodes/aarch64-opc.c b/opcodes/aarch64-opc.c
index e8d4f7451a348193377dbf7d58ddcfe4243d833c..1fcabb39df642df2336b761522f50eda08197215 100644 (file)
--- a/opcodes/aarch64-opc.c
+++ b/opcodes/aarch64-opc.c
@@ -3119,6 +3119,17 @@ get_cap_reg_name (int regno, int sp_reg_p)
   return int_reg[has_zr][2][regno];
 }
 
+static inline const char *
+get_altbase_reg_name (aarch64_feature_set features, int regno, int sp_reg_p,
+                     const aarch64_opcode *opcode)
+{
+  if (AARCH64_CPU_HAS_FEATURE(features, AARCH64_FEATURE_C64)
+      && opcode->iclass != br_capaddr)
+    return get_64bit_int_reg_name (regno, sp_reg_p);
+  else
+    return get_cap_reg_name (regno, sp_reg_p);
+}
+
 static inline const char *
 get_base_reg_name (aarch64_feature_set features, int regno, int sp_reg_p)
 {
@@ -3433,6 +3444,7 @@ aarch64_print_operand (char *buf, size_t size, bfd_vma pc,
     case AARCH64_OPND_Rn:
     case AARCH64_OPND_Rm:
     case AARCH64_OPND_Rt:
+    case AARCH64_OPND_Wt:
     case AARCH64_OPND_Rt2:
     case AARCH64_OPND_Rs:
     case AARCH64_OPND_Ra:
@@ -3927,7 +3939,7 @@ aarch64_print_operand (char *buf, size_t size, bfd_vma pc,
 
     case AARCH64_OPND_CAPADDR_SIMPLE:
       snprintf (buf, size, "[%s]",
-               get_cap_reg_name (opnd->addr.base_regno, 1));
+               get_altbase_reg_name (features, opnd->addr.base_regno, 1, opcode));
       break;
 
     case AARCH64_OPND_ADDR_SIMPLE:
diff --git a/opcodes/aarch64-tbl.h b/opcodes/aarch64-tbl.h
index 5cb8d9ee2ec0f5640b93406dc229f8bdad211101..e782777f5b54467bc4162d24ad511c5b05d44683 100644 (file)
--- a/opcodes/aarch64-tbl.h
+++ b/opcodes/aarch64-tbl.h
@@ -2427,6 +2427,12 @@
   QLF2(CA, S_Q),               \
 }
 
+/* LDAR Wt, [<Cn|CSP>] */
+#define QL2_A64C_W_CAPADDR     \
+{                              \
+  QLF2(W, S_S),                \
+}
+
 /* LDAPR Ct, [<Xn|SP>] */
 #define QL2_A64C_CA_ADDR       \
 {                              \
@@ -4232,6 +4238,14 @@ const struct aarch64_opcode aarch64_opcode_table[] =
   A64C_INSN ("swpal", 0xa2e08000, 0xffe0fc00, a64c, 0, OP3 (Cas, Cat, ADDR_SIMPLE), QL3_A64C_CA_CA_ADDR, 0),
   A64C_INSN ("swpl", 0xa2608000, 0xffe0fc00, a64c, 0, OP3 (Cas, Cat, ADDR_SIMPLE), QL3_A64C_CA_CA_ADDR, 0),
 
+  /* Load/stores with alternate base, i.e. [<Cn|CSP>] in A64 mode and [<Xn|SP>] in C64 mode.  */
+  A64C_INSN ("ldar", 0x425f7c00, 0xfffffc00, ldstexcl, 0, OP2 (Cat, CAPADDR_SIMPLE), QL2_A64C_CA_CAPADDR, 0),
+  A64C_INSN ("ldar", 0x427ffc00, 0xfffffc00, ldstexcl, 0, OP2 (Wt, CAPADDR_SIMPLE), QL2_A64C_W_CAPADDR, 0),
+  A64C_INSN ("ldarb", 0x427f7c00, 0xfffffc00, ldstexcl, 0, OP2 (Wt, CAPADDR_SIMPLE), QL2_A64C_W_CAPADDR, 0),
+  A64C_INSN ("stlr", 0x421f7c00, 0xfffffc00, ldstexcl, 0, OP2 (Cat, CAPADDR_SIMPLE), QL2_A64C_CA_ADDR, 0),
+  A64C_INSN ("stlr", 0x423ffc00, 0xfffffc00, ldstexcl, 0, OP2 (Wt, CAPADDR_SIMPLE), QL2_A64C_W_CAPADDR, 0),
+  A64C_INSN ("stlrb", 0x423f7c00, 0xfffffc00, ldstexcl, 0, OP2 (Wt, CAPADDR_SIMPLE), QL2_A64C_W_CAPADDR, 0),
+
   A64C_INSN ("ret", 0xc2c25000, 0xfffffc1f, a64c, 0, OP1 (Can), QL1_A64C_CA, F_OPD0_OPT | F_DEFAULT (30)),
   A64C_INSN ("retr", 0xc2c25003, 0xfffffc1f, a64c, 0, OP1 (Can), QL1_A64C_CA, 0),
   A64C_INSN ("rets", 0xc2c25002, 0xfffffc1f, a64c, 0, OP1 (Can), QL1_A64C_CA, 0),
@@ -5697,6 +5711,7 @@ const struct aarch64_opcode aarch64_opcode_table[] =
     Y(INT_REG, regno, "Rn", 0, F(FLD_Rn), "an integer register")       \
     Y(INT_REG, regno, "Rm", 0, F(FLD_Rm), "an integer register")       \
     Y(INT_REG, regno, "Rt", 0, F(FLD_Rt), "an integer register")       \
+    Y(INT_REG, regno, "Wt", 0, F(FLD_Rt), "a 32-bit integer register") \
     Y(INT_REG, regno, "Rt2", 0, F(FLD_Rt2), "an integer register")     \
     Y(INT_REG, regno, "Rt_LS64", 0, F(FLD_Rt), "an integer register")  \
     Y(INT_REG, regno, "Rt_SP", OPD_F_MAYBE_SP, F(FLD_Rt),              \
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