riscv: dts: sophgo: sg2044: Add GPIO device

The GPIO controller is a standard Synopsys IP, which is already
supported by the kernel.

Add GPIO DT node for SG2044 SoC.

Link: https://lore.kernel.org/r/20250608232836.784737-4-inochiama@gmail.com
Signed-off-by: Inochi Amaoto <inochiama@gmail.com>
Signed-off-by: Chen Wang <unicorn_wang@outlook.com>
Signed-off-by: Chen Wang <wangchen20@iscas.ac.cn>

diff --git a/arch/riscv/boot/dts/sophgo/sg2044.dtsi b/arch/riscv/boot/dts/sophgo/sg2044.dtsi
index d21a59948186f8d2f114b9b0cf600fb37f3ab7db..70d1096f959f2fe3aa05c97513b1551ecf1d7fc8 100644 (file)
--- a/arch/riscv/boot/dts/sophgo/sg2044.dtsi
+++ b/arch/riscv/boot/dts/sophgo/sg2044.dtsi
@@ -6,6 +6,7 @@
 #include <dt-bindings/clock/sophgo,sg2044-pll.h>
 #include <dt-bindings/clock/sophgo,sg2044-clk.h>
 #include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/gpio/gpio.h>
 
 #include "sg2044-cpus.dtsi"
 #include "sg2044-reset.h"
@@ -90,6 +91,75 @@
                        status = "disabled";
                };
 
+               gpio0: gpio@7040009000 {
+                       compatible = "snps,dw-apb-gpio";
+                       reg = <0x70 0x40009000 0x0 0x1000>;
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+                       clocks = <&clk CLK_GATE_APB_GPIO>,
+                                <&clk CLK_GATE_GPIO_DB>;
+                       clock-names = "bus", "db";
+                       resets = <&rst RST_GPIO0>;
+
+                       porta: gpio-controller@0 {
+                               compatible = "snps,dw-apb-gpio-port";
+                               reg = <0>;
+                               gpio-controller;
+                               #gpio-cells = <2>;
+                               ngpios = <32>;
+                               interrupt-controller;
+                               #interrupt-cells = <2>;
+                               interrupt-parent = <&intc>;
+                               interrupts = <26 IRQ_TYPE_LEVEL_HIGH>;
+                       };
+               };
+
+               gpio1: gpio@704000a000 {
+                       compatible = "snps,dw-apb-gpio";
+                       reg = <0x70 0x4000a000 0x0 0x1000>;
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+                       clocks = <&clk CLK_GATE_APB_GPIO>,
+                                <&clk CLK_GATE_GPIO_DB>;
+                       clock-names = "bus", "db";
+                       resets = <&rst RST_GPIO1>;
+
+                       portb: gpio-controller@0 {
+                               compatible = "snps,dw-apb-gpio-port";
+                               reg = <0>;
+                               gpio-controller;
+                               #gpio-cells = <2>;
+                               ngpios = <32>;
+                               interrupt-controller;
+                               #interrupt-cells = <2>;
+                               interrupt-parent = <&intc>;
+                               interrupts = <27 IRQ_TYPE_LEVEL_HIGH>;
+                       };
+               };
+
+               gpio2: gpio@704000b000 {
+                       compatible = "snps,dw-apb-gpio";
+                       reg = <0x70 0x4000b000 0x0 0x1000>;
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+                       clocks = <&clk CLK_GATE_APB_GPIO>,
+                                <&clk CLK_GATE_GPIO_DB>;
+                       clock-names = "bus", "db";
+                       resets = <&rst RST_GPIO2>;
+
+                       portc: gpio-controller@0 {
+                               compatible = "snps,dw-apb-gpio-port";
+                               reg = <0>;
+                               gpio-controller;
+                               #gpio-cells = <2>;
+                               ngpios = <32>;
+                               interrupt-controller;
+                               #interrupt-cells = <2>;
+                               interrupt-parent = <&intc>;
+                               interrupts = <28 IRQ_TYPE_LEVEL_HIGH>;
+                       };
+               };
+
                syscon: syscon@7050000000 {
                        compatible = "sophgo,sg2044-top-syscon", "syscon";
                        reg = <0x70 0x50000000 0x0 0x1000>;