drm/i915/dp: Restrict max source rate for WCL to HBR3

WCL supports a maximum of HBR3 8.1 Gbps for both eDP/DP.
Limit the max source rate to HBR3 for WCL.

v2: Move the check inside mtl_max_source_rate(). (Suraj)

Bspec:74286
Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>
Link: https://patch.msgid.link/20251122053651.759389-1-ankit.k.nautiyal@intel.com

diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 44199548674553c0390b12451c0139cc7750204f..c27e9186a754a601674466622bf9cbe8efb8fb63 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -520,7 +520,8 @@ static int mtl_max_source_rate(struct intel_dp *intel_dp)
        struct intel_display *display = to_intel_display(intel_dp);
        struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
 
-       if (intel_encoder_is_c10phy(encoder))
+       if (intel_encoder_is_c10phy(encoder) ||
+           display->platform.pantherlake_wildcatlake)
                return 810000;
 
        if (DISPLAY_VERx100(display) == 1401)