RISC-V: Add VLS modes VEC_PERM support[PR111311]

This patch add VLS modes VEC_PERM support which fix these following
FAILs in https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111311:

FAIL: gcc.dg/tree-ssa/forwprop-40.c scan-tree-dump-times optimized "BIT_FIELD_REF" 0
FAIL: gcc.dg/tree-ssa/forwprop-40.c scan-tree-dump-times optimized "BIT_INSERT_EXPR" 0
FAIL: gcc.dg/tree-ssa/forwprop-41.c scan-tree-dump-times optimized "BIT_FIELD_REF" 0
FAIL: gcc.dg/tree-ssa/forwprop-41.c scan-tree-dump-times optimized "BIT_INSERT_EXPR" 1

These FAILs are fixed after this patch.

	PR target/111311

gcc/ChangeLog:

	* config/riscv/autovec.md: Add VLS modes.
	* config/riscv/riscv-protos.h (cmp_lmul_le_one): New function.
	(cmp_lmul_gt_one): Ditto.
	* config/riscv/riscv-v.cc (cmp_lmul_le_one): Ditto.
	(cmp_lmul_gt_one): Ditto.
	* config/riscv/riscv.cc (riscv_print_operand): Add VLS modes.
	(riscv_vectorize_vec_perm_const): Ditto.
	* config/riscv/vector-iterators.md: Ditto.
	* config/riscv/vector.md: Ditto.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/rvv/autovec/partial/slp-1.c: Adapt test.
	* gcc.target/riscv/rvv/autovec/partial/slp-16.c: Ditto.
	* gcc.target/riscv/rvv/autovec/partial/slp-17.c: Ditto.
	* gcc.target/riscv/rvv/autovec/partial/slp-3.c: Ditto.
	* gcc.target/riscv/rvv/autovec/partial/slp-5.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vls/compress-1.c: New test.
	* gcc.target/riscv/rvv/autovec/vls/compress-2.c: New test.
	* gcc.target/riscv/rvv/autovec/vls/compress-3.c: New test.
	* gcc.target/riscv/rvv/autovec/vls/compress-4.c: New test.
	* gcc.target/riscv/rvv/autovec/vls/compress-5.c: New test.
	* gcc.target/riscv/rvv/autovec/vls/compress-6.c: New test.
	* gcc.target/riscv/rvv/autovec/vls/merge-1.c: New test.
	* gcc.target/riscv/rvv/autovec/vls/merge-2.c: New test.
	* gcc.target/riscv/rvv/autovec/vls/merge-3.c: New test.
	* gcc.target/riscv/rvv/autovec/vls/merge-4.c: New test.
	* gcc.target/riscv/rvv/autovec/vls/merge-5.c: New test.
	* gcc.target/riscv/rvv/autovec/vls/merge-6.c: New test.
	* gcc.target/riscv/rvv/autovec/vls/merge-7.c: New test.
	* gcc.target/riscv/rvv/autovec/vls/perm-1.c: New test.
	* gcc.target/riscv/rvv/autovec/vls/perm-2.c: New test.
	* gcc.target/riscv/rvv/autovec/vls/perm-3.c: New test.
	* gcc.target/riscv/rvv/autovec/vls/perm-4.c: New test.
	* gcc.target/riscv/rvv/autovec/vls/perm-5.c: New test.
	* gcc.target/riscv/rvv/autovec/vls/perm-6.c: New test.
	* gcc.target/riscv/rvv/autovec/vls/perm-7.c: New test.

diff --git a/gcc/config/riscv/autovec.md b/gcc/config/riscv/autovec.md
index 98cd0c07625bb2ed42cebcdb72259f0a9ff87aa3..50ed1a900773f7bb9216f5b89e946ddc8a02dfac 100644 (file)
--- a/gcc/config/riscv/autovec.md
+++ b/gcc/config/riscv/autovec.md
@@ -354,9 +354,9 @@
 ;; -------------------------------------------------------------------------
 
 (define_expand "vec_perm<mode>"
-  [(match_operand:V 0 "register_operand")
-   (match_operand:V 1 "register_operand")
-   (match_operand:V 2 "register_operand")
+  [(match_operand:V_VLS 0 "register_operand")
+   (match_operand:V_VLS 1 "register_operand")
+   (match_operand:V_VLS 2 "register_operand")
    (match_operand:<VINDEX> 3 "vector_perm_operand")]
   "TARGET_VECTOR && GET_MODE_NUNITS (<MODE>mode).is_constant ()"
   {

diff --git a/gcc/config/riscv/riscv-protos.h b/gcc/config/riscv/riscv-protos.h
index 6dbf6b9f9436dd6aa2140e6a16eb1ad252dba7f0..46d77ef927c2a1adcba839418efb30d97a62deed 100644 (file)
--- a/gcc/config/riscv/riscv-protos.h
+++ b/gcc/config/riscv/riscv-protos.h
@@ -500,6 +500,8 @@ opt_machine_mode vectorize_related_mode (machine_mode, scalar_mode,
 unsigned int autovectorize_vector_modes (vec<machine_mode> *, bool);
 hash_set<basic_block> get_all_predecessors (basic_block);
 hash_set<basic_block> get_all_successors (basic_block);
+bool cmp_lmul_le_one (machine_mode);
+bool cmp_lmul_gt_one (machine_mode);
 }
 
 /* We classify builtin types into two classes:

diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc
index 847bc2487c84ac5a2a9f94659ffcab200bc1fea4..3cd1f61de0ee515d754e9f24db3226c9af25ca83 100644 (file)
--- a/gcc/config/riscv/riscv-v.cc
+++ b/gcc/config/riscv/riscv-v.cc
@@ -3436,4 +3436,26 @@ get_all_successors (basic_block bb)
   return blocks;
 }
 
+/* Return true if the LMUL of comparison less than or equal to one.  */
+bool
+cmp_lmul_le_one (machine_mode mode)
+{
+  if (riscv_v_ext_vector_mode_p (mode))
+    return known_le (GET_MODE_SIZE (mode), BYTES_PER_RISCV_VECTOR);
+  else if (riscv_v_ext_vls_mode_p (mode))
+    return known_le (GET_MODE_BITSIZE (mode), TARGET_MIN_VLEN);
+  return false;
+}
+
+/* Return true if the LMUL of comparison greater than one.  */
+bool
+cmp_lmul_gt_one (machine_mode mode)
+{
+  if (riscv_v_ext_vector_mode_p (mode))
+    return known_gt (GET_MODE_SIZE (mode), BYTES_PER_RISCV_VECTOR);
+  else if (riscv_v_ext_vls_mode_p (mode))
+    return known_gt (GET_MODE_BITSIZE (mode), TARGET_MIN_VLEN);
+  return false;
+}
+
 } // namespace riscv_vector

diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index 1d7332ff32be2275fe7a88fa8a8a8d26f0b1fca4..12926b206ace8c657bb4479b9625a9abae3db2e6 100644 (file)
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -5387,7 +5387,7 @@ riscv_print_operand (FILE *file, rtx op, int letter)
           1. If the operand is VECTOR REG, we print 'v'(vnsrl.wv).
           2. If the operand is CONST_INT/CONST_VECTOR, we print 'i'(vnsrl.wi).
           3. If the operand is SCALAR REG, we print 'x'(vnsrl.wx).  */
-       if (riscv_v_ext_vector_mode_p (mode))
+       if (riscv_v_ext_mode_p (mode))
          {
            if (REG_P (op))
              asm_fprintf (file, "v");
@@ -9473,7 +9473,7 @@ riscv_vectorize_vec_perm_const (machine_mode vmode, machine_mode op_mode,
                                rtx target, rtx op0, rtx op1,
                                const vec_perm_indices &sel)
 {
-  if (TARGET_VECTOR && riscv_v_ext_vector_mode_p (vmode))
+  if (TARGET_VECTOR && riscv_v_ext_mode_p (vmode))
     return riscv_vector::expand_vec_perm_const (vmode, op_mode, target, op0,
                                                op1, sel);
 

diff --git a/gcc/config/riscv/vector-iterators.md b/gcc/config/riscv/vector-iterators.md
index 5694c0c8f37712087c2c40c184ca078952133560..2f7f7cbe08c012f67c3d8981e132687de2c2efbb 100644 (file)
--- a/gcc/config/riscv/vector-iterators.md
+++ b/gcc/config/riscv/vector-iterators.md
@@ -376,6 +376,85 @@
 
   (RVVM8DF "TARGET_VECTOR_ELEN_FP_64") (RVVM4DF "TARGET_VECTOR_ELEN_FP_64")
   (RVVM2DF "TARGET_VECTOR_ELEN_FP_64") (RVVM1DF "TARGET_VECTOR_ELEN_FP_64")
+
+  (V1QI "TARGET_VECTOR_VLS")
+  (V2QI "TARGET_VECTOR_VLS")
+  (V4QI "TARGET_VECTOR_VLS")
+  (V8QI "TARGET_VECTOR_VLS")
+  (V16QI "TARGET_VECTOR_VLS")
+  (V32QI "TARGET_VECTOR_VLS")
+  (V64QI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 64")
+  (V128QI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 128")
+  (V256QI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 256")
+  (V512QI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 512")
+  (V1024QI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 1024")
+  (V2048QI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 2048")
+  (V1HI "TARGET_VECTOR_VLS")
+  (V2HI "TARGET_VECTOR_VLS")
+  (V4HI "TARGET_VECTOR_VLS")
+  (V8HI "TARGET_VECTOR_VLS")
+  (V16HI "TARGET_VECTOR_VLS")
+  (V32HI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 64")
+  (V64HI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 128")
+  (V128HI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 256")
+  (V256HI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 512")
+  (V512HI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 1024")
+  (V1024HI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 2048")
+  (V2048HI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 4096")
+  (V1SI "TARGET_VECTOR_VLS")
+  (V2SI "TARGET_VECTOR_VLS")
+  (V4SI "TARGET_VECTOR_VLS")
+  (V8SI "TARGET_VECTOR_VLS")
+  (V16SI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 64")
+  (V32SI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 128")
+  (V64SI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 256")
+  (V128SI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 512")
+  (V256SI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 1024")
+  (V512SI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 2048")
+  (V1024SI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 4096")
+  (V1DI "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_64")
+  (V2DI "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_64")
+  (V4DI "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_64")
+  (V8DI "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN >= 64")
+  (V16DI "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN >= 128")
+  (V32DI "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN >= 256")
+  (V64DI "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN >= 512")
+  (V128DI "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN >= 1024")
+  (V256DI "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN >= 2048")
+  (V512DI "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN >= 4096")
+  (V1HF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_16")
+  (V2HF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_16")
+  (V4HF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_16")
+  (V8HF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_16")
+  (V16HF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_16")
+  (V32HF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN >= 64")
+  (V64HF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN >= 128")
+  (V128HF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN >= 256")
+  (V256HF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN >= 512")
+  (V512HF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN >= 1024")
+  (V1024HF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN >= 2048")
+  (V2048HF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN >= 4096")
+  (V1SF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_32")
+  (V2SF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_32")
+  (V4SF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_32")
+  (V8SF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_32")
+  (V16SF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 64")
+  (V32SF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 128")
+  (V64SF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 256")
+  (V128SF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 512")
+  (V256SF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 1024")
+  (V512SF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 2048")
+  (V1024SF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 4096")
+  (V1DF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_64")
+  (V2DF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_64")
+  (V4DF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_64")
+  (V8DF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN >= 64")
+  (V16DF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN >= 128")
+  (V32DF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN >= 256")
+  (V64DF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN >= 512")
+  (V128DF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN >= 1024")
+  (V256DF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN >= 2048")
+  (V512DF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN >= 4096")
 ])
 
 (define_mode_iterator VI [
@@ -646,6 +725,7 @@
   (RVVM8DI "TARGET_VECTOR_ELEN_64") (RVVM4DI "TARGET_VECTOR_ELEN_64")
   (RVVM2DI "TARGET_VECTOR_ELEN_64") (RVVM1DI "TARGET_VECTOR_ELEN_64")
 
+  (V1DI "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_64")
   (V2DI "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_64")
   (V4DI "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_64")
   (V8DI "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN >= 64")
@@ -1200,6 +1280,86 @@
   (RVVM8DI "RVVM8DI") (RVVM4DI "RVVM4DI") (RVVM2DI "RVVM2DI") (RVVM1DI "RVVM1DI")
 
   (RVVM8DF "RVVM8DI") (RVVM4DF "RVVM4DI") (RVVM2DF "RVVM2DI") (RVVM1DF "RVVM1DI")
+
+  (V1QI "V1QI")
+  (V2QI "V2QI")
+  (V4QI "V4QI")
+  (V8QI "V8QI")
+  (V16QI "V16QI")
+  (V32QI "V32QI")
+  (V64QI "V64QI")
+  (V128QI "V128QI")
+  (V256QI "V256QI")
+  (V512QI "V512QI")
+  (V1024QI "V1024QI")
+  (V2048QI "V2048QI")
+  (V4096QI "V4096QI")
+  (V1HI "V1HI")
+  (V2HI "V2HI")
+  (V4HI "V4HI")
+  (V8HI "V8HI")
+  (V16HI "V16HI")
+  (V32HI "V32HI")
+  (V64HI "V64HI")
+  (V128HI "V128HI")
+  (V256HI "V256HI")
+  (V512HI "V512HI")
+  (V1024HI "V1024HI")
+  (V2048HI "V2048HI")
+  (V1SI "V1SI")
+  (V2SI "V2SI")
+  (V4SI "V4SI")
+  (V8SI "V8SI")
+  (V16SI "V16SI")
+  (V32SI "V32SI")
+  (V64SI "V64SI")
+  (V128SI "V128SI")
+  (V256SI "V256SI")
+  (V512SI "V512SI")
+  (V1024SI "V1024SI")
+  (V1DI "V1DI")
+  (V2DI "V2DI")
+  (V4DI "V4DI")
+  (V8DI "V8DI")
+  (V16DI "V16DI")
+  (V32DI "V32DI")
+  (V64DI "V64DI")
+  (V128DI "V128DI")
+  (V256DI "V256DI")
+  (V512DI "V512DI")
+  (V1HF "V1HI")
+  (V2HF "V2HI")
+  (V4HF "V4HI")
+  (V8HF "V8HI")
+  (V16HF "V16HI")
+  (V32HF "V32HI")
+  (V64HF "V64HI")
+  (V128HF "V128HI")
+  (V256HF "V256HI")
+  (V512HF "V512HI")
+  (V1024HF "V1024HI")
+  (V2048HF "V2048HI")
+  (V1SF "V1SI")
+  (V2SF "V2SI")
+  (V4SF "V4SI")
+  (V8SF "V8SI")
+  (V16SF "V16SI")
+  (V32SF "V32SI")
+  (V64SF "V64SI")
+  (V128SF "V128SI")
+  (V256SF "V256SI")
+  (V512SF "V512SI")
+  (V1024SF "V1024SI")
+  (V1DF "V1DI")
+  (V2DF "V2DI")
+  (V4DF "V4DI")
+  (V8DF "V8DI")
+  (V16DF "V16DI")
+  (V32DF "V32DI")
+  (V64DF "V64DI")
+  (V128DF "V128DI")
+  (V256DF "V256DI")
+  (V512DF "V512DI")
 ])
 
 (define_mode_attr VINDEXEI16 [
@@ -1216,6 +1376,85 @@
   (RVVM8SF "RVVM4HI") (RVVM4SF "RVVM2HI") (RVVM2SF "RVVM1HI") (RVVM1SF "RVVMF2HI") (RVVMF2SF "RVVMF4HI")
 
   (RVVM8DF "RVVM2HI") (RVVM4DF "RVVM1HI") (RVVM2DF "RVVMF2HI") (RVVM1DF "RVVMF4HI")
+
+  (V1QI "V1HI")
+  (V2QI "V2HI")
+  (V4QI "V4HI")
+  (V8QI "V8HI")
+  (V16QI "V16HI")
+  (V32QI "V32HI")
+  (V64QI "V64HI")
+  (V128QI "V128HI")
+  (V256QI "V256HI")
+  (V512QI "V512HI")
+  (V1024QI "V1024HI")
+  (V2048QI "V2048HI")
+  (V1HI "V1HI")
+  (V2HI "V2HI")
+  (V4HI "V4HI")
+  (V8HI "V8HI")
+  (V16HI "V16HI")
+  (V32HI "V32HI")
+  (V64HI "V64HI")
+  (V128HI "V128HI")
+  (V256HI "V256HI")
+  (V512HI "V512HI")
+  (V1024HI "V1024HI")
+  (V2048HI "V2048HI")
+  (V1SI "V1HI")
+  (V2SI "V2HI")
+  (V4SI "V4HI")
+  (V8SI "V8HI")
+  (V16SI "V16HI")
+  (V32SI "V32HI")
+  (V64SI "V64HI")
+  (V128SI "V128HI")
+  (V256SI "V256HI")
+  (V512SI "V512HI")
+  (V1024SI "V1024HI")
+  (V1DI "V1HI")
+  (V2DI "V2HI")
+  (V4DI "V4HI")
+  (V8DI "V8HI")
+  (V16DI "V16HI")
+  (V32DI "V32HI")
+  (V64DI "V64HI")
+  (V128DI "V128HI")
+  (V256DI "V256HI")
+  (V512DI "V512HI")
+  (V1HF "V1HI")
+  (V2HF "V2HI")
+  (V4HF "V4HI")
+  (V8HF "V8HI")
+  (V16HF "V16HF")
+  (V32HF "V32HI")
+  (V64HF "V64HI")
+  (V128HF "V128HI")
+  (V256HF "V256HI")
+  (V512HF "V512HI")
+  (V1024HF "V1024HI")
+  (V2048HF "V2048HI")
+  (V1SF "V1HI")
+  (V2SF "V2HI")
+  (V4SF "V4HI")
+  (V8SF "V8HI")
+  (V16SF "V16HI")
+  (V32SF "V32HI")
+  (V64SF "V64HI")
+  (V128SF "V128HI")
+  (V256SF "V256HI")
+  (V512SF "V512HI")
+  (V1024SF "V1024HI")
+  (V1DF "V1HI")
+  (V2DF "V2HI")
+  (V4DF "V4HI")
+  (V8DF "V8HI")
+  (V16DF "V16HI")
+  (V32DF "V32HI")
+  (V64DF "V64HI")
+  (V128DF "V128HI")
+  (V256DF "V256HI")
+  (V512DF "V512HI")
 ])
 
 (define_mode_attr VM [
@@ -1587,11 +1826,11 @@
   (RVVM8DF "SF") (RVVM4DF "SF") (RVVM2DF "SF") (RVVM1DF "SF")
 
   ;; VLS modes.
-  (V2HI "QI") (V4HI "QI") (V8HI "QI") (V16HI "QI") (V32HI "QI") (V64HI "QI") (V128HI "QI") (V256HI "QI")
+  (V1HI "QI") (V2HI "QI") (V4HI "QI") (V8HI "QI") (V16HI "QI") (V32HI "QI") (V64HI "QI") (V128HI "QI") (V256HI "QI")
   (V512HI "QI") (V1024HI "QI") (V2048HI "QI")
-  (V2SI "HI") (V4SI "HI") (V8SI "HI") (V16SI "HI") (V32SI "HI") (V64SI "HI") (V128SI "HI") (V256SI "HI")
+  (V1SI "HI") (V2SI "HI") (V4SI "HI") (V8SI "HI") (V16SI "HI") (V32SI "HI") (V64SI "HI") (V128SI "HI") (V256SI "HI")
   (V512SI "HI") (V1024SI "HI")
-  (V2DI "SI") (V4DI "SI") (V8DI "SI") (V16DI "SI") (V32DI "SI") (V64DI "SI") (V128DI "SI") (V256DI "SI") (V512DI "SI")
+  (V1DI "SI") (V2DI "SI") (V4DI "SI") (V8DI "SI") (V16DI "SI") (V32DI "SI") (V64DI "SI") (V128DI "SI") (V256DI "SI") (V512DI "SI")
 ])
 
 (define_mode_attr nf [
@@ -1945,10 +2184,30 @@
 
 (define_mode_attr VDEMOTE [
   (RVVM8DI "RVVM8SI") (RVVM4DI "RVVM4SI") (RVVM2DI "RVVM2SI") (RVVM1DI "RVVM1SI")
+  (V1DI "V1SI")
+  (V2DI "V2SI")
+  (V4DI "V4SI")
+  (V8DI "V8SI")
+  (V16DI "V16SI")
+  (V32DI "V32SI")
+  (V64DI "V64SI")
+  (V128DI "V128SI")
+  (V256DI "V256SI")
+  (V512DI "V512SI")
 ])
 
 (define_mode_attr VMDEMOTE [
   (RVVM8DI "RVVMF4BI") (RVVM4DI "RVVMF8BI") (RVVM2DI "RVVMF16BI") (RVVM1DI "RVVMF32BI")
+  (V1DI "V1BI")
+  (V2DI "V2BI")
+  (V4DI "V4BI")
+  (V8DI "V8BI")
+  (V16DI "V16BI")
+  (V32DI "V32BI")
+  (V64DI "V64BI")
+  (V128DI "V128BI")
+  (V256DI "V256BI")
+  (V512DI "V512BI")
 ])
 
 (define_mode_attr gs_extension [
@@ -2589,18 +2848,18 @@
   (V512DI "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN >= 4096")])
 
 (define_mode_iterator VLSF [
-  (V1HF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_16")
-  (V2HF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_16")
-  (V4HF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_16")
-  (V8HF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_16")
-  (V16HF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_16")
-  (V32HF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN >= 64")
-  (V64HF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN >= 128")
-  (V128HF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN >= 256")
-  (V256HF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN >= 512")
-  (V512HF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN >= 1024")
-  (V1024HF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN >= 2048")
-  (V2048HF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN >= 4096")
+  (V1HF "TARGET_VECTOR_VLS && TARGET_ZVFH")
+  (V2HF "TARGET_VECTOR_VLS && TARGET_ZVFH")
+  (V4HF "TARGET_VECTOR_VLS && TARGET_ZVFH")
+  (V8HF "TARGET_VECTOR_VLS && TARGET_ZVFH")
+  (V16HF "TARGET_VECTOR_VLS && TARGET_ZVFH")
+  (V32HF "TARGET_VECTOR_VLS && TARGET_ZVFH && TARGET_MIN_VLEN >= 64")
+  (V64HF "TARGET_VECTOR_VLS && TARGET_ZVFH && TARGET_MIN_VLEN >= 128")
+  (V128HF "TARGET_VECTOR_VLS && TARGET_ZVFH && TARGET_MIN_VLEN >= 256")
+  (V256HF "TARGET_VECTOR_VLS && TARGET_ZVFH && TARGET_MIN_VLEN >= 512")
+  (V512HF "TARGET_VECTOR_VLS && TARGET_ZVFH && TARGET_MIN_VLEN >= 1024")
+  (V1024HF "TARGET_VECTOR_VLS && TARGET_ZVFH && TARGET_MIN_VLEN >= 2048")
+  (V2048HF "TARGET_VECTOR_VLS && TARGET_ZVFH && TARGET_MIN_VLEN >= 4096")
   (V1SF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_32")
   (V2SF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_32")
   (V4SF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_32")

diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md
index 7c086d40f7d03f90ed2754d9eba35aa8a5343a87..58e659e5cd4c0d8e707d680b0f87c3c0386b4e7f 100644 (file)
--- a/gcc/config/riscv/vector.md
+++ b/gcc/config/riscv/vector.md
@@ -1588,19 +1588,19 @@
    (set_attr "vl_op_idx" "3")])
 
 (define_insn "@pred_merge<mode>"
-  [(set (match_operand:V 0 "register_operand"        "=vd,vd,vd,vd")
-    (if_then_else:V
+  [(set (match_operand:V_VLS 0 "register_operand"        "=vd,vd,vd,vd")
+    (if_then_else:V_VLS
       (unspec:<VM>
         [(match_operand 5 "vector_length_operand"    " rK,rK,rK,rK")
          (match_operand 6 "const_int_operand"        "  i, i, i, i")
          (match_operand 7 "const_int_operand"        "  i, i, i, i")
          (reg:SI VL_REGNUM)
          (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
-      (vec_merge:V
-        (match_operand:V 3 "vector_arith_operand"    " vr,vr,vi,vi")
-        (match_operand:V 2 "register_operand"        " vr,vr,vr,vr")
+      (vec_merge:V_VLS
+        (match_operand:V_VLS 3 "vector_arith_operand"    " vr,vr,vi,vi")
+        (match_operand:V_VLS 2 "register_operand"        " vr,vr,vr,vr")
        (match_operand:<VM> 4 "register_operand"     " vm,vm,vm,vm"))
-      (match_operand:V 1 "vector_merge_operand"      " vu, 0,vu, 0")))]
+      (match_operand:V_VLS 1 "vector_merge_operand"      " vu, 0,vu, 0")))]
   "TARGET_VECTOR"
   "vmerge.v%o3m\t%0,%2,%v3,%4"
   [(set_attr "type" "vimerge")
@@ -4204,8 +4204,8 @@
             (reg:SI VL_REGNUM)
             (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
          (match_operator:<VM> 3 "comparison_except_ltge_operator"
-            [(match_operand:VI 4 "register_operand")
-             (match_operand:VI 5 "vector_arith_operand")])
+            [(match_operand:V_VLSI 4 "register_operand")
+             (match_operand:V_VLSI 5 "vector_arith_operand")])
          (match_operand:<VM> 2 "vector_merge_operand")))]
   "TARGET_VECTOR"
   {})
@@ -4221,8 +4221,8 @@
             (reg:SI VL_REGNUM)
             (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
          (match_operator:<VM> 2 "comparison_except_ltge_operator"
-            [(match_operand:VI 3 "register_operand"         "  vr")
-             (match_operand:VI 4 "vector_arith_operand"     "vrvi")])
+            [(match_operand:V_VLSI 3 "register_operand"         "  vr")
+             (match_operand:V_VLSI 4 "vector_arith_operand"     "vrvi")])
          (match_dup 1)))]
   "TARGET_VECTOR"
   "vms%B2.v%o4\t%0,%3,%v4,v0.t"
@@ -4245,10 +4245,10 @@
             (reg:SI VL_REGNUM)
             (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
          (match_operator:<VM> 3 "comparison_except_ltge_operator"
-            [(match_operand:VI 4 "register_operand"          "   vr,   vr,   vr,   vr")
-             (match_operand:VI 5 "vector_arith_operand"      "   vr,   vr,   vi,   vi")])
+            [(match_operand:V_VLSI 4 "register_operand"          "   vr,   vr,   vr,   vr")
+             (match_operand:V_VLSI 5 "vector_arith_operand"      "   vr,   vr,   vi,   vi")])
          (match_operand:<VM> 2 "vector_merge_operand"        "   vu,    0,   vu,    0")))]
-  "TARGET_VECTOR && known_le (GET_MODE_SIZE (<MODE>mode), BYTES_PER_RISCV_VECTOR)"
+  "TARGET_VECTOR && riscv_vector::cmp_lmul_le_one (<MODE>mode)"
   "vms%B3.v%o5\t%0,%4,%v5%p1"
   [(set_attr "type" "vicmp")
    (set_attr "mode" "<MODE>")])
@@ -4265,10 +4265,10 @@
             (reg:SI VL_REGNUM)
             (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
          (match_operator:<VM> 3 "comparison_except_ltge_operator"
-            [(match_operand:VI 4 "register_operand"          "   vr,    0,   vr,    0,    0,   vr,    0,   vr,   vr")
-             (match_operand:VI 5 "vector_arith_operand"      " vrvi, vrvi,    0,    0, vrvi,    0,    0, vrvi, vrvi")])
+            [(match_operand:V_VLSI 4 "register_operand"          "   vr,    0,   vr,    0,    0,   vr,    0,   vr,   vr")
+             (match_operand:V_VLSI 5 "vector_arith_operand"      " vrvi, vrvi,    0,    0, vrvi,    0,    0, vrvi, vrvi")])
          (match_operand:<VM> 2 "vector_merge_operand"        "   vu,   vu,   vu,   vu,    0,    0,    0,   vu,    0")))]
-  "TARGET_VECTOR && known_gt (GET_MODE_SIZE (<MODE>mode), BYTES_PER_RISCV_VECTOR)"
+  "TARGET_VECTOR && riscv_vector::cmp_lmul_gt_one (<MODE>mode)"
   "vms%B3.v%o5\t%0,%4,%v5%p1"
   [(set_attr "type" "vicmp")
    (set_attr "mode" "<MODE>")])
@@ -4284,8 +4284,8 @@
             (reg:SI VL_REGNUM)
             (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
          (match_operator:<VM> 3 "ltge_operator"
-            [(match_operand:VI 4 "register_operand")
-             (match_operand:VI 5 "vector_neg_arith_operand")])
+            [(match_operand:V_VLSI 4 "register_operand")
+             (match_operand:V_VLSI 5 "vector_neg_arith_operand")])
          (match_operand:<VM> 2 "vector_merge_operand")))]
   "TARGET_VECTOR"
   {})
@@ -4301,8 +4301,8 @@
             (reg:SI VL_REGNUM)
             (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
          (match_operator:<VM> 2 "ltge_operator"
-            [(match_operand:VI 3 "register_operand"         "  vr")
-             (match_operand:VI 4 "vector_neg_arith_operand" "vrvj")])
+            [(match_operand:V_VLSI 3 "register_operand"         "  vr")
+             (match_operand:V_VLSI 4 "vector_neg_arith_operand" "vrvj")])
          (match_dup 1)))]
   "TARGET_VECTOR"
   "vms%B2.v%o4\t%0,%3,%v4,v0.t"
@@ -4325,10 +4325,10 @@
             (reg:SI VL_REGNUM)
             (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
          (match_operator:<VM> 3 "ltge_operator"
-            [(match_operand:VI 4 "register_operand"          "   vr,   vr,   vr,   vr")
-             (match_operand:VI 5 "vector_neg_arith_operand"  "   vr,   vr,   vj,   vj")])
+            [(match_operand:V_VLSI 4 "register_operand"          "   vr,   vr,   vr,   vr")
+             (match_operand:V_VLSI 5 "vector_neg_arith_operand"  "   vr,   vr,   vj,   vj")])
          (match_operand:<VM> 2 "vector_merge_operand"        "   vu,    0,   vu,    0")))]
-  "TARGET_VECTOR && known_le (GET_MODE_SIZE (<MODE>mode), BYTES_PER_RISCV_VECTOR)"
+  "TARGET_VECTOR && riscv_vector::cmp_lmul_le_one (<MODE>mode)"
   "vms%B3.v%o5\t%0,%4,%v5%p1"
   [(set_attr "type" "vicmp")
    (set_attr "mode" "<MODE>")])
@@ -4345,10 +4345,10 @@
             (reg:SI VL_REGNUM)
             (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
          (match_operator:<VM> 3 "ltge_operator"
-            [(match_operand:VI 4 "register_operand"          "   vr,    0,   vr,    0,    0,   vr,    0,   vr,   vr")
-             (match_operand:VI 5 "vector_neg_arith_operand"  " vrvj, vrvj,    0,    0, vrvj,    0,    0, vrvj, vrvj")])
+            [(match_operand:V_VLSI 4 "register_operand"          "   vr,    0,   vr,    0,    0,   vr,    0,   vr,   vr")
+             (match_operand:V_VLSI 5 "vector_neg_arith_operand"  " vrvj, vrvj,    0,    0, vrvj,    0,    0, vrvj, vrvj")])
          (match_operand:<VM> 2 "vector_merge_operand"        "   vu,   vu,   vu,   vu,    0,    0,    0,   vu,    0")))]
-  "TARGET_VECTOR && known_gt (GET_MODE_SIZE (<MODE>mode), BYTES_PER_RISCV_VECTOR)"
+  "TARGET_VECTOR && riscv_vector::cmp_lmul_gt_one (<MODE>mode)"
   "vms%B3.v%o5\t%0,%4,%v5%p1"
   [(set_attr "type" "vicmp")
    (set_attr "mode" "<MODE>")])
@@ -4364,8 +4364,8 @@
             (reg:SI VL_REGNUM)
             (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
          (match_operator:<VM> 3 "comparison_except_eqge_operator"
-            [(match_operand:VI_QHS 4 "register_operand")
-             (vec_duplicate:VI_QHS
+            [(match_operand:V_VLSI_QHS 4 "register_operand")
+             (vec_duplicate:V_VLSI_QHS
                (match_operand:<VEL> 5 "register_operand"))])
          (match_operand:<VM> 2 "vector_merge_operand")))]
   "TARGET_VECTOR"
@@ -4382,8 +4382,8 @@
             (reg:SI VL_REGNUM)
             (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
          (match_operator:<VM> 2 "comparison_except_eqge_operator"
-            [(match_operand:VI_QHS 3 "register_operand"       " vr")
-             (vec_duplicate:VI_QHS
+            [(match_operand:V_VLSI_QHS 3 "register_operand"       " vr")
+             (vec_duplicate:V_VLSI_QHS
                (match_operand:<VEL> 4 "register_operand"      "  r"))])
          (match_dup 1)))]
   "TARGET_VECTOR"
@@ -4407,11 +4407,11 @@
             (reg:SI VL_REGNUM)
             (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
          (match_operator:<VM> 3 "comparison_except_eqge_operator"
-            [(match_operand:VI_QHS 4 "register_operand"      "   vr,   vr")
-             (vec_duplicate:VI_QHS
+            [(match_operand:V_VLSI_QHS 4 "register_operand"      "   vr,   vr")
+             (vec_duplicate:V_VLSI_QHS
                (match_operand:<VEL> 5 "register_operand"     "    r,    r"))])
          (match_operand:<VM> 2 "vector_merge_operand"        "   vu,    0")))]
-  "TARGET_VECTOR && known_le (GET_MODE_SIZE (<MODE>mode), BYTES_PER_RISCV_VECTOR)"
+  "TARGET_VECTOR && riscv_vector::cmp_lmul_le_one (<MODE>mode)"
   "vms%B3.vx\t%0,%4,%5%p1"
   [(set_attr "type" "vicmp")
    (set_attr "mode" "<MODE>")])
@@ -4428,11 +4428,11 @@
             (reg:SI VL_REGNUM)
             (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
          (match_operator:<VM> 3 "comparison_except_eqge_operator"
-            [(match_operand:VI_QHS 4 "register_operand"   "   vr,    0,    0,   vr,   vr")
-             (vec_duplicate:VI_QHS
+            [(match_operand:V_VLSI_QHS 4 "register_operand"   "   vr,    0,    0,   vr,   vr")
+             (vec_duplicate:V_VLSI_QHS
                (match_operand:<VEL> 5 "register_operand"  "    r,    r,    r,    r,    r"))])
          (match_operand:<VM> 2 "vector_merge_operand"     "   vu,   vu,    0,   vu,    0")))]
-  "TARGET_VECTOR && known_gt (GET_MODE_SIZE (<MODE>mode), BYTES_PER_RISCV_VECTOR)"
+  "TARGET_VECTOR && riscv_vector::cmp_lmul_gt_one (<MODE>mode)"
   "vms%B3.vx\t%0,%4,%5%p1"
   [(set_attr "type" "vicmp")
    (set_attr "mode" "<MODE>")])
@@ -4448,9 +4448,9 @@
             (reg:SI VL_REGNUM)
             (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
          (match_operator:<VM> 3 "equality_operator"
-            [(vec_duplicate:VI_QHS
+            [(vec_duplicate:V_VLSI_QHS
                (match_operand:<VEL> 5 "register_operand"))
-             (match_operand:VI_QHS 4 "register_operand")])
+             (match_operand:V_VLSI_QHS 4 "register_operand")])
          (match_operand:<VM> 2 "vector_merge_operand")))]
   "TARGET_VECTOR"
   {})
@@ -4466,9 +4466,9 @@
             (reg:SI VL_REGNUM)
             (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
          (match_operator:<VM> 2 "equality_operator"
-            [(vec_duplicate:VI_QHS
+            [(vec_duplicate:V_VLSI_QHS
                (match_operand:<VEL> 4 "register_operand"       "  r"))
-             (match_operand:VI_QHS 3 "register_operand"        " vr")])
+             (match_operand:V_VLSI_QHS 3 "register_operand"        " vr")])
          (match_dup 1)))]
   "TARGET_VECTOR"
   "vms%B2.vx\t%0,%3,%4,v0.t"
@@ -4491,11 +4491,11 @@
             (reg:SI VL_REGNUM)
             (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
          (match_operator:<VM> 3 "equality_operator"
-            [(vec_duplicate:VI_QHS
+            [(vec_duplicate:V_VLSI_QHS
                (match_operand:<VEL> 5 "register_operand"     "    r,    r"))
-             (match_operand:VI_QHS 4 "register_operand"      "   vr,   vr")])
+             (match_operand:V_VLSI_QHS 4 "register_operand"      "   vr,   vr")])
          (match_operand:<VM> 2 "vector_merge_operand"        "   vu,    0")))]
-  "TARGET_VECTOR && known_le (GET_MODE_SIZE (<MODE>mode), BYTES_PER_RISCV_VECTOR)"
+  "TARGET_VECTOR && riscv_vector::cmp_lmul_le_one (<MODE>mode)"
   "vms%B3.vx\t%0,%4,%5%p1"
   [(set_attr "type" "vicmp")
    (set_attr "mode" "<MODE>")])
@@ -4512,11 +4512,11 @@
             (reg:SI VL_REGNUM)
             (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
          (match_operator:<VM> 3 "equality_operator"
-            [(vec_duplicate:VI_QHS
+            [(vec_duplicate:V_VLSI_QHS
                (match_operand:<VEL> 5 "register_operand"     "    r,    r,    r,    r,    r"))
-             (match_operand:VI_QHS 4 "register_operand"      "   vr,    0,    0,   vr,   vr")])
+             (match_operand:V_VLSI_QHS 4 "register_operand"      "   vr,    0,    0,   vr,   vr")])
          (match_operand:<VM> 2 "vector_merge_operand"        "   vu,   vu,    0,   vu,    0")))]
-  "TARGET_VECTOR && known_gt (GET_MODE_SIZE (<MODE>mode), BYTES_PER_RISCV_VECTOR)"
+  "TARGET_VECTOR && riscv_vector::cmp_lmul_gt_one (<MODE>mode)"
   "vms%B3.vx\t%0,%4,%5%p1"
   [(set_attr "type" "vicmp")
    (set_attr "mode" "<MODE>")])
@@ -4534,8 +4534,8 @@
             (reg:SI VL_REGNUM)
             (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
          (match_operator:<VM> 3 "comparison_except_eqge_operator"
-            [(match_operand:VI_D 4 "register_operand")
-             (vec_duplicate:VI_D
+            [(match_operand:V_VLSI_D 4 "register_operand")
+             (vec_duplicate:V_VLSI_D
                (match_operand:<VEL> 5 "reg_or_int_operand"))])
          (match_operand:<VM> 2 "vector_merge_operand")))]
   "TARGET_VECTOR"
@@ -4573,9 +4573,9 @@
             (reg:SI VL_REGNUM)
             (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
          (match_operator:<VM> 3 "equality_operator"
-            [(vec_duplicate:VI_D
+            [(vec_duplicate:V_VLSI_D
                (match_operand:<VEL> 5 "reg_or_int_operand"))
-             (match_operand:VI_D 4 "register_operand")])
+             (match_operand:V_VLSI_D 4 "register_operand")])
          (match_operand:<VM> 2 "vector_merge_operand")))]
   "TARGET_VECTOR"
 {
@@ -4605,8 +4605,8 @@
             (reg:SI VL_REGNUM)
             (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
          (match_operator:<VM> 2 "comparison_except_eqge_operator"
-            [(match_operand:VI_D 3 "register_operand"          " vr")
-             (vec_duplicate:VI_D
+            [(match_operand:V_VLSI_D 3 "register_operand"          " vr")
+             (vec_duplicate:V_VLSI_D
                (match_operand:<VEL> 4 "register_operand"       "  r"))])
          (match_dup 1)))]
   "TARGET_VECTOR"
@@ -4629,9 +4629,9 @@
             (reg:SI VL_REGNUM)
             (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
          (match_operator:<VM> 2 "equality_operator"
-            [(vec_duplicate:VI_D
+            [(vec_duplicate:V_VLSI_D
                (match_operand:<VEL> 4 "register_operand"       "  r"))
-             (match_operand:VI_D 3 "register_operand"          " vr")])
+             (match_operand:V_VLSI_D 3 "register_operand"          " vr")])
          (match_dup 1)))]
   "TARGET_VECTOR"
   "vms%B2.vx\t%0,%3,%4,v0.t"
@@ -4654,11 +4654,11 @@
             (reg:SI VL_REGNUM)
             (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
          (match_operator:<VM> 3 "comparison_except_eqge_operator"
-            [(match_operand:VI_D 4 "register_operand"        "   vr,   vr")
-             (vec_duplicate:VI_D
+            [(match_operand:V_VLSI_D 4 "register_operand"        "   vr,   vr")
+             (vec_duplicate:V_VLSI_D
                (match_operand:<VEL> 5 "register_operand"     "    r,    r"))])
          (match_operand:<VM> 2 "vector_merge_operand"        "   vu,    0")))]
-  "TARGET_VECTOR && known_le (GET_MODE_SIZE (<MODE>mode), BYTES_PER_RISCV_VECTOR)"
+  "TARGET_VECTOR && riscv_vector::cmp_lmul_le_one (<MODE>mode)"
   "vms%B3.vx\t%0,%4,%5%p1"
   [(set_attr "type" "vicmp")
    (set_attr "mode" "<MODE>")])
@@ -4675,11 +4675,11 @@
             (reg:SI VL_REGNUM)
             (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
          (match_operator:<VM> 3 "comparison_except_eqge_operator"
-            [(match_operand:VI_D 4 "register_operand"     "   vr,    0,    0,   vr,   vr")
-             (vec_duplicate:VI_D
+            [(match_operand:V_VLSI_D 4 "register_operand"     "   vr,    0,    0,   vr,   vr")
+             (vec_duplicate:V_VLSI_D
                (match_operand:<VEL> 5 "register_operand"  "    r,    r,    r,    r,    r"))])
          (match_operand:<VM> 2 "vector_merge_operand"     "   vu,   vu,    0,   vu,    0")))]
-  "TARGET_VECTOR && known_gt (GET_MODE_SIZE (<MODE>mode), BYTES_PER_RISCV_VECTOR)"
+  "TARGET_VECTOR && riscv_vector::cmp_lmul_gt_one (<MODE>mode)"
   "vms%B3.vx\t%0,%4,%5%p1"
   [(set_attr "type" "vicmp")
    (set_attr "mode" "<MODE>")])
@@ -4696,11 +4696,11 @@
             (reg:SI VL_REGNUM)
             (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
          (match_operator:<VM> 3 "equality_operator"
-            [(vec_duplicate:VI_D
+            [(vec_duplicate:V_VLSI_D
                (match_operand:<VEL> 5 "register_operand"     "    r,    r"))
-             (match_operand:VI_D 4 "register_operand"        "   vr,   vr")])
+             (match_operand:V_VLSI_D 4 "register_operand"        "   vr,   vr")])
          (match_operand:<VM> 2 "vector_merge_operand"        "   vu,    0")))]
-  "TARGET_VECTOR && known_le (GET_MODE_SIZE (<MODE>mode), BYTES_PER_RISCV_VECTOR)"
+  "TARGET_VECTOR && riscv_vector::cmp_lmul_le_one (<MODE>mode)"
   "vms%B3.vx\t%0,%4,%5%p1"
   [(set_attr "type" "vicmp")
    (set_attr "mode" "<MODE>")])
@@ -4717,11 +4717,11 @@
             (reg:SI VL_REGNUM)
             (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
          (match_operator:<VM> 3 "equality_operator"
-            [(vec_duplicate:VI_D
+            [(vec_duplicate:V_VLSI_D
                (match_operand:<VEL> 5 "register_operand"     "    r,    r,    r,    r,    r"))
-             (match_operand:VI_D 4 "register_operand"        "   vr,    0,    0,   vr,   vr")])
+             (match_operand:V_VLSI_D 4 "register_operand"        "   vr,    0,    0,   vr,   vr")])
          (match_operand:<VM> 2 "vector_merge_operand"        "   vu,   vu,    0,   vu,    0")))]
-  "TARGET_VECTOR && known_gt (GET_MODE_SIZE (<MODE>mode), BYTES_PER_RISCV_VECTOR)"
+  "TARGET_VECTOR && riscv_vector::cmp_lmul_gt_one (<MODE>mode)"
   "vms%B3.vx\t%0,%4,%5%p1"
   [(set_attr "type" "vicmp")
    (set_attr "mode" "<MODE>")])
@@ -4737,8 +4737,8 @@
             (reg:SI VL_REGNUM)
             (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
          (match_operator:<VM> 2 "comparison_except_eqge_operator"
-            [(match_operand:VI_D 3 "register_operand"         " vr")
-             (vec_duplicate:VI_D
+            [(match_operand:V_VLSI_D 3 "register_operand"         " vr")
+             (vec_duplicate:V_VLSI_D
                (sign_extend:<VEL>
                  (match_operand:<VSUBEL> 4 "register_operand" "  r")))])
          (match_dup 1)))]
@@ -4763,12 +4763,12 @@
             (reg:SI VL_REGNUM)
             (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
          (match_operator:<VM> 3 "comparison_except_eqge_operator"
-            [(match_operand:VI_D 4 "register_operand"         "   vr,   vr")
-             (vec_duplicate:VI_D
+            [(match_operand:V_VLSI_D 4 "register_operand"         "   vr,   vr")
+             (vec_duplicate:V_VLSI_D
                (sign_extend:<VEL>
                  (match_operand:<VSUBEL> 5 "register_operand" "    r,    r")))])
          (match_operand:<VM> 2 "vector_merge_operand"         "   vu,    0")))]
-  "TARGET_VECTOR && known_le (GET_MODE_SIZE (<MODE>mode), BYTES_PER_RISCV_VECTOR)"
+  "TARGET_VECTOR && riscv_vector::cmp_lmul_le_one (<MODE>mode)"
   "vms%B3.vx\t%0,%4,%5%p1"
   [(set_attr "type" "vicmp")
    (set_attr "mode" "<MODE>")])
@@ -4784,12 +4784,12 @@
             (reg:SI VL_REGNUM)
             (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
          (match_operator:<VM> 3 "comparison_except_eqge_operator"
-            [(match_operand:VI_D 4 "register_operand"         "   vr,    0,    0,   vr,   vr")
-             (vec_duplicate:VI_D
+            [(match_operand:V_VLSI_D 4 "register_operand"         "   vr,    0,    0,   vr,   vr")
+             (vec_duplicate:V_VLSI_D
                (sign_extend:<VEL>
                  (match_operand:<VSUBEL> 5 "register_operand" "    r,    r,    r,    r,    r")))])
          (match_operand:<VM> 2 "vector_merge_operand"         "   vu,   vu,    0,   vu,    0")))]
-  "TARGET_VECTOR && known_gt (GET_MODE_SIZE (<MODE>mode), BYTES_PER_RISCV_VECTOR)"
+  "TARGET_VECTOR && riscv_vector::cmp_lmul_gt_one (<MODE>mode)"
   "vms%B3.vx\t%0,%4,%5%p1"
   [(set_attr "type" "vicmp")
    (set_attr "mode" "<MODE>")])
@@ -4805,10 +4805,10 @@
             (reg:SI VL_REGNUM)
             (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
          (match_operator:<VM> 2 "equality_operator"
-            [(vec_duplicate:VI_D
+            [(vec_duplicate:V_VLSI_D
                (sign_extend:<VEL>
                  (match_operand:<VSUBEL> 4 "register_operand"   "  r")))
-             (match_operand:VI_D 3 "register_operand"           " vr")])
+             (match_operand:V_VLSI_D 3 "register_operand"           " vr")])
          (match_dup 1)))]
   "TARGET_VECTOR"
   "vms%B2.vx\t%0,%3,%4,v0.t"
@@ -4831,12 +4831,12 @@
             (reg:SI VL_REGNUM)
             (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
          (match_operator:<VM> 3 "equality_operator"
-            [(vec_duplicate:VI_D
+            [(vec_duplicate:V_VLSI_D
                (sign_extend:<VEL>
                  (match_operand:<VSUBEL> 5 "register_operand" "    r,    r")))
-             (match_operand:VI_D 4 "register_operand"         "   vr,   vr")])
+             (match_operand:V_VLSI_D 4 "register_operand"         "   vr,   vr")])
          (match_operand:<VM> 2 "vector_merge_operand"         "   vu,    0")))]
-  "TARGET_VECTOR && known_le (GET_MODE_SIZE (<MODE>mode), BYTES_PER_RISCV_VECTOR)"
+  "TARGET_VECTOR && riscv_vector::cmp_lmul_le_one (<MODE>mode)"
   "vms%B3.vx\t%0,%4,%5%p1"
   [(set_attr "type" "vicmp")
    (set_attr "mode" "<MODE>")])
@@ -4852,12 +4852,12 @@
             (reg:SI VL_REGNUM)
             (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
          (match_operator:<VM> 3 "equality_operator"
-            [(vec_duplicate:VI_D
+            [(vec_duplicate:V_VLSI_D
                (sign_extend:<VEL>
                  (match_operand:<VSUBEL> 5 "register_operand" "    r,    r,    r,    r,    r")))
-             (match_operand:VI_D 4 "register_operand"         "   vr,    0,    0,   vr,   vr")])
+             (match_operand:V_VLSI_D 4 "register_operand"         "   vr,    0,    0,   vr,   vr")])
          (match_operand:<VM> 2 "vector_merge_operand"         "   vu,   vu,    0,   vu,    0")))]
-  "TARGET_VECTOR && known_gt (GET_MODE_SIZE (<MODE>mode), BYTES_PER_RISCV_VECTOR)"
+  "TARGET_VECTOR && riscv_vector::cmp_lmul_gt_one (<MODE>mode)"
   "vms%B3.vx\t%0,%4,%5%p1"
   [(set_attr "type" "vicmp")
    (set_attr "mode" "<MODE>")])
@@ -4886,8 +4886,8 @@
             (reg:SI VL_REGNUM)
             (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
          (match_operator:<VM> 3 "ge_operator"
-            [(match_operand:VI 4 "register_operand")
-             (vec_duplicate:VI
+            [(match_operand:V_VLSI 4 "register_operand")
+             (vec_duplicate:V_VLSI
                (match_operand:<VEL> 5 "reg_or_int_operand"))])
          (match_operand:<VM> 2 "vector_merge_operand")))]
   "TARGET_VECTOR"
@@ -5848,18 +5848,18 @@
 ;; For example, if we have vmxor.mm v1,v1,v1. It will be optmized as vmclr.m which
 ;; is generated by pred_mov.
 (define_insn "@pred_<optab><mode>"
-  [(set (match_operand:VB 0 "register_operand"                   "=vr")
-       (if_then_else:VB
-         (unspec:VB
-           [(match_operand:VB 1 "vector_all_trues_mask_operand" "Wc1")
+  [(set (match_operand:VB_VLS 0 "register_operand"                   "=vr")
+       (if_then_else:VB_VLS
+         (unspec:VB_VLS
+           [(match_operand:VB_VLS 1 "vector_all_trues_mask_operand" "Wc1")
             (match_operand 5 "vector_length_operand"            " rK")
             (match_operand 6 "const_int_operand"                "  i")
             (reg:SI VL_REGNUM)
             (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
-         (any_bitwise:VB
-           (match_operand:VB 3 "register_operand"               " vr")
-           (match_operand:VB 4 "register_operand"               " vr"))
-         (match_operand:VB 2 "vector_undef_operand"             " vu")))]
+         (any_bitwise:VB_VLS
+           (match_operand:VB_VLS 3 "register_operand"               " vr")
+           (match_operand:VB_VLS 4 "register_operand"               " vr"))
+         (match_operand:VB_VLS 2 "vector_undef_operand"             " vu")))]
   "TARGET_VECTOR"
   "vm<insn>.mm\t%0,%3,%4"
   [(set_attr "type" "vmalu")
@@ -5868,19 +5868,19 @@
    (set (attr "avl_type") (symbol_ref "INTVAL (operands[6])"))])
 
 (define_insn "@pred_n<optab><mode>"
-  [(set (match_operand:VB 0 "register_operand"                   "=vr")
-       (if_then_else:VB
-         (unspec:VB
-           [(match_operand:VB 1 "vector_all_trues_mask_operand" "Wc1")
+  [(set (match_operand:VB_VLS 0 "register_operand"                   "=vr")
+       (if_then_else:VB_VLS
+         (unspec:VB_VLS
+           [(match_operand:VB_VLS 1 "vector_all_trues_mask_operand" "Wc1")
             (match_operand 5 "vector_length_operand"            " rK")
             (match_operand 6 "const_int_operand"                "  i")
             (reg:SI VL_REGNUM)
             (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
-         (not:VB
-           (any_bitwise:VB
-             (match_operand:VB 3 "register_operand"             " vr")
-             (match_operand:VB 4 "register_operand"             " vr")))
-         (match_operand:VB 2 "vector_undef_operand"             " vu")))]
+         (not:VB_VLS
+           (any_bitwise:VB_VLS
+             (match_operand:VB_VLS 3 "register_operand"             " vr")
+             (match_operand:VB_VLS 4 "register_operand"             " vr")))
+         (match_operand:VB_VLS 2 "vector_undef_operand"             " vu")))]
   "TARGET_VECTOR"
   "vm<ninsn>.mm\t%0,%3,%4"
   [(set_attr "type" "vmalu")
@@ -5889,19 +5889,19 @@
    (set (attr "avl_type") (symbol_ref "INTVAL (operands[6])"))])
 
 (define_insn "@pred_<optab>not<mode>"
-  [(set (match_operand:VB 0 "register_operand"                   "=vr")
-       (if_then_else:VB
-         (unspec:VB
-           [(match_operand:VB 1 "vector_all_trues_mask_operand" "Wc1")
+  [(set (match_operand:VB_VLS 0 "register_operand"                   "=vr")
+       (if_then_else:VB_VLS
+         (unspec:VB_VLS
+           [(match_operand:VB_VLS 1 "vector_all_trues_mask_operand" "Wc1")
             (match_operand 5 "vector_length_operand"            " rK")
             (match_operand 6 "const_int_operand"                "  i")
             (reg:SI VL_REGNUM)
             (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
-         (and_ior:VB
-           (match_operand:VB 3 "register_operand"               " vr")
-           (not:VB
-             (match_operand:VB 4 "register_operand"             " vr")))
-         (match_operand:VB 2 "vector_undef_operand"             " vu")))]
+         (and_ior:VB_VLS
+           (match_operand:VB_VLS 3 "register_operand"               " vr")
+           (not:VB_VLS
+             (match_operand:VB_VLS 4 "register_operand"             " vr")))
+         (match_operand:VB_VLS 2 "vector_undef_operand"             " vu")))]
   "TARGET_VECTOR"
   "vm<insn>n.mm\t%0,%3,%4"
   [(set_attr "type" "vmalu")
@@ -5910,17 +5910,17 @@
    (set (attr "avl_type") (symbol_ref "INTVAL (operands[6])"))])
 
 (define_insn "@pred_not<mode>"
-  [(set (match_operand:VB 0 "register_operand"                   "=vr")
-       (if_then_else:VB
-         (unspec:VB
-           [(match_operand:VB 1 "vector_all_trues_mask_operand" "Wc1")
+  [(set (match_operand:VB_VLS 0 "register_operand"                   "=vr")
+       (if_then_else:VB_VLS
+         (unspec:VB_VLS
+           [(match_operand:VB_VLS 1 "vector_all_trues_mask_operand" "Wc1")
             (match_operand 4 "vector_length_operand"            " rK")
             (match_operand 5 "const_int_operand"                "  i")
             (reg:SI VL_REGNUM)
             (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
-         (not:VB
-           (match_operand:VB 3 "register_operand"               " vr"))
-         (match_operand:VB 2 "vector_undef_operand"             " vu")))]
+         (not:VB_VLS
+           (match_operand:VB_VLS 3 "register_operand"               " vr"))
+         (match_operand:VB_VLS 2 "vector_undef_operand"             " vu")))]
   "TARGET_VECTOR"
   "vmnot.m\t%0,%3"
   [(set_attr "type" "vmalu")
@@ -8186,8 +8186,8 @@
 
 ;; vslide instructions
 (define_insn "@pred_slide<ud><mode>"
-  [(set (match_operand:V 0 "register_operand"             "<ud_constraint>")
-       (unspec:V
+  [(set (match_operand:V_VLS 0 "register_operand"             "<ud_constraint>")
+       (unspec:V_VLS
          [(unspec:<VM>
             [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1")
              (match_operand 5 "vector_length_operand"    " rK, rK, rK, rK")
@@ -8196,8 +8196,8 @@
              (match_operand 8 "const_int_operand"        "  i,  i,  i,  i")
              (reg:SI VL_REGNUM)
              (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
-          (match_operand:V 2 "vector_merge_operand"      " vu,  0, vu,  0")
-          (match_operand:V 3 "register_operand"          " vr, vr, vr, vr")
+          (match_operand:V_VLS 2 "vector_merge_operand"      " vu,  0, vu,  0")
+          (match_operand:V_VLS 3 "register_operand"          " vr, vr, vr, vr")
           (match_operand 4 "pmode_reg_or_uimm5_operand"  " rK, rK, rK, rK")] VSLIDES))]
   "TARGET_VECTOR"
   "vslide<ud>.v%o4\t%0,%3,%4%p1"
@@ -8206,8 +8206,8 @@
 
 ;; vslide1 instructions
 (define_insn "@pred_slide<ud><mode>"
-  [(set (match_operand:VI_QHS 0 "register_operand"        "<ud_constraint>")
-       (unspec:VI_QHS
+  [(set (match_operand:V_VLSI_QHS 0 "register_operand"        "<ud_constraint>")
+       (unspec:V_VLSI_QHS
          [(unspec:<VM>
             [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1")
              (match_operand 5 "vector_length_operand"    " rK, rK, rK, rK")
@@ -8216,8 +8216,8 @@
              (match_operand 8 "const_int_operand"        "  i,  i,  i,  i")
              (reg:SI VL_REGNUM)
              (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
-          (match_operand:VI_QHS 2 "vector_merge_operand" " vu,  0, vu,  0")
-          (match_operand:VI_QHS 3 "register_operand"     " vr, vr, vr, vr")
+          (match_operand:V_VLSI_QHS 2 "vector_merge_operand" " vu,  0, vu,  0")
+          (match_operand:V_VLSI_QHS 3 "register_operand"     " vr, vr, vr, vr")
           (match_operand:<VEL> 4 "reg_or_0_operand"      " rJ, rJ, rJ, rJ")] VSLIDES1))]
   "TARGET_VECTOR"
   "vslide<ud>.vx\t%0,%3,%z4%p1"
@@ -8225,8 +8225,8 @@
    (set_attr "mode" "<MODE>")])
 
 (define_expand "@pred_slide<ud><mode>"
-  [(set (match_operand:VI_D 0 "register_operand")
-       (unspec:VI_D
+  [(set (match_operand:V_VLSI_D 0 "register_operand")
+       (unspec:V_VLSI_D
          [(unspec:<VM>
             [(match_operand:<VM> 1 "vector_mask_operand")
              (match_operand 5 "reg_or_int_operand")
@@ -8235,8 +8235,8 @@
              (match_operand 8 "const_int_operand")
              (reg:SI VL_REGNUM)
              (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
-          (match_operand:VI_D 2 "vector_merge_operand")
-          (match_operand:VI_D 3 "register_operand")
+          (match_operand:V_VLSI_D 2 "vector_merge_operand")
+          (match_operand:V_VLSI_D 3 "register_operand")
           (match_operand:<VEL> 4 "reg_or_int_operand")] VSLIDES1))]
   "TARGET_VECTOR"
 {
@@ -8247,8 +8247,8 @@
 })
 
 (define_insn "*pred_slide<ud><mode>"
-  [(set (match_operand:VI_D 0 "register_operand"          "<ud_constraint>")
-       (unspec:VI_D
+  [(set (match_operand:V_VLSI_D 0 "register_operand"          "<ud_constraint>")
+       (unspec:V_VLSI_D
          [(unspec:<VM>
             [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1")
              (match_operand 5 "vector_length_operand"    " rK, rK, rK, rK")
@@ -8257,8 +8257,8 @@
              (match_operand 8 "const_int_operand"        "  i,  i,  i,  i")
              (reg:SI VL_REGNUM)
              (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
-          (match_operand:VI_D 2 "vector_merge_operand"   " vu,  0, vu,  0")
-          (match_operand:VI_D 3 "register_operand"       " vr, vr, vr, vr")
+          (match_operand:V_VLSI_D 2 "vector_merge_operand"   " vu,  0, vu,  0")
+          (match_operand:V_VLSI_D 3 "register_operand"       " vr, vr, vr, vr")
           (match_operand:<VEL> 4 "reg_or_0_operand"      " rJ, rJ, rJ, rJ")] VSLIDES1))]
   "TARGET_VECTOR"
   "vslide<ud>.vx\t%0,%3,%z4%p1"
@@ -8266,8 +8266,8 @@
    (set_attr "mode" "<MODE>")])
 
 (define_insn "*pred_slide<ud><mode>_extended"
-  [(set (match_operand:VI_D 0 "register_operand"          "<ud_constraint>")
-       (unspec:VI_D
+  [(set (match_operand:V_VLSI_D 0 "register_operand"          "<ud_constraint>")
+       (unspec:V_VLSI_D
          [(unspec:<VM>
             [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1")
              (match_operand 5 "vector_length_operand"    " rK, rK, rK, rK")
@@ -8276,8 +8276,8 @@
              (match_operand 8 "const_int_operand"        "  i,  i,  i,  i")
              (reg:SI VL_REGNUM)
              (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
-          (match_operand:VI_D 2 "vector_merge_operand"   " vu,  0, vu,  0")
-          (match_operand:VI_D 3 "register_operand"       " vr, vr, vr, vr")
+          (match_operand:V_VLSI_D 2 "vector_merge_operand"   " vu,  0, vu,  0")
+          (match_operand:V_VLSI_D 3 "register_operand"       " vr, vr, vr, vr")
           (sign_extend:<VEL>
             (match_operand:<VSUBEL> 4 "reg_or_0_operand" " rJ, rJ, rJ, rJ"))] VSLIDES1))]
   "TARGET_VECTOR"
@@ -8307,8 +8307,8 @@
 
 ;; vrgather
 (define_insn "@pred_gather<mode>"
-  [(set (match_operand:V 0 "register_operand"              "=&vr,  &vr")
-       (if_then_else:V
+  [(set (match_operand:V_VLS 0 "register_operand"              "=&vr,  &vr")
+       (if_then_else:V_VLS
          (unspec:<VM>
            [(match_operand:<VM> 1 "vector_mask_operand"  "vmWc1,vmWc1")
             (match_operand 5 "vector_length_operand"     "   rK,   rK")
@@ -8317,18 +8317,18 @@
             (match_operand 8 "const_int_operand"         "    i,    i")
             (reg:SI VL_REGNUM)
             (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
-         (unspec:V
-           [(match_operand:V 3 "register_operand"        "   vr,   vr")
+         (unspec:V_VLS
+           [(match_operand:V_VLS 3 "register_operand"        "   vr,   vr")
             (match_operand:<VINDEX> 4 "register_operand" "   vr,   vr")] UNSPEC_VRGATHER)
-         (match_operand:V 2 "vector_merge_operand"       "   vu,    0")))]
+         (match_operand:V_VLS 2 "vector_merge_operand"       "   vu,    0")))]
   "TARGET_VECTOR"
   "vrgather.vv\t%0,%3,%4%p1"
   [(set_attr "type" "vgather")
    (set_attr "mode" "<MODE>")])
 
 (define_insn "@pred_gather<mode>_scalar"
-  [(set (match_operand:V 0 "register_operand"               "=&vr,  &vr")
-       (if_then_else:V
+  [(set (match_operand:V_VLS 0 "register_operand"               "=&vr,  &vr")
+       (if_then_else:V_VLS
          (unspec:<VM>
            [(match_operand:<VM> 1 "vector_mask_operand"   "vmWc1,vmWc1")
             (match_operand 5 "vector_length_operand"      "   rK,   rK")
@@ -8337,10 +8337,10 @@
             (match_operand 8 "const_int_operand"          "    i,    i")
             (reg:SI VL_REGNUM)
             (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
-         (unspec:V
-           [(match_operand:V 3 "register_operand"         "   vr,   vr")
+         (unspec:V_VLS
+           [(match_operand:V_VLS 3 "register_operand"         "   vr,   vr")
             (match_operand 4 "pmode_reg_or_uimm5_operand" "   rK,   rK")] UNSPEC_VRGATHER)
-         (match_operand:V 2 "vector_merge_operand"        "   vu,    0")))]
+         (match_operand:V_VLS 2 "vector_merge_operand"        "   vu,    0")))]
   "TARGET_VECTOR"
   "vrgather.v%o4\t%0,%3,%4%p1"
   [(set_attr "type" "vgather")
@@ -8369,8 +8369,8 @@
 
 ;; vcompress
 (define_insn "@pred_compress<mode>"
-  [(set (match_operand:V 0 "register_operand"            "=&vr,  &vr")
-       (unspec:V
+  [(set (match_operand:V_VLS 0 "register_operand"            "=&vr,  &vr")
+       (unspec:V_VLS
          [(unspec:<VM>
            [(match_operand:<VM> 3 "register_operand"    "  vm,  vm")
             (match_operand 4 "vector_length_operand"    "  rK,  rK")
@@ -8378,8 +8378,8 @@
             (match_operand 6 "const_int_operand"        "   i,   i")
             (reg:SI VL_REGNUM)
             (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
-          (match_operand:V 2 "register_operand"         "  vr,  vr")
-          (match_operand:V 1 "vector_merge_operand"     "  vu,   0")] UNSPEC_VCOMPRESS))]
+          (match_operand:V_VLS 2 "register_operand"         "  vr,  vr")
+          (match_operand:V_VLS 1 "vector_merge_operand"     "  vu,   0")] UNSPEC_VCOMPRESS))]
   "TARGET_VECTOR"
   "vcompress.vm\t%0,%2,%3"
   [(set_attr "type" "vcompress")

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-1.c
index 3571a325f73aa80c21cd1ca804f05409ba4e155b..34622ce9afff8b2d28510043565089b9f890db4d 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-1.c
@@ -21,6 +21,6 @@ f (int8_t *restrict a, int8_t *restrict b, int n)
 
 /* FIXME: Since we don't have VECT cost model yet, LOAD_LANES/STORE_LANES are chosen
    instead of SLP when riscv-autovec-lmul=m1 or m2.  */
-/* { dg-final { scan-tree-dump-times "\.VEC_PERM" 1 "optimized" { xfail { any-opts "--param riscv-autovec-lmul=m1" "--param riscv-autovec-lmul=m2" } } } } */
+/* { dg-final { scan-tree-dump-times "\.VEC_PERM" 1 "optimized" { xfail { any-opts "--param riscv-autovec-lmul=m1" "--param riscv-autovec-lmul=m2" "--param riscv-autovec-lmul=m8" } } } } */
 /* { dg-final { scan-assembler {\tvid\.v} { xfail { any-opts "--param riscv-autovec-lmul=m1" "--param riscv-autovec-lmul=m2" } } } } */
 /* { dg-final { scan-assembler {\tvand} { xfail { any-opts "--param riscv-autovec-lmul=m1" "--param riscv-autovec-lmul=m2" } } } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-16.c
index 8c5c65152c83cda99abd0e7b70d02e8063e6f2d3..80c77ef679a6f031c9c403dcf5bcc5fda962eefd 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-16.c
@@ -21,6 +21,6 @@ f (uint8_t *restrict a, uint8_t *restrict b, int n)
 
 /* FIXME: Since we don't have VECT cost model yet, LOAD_LANES/STORE_LANES are chosen
    instead of SLP when riscv-autovec-lmul=m1 or m2.  */
-/* { dg-final { scan-tree-dump-times "\.VEC_PERM" 1 "optimized" { xfail { any-opts "--param riscv-autovec-lmul=m1" "--param riscv-autovec-lmul=m2" } } } } */
+/* { dg-final { scan-tree-dump-times "\.VEC_PERM" 1 "optimized" { xfail { any-opts "--param riscv-autovec-lmul=m1" "--param riscv-autovec-lmul=m2" "--param riscv-autovec-lmul=m8" } } } } */
 /* { dg-final { scan-assembler {\tvid\.v} { xfail { any-opts "--param riscv-autovec-lmul=m1" "--param riscv-autovec-lmul=m2" } } } } */
 /* { dg-final { scan-assembler-not {\tvmul} } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-17.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-17.c
index 67dbadafc48cb84ee484f40809c849744cc5e102..50d06d501bad55352a8de123a48181e5f0b0c583 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-17.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-17.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d --param riscv-autovec-preference=scalable -fdump-tree-optimized-details" } */
+/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d --param riscv-autovec-preference=scalable -fno-vect-cost-model -fdump-tree-optimized-details" } */
 
 #include <stdint-gcc.h>
 

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-3.c
index fde54e1f059becbcad84b9e19a8e69fab94186b4..75298bd7525a61174167770b306e0357caeb4a9e 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-3.c
@@ -21,4 +21,4 @@ f (int8_t *restrict a, int8_t *restrict b, int n)
 
 /* FIXME: Since we don't have VECT cost model yet, LOAD_LANES/STORE_LANES are chosen
    instead of SLP when riscv-autovec-lmul=m1 or m2.  */
-/* { dg-final { scan-tree-dump-times "\.VEC_PERM" 1 "optimized" { xfail { any-opts "--param riscv-autovec-lmul=m1" "--param riscv-autovec-lmul=m2" } } } } */
+/* { dg-final { scan-tree-dump-times "\.VEC_PERM" 1 "optimized" { xfail { any-opts "--param riscv-autovec-lmul=m1" "--param riscv-autovec-lmul=m2" "--param riscv-autovec-lmul=m8" } } } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-5.c
index 600699be9d121b0c42311731988dd0a6f2beff49..c1b31a430f29cc9a29c80b04383d968463816411 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-5.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-5.c
@@ -21,4 +21,4 @@ f (int8_t *restrict a, int8_t *restrict b, int n)
 
 /* FIXME: Since we don't have VECT cost model yet, LOAD_LANES/STORE_LANES are chosen
    instead of SLP when riscv-autovec-lmul=m1 or m2.  */
-/* { dg-final { scan-tree-dump-times "\.VEC_PERM" 1 "optimized" { xfail { any-opts "--param riscv-autovec-lmul=m1" "--param riscv-autovec-lmul=m2" } } } } */
+/* { dg-final { scan-tree-dump-times "\.VEC_PERM" 1 "optimized" { xfail { any-opts "--param riscv-autovec-lmul=m1" "--param riscv-autovec-lmul=m2" "--param riscv-autovec-lmul=m8" } } } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/compress-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/compress-1.c
new file mode 100644 (file)
index 0000000..537a032
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/compress-1.c
@@ -0,0 +1,6 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv_zvfhmin -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8" } */
+
+#include "../vls-vlmax/compress-1.c"
+
+/* { dg-final { scan-assembler-times {\tvcompress\.vm} 2 } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/compress-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/compress-2.c
new file mode 100644 (file)
index 0000000..e643147
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/compress-2.c
@@ -0,0 +1,7 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv_zvfhmin -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8" } */
+
+#include "../vls-vlmax/compress-2.c"
+
+/* { dg-final { scan-assembler-times {\tvcompress\.vm} 5 } } */
+/* { dg-final { scan-assembler-times {\tvslideup} 2 } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/compress-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/compress-3.c
new file mode 100644 (file)
index 0000000..5e87294
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/compress-3.c
@@ -0,0 +1,7 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv_zvfhmin -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8" } */
+
+#include "../vls-vlmax/compress-3.c"
+
+/* { dg-final { scan-assembler-times {\tvcompress.vm} 8 } } */
+/* { dg-final { scan-assembler-times {\tvslideup} 8 } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/compress-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/compress-4.c
new file mode 100644 (file)
index 0000000..a4ceb62
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/compress-4.c
@@ -0,0 +1,7 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv_zvfhmin -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8" } */
+
+#include "../vls-vlmax/compress-4.c"
+
+/* { dg-final { scan-assembler-times {\tvcompress.vm} 11 } } */
+/* { dg-final { scan-assembler-times {\tvslideup} 11 } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/compress-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/compress-5.c
new file mode 100644 (file)
index 0000000..f407027
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/compress-5.c
@@ -0,0 +1,6 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv_zvfhmin -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8" } */
+
+#include "../vls-vlmax/compress-5.c"
+
+/* { dg-final { scan-assembler-times {\tvcompress.vm} 11 } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/compress-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/compress-6.c
new file mode 100644 (file)
index 0000000..ffc0b8f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/compress-6.c
@@ -0,0 +1,6 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv_zvfhmin -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8" } */
+
+#include "../vls-vlmax/compress-6.c"
+
+/* { dg-final { scan-assembler-times {\tvcompress.vm} 11 } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/merge-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/merge-1.c
new file mode 100644 (file)
index 0000000..9cbc845
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/merge-1.c
@@ -0,0 +1,6 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv_zvfhmin -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8" } */
+
+#include "../vls-vlmax/merge-1.c"
+
+/* { dg-final { scan-assembler-times {\tvmerge.vvm} 11 } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/merge-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/merge-2.c
new file mode 100644 (file)
index 0000000..e270db9
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/merge-2.c
@@ -0,0 +1,6 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv_zvfhmin -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8" } */
+
+#include "../vls-vlmax/merge-2.c"
+
+/* { dg-final { scan-assembler-times {\tvmerge.vvm} 11 } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/merge-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/merge-3.c
new file mode 100644 (file)
index 0000000..033952f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/merge-3.c
@@ -0,0 +1,6 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv_zvfhmin -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8" } */
+
+#include "../vls-vlmax/merge-3.c"
+
+/* { dg-final { scan-assembler-times {\tvmerge.vvm} 11 } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/merge-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/merge-4.c
new file mode 100644 (file)
index 0000000..62ed1a5
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/merge-4.c
@@ -0,0 +1,6 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv_zvfhmin -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8" } */
+
+#include "../vls-vlmax/merge-4.c"
+
+/* dg-final scan-assembler-times {\tvmerge.vvm} 11 */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/merge-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/merge-5.c
new file mode 100644 (file)
index 0000000..42fa2ec
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/merge-5.c
@@ -0,0 +1,6 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv_zvfhmin -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8" } */
+
+#include "../vls-vlmax/merge-5.c"
+
+/* { dg-final { scan-assembler-times {\tvmerge.vvm} 8 } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/merge-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/merge-6.c
new file mode 100644 (file)
index 0000000..d5222f6
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/merge-6.c
@@ -0,0 +1,6 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv_zvfhmin -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8" } */
+
+#include "../vls-vlmax/merge-6.c"
+
+/* { dg-final { scan-assembler-times {\tvmerge.vvm} 5 } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/merge-7.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/merge-7.c
new file mode 100644 (file)
index 0000000..bd097f0
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/merge-7.c
@@ -0,0 +1,6 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv_zvfhmin -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8" } */
+
+#include "../vls-vlmax/merge-7.c"
+
+/* { dg-final { scan-assembler-times {\tvmerge.vvm} 2 } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/perm-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/perm-1.c
new file mode 100644 (file)
index 0000000..327913b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/perm-1.c
@@ -0,0 +1,6 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv_zvfhmin -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8" } */
+
+#include "../vls-vlmax/perm-1.c"
+
+/* { dg-final { scan-assembler-times {vrgather\.vi\tv[0-9]+,\s*v[0-9]+,\s*1} 31 } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/perm-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/perm-2.c
new file mode 100644 (file)
index 0000000..d562312
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/perm-2.c
@@ -0,0 +1,6 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv_zvfhmin -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8" } */
+
+#include "../vls-vlmax/perm-2.c"
+
+/* { dg-final { scan-assembler-times {vrgather\.vi\tv[0-9]+,\s*v[0-9]+,\s*31} 7 } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/perm-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/perm-3.c
new file mode 100644 (file)
index 0000000..87319e3
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/perm-3.c
@@ -0,0 +1,6 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv_zvfhmin -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8" } */
+
+#include "../vls-vlmax/perm-3.c"
+
+/* { dg-final { scan-assembler-times {vrgather\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 3 } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/perm-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/perm-4.c
new file mode 100644 (file)
index 0000000..46cad8e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/perm-4.c
@@ -0,0 +1,8 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv_zvfhmin -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8" } */
+
+#include "../vls-vlmax/perm-4.c"
+
+/* { dg-final { scan-assembler-times {vrgather\.vv\tv[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 31 } } */
+/* { dg-final { scan-assembler-times {vrsub\.vi} 24 } } */
+/* { dg-final { scan-assembler-times {vrsub\.vx} 7 } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/perm-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/perm-5.c
new file mode 100644 (file)
index 0000000..3460315
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/perm-5.c
@@ -0,0 +1,6 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv_zvfhmin -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8" } */
+
+#include "../vls-vlmax/perm-5.c"
+
+/* { dg-final { scan-assembler-times {vrgather\.vv\tv[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 31 } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/perm-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/perm-6.c
new file mode 100644 (file)
index 0000000..a2a722f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/perm-6.c
@@ -0,0 +1,6 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv_zvfhmin -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8" } */
+
+#include "../vls-vlmax/perm-6.c"
+
+/* { dg-final { scan-assembler-times {vrgather\.vi\tv[0-9]+,\s*v[0-9]+,\s*1} 31 } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/perm-7.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/perm-7.c
new file mode 100644 (file)
index 0000000..b474ccf
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/perm-7.c
@@ -0,0 +1,6 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv_zvfhmin -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8" } */
+
+#include "../vls-vlmax/perm-7.c"
+
+/* { dg-final { scan-assembler-times {vrgather\.vv\tv[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 31 } } */